diff options
author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
---|---|---|
committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:29 -0500 |
commit | 93c0307d418e08db609818f19f5d2b02d45e7465 (patch) | |
tree | 1f72a6617fb4a74d904a933bc48136fa0760bd19 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | |
parent | f2db2a96d181f796e6e475121f10230b9d1d007f (diff) | |
download | gem5-93c0307d418e08db609818f19f5d2b02d45e7465.tar.xz |
tests: Update regressions for the new kernels and various preceeding fixes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4157 |
1 files changed, 2117 insertions, 2040 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 37ec7ce19..ffa50b552 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.658488 # Number of seconds simulated -sim_ticks 2658488068000 # Number of ticks simulated -final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.843718 # Number of seconds simulated +sim_ticks 2843718094000 # Number of ticks simulated +final_tick 2843718094000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70694 # Simulator instruction rate (inst/s) -host_op_rate 85127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2981704600 # Simulator tick rate (ticks/s) -host_mem_usage 438480 # Number of bytes of host memory used -host_seconds 891.60 # Real time elapsed on the host -sim_insts 63030433 # Number of instructions simulated -sim_ops 75898814 # Number of ops (including micro ops) simulated +host_inst_rate 161241 # Simulator instruction rate (inst/s) +host_op_rate 195251 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3650642703 # Simulator tick rate (ticks/s) +host_mem_usage 606904 # Number of bytes of host memory used +host_seconds 778.96 # Real time elapsed on the host +sim_insts 125601128 # Number of instructions simulated +sim_ops 152093417 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 10240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1341052 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10709120 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory -system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory +system.physmem.bytes_read::cpu1.inst 541088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1237760 # Number of bytes read from this memory +system.physmem.bytes_read::total 13841180 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 411264 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 31936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 443200 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7176832 # Number of bytes written to this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory +system.physmem.bytes_written::total 9512912 # Number of bytes written to this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 160 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 21479 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 167330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15512805 # Number of read requests accepted -system.physmem.writeReqs 825159 # Number of write requests accepted -system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue -system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 969393 # Per bank write bursts -system.physmem.perBankRdBursts::1 969270 # Per bank write bursts -system.physmem.perBankRdBursts::2 969024 # Per bank write bursts -system.physmem.perBankRdBursts::3 969581 # Per bank write bursts -system.physmem.perBankRdBursts::4 971912 # Per bank write bursts -system.physmem.perBankRdBursts::5 969565 # Per bank write bursts -system.physmem.perBankRdBursts::6 969152 # Per bank write bursts -system.physmem.perBankRdBursts::7 969036 # Per bank write bursts -system.physmem.perBankRdBursts::8 969555 # Per bank write bursts -system.physmem.perBankRdBursts::9 969606 # Per bank write bursts -system.physmem.perBankRdBursts::10 969469 # Per bank write bursts -system.physmem.perBankRdBursts::11 968910 # Per bank write bursts -system.physmem.perBankRdBursts::12 969137 # Per bank write bursts -system.physmem.perBankRdBursts::13 969414 # Per bank write bursts -system.physmem.perBankRdBursts::14 969294 # Per bank write bursts -system.physmem.perBankRdBursts::15 968822 # Per bank write bursts -system.physmem.perBankWrBursts::0 7303 # Per bank write bursts -system.physmem.perBankWrBursts::1 7359 # Per bank write bursts -system.physmem.perBankWrBursts::2 6981 # Per bank write bursts -system.physmem.perBankWrBursts::3 7260 # Per bank write bursts -system.physmem.perBankWrBursts::4 7486 # Per bank write bursts -system.physmem.perBankWrBursts::5 7442 # Per bank write bursts -system.physmem.perBankWrBursts::6 7374 # Per bank write bursts -system.physmem.perBankWrBursts::7 7195 # Per bank write bursts -system.physmem.perBankWrBursts::8 7413 # Per bank write bursts -system.physmem.perBankWrBursts::9 7378 # Per bank write bursts -system.physmem.perBankWrBursts::10 7327 # Per bank write bursts -system.physmem.perBankWrBursts::11 7067 # Per bank write bursts -system.physmem.perBankWrBursts::12 6951 # Per bank write bursts -system.physmem.perBankWrBursts::13 7051 # Per bank write bursts -system.physmem.perBankWrBursts::14 7072 # Per bank write bursts -system.physmem.perBankWrBursts::15 6798 # Per bank write bursts +system.physmem.num_reads::cpu1.inst 8478 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 19340 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216817 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112138 # Number of write requests responded to by this memory +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory +system.physmem.num_writes::total 152798 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 3601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 471584 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3765887 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 190275 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 435261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4867283 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 144622 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 11230 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 155852 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2523749 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::realview.ide 815248 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3345237 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2523749 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 815586 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 477810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3765887 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 190289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 435261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8212520 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 216817 # Number of read requests accepted +system.physmem.writeReqs 152798 # Number of write requests accepted +system.physmem.readBursts 216817 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 152798 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13860672 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9527424 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13841180 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9512912 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 244 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3916 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 13461 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 14081 # Per bank write bursts +system.physmem.perBankRdBursts::1 13907 # Per bank write bursts +system.physmem.perBankRdBursts::2 14464 # Per bank write bursts +system.physmem.perBankRdBursts::3 13988 # Per bank write bursts +system.physmem.perBankRdBursts::4 16210 # Per bank write bursts +system.physmem.perBankRdBursts::5 13087 # Per bank write bursts +system.physmem.perBankRdBursts::6 13697 # Per bank write bursts +system.physmem.perBankRdBursts::7 13930 # Per bank write bursts +system.physmem.perBankRdBursts::8 13098 # Per bank write bursts +system.physmem.perBankRdBursts::9 13410 # Per bank write bursts +system.physmem.perBankRdBursts::10 13015 # Per bank write bursts +system.physmem.perBankRdBursts::11 11706 # Per bank write bursts +system.physmem.perBankRdBursts::12 12947 # Per bank write bursts +system.physmem.perBankRdBursts::13 13659 # Per bank write bursts +system.physmem.perBankRdBursts::14 12722 # Per bank write bursts +system.physmem.perBankRdBursts::15 12652 # Per bank write bursts +system.physmem.perBankWrBursts::0 9756 # Per bank write bursts +system.physmem.perBankWrBursts::1 10039 # Per bank write bursts +system.physmem.perBankWrBursts::2 10215 # Per bank write bursts +system.physmem.perBankWrBursts::3 9785 # Per bank write bursts +system.physmem.perBankWrBursts::4 9214 # Per bank write bursts +system.physmem.perBankWrBursts::5 9161 # Per bank write bursts +system.physmem.perBankWrBursts::6 9492 # Per bank write bursts +system.physmem.perBankWrBursts::7 9434 # Per bank write bursts +system.physmem.perBankWrBursts::8 9026 # Per bank write bursts +system.physmem.perBankWrBursts::9 9356 # Per bank write bursts +system.physmem.perBankWrBursts::10 9095 # Per bank write bursts +system.physmem.perBankWrBursts::11 8550 # Per bank write bursts +system.physmem.perBankWrBursts::12 9129 # Per bank write bursts +system.physmem.perBankWrBursts::13 9225 # Per bank write bursts +system.physmem.perBankWrBursts::14 8893 # Per bank write bursts +system.physmem.perBankWrBursts::15 8496 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2658486560500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2843715756500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 59 # Read request sizes (log2) -system.physmem.readPktSize::3 15335449 # Read request sizes (log2) +system.physmem.readPktSize::2 559 # Read request sizes (log2) +system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 177297 # Read request sizes (log2) +system.physmem.readPktSize::6 216230 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 757284 # Write request sizes (log2) +system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67875 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1046149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1019751 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 986849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1098941 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 993476 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1059379 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2733951 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2632980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3427107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 133098 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 114256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 105608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 102115 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 143 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 10 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148362 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62454 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9329 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8314 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7470 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 438 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 316 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 218 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 109 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see @@ -176,630 +179,633 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4048 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4083 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4691 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5817 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6785 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6904 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7259 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7270 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7345 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1037609 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads -system.physmem.totQLat 404032545000 # Total ticks spent queuing -system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3559 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4302 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7531 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10919 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10534 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10395 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10863 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 299 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 247 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 197 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 163 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 157 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 107 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 113 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 30 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92355 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 253.241254 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.538036 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 308.020470 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46699 50.56% 50.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18860 20.42% 70.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6817 7.38% 78.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3583 3.88% 82.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3053 3.31% 85.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2112 2.29% 87.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1277 1.38% 89.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1140 1.23% 90.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8814 9.54% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92355 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7471 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.988355 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 530.902810 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7470 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7471 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7471 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.925847 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.607688 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 10.837629 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6200 82.99% 82.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 464 6.21% 89.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 76 1.02% 90.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 210 2.81% 93.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 192 2.57% 95.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 15 0.20% 95.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 27 0.36% 96.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.20% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 29 0.39% 96.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.13% 96.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.12% 97.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.08% 97.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 163 2.18% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.05% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.07% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 4 0.05% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 14 0.19% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.05% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7471 # Writes before turning the bus around for reads +system.physmem.totQLat 7621074500 # Total ticks spent queuing +system.physmem.totMemAccLat 11681818250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1082865000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35189.40 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.77 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 53939.40 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 2.94 # Data bus utilization in percentage -system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 14503540 # Number of row buffer hits during reads -system.physmem.writeRowHits 85448 # Number of row buffer hits during writes -system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes -system.physmem.avgGap 162718.35 # Average gap between requests -system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states -system.physmem.memoryStateTime::REF 88772580000 # Time in different power states +system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.99 # Average read queue length when enqueuing +system.physmem.avgWrQLen 23.13 # Average write queue length when enqueuing +system.physmem.readRowHits 183248 # Number of row buffer hits during reads +system.physmem.writeRowHits 89836 # Number of row buffer hits during writes +system.physmem.readRowHitRate 84.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 60.34 # Row buffer hit rate for writes +system.physmem.avgGap 7693723.89 # Average gap between requests +system.physmem.pageHitRate 74.72 # Row buffer hit rate, read and write combined +system.physmem.memoryStateTime::IDLE 2710028687250 # Time in different power states +system.physmem.memoryStateTime::REF 94957980000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states +system.physmem.memoryStateTime::ACT 38731176500 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 3923753400 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 3920570640 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 2140936875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 2139200250 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 60504077400 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 60482814600 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 378432000 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 369729360 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 173639166480 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 173639166480 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 146077789680 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 145345956705 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1466951353500 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1467593312250 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1853615509335 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1853490750285 # Total energy per rank (pJ) -system.physmem.averagePower::0 697.245591 # Core power per rank (mW) -system.physmem.averagePower::1 697.198662 # Core power per rank (mW) -system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 704 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 256 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 704 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 4 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 11 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 96 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 169 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 265 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 96 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 169 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 265 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16692376 # Transaction distribution -system.membus.trans_dist::ReadResp 16692376 # Transaction distribution -system.membus.trans_dist::WriteReq 768869 # Transaction distribution -system.membus.trans_dist::WriteResp 768869 # Transaction distribution -system.membus.trans_dist::Writeback 67875 # Transaction distribution -system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution -system.membus.trans_dist::ReadExReq 15293 # Transaction distribution -system.membus.trans_dist::ReadExResp 8420 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 68687 # Total snoops (count) -system.membus.snoop_fanout::samples 327086 # Request fanout histogram +system.physmem.actEnergy::0 365654520 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 332549280 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 199513875 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 181450500 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 884239200 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 805030200 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 499582080 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 465069600 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 185737808880 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 185737808880 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 82126203345 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81336736530 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1634190168750 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1634882683500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1904003170650 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1903741328490 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.547151 # Core power per rank (mW) +system.physmem.averagePower::1 669.455073 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1280 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 512 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1280 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 20 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 450 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 450 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 450 # Total bandwidth to/from this memory (bytes/s) +system.membus.trans_dist::ReadReq 238282 # Transaction distribution +system.membus.trans_dist::ReadResp 238282 # Transaction distribution +system.membus.trans_dist::WriteReq 31054 # Transaction distribution +system.membus.trans_dist::WriteResp 31054 # Transaction distribution +system.membus.trans_dist::Writeback 112138 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 80328 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40430 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13461 # Transaction distribution +system.membus.trans_dist::ReadExReq 30145 # Transaction distribution +system.membus.trans_dist::ReadExResp 13182 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14040 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 705796 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 827846 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72718 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 900564 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1280 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21034796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21227006 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23546302 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124500 # Total snoops (count) +system.membus.snoop_fanout::samples 499399 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 499399 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 327086 # Request fanout histogram -system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 499399 # Request fanout histogram +system.membus.reqLayer0.occupancy 87896996 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11055000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12141500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) -system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1598500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17877285000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5004493562 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37922455685 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.4 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1620346498 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 2120331885 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38636884 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 92119 # number of replacements -system.l2c.tags.tagsinuse 55174.117162 # Cycle average of tags in use -system.l2c.tags.total_refs 396231 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156723 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.528225 # Average number of references to valid blocks. +system.l2c.tags.replacements 151104 # number of replacements +system.l2c.tags.tagsinuse 64343.342453 # Cycle average of tags in use +system.l2c.tags.total_refs 537709 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 215892 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.490639 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8029.027858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.830738 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029129 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2503.920237 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29498.221526 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.298488 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2007.480710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13123.308478 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.122513 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000043 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.038207 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.450107 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.030632 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200246 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.841890 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 53228 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 11362 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 13312.566907 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.661228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.033237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3627.484276 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 40388.691608 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.364745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 878.502916 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 6044.037536 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.203134 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001246 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.055351 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.616283 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000158 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.013405 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.092225 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.981801 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 46495 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 18259 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4763 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 48327 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1719 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9346 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.812195 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.173370 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5120698 # Number of tag accesses -system.l2c.tags.data_accesses 5120698 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 193 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 42 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 14931 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88016 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 237 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 59 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 19686 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76288 # number of ReadReq hits -system.l2c.ReadReq_hits::total 199452 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 215010 # number of Writeback hits -system.l2c.Writeback_hits::total 215010 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 3051 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 2025 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5076 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 100 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 313 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 2211 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 2397 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4608 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 193 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 42 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 17142 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 88016 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 237 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 59 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 22083 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 76288 # number of demand (read+write) hits -system.l2c.demand_hits::total 204060 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 193 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 42 # number of overall hits -system.l2c.overall_hits::cpu0.inst 17142 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 88016 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 237 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 59 # number of overall hits -system.l2c.overall_hits::cpu1.inst 22083 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 76288 # number of overall hits -system.l2c.overall_hits::total 204060 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4222 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq misses +system.l2c.tags.age_task_id_blocks_1022::2 432 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6889 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 34 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 16 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2341 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15618 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.709457 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000519 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.278610 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6702696 # Number of tag accesses +system.l2c.tags.data_accesses 6702696 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 575 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 71741.310436 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72875.434610 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 93895.865967 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10096.181480 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10110.003997 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10099.452575 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10081.812500 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.717147 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10078.098131 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 71808.670459 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60613.779053 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 66456.970380 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 70412.493750 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 71767.346212 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 94888.770364 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67589.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63559.799283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 100329.662461 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92183.718423 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -810,167 +816,194 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). -system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). -system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). -system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. -system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. -system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 170698 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram +system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 631 # Number of DMA write transactions. +system.toL2Bus.trans_dist::ReadReq 675950 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 675935 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31054 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31054 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 253703 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 93172 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40812 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 133984 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 39254 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 39254 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372089 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 383613 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1755702 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 42006746 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 8315748 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 50322494 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 294957 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1100978 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033136 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.178992 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1064496 96.69% 96.69% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36482 3.31% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1100978 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1599263913 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution -system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution -system.iobus.trans_dist::WriteReq 8084 # Transaction distribution -system.iobus.trans_dist::WriteResp 8084 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes) +system.toL2Bus.snoopLayer0.occupancy 1080000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2370465695 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 831346703 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 31024 # Transaction distribution +system.iobus.trans_dist::ReadResp 31024 # Transaction distribution +system.iobus.trans_dist::WriteReq 59407 # Transaction distribution +system.iobus.trans_dist::WriteResp 59440 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 738 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 393 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484122 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) -system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 441000 # Layer occupancy (ticks) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7252165 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326680325 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36847116 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu0.branchPred.lookups 34854856 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17109626 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1616877 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20006820 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14503231 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.491435 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10748202 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 771222 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -994,25 +1027,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6449087 # DTB read hits -system.cpu0.dtb.read_misses 22394 # DTB read misses -system.cpu0.dtb.write_hits 5803603 # DTB write hits -system.cpu0.dtb.write_misses 1784 # DTB write misses -system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch +system.cpu0.dtb.read_hits 23968692 # DTB read hits +system.cpu0.dtb.read_misses 61651 # DTB read misses +system.cpu0.dtb.write_hits 17871018 # DTB write hits +system.cpu0.dtb.write_misses 6619 # DTB write misses +system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 3502 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1211 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1921 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6471481 # DTB read accesses -system.cpu0.dtb.write_accesses 5805387 # DTB write accesses +system.cpu0.dtb.perms_faults 566 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24030343 # DTB read accesses +system.cpu0.dtb.write_accesses 17877637 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12252690 # DTB hits -system.cpu0.dtb.misses 24178 # DTB misses -system.cpu0.dtb.accesses 12276868 # DTB accesses +system.cpu0.dtb.hits 41839710 # DTB hits +system.cpu0.dtb.misses 68270 # DTB misses +system.cpu0.dtb.accesses 41907980 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1034,93 +1067,93 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 13302311 # ITB inst hits -system.cpu0.itb.inst_misses 3954 # ITB inst misses +system.cpu0.itb.inst_hits 70097291 # ITB inst hits +system.cpu0.itb.inst_misses 3844 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses -system.cpu0.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2220 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7362 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses -system.cpu0.itb.hits 13302311 # DTB hits -system.cpu0.itb.misses 3954 # DTB misses -system.cpu0.itb.accesses 13306265 # DTB accesses -system.cpu0.numCycles 86799146 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70101135 # ITB inst accesses +system.cpu0.itb.hits 70097291 # DTB hits +system.cpu0.itb.misses 3844 # DTB misses +system.cpu0.itb.accesses 70101135 # DTB accesses +system.cpu0.numCycles 227722348 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29471412 # Number of instructions committed -system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.945198 # CPI: cycles per instruction -system.cpu0.ipc 0.339536 # IPC: instructions per cycle +system.cpu0.committedInsts 109201964 # Number of instructions committed +system.cpu0.committedOps 132004483 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8817575 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1858 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5459726684 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.085332 # CPI: cycles per instruction +system.cpu0.ipc 0.479540 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed -system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 670908 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy +system.cpu0.kern.inst.quiesce 1864 # number of quiesce instructions executed +system.cpu0.tickCycles 192189087 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 35533261 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 1960423 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.796865 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 68128653 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1960935 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.742943 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796865 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 97 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 27268595 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 27268595 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 12627162 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 12627162 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 12627162 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 12627162 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 12627162 # number of overall hits -system.cpu0.icache.overall_hits::total 12627162 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 671424 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 671424 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 671424 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 671424 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 671424 # number of overall misses -system.cpu0.icache.overall_misses::total 671424 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5600052378 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5600052378 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5600052378 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5600052378 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5600052378 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5600052378 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 13298586 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 13298586 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 13298586 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 13298586 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 13298586 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 13298586 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050488 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050488 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050488 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050488 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050488 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050488 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8340.560328 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8340.560328 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8340.560328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8340.560328 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 142140155 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 142140155 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 68128653 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 68128653 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 68128653 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 68128653 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 68128653 # number of overall hits +system.cpu0.icache.overall_hits::total 68128653 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1960950 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1960950 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1960950 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1960950 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1960950 # number of overall misses +system.cpu0.icache.overall_misses::total 1960950 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16347715808 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16347715808 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16347715808 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16347715808 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16347715808 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16347715808 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70089603 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70089603 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70089603 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70089603 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70089603 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70089603 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027978 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.027978 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027978 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.027978 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027978 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.027978 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8336.630617 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8336.630617 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8336.630617 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8336.630617 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8336.630617 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1129,375 +1162,366 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 671424 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 671424 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 671424 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 671424 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 671424 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 671424 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4592017122 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4592017122 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4592017122 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4592017122 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4592017122 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4592017122 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 214843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 214843000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 214843000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 214843000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050488 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050488 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050488 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6839.221002 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1960950 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1960950 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1960950 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1960950 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1960950 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1960950 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13404270692 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13404270692 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13404270692 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13404270692 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13404270692 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13404270692 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276968500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276968500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 276968500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.027978 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.027978 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.027978 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.027978 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6835.600445 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6835.600445 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6835.600445 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1296970 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1098887 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10913 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10913 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 275708 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 144812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 136646 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1347493 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1381165 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13298 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 66487 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 2808443 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43116416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45547448 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21688 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119336 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 88804888 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 661783 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2010538 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.294459 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.455799 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2745512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2644445 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28520 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 513053 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 701523 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 70947 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43092 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 94006 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 7 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 290299 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 280446 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3928023 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2381529 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11804 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166842 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6488198 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 125696704 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86351322 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313268 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 212378982 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1094951 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4365889 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.223377 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.416509 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 1418517 70.55% 70.55% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3390648 77.66% 77.66% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 975241 22.34% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4365889 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2254798560 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 118870000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1011659878 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 704346240 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2947700808 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1230574902 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7877498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7385992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 36655495 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 88548223 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6510276 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 198706 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6081219 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2295 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17144913 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425558 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16187872 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 8427 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2119 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 225934 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 452636 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6267 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 516786 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1326511 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 185629 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16039.205043 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1209112 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 201843 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 5.990359 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5120294500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4761.005363 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 22.831562 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.161164 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2118.524351 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9136.682602 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.290589 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.001394 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000010 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.129304 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.557659 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.978955 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8350 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7848 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 34 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 57 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 864 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5964 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1431 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 285 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1438 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5471 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 598 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.509644 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000977 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.479004 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 22924468 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 22924468 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29315 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5251 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 886043 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 920609 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 275708 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 275708 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1811 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1811 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 729 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 729 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107812 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 107812 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29315 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5251 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 993855 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1028421 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29315 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5251 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 993855 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1028421 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 519 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 171 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 49158 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 49848 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 18945 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 18945 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 10134 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 10134 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 6 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 23532 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 23532 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 519 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 171 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 72690 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 73380 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 519 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 171 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 72690 # number of overall misses -system.cpu0.l2cache.overall_misses::total 73380 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11037500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3618999 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1323798925 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1338455424 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312100526 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 312100526 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 201024600 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 201024600 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 1393500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 1393500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 857324396 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 857324396 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11037500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3618999 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2181123321 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 2195779820 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11037500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3618999 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2181123321 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 2195779820 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 29834 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5422 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 935201 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 970457 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 275708 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 275708 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 20756 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 20756 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 10863 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 10863 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 6 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 131344 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 131344 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 29834 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5422 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1066545 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1101801 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 29834 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5422 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1066545 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1101801 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031538 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052564 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.051365 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.912748 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.912748 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.932891 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.932891 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.179163 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.179163 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.031538 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.068155 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.066600 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.031538 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.068155 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.066600 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 21163.736842 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 26929.470788 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 26850.734714 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 16474.031459 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 16474.031459 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19836.648905 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19836.648905 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 232250 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 232250 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 36432.279279 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 36432.279279 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 29923.409921 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 21266.859345 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 21163.736842 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 30005.823648 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 29923.409921 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 729 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2957 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 667 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 2 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 51 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 268 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3107 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3633 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 224 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546814 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000549 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444519 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 54811525 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 54811525 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77296 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4241 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2365837 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2447374 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 513053 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 513053 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4545 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 4545 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2277 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2277 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 221177 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 221177 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77296 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4241 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 2587014 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2668551 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77296 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4241 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 2587014 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2668551 # 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number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3288968705 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21179021871 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24497750077 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6107809749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6107809749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4518638513 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4518638513 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10626448262 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10626448262 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.035319 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034643 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.912748 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.912748 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.932891 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.932891 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.064648 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.860394 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.860394 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888981 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888981 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.163315 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.163315 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.013037 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.040932 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047895 # 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average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 26330.353335 # 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average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16932.294563 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13220.179510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13220.179510 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27175.023640 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27175.023640 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26443.685602 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15251.370166 # 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average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1505,99 +1529,98 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 362294 # number of replacements -system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.923616 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy +system.cpu0.dcache.tags.replacements 712097 # number of replacements +system.cpu0.dcache.tags.tagsinuse 497.191982 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40404438 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 712609 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.699309 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306793500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 497.191982 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.971078 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.971078 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 343 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 40 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 24357333 # 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number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 308329 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 276386 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 276386 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 10191 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 10191 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 10869 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 10869 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 584715 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 584715 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 584715 # number of overall misses -system.cpu0.dcache.overall_misses::total 584715 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 3680932639 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 3680932639 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 4210104069 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 4210104069 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 167480751 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 167480751 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 254581965 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 254581965 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1495500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 7891036708 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 7891036708 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5551965 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157499 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 11665925 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 11665925 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049782 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83631959 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83631959 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 22807107 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22807107 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 16791710 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16791710 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 380026 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 380026 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 361110 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361110 # 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mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053745 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019517 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019517 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019517 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10332.165295 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10332.165295 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14124.286908 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14124.286908 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14504.873062 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14504.873062 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19639.904924 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19639.904924 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11768.639359 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11768.639359 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1683,15 +1704,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7012649 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits +system.cpu1.branchPred.lookups 4191050 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2447557 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 261619 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2683528 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1692147 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 63.056804 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 827495 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 59633 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1715,25 +1736,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7899300 # DTB read hits -system.cpu1.dtb.read_misses 20789 # DTB read misses -system.cpu1.dtb.write_hits 6047693 # DTB write hits -system.cpu1.dtb.write_misses 2209 # DTB write misses -system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu1.dtb.read_hits 4177995 # DTB read hits +system.cpu1.dtb.read_misses 21525 # DTB read misses +system.cpu1.dtb.write_hits 3468676 # DTB write hits +system.cpu1.dtb.write_misses 1889 # DTB write misses +system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 2064 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 236 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 360 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7920089 # DTB read accesses -system.cpu1.dtb.write_accesses 6049902 # DTB write accesses +system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 4199520 # DTB read accesses +system.cpu1.dtb.write_accesses 3470565 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13946993 # DTB hits -system.cpu1.dtb.misses 22998 # DTB misses -system.cpu1.dtb.accesses 13969991 # DTB accesses +system.cpu1.dtb.hits 7646671 # DTB hits +system.cpu1.dtb.misses 23414 # DTB misses +system.cpu1.dtb.accesses 7670085 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1755,91 +1776,92 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 14215184 # ITB inst hits -system.cpu1.itb.inst_misses 5010 # ITB inst misses +system.cpu1.itb.inst_hits 7954981 # ITB inst hits +system.cpu1.itb.inst_misses 2237 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses -system.cpu1.itb.flush_tlb 4 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb 66 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses -system.cpu1.itb.hits 14215184 # DTB hits -system.cpu1.itb.misses 5010 # DTB misses -system.cpu1.itb.accesses 14220194 # DTB accesses -system.cpu1.numCycles 502294457 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7957218 # ITB inst accesses +system.cpu1.itb.hits 7954981 # DTB hits +system.cpu1.itb.misses 2237 # DTB misses +system.cpu1.itb.accesses 7957218 # DTB accesses +system.cpu1.numCycles 42108230 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 33559021 # Number of instructions committed -system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 14.967494 # CPI: cycles per instruction -system.cpu1.ipc 0.066811 # IPC: instructions per cycle +system.cpu1.committedInsts 16399164 # Number of instructions committed +system.cpu1.committedOps 20088934 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1607897 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2744 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5644728223 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.567706 # CPI: cycles per instruction +system.cpu1.ipc 0.389453 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed -system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 777492 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 2745 # number of quiesce instructions executed +system.cpu1.tickCycles 30601119 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 11507111 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 921368 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.459165 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7030999 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 921880 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.626805 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 71222254500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459165 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits -system.cpu1.icache.overall_hits::total 13433657 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses -system.cpu1.icache.overall_misses::total 778004 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 16827638 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16827638 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 7030999 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7030999 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7030999 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7030999 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7030999 # number of overall hits +system.cpu1.icache.overall_hits::total 7030999 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 921880 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 921880 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 921880 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 921880 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 921880 # number of overall misses +system.cpu1.icache.overall_misses::total 921880 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7511609427 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7511609427 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7511609427 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7511609427 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7511609427 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7511609427 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7952879 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7952879 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7952879 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7952879 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7952879 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7952879 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.115918 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.115918 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.115918 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.115918 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.115918 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.115918 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8148.142304 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8148.142304 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8148.142304 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8148.142304 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8148.142304 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1848,370 +1870,362 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 921880 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 921880 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 921880 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 921880 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 921880 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 921880 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6126335573 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6126335573 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6126335573 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6126335573 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6126335573 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6126335573 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10451250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10451250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10451250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 10451250 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.115918 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.115918 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.115918 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.115918 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6645.480510 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6645.480510 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6645.480510 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 606235 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1617912 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1172300 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2534 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 119069 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 160310 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84990 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41555 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86189 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 79780 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67226 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1843990 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 788213 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6991 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 54848 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2694042 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 59007680 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25579748 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10764 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100400 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 84698592 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 851885 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2136582 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.360548 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.480160 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1366242 63.95% 63.95% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 770340 36.05% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2136582 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 806533923 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80269000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1384243177 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 391135835 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 4300499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 29750249 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7297386 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 43768 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 7137149 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1402 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2677 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 112390 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 731398 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 179644 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 112338 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29293 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7458 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1038692 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1075443 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29293 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7458 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1038692 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1075443 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 495 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 146 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61595 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 62236 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18656 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 18656 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12530 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 12530 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 3 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 23997 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 23997 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 495 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 146 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 85592 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 86233 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 495 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 146 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 85592 # number of overall misses -system.cpu1.l2cache.overall_misses::total 86233 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 11596750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3042000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1525132928 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1539771678 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 312251712 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 312251712 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 251269185 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 251269185 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 836500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 836500 # 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Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3286 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 5 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 2980 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1783 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.618530 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.305542 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 22015192 # 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number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25100 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2691 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1096815 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1124606 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 119069 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 119069 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 30209 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 30209 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23325 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23325 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 62748 # 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miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067020 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.066122 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.937270 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937270 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968446 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968446 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.520160 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.520160 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.024223 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090673 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.091541 # 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miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044712 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15113.295648 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15113.295648 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23383.252420 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23383.252420 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18171.060118 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18171.060118 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23308.671426 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23308.671426 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 14672.798302 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 14672.798302 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 14672.798302 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18752.179923 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18752.179923 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18752.179923 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2317,76 +2332,74 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 242084 # number of writebacks -system.cpu1.dcache.writebacks::total 242084 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 36921 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 36921 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 129344 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 129344 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.inst 46 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 46 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 166265 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 166265 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 166265 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 166265 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 198271 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 198271 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 156936 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 156936 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11867 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11867 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13691 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 13691 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 355207 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 355207 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 355207 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 355207 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202163297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202163297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2284592028 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2284592028 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 190117000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 190117000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286543590 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286543590 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 863000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 863000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4486755325 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4486755325 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4486755325 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4486755325 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183747450747 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183747450747 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481854358 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481854358 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218229305105 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218229305105 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029992 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030726 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030726 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.124526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143793 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143793 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030312 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.030312 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11106.835074 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11106.835074 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14557.475837 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14557.475837 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16020.645487 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16020.645487 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20929.339712 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20929.339712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 119069 # number of writebacks +system.cpu1.dcache.writebacks::total 119069 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15047 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15047 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 52186 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52186 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 67233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 67233 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 67233 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 67233 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 169666 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 169666 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 92953 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92953 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5273 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5273 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23325 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 262619 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 262619 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 262619 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 262619 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2247676267 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247676267 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2022089921 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2022089921 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 85260000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 85260000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 495802239 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 495802239 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 310500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 310500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4269766188 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4269766188 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4269766188 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4269766188 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 405245745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 405245745 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 279561993 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 279561993 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 684807738 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 684807738 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.041913 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.041913 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027921 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027921 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054762 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.246802 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.246802 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.035599 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035599 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035599 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13247.652841 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13247.652841 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 21753.896281 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 21753.896281 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16169.163664 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16169.163664 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21256.258907 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21256.258907 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16258.405477 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16258.405477 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2394,30 +2407,94 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.replacements 36445 # number of replacements +system.iocache.tags.tagsinuse 14.485749 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.iocache.tags.tag_accesses 0 # Number of tag accesses -system.iocache.tags.data_accesses 0 # Number of data accesses +system.iocache.tags.sampled_refs 36461 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 268964842000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.485749 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.905359 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.905359 # Average percentage of cache occupancy +system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id +system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id +system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id +system.iocache.tags.tag_accesses 328575 # Number of tag accesses +system.iocache.tags.data_accesses 328575 # Number of data accesses +system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits +system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits +system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses +system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses +system.iocache.demand_misses::realview.ide 255 # number of demand (read+write) misses +system.iocache.demand_misses::total 255 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 255 # number of overall misses +system.iocache.overall_misses::total 255 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31822377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31822377 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31822377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31822377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31822377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31822377 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.demand_accesses::realview.ide 255 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 255 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 255 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 255 # number of overall (read+write) accesses +system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses +system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses +system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses +system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses +system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses +system.iocache.ReadReq_avg_miss_latency::realview.ide 124793.635294 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124793.635294 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124793.635294 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124793.635294 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124793.635294 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.fast_writes 36224 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles -system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency -system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency -system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.demand_mshr_misses::realview.ide 255 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 255 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 255 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 255 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18561377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18561377 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2257984064 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2257984064 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18561377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18561377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18561377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18561377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses +system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses +system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses +system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses +system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses +system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72789.713725 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72789.713725 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72789.713725 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72789.713725 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |