diff options
author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-23 13:50:57 +0100 |
---|---|---|
committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2015-05-23 13:50:57 +0100 |
commit | dbdb9ab518f919cf71c0acd03c16738202eeb61f (patch) | |
tree | c2d0b6ca90110f7607e108628337e828bdb067ba /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | |
parent | f3f06e1684c6575e25b965ab0585473bb47e58cc (diff) | |
download | gem5-dbdb9ab518f919cf71c0acd03c16738202eeb61f.tar.xz |
arm, stats: Update stats to reflect changes to generic timer
The addition of a virtual timer affects stats in minor and o3.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4592 |
1 files changed, 2276 insertions, 2316 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index bb4196597..6bbef9107 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.846145 # Number of seconds simulated -sim_ticks 2846145040000 # Number of ticks simulated -final_tick 2846145040000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.846107 # Number of seconds simulated +sim_ticks 2846106511000 # Number of ticks simulated +final_tick 2846106511000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 162017 # Simulator instruction rate (inst/s) -host_op_rate 196203 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3671761280 # Simulator tick rate (ticks/s) -host_mem_usage 648900 # Number of bytes of host memory used -host_seconds 775.14 # Real time elapsed on the host -sim_insts 125586921 # Number of instructions simulated -sim_ops 152085297 # Number of ops (including micro ops) simulated +host_inst_rate 154405 # Simulator instruction rate (inst/s) +host_op_rate 186958 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3504377822 # Simulator tick rate (ticks/s) +host_mem_usage 600496 # Number of bytes of host memory used +host_seconds 812.16 # Real time elapsed on the host +sim_insts 125401163 # Number of instructions simulated +sim_ops 151839522 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1497984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1248876 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8305216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 388800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 684240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 582144 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1669760 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1336112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8514432 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 219648 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 604112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 400768 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12719228 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1497984 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 388800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1886784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8861888 # Number of bytes written to this memory +system.physmem.bytes_read::total 12756096 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1669760 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 219648 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1889408 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8854144 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8879452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 130 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8871708 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 138 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 23406 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20035 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 129769 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6075 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10711 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9096 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26090 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21399 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133038 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 22 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3432 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9459 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6262 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 199279 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138467 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138346 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142858 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142737 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3103 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 526320 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 438796 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2918058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 136606 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 240409 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 204538 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 586682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 469453 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2991607 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 495 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 77175 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 212259 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 140813 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4468932 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 526320 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 136606 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 662926 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3113646 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4481946 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 586682 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 77175 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 663857 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3110967 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6157 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3119817 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3113646 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3117138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3110967 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3103 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 526320 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 444953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2918058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 899 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 136606 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 240423 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 204538 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 586682 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 475610 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2991607 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 495 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 77175 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 212273 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 140813 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7588749 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 199279 # Number of read requests accepted -system.physmem.writeReqs 179082 # Number of write requests accepted -system.physmem.readBursts 199279 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 179082 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12747712 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6144 # Total number of bytes read from write queue -system.physmem.bytesWritten 9932032 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12719228 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 11197788 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23866 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14978 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12467 # Per bank write bursts -system.physmem.perBankRdBursts::1 12549 # Per bank write bursts -system.physmem.perBankRdBursts::2 12590 # Per bank write bursts -system.physmem.perBankRdBursts::3 12626 # Per bank write bursts -system.physmem.perBankRdBursts::4 14976 # Per bank write bursts -system.physmem.perBankRdBursts::5 12125 # Per bank write bursts -system.physmem.perBankRdBursts::6 13379 # Per bank write bursts -system.physmem.perBankRdBursts::7 13505 # Per bank write bursts -system.physmem.perBankRdBursts::8 12274 # Per bank write bursts -system.physmem.perBankRdBursts::9 12440 # Per bank write bursts -system.physmem.perBankRdBursts::10 11813 # Per bank write bursts -system.physmem.perBankRdBursts::11 11246 # Per bank write bursts -system.physmem.perBankRdBursts::12 11354 # Per bank write bursts -system.physmem.perBankRdBursts::13 11924 # Per bank write bursts -system.physmem.perBankRdBursts::14 11833 # Per bank write bursts -system.physmem.perBankRdBursts::15 12082 # Per bank write bursts -system.physmem.perBankWrBursts::0 9603 # Per bank write bursts -system.physmem.perBankWrBursts::1 9871 # Per bank write bursts -system.physmem.perBankWrBursts::2 10084 # Per bank write bursts -system.physmem.perBankWrBursts::3 9904 # Per bank write bursts -system.physmem.perBankWrBursts::4 9385 # Per bank write bursts -system.physmem.perBankWrBursts::5 9666 # Per bank write bursts -system.physmem.perBankWrBursts::6 10609 # Per bank write bursts -system.physmem.perBankWrBursts::7 10482 # Per bank write bursts -system.physmem.perBankWrBursts::8 9764 # Per bank write bursts -system.physmem.perBankWrBursts::9 9386 # Per bank write bursts -system.physmem.perBankWrBursts::10 9428 # Per bank write bursts -system.physmem.perBankWrBursts::11 9248 # Per bank write bursts -system.physmem.perBankWrBursts::12 9294 # Per bank write bursts -system.physmem.perBankWrBursts::13 9689 # Per bank write bursts -system.physmem.perBankWrBursts::14 9592 # Per bank write bursts -system.physmem.perBankWrBursts::15 9183 # Per bank write bursts +system.physmem.bw_total::total 7599085 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199856 # Number of read requests accepted +system.physmem.writeReqs 178961 # Number of write requests accepted +system.physmem.readBursts 199856 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 178961 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12785664 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 5120 # Total number of bytes read from write queue +system.physmem.bytesWritten 9927488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12756096 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 11190044 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 80 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23813 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 14250 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12367 # Per bank write bursts +system.physmem.perBankRdBursts::1 12533 # Per bank write bursts +system.physmem.perBankRdBursts::2 12905 # Per bank write bursts +system.physmem.perBankRdBursts::3 12918 # Per bank write bursts +system.physmem.perBankRdBursts::4 15006 # Per bank write bursts +system.physmem.perBankRdBursts::5 12397 # Per bank write bursts +system.physmem.perBankRdBursts::6 13141 # Per bank write bursts +system.physmem.perBankRdBursts::7 13266 # Per bank write bursts +system.physmem.perBankRdBursts::8 12256 # Per bank write bursts +system.physmem.perBankRdBursts::9 12318 # Per bank write bursts +system.physmem.perBankRdBursts::10 12174 # Per bank write bursts +system.physmem.perBankRdBursts::11 11385 # Per bank write bursts +system.physmem.perBankRdBursts::12 11522 # Per bank write bursts +system.physmem.perBankRdBursts::13 12342 # Per bank write bursts +system.physmem.perBankRdBursts::14 11687 # Per bank write bursts +system.physmem.perBankRdBursts::15 11559 # Per bank write bursts +system.physmem.perBankWrBursts::0 9829 # Per bank write bursts +system.physmem.perBankWrBursts::1 10209 # Per bank write bursts +system.physmem.perBankWrBursts::2 10296 # Per bank write bursts +system.physmem.perBankWrBursts::3 10100 # Per bank write bursts +system.physmem.perBankWrBursts::4 9093 # Per bank write bursts +system.physmem.perBankWrBursts::5 9584 # Per bank write bursts +system.physmem.perBankWrBursts::6 10130 # Per bank write bursts +system.physmem.perBankWrBursts::7 10398 # Per bank write bursts +system.physmem.perBankWrBursts::8 9607 # Per bank write bursts +system.physmem.perBankWrBursts::9 9596 # Per bank write bursts +system.physmem.perBankWrBursts::10 9832 # Per bank write bursts +system.physmem.perBankWrBursts::11 9707 # Per bank write bursts +system.physmem.perBankWrBursts::12 9196 # Per bank write bursts +system.physmem.perBankWrBursts::13 9428 # Per bank write bursts +system.physmem.perBankWrBursts::14 9291 # Per bank write bursts +system.physmem.perBankWrBursts::15 8821 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 107 # Number of times write queue was full causing retry -system.physmem.totGap 2846144533500 # Total gap between requests +system.physmem.numWrRetry 44 # Number of times write queue was full causing retry +system.physmem.totGap 2846106004500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 551 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 198700 # Read request sizes (log2) +system.physmem.readPktSize::6 199276 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 174691 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 98289 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 47643 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 13113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7835 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6424 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5388 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4763 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 766 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 254 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 167 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 174570 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 98276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 48017 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 13343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9981 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7920 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6441 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5383 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4706 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 742 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 273 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 128 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see @@ -188,164 +184,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2161 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2432 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3791 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5553 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8315 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7470 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7525 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9574 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 8177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8060 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10880 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8816 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1605 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2476 # 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Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 249.965201 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 140.421700 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 309.995255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 47261 52.01% 52.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18080 19.90% 71.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6274 6.90% 78.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3625 3.99% 82.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2837 3.12% 85.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1606 1.77% 87.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 998 1.10% 88.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1046 1.15% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9138 10.06% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90865 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6548 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.509316 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 555.919891 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6546 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6574 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.606328 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.587470 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.316435 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6233 94.81% 94.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 88 1.34% 96.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 20 0.30% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 23 0.35% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 27 0.41% 97.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 26 0.40% 97.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 23 0.35% 97.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 19 0.29% 98.25% # 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Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 5 0.08% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 6 0.09% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.09% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 9 0.14% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::416-431 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 3 0.05% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 2 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::544-559 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::560-575 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::640-655 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 2 0.03% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::928-943 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6574 # Writes before turning the bus around for reads -system.physmem.totQLat 5766362365 # Total ticks spent queuing -system.physmem.totMemAccLat 9501043615 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 995915000 # Total ticks spent in databus transfers -system.physmem.avgQLat 28950.07 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6548 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6548 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.689218 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.640113 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 40.676171 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 6193 94.58% 94.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 92 1.41% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 24 0.37% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.24% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 27 0.41% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 36 0.55% 97.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 25 0.38% 97.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 12 0.18% 98.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.26% 98.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 3 0.05% 98.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 21 0.32% 98.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.27% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 11 0.17% 99.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 3 0.05% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 2 0.03% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.08% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 1 0.02% 99.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 1 0.02% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 8 0.12% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 9 0.14% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 3 0.05% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::608-623 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::912-927 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6548 # Writes before turning the bus around for reads +system.physmem.totQLat 5702655246 # Total ticks spent queuing +system.physmem.totMemAccLat 9448455246 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 998880000 # Total ticks spent in databus transfers +system.physmem.avgQLat 28545.25 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 47700.07 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 47295.25 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.49 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.47 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.93 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.19 # Average write queue length when enqueuing -system.physmem.readRowHits 165729 # Number of row buffer hits during reads -system.physmem.writeRowHits 97368 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.20 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 62.73 # Row buffer hit rate for writes -system.physmem.avgGap 7522298.90 # Average gap between requests -system.physmem.pageHitRate 74.24 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 359432640 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 196119000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 812892600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 515833920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83250586485 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634656782000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1905687617685 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.569329 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719272584266 # Time in different power states -system.physmem_0.memoryStateTime::REF 95038840000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.22 # Average write queue length when enqueuing +system.physmem.readRowHits 166460 # Number of row buffer hits during reads +system.physmem.writeRowHits 97567 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.89 # Row buffer hit rate for writes +system.physmem.avgGap 7513142.24 # Average gap between requests +system.physmem.pageHitRate 74.39 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 359425080 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 196114875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 815357400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 516060720 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83232319410 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634649447000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1905662152725 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.569541 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719260667390 # Time in different power states +system.physmem_0.memoryStateTime::REF 95037540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 31827943234 # Time in different power states +system.physmem_0.memoryStateTime::ACT 31802228860 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 330591240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180382125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 740727000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 489784320 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185895971040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82231883055 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635550381500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1905419720280 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.475203 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2720770086744 # Time in different power states -system.physmem_1.memoryStateTime::REF 95038840000 # Time in different power states +system.physmem_1.actEnergy 327514320 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 178703250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 742887600 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 489097440 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 185893428240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82208245725 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635547757250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1905387633825 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.473086 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2720763679724 # Time in different power states +system.physmem_1.memoryStateTime::REF 95037540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 30336000256 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30305178276 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory @@ -371,15 +363,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 33812647 # Number of BP lookups -system.cpu0.branchPred.condPredicted 16331756 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1585484 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 19439562 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14041669 # Number of BTB hits +system.cpu0.branchPred.lookups 20636360 # Number of BP lookups +system.cpu0.branchPred.condPredicted 13610949 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1051916 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13187821 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9315921 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.232435 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10663467 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 792082 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 70.640336 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3367590 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 213586 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -410,58 +402,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 65253 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 65253 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 42795 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22458 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 65253 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 65253 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 65253 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6648 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 9627.369284 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 8488.785540 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6159.752779 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6446 96.96% 96.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 188 2.83% 99.79% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 4 0.06% 99.85% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 7 0.11% 99.95% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 2 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6648 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 69356 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69356 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46232 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23124 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69356 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69356 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69356 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6817 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9525.708083 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8414.892081 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6090.769517 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 6639 97.39% 97.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 162 2.38% 99.77% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 6 0.09% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 4 0.06% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6817 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 328505000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 328505000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 328505000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5136 77.26% 77.26% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1512 22.74% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6648 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65253 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5248 76.98% 76.98% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1569 23.02% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6817 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69356 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65253 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6648 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69356 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6817 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6648 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 71901 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6817 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 76173 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 22995822 # DTB read hits -system.cpu0.dtb.read_misses 59685 # DTB read misses -system.cpu0.dtb.write_hits 17147924 # DTB write hits -system.cpu0.dtb.write_misses 5568 # DTB write misses +system.cpu0.dtb.read_hits 17307432 # DTB read hits +system.cpu0.dtb.read_misses 63365 # DTB read misses +system.cpu0.dtb.write_hits 14534577 # DTB write hits +system.cpu0.dtb.write_misses 5991 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3505 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1156 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1615 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3513 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1432 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1922 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 564 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23055507 # DTB read accesses -system.cpu0.dtb.write_accesses 17153492 # DTB write accesses +system.cpu0.dtb.perms_faults 561 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17370797 # DTB read accesses +system.cpu0.dtb.write_accesses 14540568 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 40143746 # DTB hits -system.cpu0.dtb.misses 65253 # DTB misses -system.cpu0.dtb.accesses 40208999 # DTB accesses +system.cpu0.dtb.hits 31842009 # DTB hits +system.cpu0.dtb.misses 69356 # DTB misses +system.cpu0.dtb.accesses 31911365 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -491,39 +483,39 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 3866 # Table walker walks requested -system.cpu0.itb.walker.walksShort 3866 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 306 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3560 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 3866 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 3866 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 3866 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2421 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9944.030566 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8839.286720 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5045.849413 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 802 33.13% 33.13% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1572 64.93% 98.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 10 0.41% 98.47% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 35 1.45% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3833 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3833 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 307 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3526 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3833 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3833 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2411 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 9827.457901 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 8615.260983 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5288.530479 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 893 37.04% 37.04% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1467 60.85% 97.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 9 0.37% 98.26% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 39 1.62% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.08% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2421 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2411 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 328041000 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 328041000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 328041000 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2122 87.65% 87.65% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 299 12.35% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2421 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2111 87.56% 87.56% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 300 12.44% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2411 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3866 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3866 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3833 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3833 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2421 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2421 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6287 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 68390761 # ITB inst hits -system.cpu0.itb.inst_misses 3866 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2411 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6244 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 38721907 # ITB inst hits +system.cpu0.itb.inst_misses 3833 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -532,131 +524,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2224 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2217 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7604 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7269 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 68394627 # ITB inst accesses -system.cpu0.itb.hits 68390761 # DTB hits -system.cpu0.itb.misses 3866 # DTB misses -system.cpu0.itb.accesses 68394627 # DTB accesses -system.cpu0.numCycles 225488562 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 38725740 # ITB inst accesses +system.cpu0.itb.hits 38721907 # DTB hits +system.cpu0.itb.misses 3833 # DTB misses +system.cpu0.itb.accesses 38725740 # DTB accesses +system.cpu0.numCycles 164661578 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 104715622 # Number of instructions committed -system.cpu0.committedOps 126599996 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8092675 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 2098 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5466839701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.153342 # CPI: cycles per instruction -system.cpu0.ipc 0.464394 # IPC: instructions per cycle +system.cpu0.committedInsts 79519346 # Number of instructions committed +system.cpu0.committedOps 95696233 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5042389 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1874 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5527576937 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.070711 # CPI: cycles per instruction +system.cpu0.ipc 0.482926 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2103 # number of quiesce instructions executed -system.cpu0.tickCycles 187544415 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 37944147 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 678004 # number of replacements -system.cpu0.dcache.tags.tagsinuse 485.290770 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38699274 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 678516 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 57.035168 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1879 # number of quiesce instructions executed +system.cpu0.tickCycles 128007340 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 36654238 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 714687 # number of replacements +system.cpu0.dcache.tags.tagsinuse 500.798460 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 30351139 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715199 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.437334 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 346166500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.290770 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.947834 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.947834 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 500.798460 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.978122 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.978122 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 299 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 86 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 293 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 80249956 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 80249956 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 21509384 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21509384 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 16060534 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16060534 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 307394 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 307394 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 357644 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 357644 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 352742 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 352742 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 37569918 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 37569918 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 37877312 # number of overall hits -system.cpu0.dcache.overall_hits::total 37877312 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 441440 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 441440 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 555221 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 555221 # 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number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8885926805 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8885926805 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 320729731 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 320729731 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 481626159 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 481626159 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 602000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 602000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 14734448258 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14734448258 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 14734448258 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14734448258 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 21950824 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 21950824 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16615755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16615755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 439317 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 439317 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378488 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378488 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 374059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 374059 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38566579 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38566579 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39005896 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39005896 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020110 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020110 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033415 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033415 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.300291 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.300291 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055072 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055072 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056988 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056988 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025843 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.025843 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028934 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028934 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13248.734716 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13248.734716 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 16004.306042 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 16004.306042 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15387.148868 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15387.148868 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22593.524370 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22593.524370 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63691793 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63691793 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 15776398 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15776398 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13416114 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13416114 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 321622 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 321622 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365571 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 365571 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361457 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361457 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 29192512 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 29192512 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 29514134 # number of overall hits +system.cpu0.dcache.overall_hits::total 29514134 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 464236 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 464236 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 577383 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 577383 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 136671 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 136671 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21082 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21082 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20299 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20299 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1041619 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1041619 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1178290 # number of overall misses +system.cpu0.dcache.overall_misses::total 1178290 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6143546304 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6143546304 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 9155597212 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 9155597212 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 318010226 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 318010226 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 454779772 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 454779772 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 214000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 15299143516 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 15299143516 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 15299143516 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 15299143516 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16240634 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16240634 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13993497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13993497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 458293 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 458293 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386653 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 386653 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381756 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15857.060585 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15084.442937 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15084.442937 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22404.048081 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22404.048081 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14783.811404 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14783.811404 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13055.694798 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13055.694798 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14687.849891 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14687.849891 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 12984.191936 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 12984.191936 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -665,149 +657,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4793451106 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4793451106 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1567109691 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1567109691 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 90045006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 90045006 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 448833841 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 448833841 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 579500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 579500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9002312820 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9002312820 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10569422511 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10569422511 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5627001499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5627001499 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4261635500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4261635500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9888636999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9888636999 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.016940 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.016940 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018780 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226570 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226570 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.015961 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.015961 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056988 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056988 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.017733 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.017733 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020085 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020085 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11318.495319 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11318.495319 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15361.311296 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15361.311296 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15744.149765 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15744.149765 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14905.645754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14905.645754 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21055.206689 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21055.206689 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 514395 # number of writebacks +system.cpu0.dcache.writebacks::total 514395 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 72393 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 72393 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 253509 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 253509 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14653 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14653 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 325902 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 325902 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 325902 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 325902 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 391843 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 391843 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323874 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323874 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 103461 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 103461 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6429 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6429 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20299 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20299 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 715717 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 715717 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 819178 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 819178 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20386 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20386 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19085 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39471 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39471 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4433666662 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4433666662 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4919386398 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4919386398 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1621821456 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1621821456 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96313514 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96313514 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 423613728 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 423613728 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 205000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 205000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9353053060 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9353053060 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10974874516 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10974874516 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4276413999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4276413999 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3259254500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3259254500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7535668499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7535668499 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024127 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024127 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023145 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023145 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.225753 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.225753 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016627 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016627 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053173 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053173 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023672 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023672 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026690 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026690 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11314.905873 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11314.905873 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 15189.198262 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 15189.198262 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15675.679299 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15675.679299 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14981.103438 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14981.103438 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 20868.699345 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20868.699345 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13163.123509 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13163.123509 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13491.042723 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13491.042723 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 191180.018992 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 191180.018992 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 162875.425186 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 162875.425186 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 177859.581262 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 177859.581262 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13068.088448 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13068.088448 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 13397.423412 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 13397.423412 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209772.098450 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209772.098450 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 170775.713911 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 170775.713911 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 190916.584302 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 190916.584302 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1884730 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.784347 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 66497574 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1885242 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 35.272699 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1966290 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.784569 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36747505 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1966802 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.683886 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6453364250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784347 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.784569 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999579 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999579 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 138650918 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 138650918 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 66497574 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 66497574 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 66497574 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 66497574 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 66497574 # number of overall hits -system.cpu0.icache.overall_hits::total 66497574 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1885257 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1885257 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1885257 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1885257 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1885257 # number of overall misses -system.cpu0.icache.overall_misses::total 1885257 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 17590953808 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 17590953808 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 17590953808 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 17590953808 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 17590953808 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 17590953808 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 68382831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 68382831 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 68382831 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 68382831 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 68382831 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 68382831 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.027569 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.027569 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.027569 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.027569 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.027569 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.027569 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9330.798829 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9330.798829 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9330.798829 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9330.798829 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9330.798829 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 79395451 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 79395451 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 36747505 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36747505 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36747505 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36747505 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36747505 # number of overall hits +system.cpu0.icache.overall_hits::total 36747505 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1966814 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1966814 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1966814 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1966814 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1966814 # number of overall misses +system.cpu0.icache.overall_misses::total 1966814 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18563219293 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18563219293 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18563219293 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18563219293 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18563219293 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18563219293 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 38714319 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 38714319 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 38714319 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 38714319 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 38714319 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 38714319 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050803 # 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Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 310 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 388 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 298 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 75 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4109 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7718 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 3035 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062866 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.928772 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 52971740 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 52971740 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77753 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4353 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1821437 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 376273 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2279816 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 490181 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 490181 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28296 # 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number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1821437 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 588585 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2492128 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 788 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 123 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 63820 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 101159 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 165890 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 28131 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 28131 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19518 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19518 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.200003 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.067462 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.498538 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.498538 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.915650 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.915650 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # 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mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.192590 # mshr miss rate for overall accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.482455 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.482455 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.908863 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.908863 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155802 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155802 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.075859 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009955 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.031300 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036140 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.184599 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162550 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22316.905255 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28750.735065 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60961.827767 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19582.360065 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19582.360065 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14803.678348 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14803.678348 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 466499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 466499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39187.808209 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39187.808209 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 30798.654503 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 27840.736041 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16065.040650 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 38954.865391 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27143.872318 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60961.827767 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46820.715114 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163321 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23409.502965 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30021.261718 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 58911.725424 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20151.626074 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20151.626074 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14704.905686 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14704.905686 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 38572.902454 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 38572.902454 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31690.708072 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28489.024390 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 16116.788321 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 39399.870371 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27869.683975 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 58911.725424 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46268.247984 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183171.261849 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 172970.251524 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 155364.532773 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 155364.532773 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201758.155106 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 185037.100577 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 163260.964108 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 163260.964108 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 83797.000297 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 170085.124465 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 165157.928432 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 183144.010793 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 175335.490686 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2622296 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2539595 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 26165 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 490181 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 288086 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 93335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43761 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114801 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284088 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 269989 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3777247 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2323391 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11902 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166252 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6278792 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 120871872 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82524675 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17904 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 314164 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 203728615 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 661406 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3889209 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.165588 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.371711 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 2715743 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2641226 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19085 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 514393 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 305303 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 89358 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43016 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112820 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 297586 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284185 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3940361 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2387083 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11736 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 174847 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6514027 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 126091520 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86470884 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17508 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 329468 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 212909380 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 677925 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4032687 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.164340 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.370584 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 3245202 83.44% 83.44% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 644007 16.56% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3369954 83.57% 83.57% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 662733 16.43% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3889209 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2173439238 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4032687 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2258839735 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113551498 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115861999 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2837827806 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2960687293 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1188833142 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1231161241 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7429994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7364989 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 87720745 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 92493743 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 5430284 # Number of BP lookups -system.cpu1.branchPred.condPredicted 3355584 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 331008 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 3397877 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 2268406 # Number of BTB hits +system.cpu1.branchPred.lookups 18540788 # Number of BP lookups +system.cpu1.branchPred.condPredicted 6039472 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 931744 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9588411 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 6940637 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 66.759509 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 972543 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 68492 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 72.385685 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8266914 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 716215 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1275,60 +1256,61 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 30040 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 30040 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 22353 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7687 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 30040 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 30040 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 30040 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9799.871947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 8761.915074 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6575.386381 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 913 33.79% 33.79% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1652 61.14% 94.93% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 67 2.48% 97.41% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.07% 99.48% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 2 0.07% 99.56% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.19% 99.74% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 6 0.22% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::114688-122879 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 1622459264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 1622459264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 1622459264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2019 74.72% 74.72% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 683 25.28% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2702 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30040 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walks 26399 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 26399 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19296 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7103 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 26399 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 26399 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 26399 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2728 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 9779.693548 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8843.591627 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 5628.626467 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 924 33.87% 33.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1671 61.25% 95.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 66 2.42% 97.54% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 58 2.13% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 1 0.04% 99.71% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 5 0.18% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2728 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 1622643264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 1622643264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 1622643264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 2007 73.57% 73.57% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 721 26.43% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2728 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26399 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30040 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2702 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26399 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2728 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2702 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 32742 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2728 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 29127 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 5155380 # DTB read hits -system.cpu1.dtb.read_misses 27847 # DTB read misses -system.cpu1.dtb.write_hits 4232538 # DTB write hits -system.cpu1.dtb.write_misses 2193 # DTB write misses +system.cpu1.dtb.read_hits 10801915 # DTB read hits +system.cpu1.dtb.read_misses 24746 # DTB read misses +system.cpu1.dtb.write_hits 6805241 # DTB write hits +system.cpu1.dtb.write_misses 1653 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2049 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 312 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 511 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 156 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 413 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 285 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 5183227 # DTB read accesses -system.cpu1.dtb.write_accesses 4234731 # DTB write accesses +system.cpu1.dtb.perms_faults 271 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10826661 # DTB read accesses +system.cpu1.dtb.write_accesses 6806894 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 9387918 # DTB hits -system.cpu1.dtb.misses 30040 # DTB misses -system.cpu1.dtb.accesses 9417958 # DTB accesses +system.cpu1.dtb.hits 17607156 # DTB hits +system.cpu1.dtb.misses 26399 # DTB misses +system.cpu1.dtb.accesses 17633555 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1358,40 +1340,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 2268 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2268 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 178 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2090 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2268 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2268 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2268 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9869.507623 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8954.185655 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5421.941384 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 302 27.09% 27.09% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 778 69.78% 96.86% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 3 0.27% 97.13% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 27 2.42% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 1 0.09% 99.64% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.27% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::90112-98303 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1115 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 1621868264 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 1621868264 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 1621868264 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 950 85.20% 85.20% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.80% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1115 # Table walker page sizes translated +system.cpu1.itb.walker.walks 2259 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2259 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 181 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2078 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2259 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2259 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2259 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 9888.739946 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9049.592552 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4688.260195 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-4095 127 11.35% 11.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 167 14.92% 26.27% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 537 47.99% 74.26% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 253 22.61% 96.87% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 2 0.18% 97.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.27% 97.32% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 16 1.43% 98.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 11 0.98% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 2 0.18% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::45056-49151 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1119 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 1622052264 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 1622052264 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 1622052264 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 951 84.99% 84.99% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 168 15.01% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1119 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2268 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2268 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2259 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2259 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1115 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1115 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3383 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 10199097 # ITB inst hits -system.cpu1.itb.inst_misses 2268 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1119 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3378 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 39782626 # ITB inst hits +system.cpu1.itb.inst_misses 2259 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1400,130 +1385,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1153 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1157 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1907 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1864 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 10201365 # ITB inst accesses -system.cpu1.itb.hits 10199097 # DTB hits -system.cpu1.itb.misses 2268 # DTB misses -system.cpu1.itb.accesses 10201365 # DTB accesses -system.cpu1.numCycles 54377537 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 39784885 # ITB inst accesses +system.cpu1.itb.hits 39782626 # DTB hits +system.cpu1.itb.misses 2259 # DTB misses +system.cpu1.itb.accesses 39784885 # DTB accesses +system.cpu1.numCycles 114626006 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 20871299 # Number of instructions committed -system.cpu1.committedOps 25485301 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1815368 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2715 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5637293692 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.605374 # CPI: cycles per instruction -system.cpu1.ipc 0.383822 # IPC: instructions per cycle +system.cpu1.committedInsts 45881817 # Number of instructions committed +system.cpu1.committedOps 56143289 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4843481 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2780 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5576973220 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.498288 # CPI: cycles per instruction +system.cpu1.ipc 0.400274 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2716 # number of quiesce instructions executed -system.cpu1.tickCycles 38719894 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 15657643 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 231595 # number of replacements -system.cpu1.dcache.tags.tagsinuse 482.666397 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 8898721 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 231963 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.362674 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 90493998000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 482.666397 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.942708 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.942708 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 368 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 315 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.718750 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 18845353 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 18845353 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 4715534 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 4715534 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3905905 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3905905 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65439 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65439 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88128 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88128 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80091 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80091 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 8621439 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 8621439 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 8686878 # number of overall hits -system.cpu1.dcache.overall_hits::total 8686878 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 182965 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 182965 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 168408 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 168408 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35586 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35586 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17713 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17713 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23494 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23494 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 351373 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 351373 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 386959 # 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number of replacements +system.cpu1.dcache.tags.tagsinuse 472.569028 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 17169326 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 194582 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 88.236970 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 90524286500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.569028 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922986 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922986 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 371 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 49 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.724609 # 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average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19543.097301 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19543.097301 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 17745.850925 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 17745.850925 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20416.882844 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20416.882844 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18526.611325 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18526.611325 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1532,148 +1517,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 138038 # number of writebacks -system.cpu1.dcache.writebacks::total 138038 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 18091 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 18091 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 62532 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 62532 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12272 # 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number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 513974285 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 513974285 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 347500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 347500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4644512345 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4644512345 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5177648347 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5177648347 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 978236749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 978236749 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 848797501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 848797501 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1827034250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1827034250 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033658 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033658 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025986 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025986 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.337897 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.337897 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051407 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051407 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226809 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226809 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030174 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.030174 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033601 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.033601 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13112.352791 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13112.352791 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23448.432988 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23448.432988 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15617.998652 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15617.998652 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16484.470869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16484.470869 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21876.831744 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21876.831744 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 117850 # number of writebacks +system.cpu1.dcache.writebacks::total 117850 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15942 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15942 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 52278 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 52278 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12035 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 68220 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 68220 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 68220 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 68220 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 141249 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 141249 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 92589 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 92589 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 29909 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4886 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4886 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23675 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23675 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 233838 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 233838 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 263747 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 263747 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14605 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14605 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11936 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11936 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26541 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1867063577 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1867063577 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2294961861 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2294961861 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 485499507 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 485499507 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 80204246 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 80204246 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 520729829 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 520729829 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 512500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 512500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4162025438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4162025438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4647524945 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4647524945 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2322107500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2322107500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1843997501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 1843997501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 4166105001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 4166105001 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013359 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013359 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013908 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013908 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.369808 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.369808 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050374 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050374 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248684 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248684 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013571 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.013571 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015236 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015236 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13218.242798 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13218.242798 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24786.549817 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24786.549817 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16232.555652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16232.555652 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16415.113795 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16415.113795 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21994.924139 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21994.924139 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17154.246888 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17154.246888 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16982.243681 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16982.243681 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 171140.089048 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 171140.089048 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169420.658882 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 169420.658882 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 170336.961589 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 170336.961589 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17798.755711 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17798.755711 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17621.148089 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17621.148089 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 158994.008901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 158994.008901 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 154490.407255 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 154490.407255 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 156968.652312 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 156968.652312 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 1038832 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.324542 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 9157675 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 1039344 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 8.811014 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 72123856500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324542 # Average occupied blocks per requestor +system.cpu1.icache.tags.replacements 947892 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.324313 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 38832195 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 948404 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 40.944782 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72125006000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.324313 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975243 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975243 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 459 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 53 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 461 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 21433382 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 21433382 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 9157675 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 9157675 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 9157675 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 9157675 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 9157675 # number of overall hits -system.cpu1.icache.overall_hits::total 9157675 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 1039344 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 1039344 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 1039344 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 1039344 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 1039344 # number of overall misses -system.cpu1.icache.overall_misses::total 1039344 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9221968883 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9221968883 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9221968883 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9221968883 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9221968883 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9221968883 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 10197019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 10197019 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 10197019 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 10197019 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 10197019 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 10197019 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.101926 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.101926 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.101926 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.101926 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.101926 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.101926 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8872.874508 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8872.874508 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8872.874508 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8872.874508 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8872.874508 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 80509602 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 80509602 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 38832195 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 38832195 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 38832195 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 38832195 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 38832195 # number of overall hits +system.cpu1.icache.overall_hits::total 38832195 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 948404 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 948404 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 948404 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 948404 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 948404 # number of overall misses +system.cpu1.icache.overall_misses::total 948404 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8190397665 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8190397665 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8190397665 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8190397665 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8190397665 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8190397665 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 39780599 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 39780599 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 39780599 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 39780599 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 39780599 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 39780599 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023841 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.023841 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023841 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.023841 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023841 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.023841 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8635.979672 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8635.979672 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8635.979672 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8635.979672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8635.979672 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8635.979672 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1682,415 +1667,415 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5626.461246 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2273.619533 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1588.024777 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.373262 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003670 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000059 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.343412 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.138771 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.096925 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.956100 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1163 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 63 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13723 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 7883.130354 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 45.774786 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.102173 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4372.978904 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2161.890501 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 852.654278 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.481148 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002794 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.266905 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.131951 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.052042 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.934847 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1060 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13867 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 666 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 493 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 654 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 402 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 31 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 6148 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 7266 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.070984 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003845 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.837585 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 25009138 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 25009138 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 33079 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2665 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 1011889 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 130945 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1178578 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 138038 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 138038 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1986 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1986 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1041 # 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mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.127580 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16899.951851 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 21182.658462 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36122.588756 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16664.330725 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16664.330725 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15034.151160 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15034.151160 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.123653 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 15579.630342 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18504.949162 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39082.755092 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15953.535887 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15953.535887 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15090.519338 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15090.519338 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32245.566240 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32245.566240 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24065.183685 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 18518.407932 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13924.657534 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32766.114878 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21936.337984 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36122.588756 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26525.578216 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 163134.141008 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161609.943377 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161902.894012 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161902.894012 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83821.428571 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 162559.038691 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161745.363443 # average overall mshr uncacheable latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32217.510128 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32217.510128 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 22235.051616 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16634.932917 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13707.584821 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 28502.372110 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21041.845550 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39082.755092 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 24846.672490 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150993.426909 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 150480.583679 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 146980.311578 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 146980.311578 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 83604.910714 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 149188.651483 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 148913.058530 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1679463 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1332654 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 5010 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 138038 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 44141 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76606 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42998 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 97798 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 80302 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2078912 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 908693 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7242 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 71512 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3066359 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 66525184 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29710243 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11536 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 135140 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 96382103 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 669363 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2146516 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.290923 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.454188 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 1570481 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1215284 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11936 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 117850 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 29116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 76106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42118 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86519 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 85085 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 67041 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1897032 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 831140 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7228 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62942 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2798342 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 60705024 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25653404 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117760 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 86487752 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 646083 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1988037 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.303225 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.459652 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1522045 70.91% 70.91% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 624471 29.09% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1385215 69.68% 69.68% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 602822 30.32% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2146516 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 922622470 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1988037 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 835355978 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 87676498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80571000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1560397383 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1423456915 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 459276108 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 410007475 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4359499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4338499 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37739490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 33513487 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30987 # Transaction distribution -system.iobus.trans_dist::ReadResp 30987 # Transaction distribution +system.iobus.trans_dist::ReadReq 31003 # Transaction distribution +system.iobus.trans_dist::ReadResp 31003 # Transaction distribution system.iobus.trans_dist::WriteReq 59422 # Transaction distribution system.iobus.trans_dist::WriteResp 23198 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution @@ -2099,7 +2084,7 @@ system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2115,16 +2100,16 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107912 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72906 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72906 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180818 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180850 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2140,10 +2125,10 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162794 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321064 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483858 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483972 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 40091000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) @@ -2154,7 +2139,7 @@ system.iobus.reqLayer3.occupancy 12000 # La system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 504000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) @@ -2184,52 +2169,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198858516 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198954212 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84714000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36733518 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36786767 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36403 # number of replacements -system.iocache.tags.tagsinuse 1.010559 # Cycle average of tags in use +system.iocache.tags.replacements 36433 # number of replacements +system.iocache.tags.tagsinuse 14.479130 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36419 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36449 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270375766000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.010559 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.063160 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.063160 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270363169000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.479130 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904946 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904946 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328077 # Number of tag accesses -system.iocache.tags.data_accesses 328077 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 229 # number of ReadReq misses -system.iocache.ReadReq_misses::total 229 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 229 # number of demand (read+write) misses -system.iocache.demand_misses::total 229 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 229 # number of overall misses -system.iocache.overall_misses::total 229 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29476377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29476377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6677842621 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6677842621 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29476377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29476377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29476377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29476377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 229 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 229 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses +system.iocache.demand_misses::total 243 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 243 # number of overall misses +system.iocache.overall_misses::total 243 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 31382127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31382127 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6655722318 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6655722318 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31382127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31382127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31382127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31382127 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 229 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 229 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 229 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 229 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -2238,40 +2223,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128717.803493 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128717.803493 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 184348.570589 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 184348.570589 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128717.803493 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128717.803493 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128717.803493 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 23020 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129144.555556 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129144.555556 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183737.917348 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183737.917348 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129144.555556 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129144.555556 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129144.555556 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22459 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3484 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3430 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.607348 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.547813 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.writebacks::writebacks 36174 # number of writebacks -system.iocache.writebacks::total 36174 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 229 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 229 # number of ReadReq MSHR misses +system.iocache.writebacks::writebacks 36190 # number of writebacks +system.iocache.writebacks::total 36190 # number of writebacks +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 229 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 229 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 229 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 229 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17561377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17561377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4794158657 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4794158657 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17561377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17561377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17561377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17561377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18687627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18687627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4772040352 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4772040352 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18687627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18687627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18687627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18687627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -2280,593 +2265,568 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76687.235808 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76687.235808 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 132347.577766 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 132347.577766 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76687.235808 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76687.235808 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76903.814815 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76903.814815 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131736.979682 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131736.979682 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76903.814815 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76903.814815 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 136197 # number of replacements -system.l2c.tags.tagsinuse 64163.282922 # Cycle average of tags in use -system.l2c.tags.total_refs 379817 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 200471 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.894623 # Average number of references to valid blocks. +system.l2c.tags.replacements 136145 # number of replacements +system.l2c.tags.tagsinuse 64036.316369 # Cycle average of tags in use +system.l2c.tags.total_refs 380367 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200629 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 1.895872 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12850.317421 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 69.201711 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.031095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 6628.601764 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1957.826461 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32727.538139 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 28.180445 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.851989 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 4115.294958 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1518.513926 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4266.925013 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.196080 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001056 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 12112.427093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 74.878570 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.028766 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8551.494132 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2840.139732 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 35681.498153 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 16.446887 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2203.793190 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 582.329943 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1973.279904 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.184821 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001143 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.101144 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.029874 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.499383 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000430 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.062794 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.023171 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.065108 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.979054 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 30066 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 78 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34130 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 141 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5589 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24336 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 78 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 12 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 298 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3041 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 30776 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.458771 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.001190 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.520782 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5295828 # Number of tag accesses -system.l2c.tags.data_accesses 5295828 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 375 # 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average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68960.332013 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 74999.046028 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71846.153846 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 73717.391304 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67786.821886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 78257.137128 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91740.464995 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 73037.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 70500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70300.124184 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71250.700931 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 110423.013938 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 87000.263060 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 67999.096952 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 77842.141767 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 91309.167392 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 74659.090909 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 70315.424670 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 69883.361936 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 117470.195465 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 86591.909652 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 163641.771141 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143630.996148 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151419.130592 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 136846.302312 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 143297.904391 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 137883.111500 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182216.999411 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 131493.425108 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 151981.243176 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 144734.739324 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 128440.725620 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138465.265498 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60798.336798 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 151031.543401 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60857.142857 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 143475.354505 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 145373.407943 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 164093.594031 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 60636.160714 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 130120.360289 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 145947.321096 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 215059 # Transaction distribution -system.membus.trans_dist::ReadResp 215059 # Transaction distribution -system.membus.trans_dist::WriteReq 31175 # Transaction distribution -system.membus.trans_dist::WriteResp 31175 # Transaction distribution -system.membus.trans_dist::Writeback 138467 # Transaction distribution +system.membus.trans_dist::ReadReq 215398 # Transaction distribution +system.membus.trans_dist::ReadResp 215398 # Transaction distribution +system.membus.trans_dist::WriteReq 31021 # Transaction distribution +system.membus.trans_dist::WriteResp 31021 # Transaction distribution +system.membus.trans_dist::Writeback 138346 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78265 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41611 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15010 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 39963 # Transaction distribution -system.membus.trans_dist::ReadExResp 19392 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeReq 76455 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40833 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14266 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.membus.trans_dist::ReadExReq 39995 # Transaction distribution +system.membus.trans_dist::ReadExResp 19465 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14788 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 665413 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 788151 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108866 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 897017 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 663047 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 785159 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108896 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 894055 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29576 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19282584 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19476170 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4634432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 24110602 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 126068 # Total snoops (count) -system.membus.snoop_fanout::samples 580884 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28316 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19310684 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19503012 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 24138468 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124155 # Total snoops (count) +system.membus.snoop_fanout::samples 578323 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 580884 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 578323 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 580884 # Request fanout histogram -system.membus.reqLayer0.occupancy 88642500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 578323 # Request fanout histogram +system.membus.reqLayer0.occupancy 88747000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 13073499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12490999 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1170162100 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1169123868 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1173257543 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1173969642 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37390482 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 37485233 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2899,44 +2859,44 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 519203 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 519188 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31175 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31175 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 233506 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36278 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 82002 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 41949 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 123951 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51897 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51897 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1081118 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 347519 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1428637 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 32891255 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6822675 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 39713930 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 293844 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 996034 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.036652 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.187907 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 516846 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 516831 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31021 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31021 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 232833 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 79939 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41160 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 121099 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 16 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51726 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51726 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1083746 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 338123 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1421869 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34155096 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5564428 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39719524 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 288847 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 989795 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.036873 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.188451 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 959527 96.33% 96.33% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36507 3.67% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 953298 96.31% 96.31% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36497 3.69% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 996034 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 791138952 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 989795 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 786931704 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 321000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342000 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 673122022 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 682239026 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 273051412 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 258695257 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |