diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2017-02-19 05:30:32 -0500 |
commit | f2e2410a505ef48516f121ce1b2232ba7aa389af (patch) | |
tree | dbe4c8482b37e854302410318fc474f507310724 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | |
parent | 184c6d7ebd7faa0869f294526a54a239a216b7c8 (diff) | |
download | gem5-f2e2410a505ef48516f121ce1b2232ba7aa389af.tar.xz |
stats: Get all stats updated to reflect current behaviour
Line everything up again.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 5082 |
1 files changed, 2534 insertions, 2548 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 37e31e615..b789abbb5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,163 +1,163 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848913 # Number of seconds simulated -sim_ticks 2848912955000 # Number of ticks simulated -final_tick 2848912955000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848599 # Number of seconds simulated +sim_ticks 2848598682500 # Number of ticks simulated +final_tick 2848598682500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 258856 # Simulator instruction rate (inst/s) -host_op_rate 313468 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5762698171 # Simulator tick rate (ticks/s) -host_mem_usage 627144 # Number of bytes of host memory used -host_seconds 494.37 # Real time elapsed on the host -sim_insts 127970828 # Number of instructions simulated -sim_ops 154969713 # Number of ops (including micro ops) simulated +host_inst_rate 262669 # Simulator instruction rate (inst/s) +host_op_rate 318064 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5881753499 # Simulator tick rate (ticks/s) +host_mem_usage 626168 # Number of bytes of host memory used +host_seconds 484.31 # Real time elapsed on the host +sim_insts 127213455 # Number of instructions simulated +sim_ops 154041729 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 9408 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 9280 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1675840 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1349948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8501504 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 229824 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 661012 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 405952 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1663936 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1359352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8597824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 234560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 659412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 325376 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12835728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1675840 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 229824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1905664 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 9061888 # Number of bytes written to this memory +system.physmem.bytes_read::total 12852044 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1663936 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 234560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1898496 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8978368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9079452 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 147 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8995932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 145 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26185 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21618 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 132836 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3591 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10349 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 6343 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 25999 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21764 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3665 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5084 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 201104 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 141592 # Number of write requests responded to by this memory +system.physmem.num_reads::total 201358 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140287 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 145983 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3302 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144678 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3258 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 588238 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 473847 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2984122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 427 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 80671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 232023 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 142494 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 584124 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 477200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3018264 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 449 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 82342 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 231486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 114223 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4505483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 588238 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 80671 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 668909 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3180823 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4511707 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 584124 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 82342 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 666467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3151854 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6152 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3186988 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3180823 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3158020 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3151854 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3258 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 588238 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 479998 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2984122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 80671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 232037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 142494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 584124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 483352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3018264 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 449 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 82342 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 231500 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 114223 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7692471 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 201104 # Number of read requests accepted -system.physmem.writeReqs 145983 # Number of write requests accepted -system.physmem.readBursts 201104 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 145983 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12861056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue -system.physmem.bytesWritten 9091968 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12835728 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9079452 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one +system.physmem.bw_total::total 7669728 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 201358 # Number of read requests accepted +system.physmem.writeReqs 144678 # Number of write requests accepted +system.physmem.readBursts 201358 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144678 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12877760 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9152 # Total number of bytes read from write queue +system.physmem.bytesWritten 9008896 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12852044 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8995932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 143 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12429 # Per bank write bursts -system.physmem.perBankRdBursts::1 12794 # Per bank write bursts -system.physmem.perBankRdBursts::2 13696 # Per bank write bursts -system.physmem.perBankRdBursts::3 13190 # Per bank write bursts -system.physmem.perBankRdBursts::4 15337 # Per bank write bursts -system.physmem.perBankRdBursts::5 12894 # Per bank write bursts -system.physmem.perBankRdBursts::6 12741 # Per bank write bursts -system.physmem.perBankRdBursts::7 13088 # Per bank write bursts -system.physmem.perBankRdBursts::8 12333 # Per bank write bursts -system.physmem.perBankRdBursts::9 12486 # Per bank write bursts -system.physmem.perBankRdBursts::10 11357 # Per bank write bursts -system.physmem.perBankRdBursts::11 10671 # Per bank write bursts -system.physmem.perBankRdBursts::12 11888 # Per bank write bursts -system.physmem.perBankRdBursts::13 12773 # Per bank write bursts -system.physmem.perBankRdBursts::14 11762 # Per bank write bursts -system.physmem.perBankRdBursts::15 11515 # Per bank write bursts -system.physmem.perBankWrBursts::0 8987 # Per bank write bursts -system.physmem.perBankWrBursts::1 9459 # Per bank write bursts -system.physmem.perBankWrBursts::2 10102 # Per bank write bursts -system.physmem.perBankWrBursts::3 9553 # Per bank write bursts -system.physmem.perBankWrBursts::4 8641 # Per bank write bursts -system.physmem.perBankWrBursts::5 9022 # Per bank write bursts -system.physmem.perBankWrBursts::6 9160 # Per bank write bursts -system.physmem.perBankWrBursts::7 9289 # Per bank write bursts -system.physmem.perBankWrBursts::8 8726 # Per bank write bursts -system.physmem.perBankWrBursts::9 8906 # Per bank write bursts -system.physmem.perBankWrBursts::10 8219 # Per bank write bursts -system.physmem.perBankWrBursts::11 7897 # Per bank write bursts -system.physmem.perBankWrBursts::12 8731 # Per bank write bursts -system.physmem.perBankWrBursts::13 8920 # Per bank write bursts -system.physmem.perBankWrBursts::14 8491 # Per bank write bursts -system.physmem.perBankWrBursts::15 7959 # Per bank write bursts +system.physmem.perBankRdBursts::0 12337 # Per bank write bursts +system.physmem.perBankRdBursts::1 12726 # Per bank write bursts +system.physmem.perBankRdBursts::2 13547 # Per bank write bursts +system.physmem.perBankRdBursts::3 13037 # Per bank write bursts +system.physmem.perBankRdBursts::4 15119 # Per bank write bursts +system.physmem.perBankRdBursts::5 12845 # Per bank write bursts +system.physmem.perBankRdBursts::6 12657 # Per bank write bursts +system.physmem.perBankRdBursts::7 13022 # Per bank write bursts +system.physmem.perBankRdBursts::8 12280 # Per bank write bursts +system.physmem.perBankRdBursts::9 12341 # Per bank write bursts +system.physmem.perBankRdBursts::10 11583 # Per bank write bursts +system.physmem.perBankRdBursts::11 10739 # Per bank write bursts +system.physmem.perBankRdBursts::12 12026 # Per bank write bursts +system.physmem.perBankRdBursts::13 12946 # Per bank write bursts +system.physmem.perBankRdBursts::14 12179 # Per bank write bursts +system.physmem.perBankRdBursts::15 11831 # Per bank write bursts +system.physmem.perBankWrBursts::0 8873 # Per bank write bursts +system.physmem.perBankWrBursts::1 9291 # Per bank write bursts +system.physmem.perBankWrBursts::2 9856 # Per bank write bursts +system.physmem.perBankWrBursts::3 9274 # Per bank write bursts +system.physmem.perBankWrBursts::4 8405 # Per bank write bursts +system.physmem.perBankWrBursts::5 8988 # Per bank write bursts +system.physmem.perBankWrBursts::6 8961 # Per bank write bursts +system.physmem.perBankWrBursts::7 9107 # Per bank write bursts +system.physmem.perBankWrBursts::8 8695 # Per bank write bursts +system.physmem.perBankWrBursts::9 8769 # Per bank write bursts +system.physmem.perBankWrBursts::10 8272 # Per bank write bursts +system.physmem.perBankWrBursts::11 7845 # Per bank write bursts +system.physmem.perBankWrBursts::12 8751 # Per bank write bursts +system.physmem.perBankWrBursts::13 8985 # Per bank write bursts +system.physmem.perBankWrBursts::14 8630 # Per bank write bursts +system.physmem.perBankWrBursts::15 8062 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 98 # Number of times write queue was full causing retry -system.physmem.totGap 2848912399000 # Total gap between requests +system.physmem.numWrRetry 74 # Number of times write queue was full causing retry +system.physmem.totGap 2848598144000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 556 # Read request sizes (log2) +system.physmem.readPktSize::2 555 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 200520 # Read request sizes (log2) +system.physmem.readPktSize::6 200775 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 141592 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 84624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 63240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11856 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9787 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6722 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5707 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4943 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4044 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 272 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 240 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140287 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 85113 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 63389 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9690 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4878 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4009 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1035 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 239 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 134 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -185,178 +185,178 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2671 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3539 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4499 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6466 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7579 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8612 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9031 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8601 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 10035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8447 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 593 # 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Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3758 4.19% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2958 3.30% 86.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1568 1.75% 88.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1004 1.12% 89.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1009 1.13% 90.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8203 9.15% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 89688 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7073 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.410010 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 554.388606 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7071 99.97% 99.97% # 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What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 216 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 88566 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 247.121830 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 141.476955 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 302.598654 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 44693 50.46% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18724 21.14% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6637 7.49% 79.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3795 4.28% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2919 3.30% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1572 1.77% 88.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 960 1.08% 89.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1024 1.16% 90.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8242 9.31% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 88566 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.806586 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 558.021687 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6983 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7073 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7073 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.085112 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.515707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.383837 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5944 84.04% 84.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 432 6.11% 90.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 82 1.16% 91.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 52 0.74% 92.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 255 3.61% 95.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.35% 96.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 15 0.21% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 7 0.10% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.18% 96.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 9 0.13% 96.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 7 0.10% 96.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 148 2.09% 98.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 11 0.16% 99.02% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 6 0.08% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 3 0.04% 99.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 9 0.13% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.04% 99.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 6 0.08% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.08% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 3 0.04% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 4 0.06% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 4 0.06% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 4 0.06% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7073 # Writes before turning the bus around for reads -system.physmem.totQLat 9366475580 # Total ticks spent queuing -system.physmem.totMemAccLat 13134363080 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1004770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 46610.05 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6985 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6985 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.152326 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.495944 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.110349 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5869 84.02% 84.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 441 6.31% 90.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 79 1.13% 91.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 0.63% 92.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 241 3.45% 95.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 25 0.36% 95.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 96.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 10 0.14% 96.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 17 0.24% 96.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 8 0.11% 96.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 3 0.04% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 7 0.10% 96.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 146 2.09% 98.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 98.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 98.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.09% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 7 0.10% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 11 0.16% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 2 0.03% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.14% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.04% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-243 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6985 # Writes before turning the bus around for reads +system.physmem.totQLat 9483410947 # Total ticks spent queuing +system.physmem.totMemAccLat 13256192197 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1006075000 # Total ticks spent in databus transfers +system.physmem.avgQLat 47130.74 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 65360.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.51 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgMemAccLat 65880.74 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.52 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.51 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.19 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.16 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.05 # Average read queue length when enqueuing -system.physmem.avgWrQLen 22.20 # Average write queue length when enqueuing -system.physmem.readRowHits 166422 # Number of row buffer hits during reads -system.physmem.writeRowHits 86905 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 61.16 # Row buffer hit rate for writes -system.physmem.avgGap 8208064.26 # Average gap between requests -system.physmem.pageHitRate 73.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 341813220 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181678035 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 758046660 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 387391860 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 5805889440.000001 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 5444775090 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 308095680 # Energy for precharge background per rank (pJ) -system.physmem_0.actPowerDownEnergy 11642068740 # Energy for active power-down per rank (pJ) -system.physmem_0.prePowerDownEnergy 8562690720 # Energy for precharge power-down per rank (pJ) -system.physmem_0.selfRefreshEnergy 670190772435 # Energy for self refresh per rank (pJ) -system.physmem_0.totalEnergy 703626055650 # Total energy per rank (pJ) -system.physmem_0.averagePower 246.980538 # Core power per rank (mW) -system.physmem_0.totalIdleTime 2836051939093 # Total Idle time Per DRAM Rank -system.physmem_0.memoryStateTime::IDLE 546109733 # Time in different power states -system.physmem_0.memoryStateTime::REF 2466940000 # Time in different power states -system.physmem_0.memoryStateTime::SREF 2788334468750 # Time in different power states -system.physmem_0.memoryStateTime::PRE_PDN 22298648785 # Time in different power states -system.physmem_0.memoryStateTime::ACT 9735828674 # Time in different power states -system.physmem_0.memoryStateTime::ACT_PDN 25530959058 # Time in different power states -system.physmem_1.actEnergy 298566240 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 158687925 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 676764900 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 354171780 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 5707547040.000001 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 5348415450 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 325299360 # Energy for precharge background per rank (pJ) -system.physmem_1.actPowerDownEnergy 10595992200 # Energy for active power-down per rank (pJ) -system.physmem_1.prePowerDownEnergy 8817735360 # Energy for precharge power-down per rank (pJ) -system.physmem_1.selfRefreshEnergy 670663868775 # Energy for self refresh per rank (pJ) -system.physmem_1.totalEnergy 702949735620 # Total energy per rank (pJ) -system.physmem_1.averagePower 246.743143 # Core power per rank (mW) -system.physmem_1.totalIdleTime 2836330915238 # Total Idle time Per DRAM Rank -system.physmem_1.memoryStateTime::IDLE 596946927 # Time in different power states -system.physmem_1.memoryStateTime::REF 2425844000 # Time in different power states -system.physmem_1.memoryStateTime::SREF 2790131179750 # Time in different power states -system.physmem_1.memoryStateTime::PRE_PDN 22962884806 # Time in different power states -system.physmem_1.memoryStateTime::ACT 9559167335 # Time in different power states -system.physmem_1.memoryStateTime::ACT_PDN 23236932182 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.98 # Average write queue length when enqueuing +system.physmem.readRowHits 166670 # Number of row buffer hits during reads +system.physmem.writeRowHits 86742 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.83 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 61.61 # Row buffer hit rate for writes +system.physmem.avgGap 8232086.10 # Average gap between requests +system.physmem.pageHitRate 74.10 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 334044900 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 177549075 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 751770600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 379781100 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 5711234880.000001 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 5249821980 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 307614240 # Energy for precharge background per rank (pJ) +system.physmem_0.actPowerDownEnergy 11585671230 # Energy for active power-down per rank (pJ) +system.physmem_0.prePowerDownEnergy 8434613280 # Energy for precharge power-down per rank (pJ) +system.physmem_0.selfRefreshEnergy 670304268120 # Energy for self refresh per rank (pJ) +system.physmem_0.totalEnergy 703238620035 # Total energy per rank (pJ) +system.physmem_0.averagePower 246.871777 # Core power per rank (mW) +system.physmem_0.totalIdleTime 2836104738853 # Total Idle time Per DRAM Rank +system.physmem_0.memoryStateTime::IDLE 545953693 # Time in different power states +system.physmem_0.memoryStateTime::REF 2426690000 # Time in different power states +system.physmem_0.memoryStateTime::SREF 2788907518000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 21965166332 # Time in different power states +system.physmem_0.memoryStateTime::ACT 9346009704 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 25407344771 # Time in different power states +system.physmem_1.actEnergy 298323480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 158558895 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 684904500 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 355006980 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 5713078800.000001 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 5198973990 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 317598720 # Energy for precharge background per rank (pJ) +system.physmem_1.actPowerDownEnergy 10947475860 # Energy for active power-down per rank (pJ) +system.physmem_1.prePowerDownEnergy 8696180160 # Energy for precharge power-down per rank (pJ) +system.physmem_1.selfRefreshEnergy 670560217290 # Energy for self refresh per rank (pJ) +system.physmem_1.totalEnergy 702932935245 # Total energy per rank (pJ) +system.physmem_1.averagePower 246.764467 # Core power per rank (mW) +system.physmem_1.totalIdleTime 2836364452001 # Total Idle time Per DRAM Rank +system.physmem_1.memoryStateTime::IDLE 573854684 # Time in different power states +system.physmem_1.memoryStateTime::REF 2428124000 # Time in different power states +system.physmem_1.memoryStateTime::SREF 2789710596750 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 22646269258 # Time in different power states +system.physmem_1.memoryStateTime::ACT 9232187315 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 24007650493 # Time in different power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 1344 # Number of bytes read from this memory @@ -375,30 +375,30 @@ system.realview.nvmem.bw_inst_read::total 472 # I system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 20830846 # Number of BP lookups -system.cpu0.branchPred.condPredicted 13649526 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1014386 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13197369 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 8753451 # Number of BTB hits +system.cpu0.branchPred.lookups 21387746 # Number of BP lookups +system.cpu0.branchPred.condPredicted 14055793 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1067110 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 13655999 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8982856 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 66.327243 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3414506 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 211257 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 762629 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 580306 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 182323 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 100148 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.779560 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3510572 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 218030 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 788067 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 592988 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 195079 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 105213 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -428,61 +428,58 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 66699 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 66699 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 45954 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 20745 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 66699 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 66699 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 66699 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 6786 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12503.831418 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11414.396725 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6634.903581 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 6272 92.43% 92.43% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 416 6.13% 98.56% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 85 1.25% 99.81% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 5 0.07% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 5 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.03% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::212992-229375 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 6786 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 69629 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 69629 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 46094 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 23535 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 69629 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 69629 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 69629 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7649 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12135.050333 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10988.955041 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 11832.363963 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-65535 7639 99.87% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::65536-131071 6 0.08% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-262143 2 0.03% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::589824-655359 2 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7649 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 338892000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 338892000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 338892000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5256 77.45% 77.45% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1530 22.55% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6786 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 66699 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5959 77.91% 77.91% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1690 22.09% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7649 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 69629 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 66699 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6786 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 69629 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7649 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6786 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73485 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7649 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 77278 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 17337178 # DTB read hits -system.cpu0.dtb.read_misses 60105 # DTB read misses -system.cpu0.dtb.write_hits 14536732 # DTB write hits -system.cpu0.dtb.write_misses 6594 # DTB write misses +system.cpu0.dtb.read_hits 17966885 # DTB read hits +system.cpu0.dtb.read_misses 63028 # DTB read misses +system.cpu0.dtb.write_hits 15039551 # DTB write hits +system.cpu0.dtb.write_misses 6601 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3451 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1375 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1930 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3754 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1491 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2059 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 524 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 17397283 # DTB read accesses -system.cpu0.dtb.write_accesses 14543326 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 18029913 # DTB read accesses +system.cpu0.dtb.write_accesses 15046152 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 31873910 # DTB hits -system.cpu0.dtb.misses 66699 # DTB misses -system.cpu0.dtb.accesses 31940609 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 33006436 # DTB hits +system.cpu0.dtb.misses 69629 # DTB misses +system.cpu0.dtb.accesses 33076065 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -512,40 +509,40 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 4013 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4013 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 305 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3708 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4013 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4013 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4013 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2436 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12745.689655 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11895.862443 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5321.422543 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 433 17.78% 17.78% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1791 73.52% 91.30% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 138 5.67% 96.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 37 1.52% 98.48% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 36 1.48% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 4318 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4318 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 325 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3993 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4318 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4318 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4318 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2683 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12304.137160 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11560.884208 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4695.711947 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 502 18.71% 18.71% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1984 73.95% 92.66% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 147 5.48% 98.14% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 31 1.16% 99.29% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 18 0.67% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2436 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2683 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 338263500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 338263500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 338263500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2136 87.68% 87.68% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 300 12.32% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2436 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2363 88.07% 88.07% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 11.93% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2683 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4013 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4013 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4318 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4318 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2436 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2436 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6449 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 38740955 # ITB inst hits -system.cpu0.itb.inst_misses 4013 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2683 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 7001 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 39752533 # ITB inst hits +system.cpu0.itb.inst_misses 4318 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -554,798 +551,796 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2172 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2396 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7050 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7865 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 38744968 # ITB inst accesses -system.cpu0.itb.hits 38740955 # DTB hits -system.cpu0.itb.misses 4013 # DTB misses -system.cpu0.itb.accesses 38744968 # DTB accesses -system.cpu0.numPwrStateTransitions 3702 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1851 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1492467740.212318 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23926618307.518574 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1069 57.75% 57.75% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 775 41.87% 99.62% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 39756851 # ITB inst accesses +system.cpu0.itb.hits 39752533 # DTB hits +system.cpu0.itb.misses 4318 # DTB misses +system.cpu0.itb.accesses 39756851 # DTB accesses +system.cpu0.numPwrStateTransitions 3708 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1854 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1488611861.955232 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23946276211.601498 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1085 58.52% 58.52% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 762 41.10% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 1 0.05% 99.68% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1e+11-1.5e+11 1 0.05% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499963002708 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1851 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 86355167867 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2762557787133 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 172712897 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499963838164 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1854 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 88712290435 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2759886392065 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 177427128 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 79713377 # Number of instructions committed -system.cpu0.committedOps 95922535 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 5281292 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1851 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5525141996 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.166674 # CPI: cycles per instruction -system.cpu0.ipc 0.461537 # IPC: instructions per cycle -system.cpu0.op_class_0::No_OpClass 2273 0.00% 0.00% # Class of committed instruction -system.cpu0.op_class_0::IntAlu 63731011 66.44% 66.44% # Class of committed instruction -system.cpu0.op_class_0::IntMult 92142 0.10% 66.54% # Class of committed instruction -system.cpu0.op_class_0::IntDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMisc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMult 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdShift 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.54% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMisc 8073 0.01% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.55% # Class of committed instruction -system.cpu0.op_class_0::MemRead 16805807 17.52% 84.07% # Class of committed instruction -system.cpu0.op_class_0::MemWrite 15273589 15.92% 99.99% # Class of committed instruction -system.cpu0.op_class_0::FloatMemRead 2256 0.00% 99.99% # Class of committed instruction -system.cpu0.op_class_0::FloatMemWrite 7384 0.01% 100.00% # Class of committed instruction +system.cpu0.committedInsts 82154396 # Number of instructions committed +system.cpu0.committedOps 98918766 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5358225 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1854 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5519798084 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.159679 # CPI: cycles per instruction +system.cpu0.ipc 0.463032 # IPC: instructions per cycle +system.cpu0.op_class_0::No_OpClass 2315 0.00% 0.00% # Class of committed instruction +system.cpu0.op_class_0::IntAlu 65610842 66.33% 66.33% # Class of committed instruction +system.cpu0.op_class_0::IntMult 94061 0.10% 66.43% # Class of committed instruction +system.cpu0.op_class_0::IntDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatMisc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::FloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAddAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdAlu 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMisc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdShift 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdShiftAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAdd 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatAlu 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCmp 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatCvt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatDiv 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMisc 8175 0.01% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMult 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatMultAcc 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::SimdFloatSqrt 0 0.00% 66.43% # Class of committed instruction +system.cpu0.op_class_0::MemRead 17407324 17.60% 84.03% # Class of committed instruction +system.cpu0.op_class_0::MemWrite 15784753 15.96% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemRead 2708 0.00% 99.99% # Class of committed instruction +system.cpu0.op_class_0::FloatMemWrite 8588 0.01% 100.00% # Class of committed instruction system.cpu0.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.op_class_0::total 95922535 # Class of committed instruction +system.cpu0.op_class_0::total 98918766 # Class of committed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1851 # number of quiesce instructions executed -system.cpu0.tickCycles 120871852 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 51841045 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 716918 # number of replacements -system.cpu0.dcache.tags.tagsinuse 495.671066 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 30432435 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 717430 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 42.418682 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1854 # number of quiesce instructions executed +system.cpu0.tickCycles 124478065 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 52949063 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 756000 # number of replacements +system.cpu0.dcache.tags.tagsinuse 495.989536 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 31503611 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 756512 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 41.643240 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 356904000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.671066 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968108 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.968108 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 495.989536 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.968730 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.968730 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 43 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 113 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 44 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 63807329 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 63807329 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 15850504 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 15850504 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 13422208 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 13422208 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 320804 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 320804 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 365505 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 365505 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361161 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361161 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 29272712 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 29272712 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 29593516 # number of overall hits -system.cpu0.dcache.overall_hits::total 29593516 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 439135 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 439135 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 581157 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 581157 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 135756 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 135756 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20923 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 20923 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20396 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20396 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1020292 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1020292 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1156048 # number of overall misses -system.cpu0.dcache.overall_misses::total 1156048 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6443435000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6443435000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11283390500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 11283390500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 333090000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 333090000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 482408000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 482408000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 17726825500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 17726825500 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 17726825500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 17726825500 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 16289639 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 16289639 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 14003365 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 14003365 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456560 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456560 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 386428 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 386428 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381557 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 30293004 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 30293004 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 30749564 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 30749564 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026958 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.026958 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041501 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.041501 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.297345 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.297345 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054145 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.053455 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.053455 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033681 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.033681 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037596 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.037596 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14673.016271 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14673.016271 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19415.391194 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 19415.391194 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15919.801176 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15919.801176 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23652.088645 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23652.088645 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 66089687 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 66089687 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 16428136 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 16428136 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 13890443 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 13890443 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 328324 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 328324 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374119 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 374119 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370195 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370195 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 30318579 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 30318579 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 30646903 # number of overall hits +system.cpu0.dcache.overall_hits::total 30646903 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 460755 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 460755 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 603639 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 603639 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141924 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141924 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 21489 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20512 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20512 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1064394 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1064394 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1206318 # number of overall misses +system.cpu0.dcache.overall_misses::total 1206318 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6676359500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6676359500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11544866500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11544866500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 336675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 336675500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485473000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485473000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 539500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 539500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 18221226000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18221226000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 18221226000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18221226000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16888891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16888891 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 14494082 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 14494082 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 470248 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 395608 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 395608 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390707 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 390707 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 31382973 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 31382973 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 31853221 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 31853221 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.027282 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.027282 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041647 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041647 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301807 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301807 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052500 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052500 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.033916 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.033916 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.037871 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.037871 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14490.042430 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14490.042430 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 19125.448323 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 19125.448323 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15667.341430 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15667.341430 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23667.755460 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23667.755460 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17374.266877 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17374.266877 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15333.987430 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15333.987430 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17118.873274 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17118.873274 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15104.828080 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15104.828080 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 716918 # number of writebacks -system.cpu0.dcache.writebacks::total 716918 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 44597 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 44597 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 255598 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 255598 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14548 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 300195 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 300195 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 300195 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 300195 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 394538 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 394538 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325559 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 325559 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 102257 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 102257 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6375 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6375 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20396 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20396 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 720097 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 720097 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 822354 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 822354 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20581 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20581 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19270 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39851 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39851 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5273598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5273598500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6168960000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6168960000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1704833000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1704833000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102845500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 462030000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 462030000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 619500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 619500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11442558500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 11442558500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13147391500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13147391500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4607502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4607502500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4607502500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4607502500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024220 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023249 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.223973 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.223973 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016497 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016497 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.053455 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.053455 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023771 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023771 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026744 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026744 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13366.516026 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13366.516026 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18948.823408 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18948.823408 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16672.042012 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16672.042012 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16132.627451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16132.627451 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22652.971171 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22652.971171 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 756000 # number of writebacks +system.cpu0.dcache.writebacks::total 756000 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 45822 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 45822 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266133 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 266133 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14947 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14947 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 311955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 311955 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 311955 # 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number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 752439 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 752439 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 860738 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 860738 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20603 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20603 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19302 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19302 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39905 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5470255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5470255000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6299771000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6299771000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1751643500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1751643500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104376500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104376500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464977000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464977000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 523500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 523500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11770026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11770026000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13521669500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13521669500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4611679000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4611679000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4611679000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4611679000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024568 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023286 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230302 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016537 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016537 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052500 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052500 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023976 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023976 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.027022 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.027022 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13183.465764 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13183.465764 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18665.656314 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18665.656314 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16174.142882 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16174.142882 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15954.830327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15954.830327 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22668.535491 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22668.535491 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15890.301584 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15890.301584 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15987.508421 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15987.508421 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223871.653467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 223871.653467 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115618.240446 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115618.240446 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1966568 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.773009 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 36766553 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1967080 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.690929 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6697446000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.773009 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999557 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999557 # Average percentage of cache occupancy +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15642.498595 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15642.498595 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15709.390662 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15709.390662 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 223835.315245 # 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Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.774783 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999560 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999560 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 157 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 252 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 156 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 258 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 98 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 79434387 # 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average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10064.036594 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.036594 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10064.036594 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 81526207 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 81526207 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 37707013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 37707013 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 37707013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 37707013 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 37707013 # number of overall hits +system.cpu0.icache.overall_hits::total 37707013 # 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number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 39744407 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 39744407 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 39744407 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 39744407 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 39744407 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 39744407 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051262 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051262 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051262 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051262 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051262 # 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number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 323882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 323882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 323882000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 323882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050785 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050785 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050785 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050785 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.036848 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.036848 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.036848 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051262 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.051262 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051262 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.051262 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9527.303752 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9527.303752 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9527.303752 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 98834.909979 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 98834.909979 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 98834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1845428 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1845508 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 70 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927829 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1927948 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 103 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 235148 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 289262 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 15626.234267 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2591525 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 304855 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 8.500845 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 243748 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 297127 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15638.814401 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 2702273 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 312734 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 8.640803 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14514.282419 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 66.020594 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.070348 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1045.860906 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.885881 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.004030 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063834 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.953750 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 230 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15349 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 21 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 121 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 83 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14568.839087 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 61.655947 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.055478 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1008.263889 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.889211 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003763 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000003 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.061540 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954517 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 252 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15345 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 32 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 142 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 72 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 256 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5558 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1085 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.014038 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000854 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.936829 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 91498325 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 91498325 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 78219 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5306 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 83525 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 481785 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 481785 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2159151 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2159151 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 222970 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 222970 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1875280 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1875280 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 389002 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 389002 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 78219 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5306 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1875280 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 611972 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2570777 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 78219 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5306 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1875280 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 611972 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2570777 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 1055 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 176 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 1231 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 56519 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 56519 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20396 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20396 # number of SCUpgradeReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46078 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46078 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 91814 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 91814 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 114162 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 114162 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 1055 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 176 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 91814 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 160240 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 253285 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 1055 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 176 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 91814 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 160240 # number of overall misses -system.cpu0.l2cache.overall_misses::total 253285 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 45088000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4105500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 49193500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 43638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 43638000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 10254000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 10254000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 591500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 591500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2907293999 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2907293999 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4520777000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4520777000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3763870996 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3763870996 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 45088000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4105500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4520777000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6671164995 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 11241135495 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 45088000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4105500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4520777000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6671164995 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 11241135495 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 79274 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5482 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 84756 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 481785 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::total 481785 # number of WritebackDirty accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::writebacks 2159151 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.WritebackClean_accesses::total 2159151 # number of WritebackClean accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 56519 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 56519 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 20396 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20396 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 269048 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269048 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1967094 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadCleanReq_accesses::total 1967094 # number of ReadCleanReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 503164 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.ReadSharedReq_accesses::total 503164 # number of ReadSharedReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 79274 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 5482 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1967094 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 772212 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2824062 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 79274 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5482 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1967094 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 772212 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2824062 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.013308 # 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miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.015551 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.009843 # miss rate for ReadReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 1 # miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 1 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.171263 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171263 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.046675 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.046675 # miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.226888 # 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mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.086286 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.009441 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.015551 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.046819 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.193928 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.182218 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 34078.086672 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63097.730550 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17308.922663 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17308.922663 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15108.575211 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15108.575211 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.177388 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 41446.590909 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 63628.910343 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17351.312476 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17351.312476 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15124.902496 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15124.902496 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data inf # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 50274.240208 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 50274.240208 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 43245.133621 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26883.323189 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26883.323189 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36948.799964 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36797.335871 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17462.209302 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 43245.133621 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33282.312155 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63097.730550 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50415.402160 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 51416.629338 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 51416.629338 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 42309.640626 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 26915.711725 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 26915.711725 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 36862.117594 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 43930.467762 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19370.786517 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42309.640626 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 33530.887785 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 63628.910343 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50608.790647 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215866.308731 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198692.702657 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 215829.684997 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198676.926298 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 90834.909979 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111483.889990 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109914.916064 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 5521359 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2782090 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 42565 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 221607 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217384 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4223 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 119065 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2638335 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 19270 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 714834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2201699 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 105895 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 314040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 88690 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43009 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113952 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 288266 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284716 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1967094 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 603225 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3100 # Transaction distribution +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111433.128681 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 109869.968969 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 5741859 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2893899 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 221175 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 217002 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4173 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 125397 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2741625 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19302 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 743607 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2286693 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 110010 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 316910 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86864 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42906 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 299874 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 296474 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2037394 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 616815 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3112 # Transaction distribution system.cpu0.toL2Bus.trans_dist::InvalidateResp 13 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5907309 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2596679 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13203 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 166718 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 8683909 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 251964032 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 99557768 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21928 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 317096 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 351860824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 942421 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 19099824 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3784720 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.076642 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.270185 # Request fanout histogram +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6118205 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2712873 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 14034 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 176949 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9022061 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 260962176 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104517534 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22892 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 335140 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 365837742 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 939630 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 19388808 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3896038 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.075284 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.267877 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3498873 92.45% 92.45% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 281624 7.44% 99.89% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4223 0.11% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3606903 92.58% 92.58% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 284962 7.31% 99.89% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4173 0.11% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3784720 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5512121494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3896038 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5733869996 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115701354 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 115563972 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2955829450 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3061282943 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1228012492 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1285797933 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7726489 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8314992 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 87463960 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 93182962 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 19376501 # Number of BP lookups -system.cpu1.branchPred.condPredicted 6203106 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 800498 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 9925818 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3621861 # Number of BTB hits +system.cpu1.branchPred.lookups 18647514 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5782822 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 870887 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 9511803 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3428026 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 36.489295 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 8664248 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 596452 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 3651980 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 3587973 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 64007 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 23614 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 36.039708 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8548256 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 712976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 3551521 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 3498978 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 52543 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 17984 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,63 +1370,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 26236 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 26236 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19848 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6388 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 26236 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 26236 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 26236 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 2697 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12386.911383 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11389.033391 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6251.379906 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 628 23.29% 23.29% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 1805 66.93% 90.21% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 172 6.38% 96.59% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 56 2.08% 98.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 26 0.96% 99.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 2 0.07% 99.70% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 3 0.11% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.07% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 3 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 2697 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples -1855739032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 -1855739032 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total -1855739032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 2013 74.64% 74.64% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 684 25.36% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2697 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 26236 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 22971 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 22971 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19558 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3413 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 22971 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 22971 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 22971 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1848 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 12803.300866 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 11525.814953 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 15800.491207 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-65535 1844 99.78% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::65536-131071 3 0.16% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::589824-655359 1 0.05% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1848 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples -1978443032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 -1978443032 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total -1978443032 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1308 70.78% 70.78% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 540 29.22% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1848 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 22971 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 26236 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2697 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 22971 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1848 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2697 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 28933 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1848 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24819 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11335471 # DTB read hits -system.cpu1.dtb.read_misses 23997 # DTB read misses -system.cpu1.dtb.write_hits 7067505 # DTB write hits -system.cpu1.dtb.write_misses 2239 # DTB write misses +system.cpu1.dtb.read_hits 10530339 # DTB read hits +system.cpu1.dtb.read_misses 20830 # DTB read misses +system.cpu1.dtb.write_hits 6472980 # DTB write hits +system.cpu1.dtb.write_misses 2141 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1990 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 147 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 359 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1623 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 116 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 265 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11359468 # DTB read accesses -system.cpu1.dtb.write_accesses 7069744 # DTB write accesses +system.cpu1.dtb.perms_faults 184 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10551169 # DTB read accesses +system.cpu1.dtb.write_accesses 6475121 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18402976 # DTB hits -system.cpu1.dtb.misses 26236 # DTB misses -system.cpu1.dtb.accesses 18429212 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 17003319 # DTB hits +system.cpu1.dtb.misses 22971 # DTB misses +system.cpu1.dtb.accesses 17026290 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1461,45 +1450,43 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 2445 # Table walker walks requested -system.cpu1.itb.walker.walksShort 2445 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 180 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2265 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 2445 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 2445 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 2445 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12500.891266 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11818.240424 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4741.770571 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 15.60% 15.60% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 626 55.79% 71.39% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 208 18.54% 89.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.37% 94.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 21 1.87% 96.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 29 2.58% 98.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 9 0.80% 99.55% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.18% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 1 0.09% 99.82% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1122 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples -1856356532 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 -1856356532 100.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total -1856356532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 957 85.29% 85.29% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 165 14.71% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1122 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 2051 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2051 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 145 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1906 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2051 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2051 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 830 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12046.987952 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11480.071390 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4509.628818 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 126 15.18% 15.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 555 66.87% 82.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 85 10.24% 92.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 14 1.69% 93.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 22 2.65% 96.63% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 18 2.17% 98.80% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 6 0.72% 99.52% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.64% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.36% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 830 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples -1979056532 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 -1979056532 100.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total -1979056532 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 695 83.73% 83.73% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 135 16.27% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 830 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2445 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2445 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2051 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2051 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1122 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 3567 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 39707544 # ITB inst hits -system.cpu1.itb.inst_misses 2445 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 830 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 830 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2881 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 38623354 # ITB inst hits +system.cpu1.itb.inst_misses 2051 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1508,790 +1495,785 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1094 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1860 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1040 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 39709989 # ITB inst accesses -system.cpu1.itb.hits 39707544 # DTB hits -system.cpu1.itb.misses 2445 # DTB misses -system.cpu1.itb.accesses 39709989 # DTB accesses -system.cpu1.numPwrStateTransitions 5531 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2766 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1008751457.310195 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25700289930.408852 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1968 71.15% 71.15% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.71% 99.86% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 38625405 # ITB inst accesses +system.cpu1.itb.hits 38623354 # DTB hits +system.cpu1.itb.misses 2051 # DTB misses +system.cpu1.itb.accesses 38625405 # DTB accesses +system.cpu1.numPwrStateTransitions 5477 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2739 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1019571073.706097 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25827442882.959442 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1941 70.87% 70.87% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 794 28.99% 99.85% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9e+11-9.5e+11 1 0.04% 100.00% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 949980202104 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2766 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 58706424080 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2790206530920 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 117416330 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::max_value 949980394548 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2739 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 55993511619 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2792605170881 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 111990488 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 48257451 # Number of instructions committed -system.cpu1.committedOps 59047178 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 5145755 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2766 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5579767080 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.433123 # CPI: cycles per instruction -system.cpu1.ipc 0.410994 # IPC: instructions per cycle -system.cpu1.op_class_0::No_OpClass 66 0.00% 0.00% # Class of committed instruction -system.cpu1.op_class_0::IntAlu 40655660 68.85% 68.85% # Class of committed instruction -system.cpu1.op_class_0::IntMult 45723 0.08% 68.93% # Class of committed instruction -system.cpu1.op_class_0::IntDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatMisc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::FloatSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAddAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdAlu 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMisc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMult 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdMultAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdShift 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdSqrt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 68.93% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMisc 3341 0.01% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMult 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 68.94% # Class of committed instruction -system.cpu1.op_class_0::MemRead 11158922 18.90% 87.83% # Class of committed instruction -system.cpu1.op_class_0::MemWrite 7181682 12.16% 100.00% # Class of committed instruction -system.cpu1.op_class_0::FloatMemRead 516 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::FloatMemWrite 1268 0.00% 100.00% # Class of committed instruction +system.cpu1.committedInsts 45059059 # Number of instructions committed +system.cpu1.committedOps 55122963 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 4849343 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2739 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5584538446 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.485416 # CPI: cycles per instruction +system.cpu1.ipc 0.402347 # IPC: instructions per cycle +system.cpu1.op_class_0::No_OpClass 24 0.00% 0.00% # Class of committed instruction +system.cpu1.op_class_0::IntAlu 38107074 69.13% 69.13% # Class of committed instruction +system.cpu1.op_class_0::IntMult 43629 0.08% 69.21% # Class of committed instruction +system.cpu1.op_class_0::IntDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::FloatSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAddAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMisc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMult 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdMultAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdShift 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdShiftAcc 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdSqrt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAdd 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatAlu 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCmp 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatCvt 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatDiv 0 0.00% 69.21% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMisc 3226 0.01% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMult 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatMultAcc 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::SimdFloatSqrt 0 0.00% 69.22% # Class of committed instruction +system.cpu1.op_class_0::MemRead 10387367 18.84% 88.06% # Class of committed instruction +system.cpu1.op_class_0::MemWrite 6581643 11.94% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction +system.cpu1.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.op_class_0::total 59047178 # Class of committed instruction +system.cpu1.op_class_0::total 55122963 # Class of committed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2766 # number of quiesce instructions executed -system.cpu1.tickCycles 94212752 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 23203578 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 197406 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.838335 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17978253 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 197762 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 90.908531 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91321339500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.838335 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929372 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.929372 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 356 # Occupied blocks per task id +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed +system.cpu1.tickCycles 90184958 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 21805530 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 157661 # number of replacements +system.cpu1.dcache.tags.tagsinuse 475.726390 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 16648746 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 158020 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 105.358474 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91198641000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.726390 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.929153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.929153 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 284 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 72 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.695312 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36857417 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36857417 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 10958654 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10958654 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6778912 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6778912 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 50538 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 50538 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 80236 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 80236 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 71701 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 71701 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17737566 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17737566 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17788104 # number of overall hits -system.cpu1.dcache.overall_hits::total 17788104 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 149954 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 149954 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 146295 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 146295 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30728 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30728 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16950 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16950 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23669 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23669 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 296249 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 296249 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 326977 # number of overall misses -system.cpu1.dcache.overall_misses::total 326977 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2480923500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2480923500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4141245000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4141245000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 326364000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 326364000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 557050500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 557050500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 662000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 662000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6622168500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6622168500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6622168500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6622168500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 11108608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 11108608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 6925207 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 6925207 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 81266 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 81266 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 97186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 97186 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 95370 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 95370 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 18033815 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 18033815 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 18115081 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 18115081 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.013499 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.013499 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.021125 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.021125 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.378116 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.378116 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.174408 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.174408 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.248181 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.248181 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.016427 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.016427 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.018050 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.018050 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16544.563666 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16544.563666 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 28307.495130 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 28307.495130 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19254.513274 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19254.513274 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23535.024716 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23535.024716 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 34039754 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 34039754 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 10204486 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 10204486 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 6223411 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 6223411 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 43300 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 43300 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71256 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 71256 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62645 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 62645 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 16427897 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 16427897 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 16471197 # number of overall hits +system.cpu1.dcache.overall_hits::total 16471197 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 127390 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 127390 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 122263 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 122263 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24165 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24165 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16525 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16525 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23356 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23356 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 249653 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 249653 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 273818 # number of overall misses +system.cpu1.dcache.overall_misses::total 273818 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2191208500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2191208500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3801376500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3801376500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 322530000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 322530000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 548226000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 548226000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 650000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 650000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 5992585000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 5992585000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 5992585000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 5992585000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 10331876 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 10331876 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6345674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6345674 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67465 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 67465 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87781 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87781 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 86001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 86001 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16677550 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16677550 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16745015 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16745015 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.012330 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.012330 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.019267 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.019267 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358186 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358186 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.188253 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.188253 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.271578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.271578 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.014969 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.014969 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.016352 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.016352 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 17200.788916 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 17200.788916 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31091.798009 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31091.798009 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19517.700454 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19517.700454 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23472.598048 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23472.598048 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22353.386847 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22353.386847 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20252.704319 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 20252.704319 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24003.657076 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 24003.657076 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21885.285116 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21885.285116 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 197406 # number of writebacks -system.cpu1.dcache.writebacks::total 197406 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 5638 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 5638 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 53221 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 53221 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12059 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12059 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 58859 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 58859 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 58859 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 58859 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 144316 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 144316 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 93074 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 93074 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 29900 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 29900 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4891 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23669 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 237390 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 237390 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 267290 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 267290 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14424 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11757 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11757 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26181 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26181 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2239010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2239010000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2480218000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2480218000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 521766000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 521766000 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86789500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86789500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 533397500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 533397500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 646000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 646000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4719228000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4719228000 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5240994000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5240994000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2492996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2492996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2492996500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2492996500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.012991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.012991 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.013440 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.367928 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.367928 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050326 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050326 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.248181 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.248181 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.013164 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.013164 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.014755 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.014755 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15514.634552 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15514.634552 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26647.807121 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26647.807121 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17450.367893 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17450.367893 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17744.735228 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17744.735228 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22535.700706 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22535.700706 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 157661 # number of writebacks +system.cpu1.dcache.writebacks::total 157661 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 4447 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 4447 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42267 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 42267 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11747 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11747 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 46714 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 46714 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 46714 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 46714 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122943 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 122943 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79996 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79996 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23657 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23657 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4778 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4778 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23356 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23356 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 202939 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 202939 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 226596 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 226596 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14406 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14406 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11728 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11728 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26134 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1987288500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1987288500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2305734500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2305734500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 418963500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 418963500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86008500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86008500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 524885000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 524885000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 635000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 635000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4293023000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4293023000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4711986500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4711986500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2490253500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2490253500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2490253500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2490253500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.011899 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.011899 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012606 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.012606 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.350656 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.350656 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054431 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054431 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.271578 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.271578 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.012168 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.012168 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.013532 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.013532 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 16164.307850 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 16164.307850 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28823.122406 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28823.122406 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17709.916727 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17709.916727 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18000.941817 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18000.941817 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22473.240281 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22473.240281 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19879.641097 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19879.641097 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19607.894048 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19607.894048 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172836.695785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172836.695785 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95221.591994 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95221.591994 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 951563 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.187738 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 38753540 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 952075 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 40.704293 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73017738000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.187738 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974976 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974976 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21154.253249 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 21154.253249 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20794.658776 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20794.658776 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172862.244898 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 172862.244898 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95287.881687 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95287.881687 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 872875 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.208474 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 37748872 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 873387 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 43.221243 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 72896771000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.208474 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975017 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975017 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 466 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 46 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 463 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 80363305 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 80363305 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 38753540 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 38753540 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 38753540 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 38753540 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 38753540 # number of overall hits -system.cpu1.icache.overall_hits::total 38753540 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 952075 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 952075 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 952075 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 952075 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 952075 # number of overall misses -system.cpu1.icache.overall_misses::total 952075 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8812564500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8812564500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8812564500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8812564500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8812564500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8812564500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 39705615 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 39705615 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 39705615 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 39705615 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 39705615 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 39705615 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.023978 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.023978 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.023978 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.023978 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.023978 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.023978 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9256.166268 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9256.166268 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9256.166268 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9256.166268 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9256.166268 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 78117905 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 78117905 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 37748872 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 37748872 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 37748872 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 37748872 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 37748872 # number of overall hits +system.cpu1.icache.overall_hits::total 37748872 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 873387 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 873387 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 873387 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 873387 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 873387 # number of overall misses +system.cpu1.icache.overall_misses::total 873387 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8011666500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8011666500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8011666500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8011666500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8011666500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8011666500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 38622259 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 38622259 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 38622259 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 38622259 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 38622259 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 38622259 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.022614 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.022614 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022614 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.022614 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022614 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.022614 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9173.100241 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9173.100241 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9173.100241 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9173.100241 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9173.100241 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 951563 # number of writebacks -system.cpu1.icache.writebacks::total 951563 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 952075 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 952075 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 952075 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 952075 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 952075 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 952075 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 872875 # number of writebacks +system.cpu1.icache.writebacks::total 872875 # number of writebacks +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 873387 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 873387 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 873387 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 873387 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 873387 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 873387 # number of overall MSHR misses system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 112 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 112 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 112 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8336527000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8336527000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8336527000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8336527000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8336527000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8336527000 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10996500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10996500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 10996500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.023978 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.023978 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.023978 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.023978 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8756.166268 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8756.166268 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8756.166268 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98183.035714 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98183.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 202046 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 202062 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 14 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7574973000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7574973000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7574973000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7574973000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7574973000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7574973000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 11042500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 11042500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 11042500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 11042500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022614 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.022614 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022614 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.022614 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8673.100241 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8673.100241 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8673.100241 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 98593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 98593.750000 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 98593.750000 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 118852 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 118852 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 0 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 58314 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 53261 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 14759.472479 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1060224 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 67460 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 15.716336 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 49172 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 37377 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14753.834184 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 946442 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 52088 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 18.170058 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14399.124814 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 38.202581 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.100138 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 322.044945 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.878853 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002332 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.019656 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.900847 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 251 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 42 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13906 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 79 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 172 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 1287 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 7824 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4795 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.015320 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002563 # 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number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 15550500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 965321170 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 461957500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 461957500 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 354728500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 354728500 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 526000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 526000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1277222000 # 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number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3873447495 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 11857500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3693000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1145765500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2712131495 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 965321170 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4838768665 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10100500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2377583500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2387684000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10100500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2377583500 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2387684000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.028810 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 26134 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 26246 # 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number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 521000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1224744500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1224744500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 975419000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 975419000 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300674995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300674995 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4074000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 975419000 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2525419495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3521214495 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 16302000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4074000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 975419000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2525419495 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 732946008 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4254160503 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10146500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2374983500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2385130000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 10146500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2374983500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2385130000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.041037 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.551761 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.551761 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.037404 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.420927 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.420927 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119570 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.023144 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.077191 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.037404 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.454980 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637671 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637671 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.032668 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.460404 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.460404 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.119448 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.033788 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.102190 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032668 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.504922 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.140992 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16420.802534 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 36722.378742 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15370.915685 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15370.915685 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14987.683792 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14987.683792 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 526000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 526000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 36731.335557 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 36731.335557 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 32174.482604 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 19032.901739 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 19032.901739 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26400.089251 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 17411.894273 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13883.458647 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 32174.482604 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24619.259597 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 36722.378742 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27968.467730 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164835.239878 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164260.044029 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90183.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90813.318819 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90810.634009 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 2407036 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1212847 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 20197 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 118681 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 110741 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7940 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 51870 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1220498 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 11757 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 11757 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 156434 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 1031137 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 35507 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 31472 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 73789 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 42123 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86153 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 70267 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 67627 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 952075 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295896 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 106 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2855937 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 915985 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 8156 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 62049 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3842127 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 121840000 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 30925576 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 13784 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 117700 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 152897060 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 370911 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5180924 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1603484 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.097889 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.313386 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.137257 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18290.843806 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 37324.744513 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15238.915498 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15238.915498 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14925.415311 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14925.415311 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 37833.451748 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 37833.451748 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34186.842843 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18662.386039 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18662.386039 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 26733.993569 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 19880.487805 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13857.142857 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34186.842843 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 24742.762058 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 37324.744513 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28108.097146 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 164860.717756 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 164287.780686 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90593.750000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 90877.152369 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 90875.943001 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 2165902 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1090398 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18866 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115909 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 108045 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 7864 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 44859 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1106447 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11728 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 126621 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 935252 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 26571 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 23763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71775 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41777 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84685 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 58060 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 873387 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 263309 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 71 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2619873 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 793002 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6834 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50653 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3470362 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 111767936 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25786238 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 11508 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 97076 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 137662758 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 338759 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4674348 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1446654 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.103615 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.322104 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1454460 90.71% 90.71% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 141084 8.80% 99.50% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 7940 0.50% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1304623 90.18% 90.18% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 134167 9.27% 99.46% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 7864 0.54% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1603484 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2385111494 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1446654 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2144021494 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 79363429 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78336814 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1428355849 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 412276680 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1310300396 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 351676729 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4711996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3959994 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 32634978 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 26397473 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iobus.trans_dist::ReadReq 31015 # Transaction distribution -system.iobus.trans_dist::ReadResp 31015 # Transaction distribution -system.iobus.trans_dist::WriteReq 59422 # Transaction distribution -system.iobus.trans_dist::WriteResp 59422 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56602 # Packet count per connected master and slave (bytes) +system.iobus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iobus.trans_dist::ReadReq 31009 # Transaction distribution +system.iobus.trans_dist::ReadResp 31009 # Transaction distribution +system.iobus.trans_dist::WriteReq 59424 # Transaction distribution +system.iobus.trans_dist::WriteResp 59424 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2310,11 +2292,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72958 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180874 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71546 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2333,94 +2315,94 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162796 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321272 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484068 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 48355001 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 48425501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 110500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 333000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 29500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 92500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 88500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 611500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 621000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 47500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6349500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6370500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 38550000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 39055001 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187836280 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187730317 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84718000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36782000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iocache.tags.replacements 36461 # number of replacements -system.iocache.tags.tagsinuse 14.472129 # Cycle average of tags in use +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iocache.tags.replacements 36449 # number of replacements +system.iocache.tags.tagsinuse 14.472713 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36477 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272035829000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.472129 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904508 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904508 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 271902155000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.472713 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904545 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904545 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328311 # Number of tag accesses -system.iocache.tags.data_accesses 328311 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.iocache.ReadReq_misses::realview.ide 255 # number of ReadReq misses -system.iocache.ReadReq_misses::total 255 # number of ReadReq misses +system.iocache.tags.tag_accesses 328203 # Number of tag accesses +system.iocache.tags.data_accesses 328203 # Number of data accesses +system.iocache.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses +system.iocache.ReadReq_misses::total 243 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 36479 # number of demand (read+write) misses -system.iocache.demand_misses::total 36479 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 36479 # number of overall misses -system.iocache.overall_misses::total 36479 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 33894626 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 33894626 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4361652654 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4361652654 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4395547280 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4395547280 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4395547280 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4395547280 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 255 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 255 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 36467 # number of demand (read+write) misses +system.iocache.demand_misses::total 36467 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 36467 # number of overall misses +system.iocache.overall_misses::total 36467 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 32482877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32482877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4347292440 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4347292440 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4379775317 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4379775317 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4379775317 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4379775317 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 36479 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 36479 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 36479 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 36479 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 36467 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 36467 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 36467 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 36467 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2429,38 +2411,38 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 132920.101961 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 132920.101961 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120407.813991 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 120407.813991 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120495.278928 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120495.278928 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120495.278928 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 33 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 133674.390947 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 133674.390947 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 120011.385822 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 120011.385822 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 120102.430060 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 120102.430060 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 120102.430060 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.600000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 3.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 255 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 255 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 36479 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 36479 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 36479 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 36479 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 21144626 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 21144626 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2548533560 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2548533560 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2569678186 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2569678186 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2569678186 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2569678186 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 36467 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 36467 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 36467 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 36467 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20332877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20332877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2534226880 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2534226880 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2554559757 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2554559757 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2554559757 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2554559757 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2469,587 +2451,591 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82920.101961 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82920.101961 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 70354.835468 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 70354.835468 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70442.670742 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70442.670742 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 144965 # number of replacements -system.l2c.tags.tagsinuse 65152.937424 # Cycle average of tags in use -system.l2c.tags.total_refs 609190 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 210433 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.894936 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 94596333000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 6623.641464 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.873340 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030778 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8717.297780 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 6753.906827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34978.887881 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.032858 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2236.963584 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3439.697056 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2304.605856 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.101069 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001280 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 83674.390947 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 83674.390947 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 69959.885159 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 69959.885159 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70051.272575 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70051.272575 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 143599 # number of replacements +system.l2c.tags.tagsinuse 65154.346859 # Cycle average of tags in use +system.l2c.tags.total_refs 605481 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 209069 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.896082 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 94462980000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 6720.710891 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 87.363500 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.029896 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8711.779777 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 6725.180439 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34970.113845 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 14.660518 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2224.966255 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3446.409233 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2253.132505 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.102550 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001333 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.133015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.103056 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533735 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.034133 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.052486 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.035165 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.994155 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31624 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 33792 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 150 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4711 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 26763 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.132931 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.102618 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533602 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000224 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.033950 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.052588 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.034380 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994176 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 32778 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32633 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5072 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27569 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 93 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1870 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31828 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.482544 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.515625 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6850011 # Number of tag accesses -system.l2c.tags.data_accesses 6850011 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 269158 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 269158 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 42928 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 5622 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 48550 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2743 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 2305 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 5048 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4279 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1522 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5801 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 596 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 68829 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 63546 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 47286 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 133 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 32119 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 13663 # 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mshr miss rate for CleanEvict accesses system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.009323 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.039139 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.012870 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.037206 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.034353 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.035905 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.725335 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.850138 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.774587 # mshr miss rate for ReadExReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.135346 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.110887 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.433425 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.453589 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.197847 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.010309 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.249796 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.238537 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.737707 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.125000 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.098060 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.405046 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.521028 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.453589 # mshr miss rate for overall accesses -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22144.801980 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21982.532751 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22086.097946 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26283.018868 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24371.951220 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25449.468085 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 128231.592920 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86156.358582 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 110007.574997 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.010407 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.038370 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.013069 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018543 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.028298 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.022602 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.719740 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.874324 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.778735 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.131588 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171734 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.441462 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.461672 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.233119 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.011494 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.238321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.233477 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.733923 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.200000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.515982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.581960 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.461672 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 22301.742919 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 21963.483146 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22207.221350 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26482.456140 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23435.483871 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24894.957983 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 129505.734045 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 85203.000934 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 110522.964927 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 110524.278677 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 149876.760563 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 107807.640087 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 112104.795826 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 139796.117076 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 108322.950558 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 135547.619048 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 142465.517241 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 80000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 90808.019547 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 119941.732951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 109443.676397 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80578.947368 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 99787.657503 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 96659.315148 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 123225.880025 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 108029.684262 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 91899.705318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 121397.498831 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 110284.223342 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 217625 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 95788.698822 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 94470.334561 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119012.949056 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 108545.308295 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197863.927895 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146864.503155 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167402.972051 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197827.840606 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 146890.057627 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167421.474150 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 69834.757400 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102186.582520 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69183.035714 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80905.072962 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92580.706733 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 519148 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 291431 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.membus.snoop_filter.hit_multi_requests 639 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 102138.754542 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 69593.750000 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 80963.510773 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92591.249550 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 513996 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 285885 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.membus.snoop_filter.hit_multi_requests 629 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 38391 # Transaction distribution -system.membus.trans_dist::ReadResp 216211 # Transaction distribution -system.membus.trans_dist::WriteReq 31027 # Transaction distribution -system.membus.trans_dist::WriteResp 31027 # Transaction distribution -system.membus.trans_dist::WritebackDirty 141592 # Transaction distribution -system.membus.trans_dist::CleanEvict 19995 # Transaction distribution -system.membus.trans_dist::UpgradeReq 63966 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 38983 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 38395 # Transaction distribution +system.membus.trans_dist::ReadResp 216403 # Transaction distribution +system.membus.trans_dist::WriteReq 31030 # Transaction distribution +system.membus.trans_dist::WriteResp 31030 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140287 # Transaction distribution +system.membus.trans_dist::CleanEvict 19048 # Transaction distribution +system.membus.trans_dist::UpgradeReq 61128 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38691 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40431 # Transaction distribution -system.membus.trans_dist::ReadExResp 19912 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 177820 # Transaction distribution +system.membus.trans_dist::ReadExReq 40497 # Transaction distribution +system.membus.trans_dist::ReadExResp 19965 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 178008 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 4302 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107916 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::InvalidateResp 4238 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14192 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 659894 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782044 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72955 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 854999 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162796 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655043 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 777209 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 850140 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28384 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19597036 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19789560 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19529832 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19722372 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 22107704 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 127509 # Total snoops (count) -system.membus.snoopTraffic 37120 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 426843 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011580 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.106987 # Request fanout histogram +system.membus.pkt_size::total 22040516 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 124379 # Total snoops (count) +system.membus.snoopTraffic 36224 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 423974 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011487 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.106558 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 421900 98.84% 98.84% # Request fanout histogram -system.membus.snoop_fanout::1 4943 1.16% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 419104 98.85% 98.85% # Request fanout histogram +system.membus.snoop_fanout::1 4870 1.15% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 426843 # Request fanout histogram -system.membus.reqLayer0.occupancy 94581999 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 423974 # Request fanout histogram +system.membus.reqLayer0.occupancy 95170998 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23328 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12496000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12519499 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1014639485 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1006886251 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1151195264 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1152568025 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 6864902 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 6725047 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3081,78 +3067,78 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1123711 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 579018 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 224775 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 30515 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 29083 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1432 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848912955000 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 38394 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 569470 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31027 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31027 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 374544 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 155002 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 112494 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 44031 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 156525 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51717 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51717 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 531080 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4357 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateResp 3099 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1346867 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 408809 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1755676 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 38391932 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7144124 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 45536056 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 402215 # Total snoops (count) -system.toL2Bus.snoopTraffic 16179148 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 958128 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.409221 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.494721 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1101165 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 567136 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 209084 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 30878 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 29463 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1415 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2848598682500 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 38398 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 558656 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31030 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31030 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 370367 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 149733 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109212 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43837 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153049 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 31 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51538 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51538 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 520262 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4298 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateResp 3081 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1372035 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 353597 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1725632 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 39251474 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5647218 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 44898692 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 393768 # Total snoops (count) +system.toL2Bus.snoopTraffic 15844428 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 942231 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.393753 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.491645 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 567474 59.23% 59.23% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 389222 40.62% 99.85% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1432 0.15% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 572640 60.77% 60.77% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 368176 39.07% 99.85% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1415 0.15% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 958128 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 954442443 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 942231 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 939495440 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1977326 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 1962409 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 723838248 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 733983819 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 286417681 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 257943151 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |