diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-12 09:05:25 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-11-12 09:05:25 -0500 |
| commit | 4583a5114aa34efb3b83e9a2e40dd74f7c49facb (patch) | |
| tree | 2b1fef9b86d8c589f2dbc2e17c03c85a9e1900d3 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | |
| parent | 9d6d8e02aab300c524ca9cf216a11e71d10826aa (diff) | |
| download | gem5-4583a5114aa34efb3b83e9a2e40dd74f7c49facb.tar.xz | |
stats: Bump regressions to match latest changes
Updates after timezone hick-up and sorting of dictionary items in the
SimObject.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4264 |
1 files changed, 2134 insertions, 2130 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index a43b4e79e..405fa6e98 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,175 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.843665 # Number of seconds simulated -sim_ticks 2843665155500 # Number of ticks simulated -final_tick 2843665155500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.843655 # Number of seconds simulated +sim_ticks 2843654861000 # Number of ticks simulated +final_tick 2843654861000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 158211 # Simulator instruction rate (inst/s) -host_op_rate 191554 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3597700350 # Simulator tick rate (ticks/s) -host_mem_usage 605956 # Number of bytes of host memory used -host_seconds 790.41 # Real time elapsed on the host -sim_insts 125052080 # Number of instructions simulated -sim_ops 151406456 # Number of ops (including micro ops) simulated +host_inst_rate 157498 # Simulator instruction rate (inst/s) +host_op_rate 190690 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3581426538 # Simulator tick rate (ticks/s) +host_mem_usage 613612 # Number of bytes of host memory used +host_seconds 794.00 # Real time elapsed on the host +sim_insts 125053138 # Number of instructions simulated +sim_ops 151407658 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 9664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1364476 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 10766720 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1363068 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 10771008 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 533600 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 1164672 # Number of bytes read from this memory -system.physmem.bytes_read::total 13841116 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 419072 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 26240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 445312 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7174080 # Number of bytes written to this memory -system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 534304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 1165248 # Number of bytes read from this memory +system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory +system.physmem.bytes_read::total 13845276 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 418688 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 26560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 445248 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7176128 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 9510160 # Number of bytes written to this memory -system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory +system.physmem.bytes_written::total 9512208 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 151 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 21845 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 168230 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 21823 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 168297 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 8361 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 18198 # Number of read requests responded to by this memory -system.physmem.num_reads::total 216816 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 112095 # Number of write requests responded to by this memory -system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 8372 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 18207 # Number of read requests responded to by this memory +system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory +system.physmem.num_reads::total 216881 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 112127 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 152755 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory +system.physmem.num_writes::total 152787 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3398 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 479830 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3786212 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 479337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3787734 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 187645 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 409567 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4867351 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 147370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 9228 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 156598 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2522829 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::realview.ide 815263 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 187893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 409771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4868831 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 147236 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 9340 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 156576 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2523558 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 6226 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3344332 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2522829 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 815601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::realview.ide 815266 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3345064 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2523558 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3398 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 486056 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3786212 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 485562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3787734 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 187659 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 409567 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 8211683 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 216816 # Number of read requests accepted -system.physmem.writeReqs 152755 # Number of write requests accepted -system.physmem.readBursts 216816 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 152755 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 13860032 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 16192 # Total number of bytes read from write queue -system.physmem.bytesWritten 9524672 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 13841116 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 9510160 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 253 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.inst 187907 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 409771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 815604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8213896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 216881 # Number of read requests accepted +system.physmem.writeReqs 152787 # Number of write requests accepted +system.physmem.readBursts 216881 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 152787 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 13864960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 15424 # Total number of bytes read from write queue +system.physmem.bytesWritten 9526912 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 13845276 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9512208 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 241 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3914 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 13536 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 13436 # Per bank write bursts -system.physmem.perBankRdBursts::1 13084 # Per bank write bursts -system.physmem.perBankRdBursts::2 14401 # Per bank write bursts -system.physmem.perBankRdBursts::3 13747 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 13516 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 13445 # Per bank write bursts +system.physmem.perBankRdBursts::1 13090 # Per bank write bursts +system.physmem.perBankRdBursts::2 14400 # Per bank write bursts +system.physmem.perBankRdBursts::3 13760 # Per bank write bursts system.physmem.perBankRdBursts::4 15799 # Per bank write bursts -system.physmem.perBankRdBursts::5 12797 # Per bank write bursts -system.physmem.perBankRdBursts::6 13572 # Per bank write bursts -system.physmem.perBankRdBursts::7 13744 # Per bank write bursts -system.physmem.perBankRdBursts::8 13565 # Per bank write bursts -system.physmem.perBankRdBursts::9 13602 # Per bank write bursts -system.physmem.perBankRdBursts::10 13295 # Per bank write bursts -system.physmem.perBankRdBursts::11 11895 # Per bank write bursts -system.physmem.perBankRdBursts::12 13378 # Per bank write bursts -system.physmem.perBankRdBursts::13 13725 # Per bank write bursts -system.physmem.perBankRdBursts::14 13486 # Per bank write bursts -system.physmem.perBankRdBursts::15 13037 # Per bank write bursts -system.physmem.perBankWrBursts::0 9315 # Per bank write bursts -system.physmem.perBankWrBursts::1 9418 # Per bank write bursts -system.physmem.perBankWrBursts::2 10151 # Per bank write bursts -system.physmem.perBankWrBursts::3 9572 # Per bank write bursts -system.physmem.perBankWrBursts::4 8971 # Per bank write bursts -system.physmem.perBankWrBursts::5 8910 # Per bank write bursts -system.physmem.perBankWrBursts::6 9379 # Per bank write bursts -system.physmem.perBankWrBursts::7 9378 # Per bank write bursts +system.physmem.perBankRdBursts::5 12812 # Per bank write bursts +system.physmem.perBankRdBursts::6 13576 # Per bank write bursts +system.physmem.perBankRdBursts::7 13750 # Per bank write bursts +system.physmem.perBankRdBursts::8 13572 # Per bank write bursts +system.physmem.perBankRdBursts::9 13600 # Per bank write bursts +system.physmem.perBankRdBursts::10 13300 # Per bank write bursts +system.physmem.perBankRdBursts::11 11904 # Per bank write bursts +system.physmem.perBankRdBursts::12 13370 # Per bank write bursts +system.physmem.perBankRdBursts::13 13720 # Per bank write bursts +system.physmem.perBankRdBursts::14 13497 # Per bank write bursts +system.physmem.perBankRdBursts::15 13045 # Per bank write bursts +system.physmem.perBankWrBursts::0 9322 # Per bank write bursts +system.physmem.perBankWrBursts::1 9428 # Per bank write bursts +system.physmem.perBankWrBursts::2 10143 # Per bank write bursts +system.physmem.perBankWrBursts::3 9576 # Per bank write bursts +system.physmem.perBankWrBursts::4 8974 # Per bank write bursts +system.physmem.perBankWrBursts::5 8900 # Per bank write bursts +system.physmem.perBankWrBursts::6 9376 # Per bank write bursts +system.physmem.perBankWrBursts::7 9386 # Per bank write bursts system.physmem.perBankWrBursts::8 9384 # Per bank write bursts -system.physmem.perBankWrBursts::9 9425 # Per bank write bursts -system.physmem.perBankWrBursts::10 9360 # Per bank write bursts -system.physmem.perBankWrBursts::11 8832 # Per bank write bursts -system.physmem.perBankWrBursts::12 9377 # Per bank write bursts -system.physmem.perBankWrBursts::13 9192 # Per bank write bursts -system.physmem.perBankWrBursts::14 9288 # Per bank write bursts -system.physmem.perBankWrBursts::15 8871 # Per bank write bursts +system.physmem.perBankWrBursts::9 9431 # Per bank write bursts +system.physmem.perBankWrBursts::10 9355 # Per bank write bursts +system.physmem.perBankWrBursts::11 8834 # Per bank write bursts +system.physmem.perBankWrBursts::12 9379 # Per bank write bursts +system.physmem.perBankWrBursts::13 9206 # Per bank write bursts +system.physmem.perBankWrBursts::14 9289 # Per bank write bursts +system.physmem.perBankWrBursts::15 8875 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 7 # Number of times write queue was full causing retry -system.physmem.totGap 2843662895000 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2843652584000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 559 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 216229 # Read request sizes (log2) +system.physmem.readPktSize::6 216294 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4436 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 148319 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 79263 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 62843 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 17911 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12269 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 10663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 9296 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 8295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 7452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6012 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 321 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 208 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 103 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 148351 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 79253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 62833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 17902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12267 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 10637 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 9321 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 8351 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 7490 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 6044 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1174 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 425 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 210 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 171 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 138 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 100 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -197,810 +179,190 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3556 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5395 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 7496 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 8100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 8979 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 9748 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 10867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10670 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 10413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 10861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9033 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8722 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8168 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 377 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 321 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 186 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 158 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 156 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 133 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 33 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3545 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 7461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 8095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8963 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 9736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10594 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 10430 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 10909 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9025 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8830 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 168 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 51 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 31 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 21 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 16 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92579 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 252.591884 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 143.134462 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 307.650054 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46986 50.75% 50.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 18789 20.30% 71.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6843 7.39% 78.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3586 3.87% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3022 3.26% 85.58% # Bytes accessed per row activation +system.physmem.wrQLenPdf::58 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 8 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92618 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 252.562223 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 143.207145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 307.469960 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 46921 50.66% 50.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18876 20.38% 71.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6855 7.40% 78.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3600 3.89% 82.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3008 3.25% 85.58% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 2120 2.29% 87.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1307 1.41% 89.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1131 1.22% 90.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8795 9.50% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92579 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 7460 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.029759 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 529.579779 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 7459 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::768-895 1341 1.45% 89.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1115 1.20% 90.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8782 9.48% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92618 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7463 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.028407 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 529.473600 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7462 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 7460 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 7460 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 19.949464 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.624141 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.915893 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 6155 82.51% 82.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 493 6.61% 89.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 89 1.19% 90.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 200 2.68% 92.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 188 2.52% 95.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 17 0.23% 95.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 27 0.36% 96.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 16 0.21% 96.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 36 0.48% 96.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 10 0.13% 96.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 5 0.07% 97.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 4 0.05% 97.05% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 168 2.25% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 4 0.05% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.13% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 3 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 5 0.07% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 4 0.05% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 3 0.04% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.05% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 7460 # Writes before turning the bus around for reads -system.physmem.totQLat 7660076750 # Total ticks spent queuing -system.physmem.totMemAccLat 11720633000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1082815000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35371.12 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 7463 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7463 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.946134 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.603737 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.129560 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 6171 82.69% 82.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 489 6.55% 89.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 84 1.13% 90.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 205 2.75% 93.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 200 2.68% 95.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 17 0.23% 96.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 17 0.23% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.16% 96.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 25 0.33% 96.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 6 0.08% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 6 0.08% 96.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 3 0.04% 96.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.21% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.09% 99.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.08% 99.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 18 0.24% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 7 0.09% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 3 0.04% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.11% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7463 # Writes before turning the bus around for reads +system.physmem.totQLat 7683149500 # Total ticks spent queuing +system.physmem.totMemAccLat 11745149500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1083200000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35465.05 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54121.12 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.87 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 54215.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.88 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.35 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.87 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.34 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.35 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.69 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.50 # Average write queue length when enqueuing -system.physmem.readRowHits 183124 # Number of row buffer hits during reads -system.physmem.writeRowHits 89683 # Number of row buffer hits during writes +system.physmem.avgWrQLen 26.48 # Average write queue length when enqueuing +system.physmem.readRowHits 183194 # Number of row buffer hits during reads +system.physmem.writeRowHits 89685 # Number of row buffer hits during writes system.physmem.readRowHitRate 84.56 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 60.25 # Row buffer hit rate for writes -system.physmem.avgGap 7694496.85 # Average gap between requests +system.physmem.writeRowHitRate 60.24 # Row buffer hit rate for writes +system.physmem.avgGap 7692449.94 # Average gap between requests system.physmem.pageHitRate 74.66 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2709761139750 # Time in different power states -system.physmem.memoryStateTime::REF 94956160000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2709796310750 # Time in different power states +system.physmem.memoryStateTime::REF 94955640000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 38946040250 # Time in different power states +system.physmem.memoryStateTime::ACT 38900516750 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 358880760 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 341016480 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 195817875 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 186070500 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 862524000 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 826667400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 486609120 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 477763920 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 185734248960 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 185734248960 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 81966350835 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 81438405435 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1634297688000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1634760798000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1903902119550 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1903764970695 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.524448 # Core power per rank (mW) -system.physmem.averagePower::1 669.476219 # Core power per rank (mW) -system.membus.trans_dist::ReadReq 238011 # Transaction distribution -system.membus.trans_dist::ReadResp 238011 # Transaction distribution -system.membus.trans_dist::WriteReq 30931 # Transaction distribution -system.membus.trans_dist::WriteResp 30931 # Transaction distribution -system.membus.trans_dist::Writeback 112095 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 79719 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 39980 # Transaction distribution -system.membus.trans_dist::UpgradeResp 13536 # Transaction distribution -system.membus.trans_dist::ReadExReq 30379 # Transaction distribution -system.membus.trans_dist::ReadExResp 13328 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13572 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704855 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 826435 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 899141 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21031980 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21223190 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23542486 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 123442 # Total snoops (count) -system.membus.snoop_fanout::samples 498376 # Request fanout histogram -system.membus.snoop_fanout::mean 1 # Request fanout histogram -system.membus.snoop_fanout::stdev 0 # Request fanout histogram -system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 498376 100.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.membus.snoop_fanout::min_value 1 # Request fanout histogram -system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 498376 # Request fanout histogram -system.membus.reqLayer0.occupancy 87914995 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) -system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11673499 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1620072999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 2120142312 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38549614 # Layer occupancy (ticks) -system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 151709 # number of replacements -system.l2c.tags.tagsinuse 64474.290498 # Cycle average of tags in use -system.l2c.tags.total_refs 529875 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 216478 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.447708 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12364.739343 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831819 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030523 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 3875.049948 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42732.474457 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.614781 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 756.297533 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4653.252093 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.188671 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.059129 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.652046 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000162 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011540 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071003 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.983800 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 46265 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 18457 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 269 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6570 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 39426 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 245 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 2643 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 15559 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.705948 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.281631 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6643854 # Number of tag accesses -system.l2c.tags.data_accesses 6643854 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 549 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 114 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 36725 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207902 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 116 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 47 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 11423 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45111 # number of ReadReq hits -system.l2c.ReadReq_hits::total 301987 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 252491 # number of Writeback hits -system.l2c.Writeback_hits::total 252491 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 11970 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 853 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 12823 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 185 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 180 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 365 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 3516 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 1122 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4638 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 549 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 114 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 40241 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 207902 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 47 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 12545 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 45111 # number of demand (read+write) hits -system.l2c.demand_hits::total 306625 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 549 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 114 # number of overall hits -system.l2c.overall_hits::cpu0.inst 40241 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 207902 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 116 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 47 # number of overall hits -system.l2c.overall_hits::cpu1.inst 12545 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 45111 # number of overall hits -system.l2c.overall_hits::total 306625 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 11298 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18199 # number of ReadReq misses -system.l2c.ReadReq_misses::total 199730 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 9030 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11695 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 470 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1259 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1729 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 7024 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 6416 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 13440 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 18322 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 8252 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 18199 # number of demand (read+write) misses -system.l2c.demand_misses::total 213170 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 18322 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 168230 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses -system.l2c.overall_misses::cpu1.inst 8252 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 18199 # number of overall misses -system.l2c.overall_misses::total 213170 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 956701998 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1343500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 150016000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 21240863385 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 10890561 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 2732384 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 13622945 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1227450 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 930960 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2158410 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 595061904 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 477250480 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1072312384 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1551763902 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1343500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 627266480 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 22313175769 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1551763902 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18100124423 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1343500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 627266480 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2020627464 # number of overall miss cycles -system.l2c.overall_miss_latency::total 22313175769 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 700 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 115 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 48023 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 376132 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 131 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 47 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 13259 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63310 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 501717 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 252491 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 252491 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 21000 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 3518 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 24518 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 655 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1439 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2094 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 10540 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 7538 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 18078 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 700 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 115 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 58563 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 376132 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 131 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 47 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 20797 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63310 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 519795 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 700 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 115 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 58563 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 376132 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 131 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 47 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 20797 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63310 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 519795 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008696 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.235262 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.138472 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.398093 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.757533 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.476996 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.717557 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.874913 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.825692 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.666414 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.851154 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.743445 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.008696 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.312860 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.396788 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.410104 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.215714 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.008696 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.312860 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447263 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.114504 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.396788 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.287459 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.410104 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84678.881041 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81708.061002 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 106347.886572 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1206.042193 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1025.284803 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1164.852074 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2611.595745 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 739.444003 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1248.357432 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84718.380410 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74384.426434 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 79785.147619 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 104673.151799 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 84694.023687 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107591.537912 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 89566.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 76013.873000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111029.587560 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 104673.151799 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 758 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 36.095238 # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 112095 # number of writebacks -system.l2c.writebacks::total 112095 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 11298 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1836 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 199729 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9030 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 11695 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 470 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1259 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1729 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 7024 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 6416 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 13440 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 18322 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 8252 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 213169 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 18322 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168230 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 8252 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18198 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 213169 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 816212498 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 127225500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 18781676635 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91207456 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26838142 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 118045598 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4758966 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12646753 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 17405719 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 507430588 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 396239520 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 903670108 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1323643086 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 523465020 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 19685346743 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1323643086 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16028508423 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1158500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 523465020 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1798396214 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 19685346743 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518668247 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263087751 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5781755998 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4095979500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150492500 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4246472000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614647747 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413580251 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10028227998 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235262 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138472 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.398091 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.757533 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.476996 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.717557 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.874913 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.825692 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.666414 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.851154 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.743445 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.410102 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.215714 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008696 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312860 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.114504 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.396788 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.287443 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.410102 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72243.981059 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69294.934641 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 94035.801686 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10100.493466 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.597373 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.680889 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10125.459574 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10045.077840 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10066.928282 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72242.395786 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61758.029925 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 67237.359226 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72243.373322 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95277.349004 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77233.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63434.927290 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98823.838554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 92346.198289 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA -system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA -system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA -system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU -system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post -system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR -system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post -system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR -system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post -system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR -system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post -system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR -system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post -system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR -system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR -system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post -system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR -system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post -system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -system.realview.ethernet.postedInterrupts 0 # number of posts to CPU -system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.physmem.actEnergy::0 358956360 # Energy for activate commands per rank (pJ) +system.physmem.actEnergy::1 341235720 # Energy for activate commands per rank (pJ) +system.physmem.preEnergy::0 195859125 # Energy for precharge commands per rank (pJ) +system.physmem.preEnergy::1 186190125 # Energy for precharge commands per rank (pJ) +system.physmem.readEnergy::0 862929600 # Energy for read commands per rank (pJ) +system.physmem.readEnergy::1 826854600 # Energy for read commands per rank (pJ) +system.physmem.writeEnergy::0 486680400 # Energy for write commands per rank (pJ) +system.physmem.writeEnergy::1 477919440 # Energy for write commands per rank (pJ) +system.physmem.refreshEnergy::0 185733231840 # Energy for refresh commands per rank (pJ) +system.physmem.refreshEnergy::1 185733231840 # Energy for refresh commands per rank (pJ) +system.physmem.actBackEnergy::0 81937929780 # Energy for active background per rank (pJ) +system.physmem.actBackEnergy::1 81435296655 # Energy for active background per rank (pJ) +system.physmem.preBackEnergy::0 1634313275250 # Energy for precharge background per rank (pJ) +system.physmem.preBackEnergy::1 1634754181500 # Energy for precharge background per rank (pJ) +system.physmem.totalEnergy::0 1903888862355 # Total energy per rank (pJ) +system.physmem.totalEnergy::1 1903754909880 # Total energy per rank (pJ) +system.physmem.averagePower::0 669.523453 # Core power per rank (mW) +system.physmem.averagePower::1 669.476347 # Core power per rank (mW) +system.realview.nvmem.bytes_read::cpu0.inst 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 768 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 1216 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 448 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 768 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 1216 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 7 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 19 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 158 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 270 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 428 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 158 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 270 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 428 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 158 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 270 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 428 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 668242 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 668227 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30931 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30931 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 252491 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 92430 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 40345 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 132775 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 38935 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 38935 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370727 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368021 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1738748 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41983735 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7870623 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 49854358 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 291977 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 1090667 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.033442 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.179788 # Request fanout histogram -system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 1054193 96.66% 96.66% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36474 3.34% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 1090667 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 1589069612 # Layer occupancy (ticks) -system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) -system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 2362873368 # Layer occupancy (ticks) -system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 802585372 # Layer occupancy (ticks) -system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31012 # Transaction distribution -system.iobus.trans_dist::ReadResp 31012 # Transaction distribution -system.iobus.trans_dist::WriteReq 59405 # Transaction distribution -system.iobus.trans_dist::WriteResp 59440 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateReq 35 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) -system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) -system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) -system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) -system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) -system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) -system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) -system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) -system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) -system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) -system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) -system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 326655076 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) -system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36825386 # Layer occupancy (ticks) -system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.branchPred.lookups 34893743 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17129146 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1674704 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20005904 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 14465623 # Number of BTB hits +system.cpu0.branchPred.lookups 34892527 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17126488 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1674515 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20008950 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 14462185 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.306770 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 10813555 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 822515 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.278580 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 10813099 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 822816 # Number of incorrect RAS predictions. +system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1024,25 +386,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23970791 # DTB read hits -system.cpu0.dtb.read_misses 62431 # DTB read misses -system.cpu0.dtb.write_hits 17948475 # DTB write hits -system.cpu0.dtb.write_misses 6765 # DTB write misses +system.cpu0.dtb.read_hits 23969265 # DTB read hits +system.cpu0.dtb.read_misses 62663 # DTB read misses +system.cpu0.dtb.write_hits 17948332 # DTB write hits +system.cpu0.dtb.write_misses 6711 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3473 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1381 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 1976 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3475 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1396 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1982 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24033222 # DTB read accesses -system.cpu0.dtb.write_accesses 17955240 # DTB write accesses +system.cpu0.dtb.perms_faults 568 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24031928 # DTB read accesses +system.cpu0.dtb.write_accesses 17955043 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41919266 # DTB hits -system.cpu0.dtb.misses 69196 # DTB misses -system.cpu0.dtb.accesses 41988462 # DTB accesses +system.cpu0.dtb.hits 41917597 # DTB hits +system.cpu0.dtb.misses 69374 # DTB misses +system.cpu0.dtb.accesses 41986971 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1064,8 +426,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 70366530 # ITB inst hits -system.cpu0.itb.inst_misses 3846 # ITB inst misses +system.cpu0.itb.inst_hits 70358748 # ITB inst hits +system.cpu0.itb.inst_misses 3854 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1078,79 +440,256 @@ system.cpu0.itb.flush_entries 2220 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 7369 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7388 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 70370376 # ITB inst accesses -system.cpu0.itb.hits 70366530 # DTB hits -system.cpu0.itb.misses 3846 # DTB misses -system.cpu0.itb.accesses 70370376 # DTB accesses -system.cpu0.numCycles 229133691 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70362602 # ITB inst accesses +system.cpu0.itb.hits 70358748 # DTB hits +system.cpu0.itb.misses 3854 # DTB misses +system.cpu0.itb.accesses 70362602 # DTB accesses +system.cpu0.numCycles 229119066 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 109191897 # Number of instructions committed -system.cpu0.committedOps 132018821 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8795011 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1826 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5458210303 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.098450 # CPI: cycles per instruction -system.cpu0.ipc 0.476542 # IPC: instructions per cycle +system.cpu0.committedInsts 109189984 # Number of instructions committed +system.cpu0.committedOps 132016369 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8791665 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1828 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5458204948 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.098352 # CPI: cycles per instruction +system.cpu0.ipc 0.476564 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed -system.cpu0.tickCycles 193242697 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 35890994 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 1983122 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.796419 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 68375163 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1983634 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.469647 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1830 # number of quiesce instructions executed +system.cpu0.tickCycles 193229301 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 35889765 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 714801 # number of replacements +system.cpu0.dcache.tags.tagsinuse 493.827802 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 40473769 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 715313 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 56.581901 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 493.827802 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.964507 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.964507 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id +system.cpu0.dcache.tags.tag_accesses 83782876 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83782876 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 22802755 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22802755 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862558 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 16862558 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381551 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 381551 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362630 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 362630 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.inst 39665313 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 39665313 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.inst 39665313 # number of overall hits +system.cpu0.dcache.overall_hits::total 39665313 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.inst 537301 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 537301 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.inst 532764 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 532764 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6412 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 6412 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20204 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20204 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.inst 1070065 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1070065 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.inst 1070065 # number of overall misses +system.cpu0.dcache.overall_misses::total 1070065 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609674711 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6609674711 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8019150247 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 8019150247 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 105707749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 105707749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 437634051 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 437634051 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 14628824958 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 14628824958 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 14628824958 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 14628824958 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23340056 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 23340056 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395322 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17395322 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387963 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 387963 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382834 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 382834 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 40735378 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40735378 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 40735378 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40735378 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023021 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.023021 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030627 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.030627 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016527 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016527 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052775 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052775 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026269 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026269 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026269 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.026269 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12301.623691 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 12301.623691 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15051.974696 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15051.974696 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16485.924672 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16485.924672 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21660.762770 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21660.762770 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13670.968547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13670.968547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13670.968547 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 517954 # number of writebacks +system.cpu0.dcache.writebacks::total 517954 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42678 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 42678 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230706 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 230706 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273384 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 273384 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273384 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 273384 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494623 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 494623 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302058 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 302058 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6411 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6411 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20204 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20204 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796681 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 796681 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796681 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 796681 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5117531439 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5117531439 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4270825900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4270825900 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 92832750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 92832750 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 396783949 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 396783949 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9388357339 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9388357339 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9388357339 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9388357339 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191310497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191310497 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803760492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803760492 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995070989 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995070989 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021192 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021192 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017364 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016525 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016525 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052775 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052775 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.019557 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019557 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.019557 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10346.327282 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10346.327282 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14139.092161 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14139.092161 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14480.229293 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14480.229293 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19638.880865 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19638.880865 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.336942 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.icache.tags.replacements 1983566 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.796833 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 68366923 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1984078 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 34.457780 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6227191000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796419 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999602 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999602 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.796833 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999603 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999603 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 222 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 106 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 182 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 223 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 107 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 142701293 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 142701293 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 68375163 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 68375163 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 68375163 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 68375163 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 68375163 # number of overall hits -system.cpu0.icache.overall_hits::total 68375163 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1983656 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1983656 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1983656 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1983656 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1983656 # number of overall misses -system.cpu0.icache.overall_misses::total 1983656 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16542962894 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 16542962894 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 16542962894 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 16542962894 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 16542962894 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 16542962894 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 70358819 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 70358819 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 70358819 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 70358819 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 70358819 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 70358819 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028193 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028193 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028193 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028193 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028193 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028193 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.632927 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.632927 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8339.632927 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.632927 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8339.632927 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 142686127 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 142686127 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 68366923 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 68366923 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 68366923 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 68366923 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 68366923 # number of overall hits +system.cpu0.icache.overall_hits::total 68366923 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1984094 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1984094 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1984094 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1984094 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1984094 # number of overall misses +system.cpu0.icache.overall_misses::total 1984094 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 16546799645 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 16546799645 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 16546799645 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 16546799645 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 16546799645 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 16546799645 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70351017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70351017 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70351017 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70351017 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70351017 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70351017 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028203 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028203 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028203 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028203 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028203 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028203 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8339.725661 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8339.725661 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8339.725661 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8339.725661 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8339.725661 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1159,376 +698,326 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1983656 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1983656 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1983656 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1983656 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1983656 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1983656 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13565509604 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 13565509604 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13565509604 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13565509604 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13565509604 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13565509604 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1984094 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1984094 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1984094 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1984094 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1984094 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1984094 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13568682853 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13568682853 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13568682853 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13568682853 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13568682853 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13568682853 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 276787500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 276787500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 276787500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 276787500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028193 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028193 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028193 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028193 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.640169 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.640169 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.640169 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028203 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028203 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028203 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028203 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6838.729845 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6838.729845 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6838.729845 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 2764616 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2669805 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28812 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 518092 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 696796 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 70569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42644 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 93797 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 291655 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 282058 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3973433 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393866 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 167556 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6546649 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127149824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86895095 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 313964 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 214376507 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1084116 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4385551 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.219745 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.414074 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 3421847 78.03% 78.03% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 963704 21.97% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4385551 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 2275908733 # Layer occupancy (ticks) -system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 119359000 # Layer occupancy (ticks) -system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 2981732395 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1235696460 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7392491 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 89085972 # Layer occupancy (ticks) -system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17333419 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425629 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16380209 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9025 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 17337039 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 425762 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 16383461 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 9078 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6465 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512088 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329549 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 6456 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 512279 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 1329409 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 409658 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16201.472263 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3013143 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 425913 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.074550 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 2824446064500 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4208.967244 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 47.817277 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.069510 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2196.768436 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.849796 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.256895 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.002919 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.replacements 409357 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16202.462840 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3013500 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 425611 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 7.080409 # Average number of references to valid blocks. +system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.l2cache.tags.occ_blocks::writebacks 4205.324174 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 51.364575 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.062072 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2198.474976 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9747.237044 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.256673 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003135 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134080 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594962 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.988859 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8953 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7296 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 51 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 115 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2849 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5159 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 779 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.134184 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.594924 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.988920 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8963 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7281 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 54 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 134 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 2805 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5150 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 820 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 48 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 289 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3166 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3507 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 286 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.546448 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.445312 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 55304097 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 55304097 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77521 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4240 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390628 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 2472389 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 518092 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 518092 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4676 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 4676 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2297 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 2297 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223112 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 223112 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77521 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4240 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 2613740 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2695501 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77521 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4240 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 2613740 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2695501 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 970 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 166 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94231 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 95367 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27951 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27951 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17951 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 17951 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 50 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 283 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 3125 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 3482 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 341 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.547058 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.444397 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 55309059 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 55309059 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 77781 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4268 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2390782 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 2472831 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 517951 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 517951 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4630 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 4630 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 2244 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 2244 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 223140 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 223140 # number of ReadExReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 77781 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4268 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 2613922 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 2695971 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 77781 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4268 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 2613922 # number of overall hits +system.cpu0.l2cache.overall_hits::total 2695971 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 986 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 94341 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 95500 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 27941 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27941 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 17958 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 17958 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46376 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46376 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 970 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 166 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 140607 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 141743 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 970 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 166 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 140607 # number of overall misses -system.cpu0.l2cache.overall_misses::total 141743 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 31913749 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3705999 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2892277884 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 2927897632 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 496957551 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 496957551 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 355013747 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 355013747 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 46352 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 46352 # number of ReadExReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 986 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 173 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 140693 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 141852 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 986 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 140693 # number of overall misses +system.cpu0.l2cache.overall_misses::total 141852 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 32261749 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3849999 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2894443882 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 2930555630 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 497270548 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 497270548 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354837739 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354837739 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 117000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 117000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1927567955 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 1927567955 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 31913749 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3705999 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4819845839 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 4855465587 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 31913749 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3705999 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4819845839 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 4855465587 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78491 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4406 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2484859 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 2567756 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 518092 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 518092 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32627 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 32627 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20248 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 20248 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 1925679719 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 1925679719 # number of ReadExReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 32261749 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3849999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4820123601 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 4856235349 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 32261749 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3849999 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4820123601 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 4856235349 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 78767 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4441 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2485123 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 2568331 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 517951 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 517951 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 32571 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 32571 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 20202 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 20202 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269488 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 269488 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78491 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4406 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 2754347 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 2837244 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78491 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4406 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 2754347 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 2837244 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.037676 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037922 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.037140 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.856683 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.856683 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.886557 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.886557 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 269492 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 269492 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 78767 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4441 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 2754615 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2837823 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 78767 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4441 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 2754615 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2837823 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.038955 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.037962 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.037184 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.857849 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.857849 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.888922 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.888922 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.172089 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.172089 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.037676 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051049 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.049958 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012358 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.037676 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051049 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.049958 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22325.295181 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30693.486050 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30701.370831 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17779.598261 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17779.598261 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19776.822851 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19776.822851 # average SCUpgradeReq miss latency +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.171998 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.171998 # miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.038955 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.051075 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.049986 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.012518 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.038955 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.051075 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.049986 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22254.329480 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 30680.657212 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 30686.446387 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17797.163595 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17797.163595 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19759.312785 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19759.312785 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 58500 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 58500 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41563.911398 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41563.911398 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 34255.417107 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32900.772165 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22325.295181 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34278.846992 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 34255.417107 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 26197 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 41544.695353 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 41544.695353 # average ReadExReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 34234.521537 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 32719.826572 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22254.329480 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 34259.867947 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 34234.521537 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 25463 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 374 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 375 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 70.045455 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 67.901333 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 214192 # number of writebacks -system.cpu0.l2cache.writebacks::total 214192 # number of writebacks -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7707 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 7707 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3080 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 3080 # number of ReadExReq MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10787 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 10787 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10787 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 10787 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 970 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 166 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86524 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 87660 # number of ReadReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 512085 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27951 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27951 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17951 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17951 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.writebacks::writebacks 214094 # number of writebacks +system.cpu0.l2cache.writebacks::total 214094 # number of writebacks +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 7763 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 7763 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3115 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 3115 # number of ReadExReq MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 10878 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 10878 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 10878 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 10878 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 986 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 86578 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 87737 # number of ReadReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 512278 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 27941 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27941 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 17958 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 17958 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43296 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 43296 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 970 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 166 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129820 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 130956 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 970 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 166 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129820 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512085 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 643041 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2543999 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121731252 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149385000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21314968847 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476593305 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476593305 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237494522 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237494522 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 43237 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 43237 # number of ReadExReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 986 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 129815 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 130974 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 986 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 129815 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 512278 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 643252 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2638999 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2121502252 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 2149486002 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 21334624793 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 476101816 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 476101816 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 237455029 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 237455029 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 89000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 89000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1192659250 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1192659250 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2543999 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3314390502 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 3342044250 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25109749 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2543999 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3314390502 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21314968847 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 24657013097 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176307748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176307748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587485503 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587485503 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763793251 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763793251 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034820 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034139 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1189409987 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1189409987 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2638999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 3310912239 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 3338895989 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 25344751 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2638999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 3310912239 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 21334624793 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 24673520782 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6176243748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6176243748 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4587514507 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4587514507 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10763758255 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10763758255 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.034839 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.034161 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.856683 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.856683 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.886557 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.886557 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.857849 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.857849 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.888922 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.888922 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160660 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160660 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046156 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012358 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.037676 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047133 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.160439 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.160439 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.046153 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.012518 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.038955 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.047126 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226643 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24521.881235 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24519.564225 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41623.888313 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17051.028765 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17051.028765 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13230.155535 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13230.155535 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.226671 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 24503.941556 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24499.196485 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 41646.576259 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17039.541033 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17039.541033 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13222.799254 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13222.799254 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 44500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 44500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27546.638258 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27546.638258 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25520.359892 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25886.339175 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15325.295181 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25530.661701 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41623.888313 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38344.387212 # average overall mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 27509.077572 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 27509.077572 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 25492.815284 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 25704.615619 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15254.329480 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 25504.851050 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 41646.576259 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 38357.472316 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1536,192 +1025,67 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 714989 # number of replacements -system.cpu0.dcache.tags.tagsinuse 494.379861 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 40475201 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 715501 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 56.569035 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 306537500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.379861 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965586 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.965586 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 135 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 308 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id -system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83786238 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83786238 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22803865 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22803865 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16862785 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 16862785 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381543 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 381543 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362585 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 362585 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39666650 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 39666650 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39666650 # number of overall hits -system.cpu0.dcache.overall_hits::total 39666650 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 537471 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 537471 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 532850 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 532850 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6422 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 6422 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 20250 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20250 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1070321 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1070321 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1070321 # number of overall misses -system.cpu0.dcache.overall_misses::total 1070321 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6609205728 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6609205728 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8024129751 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 8024129751 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 106247249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 106247249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438093543 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 438093543 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 129000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 129000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14633335479 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 14633335479 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14633335479 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 14633335479 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23341336 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23341336 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395635 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17395635 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387965 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 387965 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 382835 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40736971 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40736971 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40736971 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40736971 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023027 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.023027 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030631 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.030631 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016553 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016553 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.052895 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052895 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026274 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026274 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026274 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.026274 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12296.860162 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 12296.860162 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15058.890403 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15058.890403 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16544.261756 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16544.261756 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 21634.249037 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21634.249037 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13671.912892 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13671.912892 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13671.912892 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 518095 # number of writebacks -system.cpu0.dcache.writebacks::total 518095 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42683 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 42683 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230741 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 230741 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 1 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 1 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273424 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 273424 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273424 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 273424 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 494788 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 494788 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 302109 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 302109 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6421 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6421 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 20250 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20250 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 796897 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 796897 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 796897 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 796897 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5118044180 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5118044180 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4273159157 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4273159157 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 93352250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 93352250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397142457 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397142457 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 121000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 121000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9391203337 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9391203337 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9391203337 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 9391203337 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6191390497 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6191390497 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4803718496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4803718496 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995108993 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995108993 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021198 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021198 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017367 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017367 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016550 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016550 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.052895 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052895 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.019562 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019562 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.019562 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10343.913312 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10343.913312 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14144.428524 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14144.428524 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14538.584333 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14538.584333 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19611.973185 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19611.973185 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11784.714131 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 4041852 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2340524 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 248983 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2647417 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1629039 # Number of BTB hits +system.cpu0.toL2Bus.trans_dist::ReadReq 2765429 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2670282 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28813 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 517951 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 696439 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 70465 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42615 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 93717 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 291656 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 282057 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3974309 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2393187 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 11845 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 168040 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6547381 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 127177856 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 86874167 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 17764 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 315068 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 214384855 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1083965 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4385734 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.219720 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.414057 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 3422100 78.03% 78.03% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 963634 21.97% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::total 4385734 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2275890990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.snoopLayer0.occupancy 119346000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer0.occupancy 2982392646 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer1.occupancy 1235371968 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer2.occupancy 7407493 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu0.toL2Bus.respLayer3.occupancy 89292476 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.cpu1.branchPred.lookups 4040174 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2339682 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 248924 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2652147 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1629183 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 61.533147 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 795039 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 55831 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 61.428835 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 794888 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 55483 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1745,25 +1109,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4061119 # DTB read hits -system.cpu1.dtb.read_misses 20366 # DTB read misses -system.cpu1.dtb.write_hits 3327004 # DTB write hits -system.cpu1.dtb.write_misses 1507 # DTB write misses +system.cpu1.dtb.read_hits 4061400 # DTB read hits +system.cpu1.dtb.read_misses 20326 # DTB read misses +system.cpu1.dtb.write_hits 3327397 # DTB write hits +system.cpu1.dtb.write_misses 1493 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2038 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 134 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2042 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 130 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 315 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 275 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4081485 # DTB read accesses -system.cpu1.dtb.write_accesses 3328511 # DTB write accesses +system.cpu1.dtb.read_accesses 4081726 # DTB read accesses +system.cpu1.dtb.write_accesses 3328890 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7388123 # DTB hits -system.cpu1.dtb.misses 21873 # DTB misses -system.cpu1.dtb.accesses 7409996 # DTB accesses +system.cpu1.dtb.hits 7388797 # DTB hits +system.cpu1.dtb.misses 21819 # DTB misses +system.cpu1.dtb.accesses 7410616 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1785,8 +1149,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 7667797 # ITB inst hits -system.cpu1.itb.inst_misses 2228 # ITB inst misses +system.cpu1.itb.inst_hits 7665717 # ITB inst hits +system.cpu1.itb.inst_misses 2240 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1795,82 +1159,256 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1156 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1155 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1890 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7670025 # ITB inst accesses -system.cpu1.itb.hits 7667797 # DTB hits -system.cpu1.itb.misses 2228 # DTB misses -system.cpu1.itb.accesses 7670025 # DTB accesses -system.cpu1.numCycles 40526065 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7667957 # ITB inst accesses +system.cpu1.itb.hits 7665717 # DTB hits +system.cpu1.itb.misses 2240 # DTB misses +system.cpu1.itb.accesses 7667957 # DTB accesses +system.cpu1.numCycles 40520229 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 15860183 # Number of instructions committed -system.cpu1.committedOps 19387635 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1556469 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2802 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5646205885 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.555208 # CPI: cycles per instruction -system.cpu1.ipc 0.391358 # IPC: instructions per cycle +system.cpu1.committedInsts 15863154 # Number of instructions committed +system.cpu1.committedOps 19391289 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1555006 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2808 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5646190749 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.554361 # CPI: cycles per instruction +system.cpu1.ipc 0.391487 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2803 # number of quiesce instructions executed -system.cpu1.tickCycles 29467033 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 11059032 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 893075 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.459055 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6772156 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 893587 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.578620 # Average number of references to valid blocks. +system.cpu1.kern.inst.quiesce 2810 # number of quiesce instructions executed +system.cpu1.tickCycles 29462484 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 11057745 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 188500 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.724355 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6998456 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 188865 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 37.055336 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.inst 474.724355 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927196 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.927196 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 309 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 56 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 14854828 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 14854828 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.inst 3752021 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3752021 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051608 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3051608 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88860 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88860 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69213 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 69213 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.inst 6803629 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6803629 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.inst 6803629 # number of overall hits +system.cpu1.dcache.overall_hits::total 6803629 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.inst 182037 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 182037 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.inst 139457 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 139457 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5164 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 5164 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23160 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23160 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.inst 321494 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 321494 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.inst 321494 # number of overall misses +system.cpu1.dcache.overall_misses::total 321494 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2747896424 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2747896424 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3339347493 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 3339347493 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93721501 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 93721501 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540094758 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 540094758 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 317500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 317500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.inst 6087243917 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6087243917 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.inst 6087243917 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6087243917 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3934058 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3934058 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3191065 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3191065 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94024 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 94024 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92373 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 92373 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.inst 7125123 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7125123 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.inst 7125123 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7125123 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046272 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.046272 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043702 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.043702 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054922 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054922 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250723 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250723 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045121 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.045121 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045121 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.045121 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15095.263183 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15095.263183 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23945.355866 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 23945.355866 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18149.012587 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18149.012587 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23320.153627 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23320.153627 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 18934.238017 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18934.238017 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 18934.238017 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.writebacks::writebacks 115754 # number of writebacks +system.cpu1.dcache.writebacks::total 115754 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15456 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 15456 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49471 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 49471 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64927 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 64927 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64927 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 64927 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166581 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 166581 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89986 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 89986 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5164 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5164 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23160 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23160 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256567 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 256567 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256567 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256567 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2204876516 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2204876516 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 1996537354 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1996537354 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83385499 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83385499 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492548242 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492548242 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 303500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 303500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4201413870 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4201413870 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4201413870 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4201413870 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329634997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329634997 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202961999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202961999 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532596996 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532596996 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042343 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042343 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028199 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028199 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054922 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054922 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250723 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250723 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.036009 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036009 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.036009 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13236.062432 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13236.062432 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22187.199720 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22187.199720 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16147.463013 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16147.463013 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21267.195250 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21267.195250 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16375.503748 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.icache.tags.replacements 893030 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.459009 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6770083 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 893542 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.576681 # Average number of references to valid blocks. system.cpu1.icache.tags.warmup_cycle 71221486500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459055 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.459009 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975506 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 465 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 48 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 16225073 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 16225073 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6772156 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6772156 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6772156 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6772156 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6772156 # number of overall hits -system.cpu1.icache.overall_hits::total 6772156 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 893587 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 893587 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 893587 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 893587 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 893587 # number of overall misses -system.cpu1.icache.overall_misses::total 893587 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266352748 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7266352748 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7266352748 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7266352748 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7266352748 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7266352748 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7665743 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7665743 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7665743 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7665743 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7665743 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7665743 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116569 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.116569 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116569 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.116569 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116569 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.116569 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8131.667927 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8131.667927 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8131.667927 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8131.667927 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8131.667927 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 16220792 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 16220792 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6770083 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6770083 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6770083 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6770083 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6770083 # number of overall hits +system.cpu1.icache.overall_hits::total 6770083 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 893542 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 893542 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 893542 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 893542 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 893542 # number of overall misses +system.cpu1.icache.overall_misses::total 893542 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7266670468 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7266670468 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7266670468 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7266670468 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7266670468 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7266670468 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7663625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7663625 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7663625 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7663625 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7663625 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7663625 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.116595 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.116595 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.116595 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.116595 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.116595 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.116595 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8132.433023 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8132.433023 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8132.433023 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8132.433023 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8132.433023 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1879,362 +1417,310 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893587 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 893587 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 893587 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 893587 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 893587 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 893587 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923590752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923590752 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923590752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5923590752 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923590752 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5923590752 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 893542 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 893542 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 893542 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 893542 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 893542 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 893542 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5923954530 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5923954530 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5923954530 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5923954530 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5923954530 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5923954530 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 10589750 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 10589750 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 10589750 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 10589750 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116569 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.116569 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116569 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.116569 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.002830 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.002830 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.002830 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.116595 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.116595 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.116595 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.116595 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6629.743795 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6629.743795 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6629.743795 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1582924 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1137885 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2119 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 115746 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 150971 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36231 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 84405 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41125 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85149 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 76810 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 64398 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787404 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 768912 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6948 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51790 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2615054 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57196928 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24920351 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10668 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 94516 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 82222463 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 838516 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2085340 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.363825 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.481099 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1326642 63.62% 63.62% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 758698 36.38% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2085340 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 782793185 # Layer occupancy (ticks) -system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78444000 # Layer occupancy (ticks) -system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1341767498 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381370915 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 4282497 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 28163996 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7065047 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40428 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914930 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1457 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 7064659 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 40510 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6914419 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 1409 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2607 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105625 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724673 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2627 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 105694 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 724613 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 79629 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15528.716598 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1138081 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 94994 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 11.980557 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.replacements 80002 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15534.005683 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1138706 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 95380 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.938624 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6912.222509 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 24.793124 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.117245 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2315.760796 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6275.822923 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.421889 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001513 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.141343 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383046 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.947798 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10144 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 29 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5192 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6818 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3193 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 6881.050205 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.485106 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.098583 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2338.762949 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 6287.608842 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.419986 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001617 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000006 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.142747 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.383765 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.948120 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 10071 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5273 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 6676 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 3263 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 17 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 243 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3095 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1854 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.619141 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001770 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.316895 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 21374644 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 21374644 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 23037 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2415 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993214 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 1018666 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 115746 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 115746 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1782 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1782 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 772 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 772 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27747 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 27747 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 23037 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2415 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1020961 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1046413 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 23037 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2415 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1020961 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1046413 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 592 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 252 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72082 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 72926 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28135 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 28135 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22404 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22404 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32295 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32295 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 592 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 252 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 104377 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 105221 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 592 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 252 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 104377 # number of overall misses -system.cpu1.l2cache.overall_misses::total 105221 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13156500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5072997 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1619935379 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1638164876 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531136882 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 531136882 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440134565 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440134565 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 329000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 329000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1130691878 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1130691878 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13156500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5072997 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750627257 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2768856754 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13156500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5072997 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750627257 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2768856754 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23629 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2667 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065296 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1091592 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 115746 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 115746 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29917 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29917 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23176 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23176 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60042 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 60042 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23629 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2667 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1125338 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1151634 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23629 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2667 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1125338 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1151634 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.094488 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067664 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.066807 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.940435 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.940435 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.966690 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.966690 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537873 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537873 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.094488 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092752 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.091367 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025054 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.094488 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092752 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.091367 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20130.940476 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22473.507658 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22463.385843 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18878.154683 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18878.154683 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19645.356410 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19645.356410 # average SCUpgradeReq miss latency +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 237 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 3167 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 1869 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.614685 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.321838 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 21370209 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 21370209 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 22701 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2439 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993088 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 1018228 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 115754 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 115754 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 740 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 740 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 27796 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27796 # number of ReadExReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 22701 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2439 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 1020884 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 1046024 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 22701 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2439 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 1020884 # number of overall hits +system.cpu1.l2cache.overall_hits::total 1046024 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 604 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 72199 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 73046 # number of ReadReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28140 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 28140 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22420 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22420 # number of SCUpgradeReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 32240 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 32240 # number of ReadExReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 604 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 104439 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 105286 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 604 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 104439 # number of overall misses +system.cpu1.l2cache.overall_misses::total 105286 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13239000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4899500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1623706138 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 1641844638 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 531483393 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 531483393 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440502566 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440502566 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 296000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 296000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1126750383 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1126750383 # number of ReadExReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13239000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4899500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2750456521 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 2768595021 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13239000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4899500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2750456521 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 2768595021 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 23305 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2682 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1065287 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 1091274 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 115754 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 115754 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29950 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 29950 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23160 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23160 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60036 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 60036 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 23305 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2682 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 1125323 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 1151310 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 23305 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2682 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 1125323 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 1151310 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090604 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.067774 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.066936 # miss rate for ReadReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.939566 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.939566 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.968048 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.968048 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.537011 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.537011 # miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.090604 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.092808 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.091449 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.025917 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.090604 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.092808 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.091449 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20162.551440 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 22489.316168 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 22476.858938 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18887.114179 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18887.114179 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19647.750491 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19647.750491 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 35011.360211 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 35011.360211 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 26314.678192 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22223.817568 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20130.940476 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26352.810073 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 26314.678192 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 4757 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 34948.833220 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 34948.833220 # average ReadExReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 26295.946479 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21918.874172 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20162.551440 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 26335.530989 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 26295.946479 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 4629 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.blocked::no_mshrs 158 # number of cycles access was blocked +system.cpu1.l2cache.blocked::no_mshrs 159 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 30.107595 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 29.113208 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 38299 # number of writebacks -system.cpu1.l2cache.writebacks::total 38299 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1547 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 1547 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 321 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 321 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1868 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 1868 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1868 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 1868 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 592 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 252 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70535 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 71379 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 105624 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28135 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28135 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22404 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22404 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31974 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 31974 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 592 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 252 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102509 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 103353 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 592 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 252 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102509 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105624 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 208977 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3308997 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1095971987 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1108291484 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2952900698 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404207806 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404207806 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308121722 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308121722 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 273000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 273000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 864621339 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 864621339 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3308997 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960593326 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 1972912823 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9010500 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3308997 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960593326 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2952900698 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4925813521 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316590752 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316590752 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186920002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186920002 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503510754 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503510754 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066212 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065390 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.writebacks::writebacks 38442 # number of writebacks +system.cpu1.l2cache.writebacks::total 38442 # number of writebacks +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 1604 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 1604 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 322 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 322 # number of ReadExReq MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 1926 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1926 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 1926 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1926 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 604 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 243 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 70595 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 71442 # number of ReadReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 105694 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28140 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28140 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22420 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22420 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 31918 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 31918 # number of ReadExReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 604 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 243 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 102513 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 103360 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 604 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 243 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 102513 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 105694 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 209054 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3198500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1098179235 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1110385737 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 2958247424 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 404415795 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 404415795 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 308218727 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 308218727 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 247000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 247000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 862164082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 862164082 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3198500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 1960343317 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 1972549819 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 9008002 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3198500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 1960343317 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 2958247424 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4930797243 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316625253 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316625253 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 186937501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 186937501 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 503562754 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 503562754 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.066269 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.065467 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.940435 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.940435 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.966690 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.966690 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.532527 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.532527 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089745 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025054 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.094488 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091092 # mshr miss rate for overall accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.939566 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.939566 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.968048 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.968048 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.531648 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.531648 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.089776 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.025917 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090604 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.091097 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181461 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15537.988048 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15526.856414 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27956.720991 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14366.724933 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14366.724933 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13752.978129 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13752.978129 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.181579 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 15556.048375 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15542.478332 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 27988.792401 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14371.563433 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14371.563433 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13747.490054 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13747.490054 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27041.387971 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27041.387971 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19089.071657 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15220.439189 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13130.940476 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19126.060404 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27956.720991 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23571.079693 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27011.845416 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27011.845416 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 19084.266825 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14913.910596 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13162.551440 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 19122.875313 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 27988.792401 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23586.237254 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2242,232 +1728,213 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 188481 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.009191 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6997616 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 188846 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 37.054616 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 107393225500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 475.009191 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.927752 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.927752 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 308 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 57 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.712891 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 14853075 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 14853075 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3751603 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3751603 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3051213 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3051213 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 88863 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88863 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69198 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 69198 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 6802816 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6802816 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 6802816 # number of overall hits -system.cpu1.dcache.overall_hits::total 6802816 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 182008 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 182008 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 139434 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 139434 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5163 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 5163 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23176 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23176 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 321442 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 321442 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 321442 # number of overall misses -system.cpu1.dcache.overall_misses::total 321442 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2744686684 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2744686684 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3345931004 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 3345931004 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 93833250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 93833250 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540125753 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 540125753 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 353500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 353500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6090617688 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6090617688 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6090617688 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6090617688 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3933611 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3933611 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3190647 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3190647 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94026 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 94026 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92374 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 92374 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7124258 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7124258 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7124258 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7124258 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046270 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.046270 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043701 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.043701 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.054910 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.054910 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.250893 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250893 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.045119 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.045119 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.045119 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.045119 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 15080.033207 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15080.033207 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 23996.521681 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 23996.521681 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18174.171993 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18174.171993 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23305.391483 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23305.391483 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 18947.796766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 18947.796766 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18947.796766 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 115746 # number of writebacks -system.cpu1.dcache.writebacks::total 115746 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15462 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 15462 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49475 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 49475 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 64937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 64937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166546 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 166546 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89959 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 89959 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5163 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5163 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23176 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23176 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256505 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 256505 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256505 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256505 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202025254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202025254 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2000006836 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2000006836 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 83498750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 83498750 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492542247 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492542247 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 337500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 337500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4202032090 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4202032090 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4202032090 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4202032090 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 329591498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 329591498 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 202938498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 202938498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 532529996 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 532529996 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042339 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042339 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.028195 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028195 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.054910 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054910 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.250893 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250893 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.036004 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.036004 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.036004 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13221.724052 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13221.724052 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 22232.426283 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 22232.426283 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16172.525663 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16172.525663 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21252.254358 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21252.254358 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16381.872049 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.toL2Bus.trans_dist::ReadReq 1582615 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1137834 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2120 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2120 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 115754 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 151048 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 84372 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41116 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85179 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 76804 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 64396 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1787314 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 769072 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6988 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 51360 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2614734 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 57194048 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24925415 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10728 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 93220 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 82223411 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 838592 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2085067 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.363773 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.481085 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1326575 63.62% 63.62% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 758492 36.38% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::total 2085067 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 782771935 # Layer occupancy (ticks) +system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78513000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer0.occupancy 1341710719 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 381436893 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer2.occupancy 4307996 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer3.occupancy 28057498 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.trans_dist::ReadReq 31012 # Transaction distribution +system.iobus.trans_dist::ReadResp 31012 # Transaction distribution +system.iobus.trans_dist::WriteReq 59407 # Transaction distribution +system.iobus.trans_dist::WriteResp 59440 # Transaction distribution +system.iobus.trans_dist::WriteInvalidateReq 33 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56656 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107970 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180904 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71600 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162850 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484026 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 40136000 # Layer occupancy (ticks) +system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer1.occupancy 90000 # Layer occupancy (ticks) +system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer2.occupancy 26000 # Layer occupancy (ticks) +system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer3.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer6.occupancy 74000 # Layer occupancy (ticks) +system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 506000 # Layer occupancy (ticks) +system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer10.occupancy 17000 # Layer occupancy (ticks) +system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer16.occupancy 40000 # Layer occupancy (ticks) +system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks) +system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer23.occupancy 5287000 # Layer occupancy (ticks) +system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer24.occupancy 143000 # Layer occupancy (ticks) +system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer25.occupancy 30680000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) +system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer27.occupancy 326658321 # Layer occupancy (ticks) +system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer0.occupancy 84754000 # Layer occupancy (ticks) +system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.iobus.respLayer3.occupancy 36824131 # Layer occupancy (ticks) +system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36417 # number of replacements -system.iocache.tags.tagsinuse 0.992209 # Cycle average of tags in use +system.iocache.tags.tagsinuse 0.992159 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36433 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. system.iocache.tags.warmup_cycle 268855800000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 0.992209 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062013 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062013 # Average percentage of cache occupancy +system.iocache.tags.occ_blocks::realview.ide 0.992159 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062010 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062010 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328483 # Number of tag accesses -system.iocache.tags.data_accesses 328483 # Number of data accesses +system.iocache.tags.tag_accesses 328467 # Number of tag accesses +system.iocache.tags.data_accesses 328467 # Number of data accesses system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses system.iocache.ReadReq_misses::total 243 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 35 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 35 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::realview.ide 33 # number of WriteInvalidateReq misses +system.iocache.WriteInvalidateReq_misses::total 33 # number of WriteInvalidateReq misses system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31692627 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31692627 # number of ReadReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31692627 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31692627 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31692627 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31692627 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31254127 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31254127 # number of ReadReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31254127 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31254127 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31254127 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31254127 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36259 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36259 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::realview.ide 36257 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteInvalidateReq_accesses::total 36257 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000965 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 0.000965 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000910 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteInvalidateReq_miss_rate::total 0.000910 # miss rate for WriteInvalidateReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130422.333333 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130422.333333 # average ReadReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130422.333333 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130422.333333 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130422.333333 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 128617.806584 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128617.806584 # average ReadReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128617.806584 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128617.806584 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128617.806584 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2482,28 +1949,565 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19056127 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19056127 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2259252335 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2259252335 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19056127 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19056127 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19056127 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19056127 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 18617627 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 18617627 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 2261621825 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 2261621825 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 18617627 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 18617627 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 18617627 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 18617627 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78420.275720 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 78420.275720 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76615.748971 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 76615.748971 # average ReadReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 78420.275720 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 78420.275720 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 76615.748971 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 76615.748971 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2c.tags.replacements 151810 # number of replacements +system.l2c.tags.tagsinuse 64480.586594 # Cycle average of tags in use +system.l2c.tags.total_refs 529933 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 216565 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.446993 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 12374.174406 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.831156 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030524 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 3874.361594 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 42727.383721 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 10.891665 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 757.615436 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4654.298093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.188815 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001249 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.059118 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.651968 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.011560 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.071019 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.983896 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 46322 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 18386 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 286 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6596 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 39440 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 8 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 273 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 2604 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 15495 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.706818 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.280548 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6644341 # Number of tag accesses +system.l2c.tags.data_accesses 6644341 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 563 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 116 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 36701 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 207577 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 56 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 11433 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 45418 # number of ReadReq hits +system.l2c.ReadReq_hits::total 301993 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 252536 # number of Writeback hits +system.l2c.Writeback_hits::total 252536 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 11942 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 830 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 12772 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 205 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.inst 179 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 384 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 3525 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 1107 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4632 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 563 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 116 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 40226 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 207577 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 56 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 12540 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 45418 # number of demand (read+write) hits +system.l2c.demand_hits::total 306625 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 563 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 116 # number of overall hits +system.l2c.overall_hits::cpu0.inst 40226 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 207577 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 129 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 56 # number of overall hits +system.l2c.overall_hits::cpu1.inst 12540 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 45418 # number of overall hits +system.l2c.overall_hits::total 306625 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 151 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 11286 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 15 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1852 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 18208 # number of ReadReq misses +system.l2c.ReadReq_misses::total 199810 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 9028 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 2665 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 11693 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 461 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1254 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1715 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 7011 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 6410 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 13421 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 151 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 18297 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 15 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 8262 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 18208 # number of demand (read+write) misses +system.l2c.demand_misses::total 213231 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 151 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.inst 18297 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 168297 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 15 # number of overall misses +system.l2c.overall_misses::cpu1.inst 8262 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 18208 # number of overall misses +system.l2c.overall_misses::total 213231 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 11975000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 955847998 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1150500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 151717498 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 21276600608 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.inst 10528075 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.inst 2736385 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 13264460 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 1131453 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 1006958 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2138411 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.inst 592519659 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.inst 475914481 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1068434140 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 11975000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1548367657 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1150500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 627631979 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 22345034748 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 11975000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1548367657 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 18133044658 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1150500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 627631979 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 2022789954 # number of overall miss cycles +system.l2c.overall_miss_latency::total 22345034748 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 714 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 117 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 47987 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 375874 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 56 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 13285 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 63626 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 501803 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 252536 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 252536 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.inst 20970 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.inst 3495 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 24465 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.inst 666 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.inst 1433 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2099 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.inst 10536 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.inst 7517 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 18053 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 714 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 117 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 58523 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 375874 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 144 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 56 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 20802 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 63626 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 519856 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 714 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 117 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 58523 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 375874 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 144 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 56 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 20802 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 63626 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 519856 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.008547 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.235189 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.139405 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.398184 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.430520 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.762518 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.477948 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.692192 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.875087 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.817056 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.inst 0.665433 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.inst 0.852734 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.743422 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.008547 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.312646 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.397173 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.410173 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.211485 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.008547 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.312646 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.447748 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.104167 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.397173 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.286172 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.410173 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 84693.248095 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 76700 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 81920.895248 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 106484.162995 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 1166.158064 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 1026.786116 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1134.393227 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 2454.344902 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 802.996810 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1246.886880 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 84512.859649 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 74245.628861 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 79609.130467 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 104792.618090 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 79304.635762 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 84624.127289 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 107744.313077 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 76700 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75966.107359 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 111093.472869 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 104792.618090 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 845 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 26 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 32.500000 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 112127 # number of writebacks +system.l2c.writebacks::total 112127 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu1.l2cache.prefetcher 1 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 1 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu1.l2cache.prefetcher 1 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 1 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu1.l2cache.prefetcher 1 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 1 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 151 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 11286 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 15 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1852 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 199809 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.inst 9028 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2665 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 11693 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 461 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1254 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1715 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.inst 7011 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.inst 6410 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 13421 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 18297 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 15 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 8262 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 213230 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 151 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 18297 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 168297 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 15 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 8262 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 18207 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 213230 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 815475498 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 965000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 128728998 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 18816537858 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91196953 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 26828647 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 118025600 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 4664957 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 12607247 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 17272204 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 505062337 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 394979019 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 900041356 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1320537835 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 965000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 523708017 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 19716579214 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10113000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1320537835 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 16060717158 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 965000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 523708017 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1800475704 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 19716579214 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5518590247 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263108750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5781698997 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096001500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150494000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4246495500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9614591747 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413602750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10028194497 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.235189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.139405 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.398182 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.430520 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.762518 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.477948 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.692192 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.875087 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.817056 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.665433 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.852734 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.743422 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.410171 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.211485 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.008547 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.312646 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.447748 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.104167 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.397173 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.286157 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.410171 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 72255.493355 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 69508.098272 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 94172.624146 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10101.567678 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10067.034522 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10093.697084 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10119.212581 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10053.625997 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.255977 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 72038.558979 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61619.191732 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 67062.167946 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 66973.509934 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72172.368968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 95430.798873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 64333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63387.559550 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 98889.202175 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 92466.253407 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadReq 238091 # Transaction distribution +system.membus.trans_dist::ReadResp 238091 # Transaction distribution +system.membus.trans_dist::WriteReq 30933 # Transaction distribution +system.membus.trans_dist::WriteResp 30933 # Transaction distribution +system.membus.trans_dist::Writeback 112127 # Transaction distribution +system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.membus.trans_dist::UpgradeReq 79652 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 39985 # Transaction distribution +system.membus.trans_dist::UpgradeResp 13516 # Transaction distribution +system.membus.trans_dist::ReadExReq 30363 # Transaction distribution +system.membus.trans_dist::ReadExResp 13313 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107970 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 38 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13576 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 704934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 826518 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72706 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 899224 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162850 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27152 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 21038188 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21229406 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2319296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23548702 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123399 # Total snoops (count) +system.membus.snoop_fanout::samples 498406 # Request fanout histogram +system.membus.snoop_fanout::mean 1 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::1 498406 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 1 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 498406 # Request fanout histogram +system.membus.reqLayer0.occupancy 87864494 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer1.occupancy 22828 # Layer occupancy (ticks) +system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer2.occupancy 11666999 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 1620379248 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) +system.membus.respLayer2.occupancy 2120601580 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.1 # Layer utilization (%) +system.membus.respLayer3.occupancy 38542869 # Layer occupancy (ticks) +system.membus.respLayer3.utilization 0.0 # Layer utilization (%) +system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA +system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA +system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU +system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR +system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU +system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR +system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU +system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR +system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU +system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR +system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU +system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR +system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU +system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post +system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU +system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR +system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU +system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR +system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post +system.realview.ethernet.postedInterrupts 0 # number of posts to CPU +system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.toL2Bus.trans_dist::ReadReq 668340 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 668325 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30933 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30933 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 252536 # Transaction distribution +system.toL2Bus.trans_dist::WriteInvalidateReq 36227 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 92316 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 40369 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 132685 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 11 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 38932 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 38932 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1370044 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 368770 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1738814 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 41959415 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7901735 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 49861150 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 291964 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1090717 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.033437 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.179774 # Request fanout histogram +system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1054247 96.66% 96.66% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 36470 3.34% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram +system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram +system.toL2Bus.snoop_fanout::total 1090717 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 1589301055 # Layer occupancy (ticks) +system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.snoopLayer0.occupancy 1026000 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) +system.toL2Bus.respLayer0.occupancy 2361799867 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.toL2Bus.respLayer1.occupancy 804005619 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |