diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-16 13:03:49 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2016-03-16 13:03:49 -0700 |
| commit | f5d1dd75e57d9c63c5f6ab4d0c7c0c45f8726a95 (patch) | |
| tree | b50e0c7255009e7be347963024ad24fe574e1f17 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual | |
| parent | d7f18fa6fab4b9941f94066af5eaeb975dd7597e (diff) | |
| download | gem5-f5d1dd75e57d9c63c5f6ab4d0c7c0c45f8726a95.tar.xz | |
stats: overdue updates to long regressions
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual')
4 files changed, 2358 insertions, 2357 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini index 979ece788..b7f7bfe13 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/config.ini @@ -12,14 +12,15 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 +exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false @@ -28,7 +29,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -43,7 +44,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -86,7 +87,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -188,7 +189,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -649,7 +649,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 @@ -762,7 +761,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_excl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 @@ -822,6 +820,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -933,7 +932,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=2 is_read_only=false max_miss_count=0 @@ -1394,7 +1392,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=1 is_read_only=true max_miss_count=0 @@ -1507,7 +1504,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_excl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=12 is_read_only=false max_miss_count=0 @@ -1567,6 +1563,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1629,7 +1626,6 @@ clk_domain=system.clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=false hit_latency=50 is_read_only=false max_miss_count=0 @@ -1666,7 +1662,6 @@ clk_domain=system.cpu_clk_domain clusivity=mostly_incl demand_mshr_reserve=1 eventq_index=0 -forward_snoops=true hit_latency=20 is_read_only=false max_miss_count=0 @@ -1701,6 +1696,7 @@ clk_domain=system.clk_domain eventq_index=0 forward_latency=4 frontend_latency=3 +point_of_coherency=true response_latency=2 snoop_filter=Null snoop_response_latency=4 @@ -2590,6 +2586,7 @@ clk_domain=system.cpu_clk_domain eventq_index=0 forward_latency=0 frontend_latency=1 +point_of_coherency=false response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout index 0dba6a71c..fe36facf2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/simout @@ -1,16 +1,18 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 4 2015 11:13:17 -gem5 started Dec 4 2015 12:40:05 -gem5 executing on e104799-lin, pid 5560 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual +gem5 compiled Mar 15 2016 21:26:42 +gem5 started Mar 15 2016 21:34:30 +gem5 executing on phenom, pid 15961 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-minor-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -27,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2848979128500 because m5_exit instruction encountered +Exiting @ tick 2649116242500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index e7604208d..e45890e36 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848869 # Number of seconds simulated -sim_ticks 2848869082500 # Number of ticks simulated -final_tick 2848869082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.649116 # Number of seconds simulated +sim_ticks 2649116242500 # Number of ticks simulated +final_tick 2649116242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 198569 # Simulator instruction rate (inst/s) -host_op_rate 240456 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4442491449 # Simulator tick rate (ticks/s) -host_mem_usage 621364 # Number of bytes of host memory used -host_seconds 641.28 # Real time elapsed on the host -sim_insts 127338052 # Number of instructions simulated -sim_ops 154199103 # Number of ops (including micro ops) simulated +host_inst_rate 120147 # Simulator instruction rate (inst/s) +host_op_rate 145490 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2497044812 # Simulator tick rate (ticks/s) +host_mem_usage 602856 # Number of bytes of host memory used +host_seconds 1060.90 # Real time elapsed on the host +sim_insts 127464482 # Number of instructions simulated +sim_ops 154350851 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8704 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 7744 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1697856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1350060 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8564736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 206784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 630484 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 333888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1526336 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1246188 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8224576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 2560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 394816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 723292 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 617536 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12794304 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1697856 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 206784 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1904640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8859904 # Number of bytes written to this memory +system.physmem.bytes_read::total 12744072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1526336 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 394816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1921152 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8953600 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8877468 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 136 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8971164 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 121 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26529 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133824 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3231 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9872 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5217 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 23849 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19993 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 128509 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 40 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11324 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 9649 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200453 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138436 # Number of write requests responded to by this memory +system.physmem.num_reads::total 199670 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139900 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142827 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 3055 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 595975 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 473893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3006363 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 72585 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 221310 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 117200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4491012 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 595975 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 72585 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 668560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3109972 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3116138 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3109972 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 3055 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 595975 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 480045 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3006363 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 72585 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 221324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 117200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7607149 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200453 # Number of read requests accepted -system.physmem.writeReqs 142827 # Number of write requests accepted -system.physmem.readBursts 200453 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 142827 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12818368 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue -system.physmem.bytesWritten 8890624 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12794304 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8877468 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue +system.physmem.num_writes::total 144291 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 2923 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 24 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 576168 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 470417 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3104649 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 966 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 149037 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 273031 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 233110 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 362 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4810688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 576168 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 149037 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 725205 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3379844 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6615 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3386474 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3379844 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 2923 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 576168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 477032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3104649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 149037 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 273047 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 233110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 362 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 8197162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 199670 # Number of read requests accepted +system.physmem.writeReqs 144291 # Number of write requests accepted +system.physmem.readBursts 199670 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144291 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12768704 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10176 # Total number of bytes read from write queue +system.physmem.bytesWritten 8984192 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12744072 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8971164 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 159 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12269 # Per bank write bursts -system.physmem.perBankRdBursts::1 12614 # Per bank write bursts -system.physmem.perBankRdBursts::2 13475 # Per bank write bursts -system.physmem.perBankRdBursts::3 12831 # Per bank write bursts -system.physmem.perBankRdBursts::4 15664 # Per bank write bursts -system.physmem.perBankRdBursts::5 12720 # Per bank write bursts -system.physmem.perBankRdBursts::6 12662 # Per bank write bursts -system.physmem.perBankRdBursts::7 12956 # Per bank write bursts -system.physmem.perBankRdBursts::8 12071 # Per bank write bursts -system.physmem.perBankRdBursts::9 12246 # Per bank write bursts -system.physmem.perBankRdBursts::10 11615 # Per bank write bursts -system.physmem.perBankRdBursts::11 10653 # Per bank write bursts -system.physmem.perBankRdBursts::12 11883 # Per bank write bursts -system.physmem.perBankRdBursts::13 12836 # Per bank write bursts -system.physmem.perBankRdBursts::14 12055 # Per bank write bursts -system.physmem.perBankRdBursts::15 11737 # Per bank write bursts -system.physmem.perBankWrBursts::0 8758 # Per bank write bursts -system.physmem.perBankWrBursts::1 9183 # Per bank write bursts -system.physmem.perBankWrBursts::2 9791 # Per bank write bursts -system.physmem.perBankWrBursts::3 9102 # Per bank write bursts -system.physmem.perBankWrBursts::4 8279 # Per bank write bursts -system.physmem.perBankWrBursts::5 8882 # Per bank write bursts -system.physmem.perBankWrBursts::6 8907 # Per bank write bursts -system.physmem.perBankWrBursts::7 8993 # Per bank write bursts -system.physmem.perBankWrBursts::8 8509 # Per bank write bursts -system.physmem.perBankWrBursts::9 8693 # Per bank write bursts -system.physmem.perBankWrBursts::10 8248 # Per bank write bursts -system.physmem.perBankWrBursts::11 7749 # Per bank write bursts -system.physmem.perBankWrBursts::12 8519 # Per bank write bursts -system.physmem.perBankWrBursts::13 8825 # Per bank write bursts -system.physmem.perBankWrBursts::14 8545 # Per bank write bursts -system.physmem.perBankWrBursts::15 7933 # Per bank write bursts +system.physmem.perBankRdBursts::0 12456 # Per bank write bursts +system.physmem.perBankRdBursts::1 12907 # Per bank write bursts +system.physmem.perBankRdBursts::2 13452 # Per bank write bursts +system.physmem.perBankRdBursts::3 12663 # Per bank write bursts +system.physmem.perBankRdBursts::4 15992 # Per bank write bursts +system.physmem.perBankRdBursts::5 12602 # Per bank write bursts +system.physmem.perBankRdBursts::6 12853 # Per bank write bursts +system.physmem.perBankRdBursts::7 13005 # Per bank write bursts +system.physmem.perBankRdBursts::8 12164 # Per bank write bursts +system.physmem.perBankRdBursts::9 12306 # Per bank write bursts +system.physmem.perBankRdBursts::10 11290 # Per bank write bursts +system.physmem.perBankRdBursts::11 10778 # Per bank write bursts +system.physmem.perBankRdBursts::12 11668 # Per bank write bursts +system.physmem.perBankRdBursts::13 12164 # Per bank write bursts +system.physmem.perBankRdBursts::14 11811 # Per bank write bursts +system.physmem.perBankRdBursts::15 11400 # Per bank write bursts +system.physmem.perBankWrBursts::0 8970 # Per bank write bursts +system.physmem.perBankWrBursts::1 9418 # Per bank write bursts +system.physmem.perBankWrBursts::2 9818 # Per bank write bursts +system.physmem.perBankWrBursts::3 9016 # Per bank write bursts +system.physmem.perBankWrBursts::4 8619 # Per bank write bursts +system.physmem.perBankWrBursts::5 8911 # Per bank write bursts +system.physmem.perBankWrBursts::6 9199 # Per bank write bursts +system.physmem.perBankWrBursts::7 9114 # Per bank write bursts +system.physmem.perBankWrBursts::8 8718 # Per bank write bursts +system.physmem.perBankWrBursts::9 8852 # Per bank write bursts +system.physmem.perBankWrBursts::10 8120 # Per bank write bursts +system.physmem.perBankWrBursts::11 7867 # Per bank write bursts +system.physmem.perBankWrBursts::12 8570 # Per bank write bursts +system.physmem.perBankWrBursts::13 8570 # Per bank write bursts +system.physmem.perBankWrBursts::14 8685 # Per bank write bursts +system.physmem.perBankWrBursts::15 7931 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 22 # Number of times write queue was full causing retry -system.physmem.totGap 2848868537000 # Total gap between requests +system.physmem.numWrRetry 32 # Number of times write queue was full causing retry +system.physmem.totGap 2649115714000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 552 # Read request sizes (log2) +system.physmem.readPktSize::2 554 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199873 # Read request sizes (log2) +system.physmem.readPktSize::6 199088 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138436 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 88840 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 61310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9520 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7786 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6277 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4618 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 139900 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 88665 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 60851 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11657 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9446 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7750 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6278 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3733 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 673 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 165 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 148 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 126 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -184,158 +184,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2746 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6227 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6320 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6684 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7381 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 8854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9840 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11658 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8119 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 84 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5326 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5137 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7386 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8198 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8939 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 8912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9656 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11650 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8389 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1203 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 417 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 213 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 138 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 150 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 85 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92557 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.543816 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.254652 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.662523 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50344 54.39% 54.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17979 19.42% 73.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6295 6.80% 80.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3544 3.83% 84.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2825 3.05% 87.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1428 1.54% 89.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 907 0.98% 90.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1020 1.10% 91.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8215 8.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92557 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6759 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.632490 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 567.452985 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6758 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::56 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 69 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 58 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 103 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 93964 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 231.501767 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 131.710526 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 295.455834 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 51656 54.97% 54.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 18156 19.32% 74.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6272 6.67% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3449 3.67% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2927 3.12% 87.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1465 1.56% 89.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 883 0.94% 90.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 950 1.01% 91.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8206 8.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 93964 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6826 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.227952 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.671734 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6825 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6759 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6759 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.552744 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.790179 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 13.439026 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5671 83.90% 83.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 455 6.73% 90.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 79 1.17% 91.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 48 0.71% 92.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 32 0.47% 92.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 21 0.31% 93.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 53 0.78% 94.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 14 0.21% 94.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 132 1.95% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 15 0.22% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 4 0.06% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 13 0.19% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 74 1.09% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 5 0.07% 97.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.04% 97.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.38% 98.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 85 1.26% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.04% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 2 0.03% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 6 0.09% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6759 # Writes before turning the bus around for reads -system.physmem.totQLat 5409044047 # Total ticks spent queuing -system.physmem.totMemAccLat 9164425297 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1001435000 # Total ticks spent in databus transfers -system.physmem.avgQLat 27006.47 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6826 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6826 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.565192 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.817384 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.562313 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5689 83.34% 83.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 486 7.12% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 93 1.36% 91.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 54 0.79% 92.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 43 0.63% 93.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 24 0.35% 93.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 57 0.84% 94.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 8 0.12% 94.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 116 1.70% 96.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 16 0.23% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.15% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 12 0.18% 96.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 73 1.07% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 7 0.10% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 98.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 20 0.29% 98.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 80 1.17% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 3 0.04% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 9 0.13% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 3 0.04% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-211 2 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6826 # Writes before turning the bus around for reads +system.physmem.totQLat 5414962245 # Total ticks spent queuing +system.physmem.totMemAccLat 9155793495 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 997555000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27141.17 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45756.47 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 45891.17 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.82 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.39 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.81 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.39 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.87 # Average write queue length when enqueuing -system.physmem.readRowHits 166261 # Number of row buffer hits during reads -system.physmem.writeRowHits 80380 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.86 # Row buffer hit rate for writes -system.physmem.avgGap 8298964.51 # Average gap between requests -system.physmem.pageHitRate 72.71 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 368829720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 201246375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 820489800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 465801840 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85113851220 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634657451750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1907701637745 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.635783 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719265528725 # Time in different power states -system.physmem_0.memoryStateTime::REF 95129840000 # Time in different power states +system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.22 # Average write queue length when enqueuing +system.physmem.readRowHits 165357 # Number of row buffer hits during reads +system.physmem.writeRowHits 80567 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.88 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.39 # Row buffer hit rate for writes +system.physmem.avgGap 7701790.94 # Average gap between requests +system.physmem.pageHitRate 72.35 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 377130600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 205775625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 826254000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 473461200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81211791960 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1518231236250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1774353018435 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.790588 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2525572951341 # Time in different power states +system.physmem_0.memoryStateTime::REF 88459800000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34469380775 # Time in different power states +system.physmem_0.memoryStateTime::ACT 35083346159 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 330840720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 180518250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 434257200 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83792356380 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635816657750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1907370338340 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.519491 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721199868682 # Time in different power states -system.physmem_1.memoryStateTime::REF 95129840000 # Time in different power states +system.physmem_1.actEnergy 333237240 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181825875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 729924000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 436188240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 173027368800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79517209320 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1519717712250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1773943465725 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.635988 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2528054644365 # Time in different power states +system.physmem_1.memoryStateTime::REF 88459800000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32535082068 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32601653135 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -346,30 +350,30 @@ system.realview.nvmem.bytes_inst_read::total 1344 system.realview.nvmem.num_reads::cpu0.inst 8 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 13 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 21 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 180 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 292 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 472 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 180 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 292 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 472 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 180 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 292 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 472 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu0.inst 193 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 314 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 507 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 193 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 314 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 507 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 193 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 314 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 507 # Total bandwidth to/from this memory (bytes/s) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 36420174 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17682232 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1669191 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20721489 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 15026104 # Number of BTB hits +system.cpu0.branchPred.lookups 19632721 # Number of BP lookups +system.cpu0.branchPred.condPredicted 12741106 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 957809 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 12414007 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 8826841 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.514596 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11397312 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 800928 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 71.103883 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3283973 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 196273 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -400,57 +404,56 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 73306 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 73306 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47488 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25818 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 73306 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 73306 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 73306 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7529 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12317.505645 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.047410 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7148.063589 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7474 99.27% 99.27% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 46 0.61% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7529 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 67362 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67362 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 44747 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 22615 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 67362 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 67362 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 67362 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 6703 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11941.220349 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 10822.969980 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 8452.619900 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 6653 99.25% 99.25% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 41 0.61% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 8 0.12% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 6703 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5847 77.66% 77.66% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1682 22.34% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7529 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5190 77.43% 77.43% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1513 22.57% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6703 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67362 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73306 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7529 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67362 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6703 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7529 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 80835 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6703 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 74065 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24946697 # DTB read hits -system.cpu0.dtb.read_misses 66576 # DTB read misses -system.cpu0.dtb.write_hits 18555175 # DTB write hits -system.cpu0.dtb.write_misses 6730 # DTB write misses +system.cpu0.dtb.read_hits 16471465 # DTB read hits +system.cpu0.dtb.read_misses 61259 # DTB read misses +system.cpu0.dtb.write_hits 13861421 # DTB write hits +system.cpu0.dtb.write_misses 6103 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3812 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3499 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1118 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1582 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 25013273 # DTB read accesses -system.cpu0.dtb.write_accesses 18561905 # DTB write accesses +system.cpu0.dtb.perms_faults 565 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 16532724 # DTB read accesses +system.cpu0.dtb.write_accesses 13867524 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43501872 # DTB hits -system.cpu0.dtb.misses 73306 # DTB misses -system.cpu0.dtb.accesses 43575178 # DTB accesses +system.cpu0.dtb.hits 30332886 # DTB hits +system.cpu0.dtb.misses 67362 # DTB misses +system.cpu0.dtb.accesses 30400248 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -480,38 +483,37 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 4169 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4169 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3845 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4169 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4169 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4169 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2671 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12688.506177 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11997.245115 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5018.704234 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2423 90.72% 90.72% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 228 8.54% 99.25% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 18 0.67% 99.93% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 3870 # Table walker walks requested +system.cpu0.itb.walker.walksShort 3870 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 303 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3567 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 3870 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 3870 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 3870 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2416 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12175.289735 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11303.436072 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5287.236665 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2213 91.60% 91.60% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 183 7.57% 99.17% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 19 0.79% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2416 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2352 88.06% 88.06% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 319 11.94% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2671 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2118 87.67% 87.67% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 298 12.33% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2416 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4169 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4169 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 3870 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 3870 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2671 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2671 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6840 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 71444406 # ITB inst hits -system.cpu0.itb.inst_misses 4169 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2416 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2416 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6286 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 36732226 # ITB inst hits +system.cpu0.itb.inst_misses 3870 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -520,131 +522,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2449 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2219 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 8126 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 7242 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71448575 # ITB inst accesses -system.cpu0.itb.hits 71444406 # DTB hits -system.cpu0.itb.misses 4169 # DTB misses -system.cpu0.itb.accesses 71448575 # DTB accesses -system.cpu0.numCycles 248815256 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 36736096 # ITB inst accesses +system.cpu0.itb.hits 36732226 # DTB hits +system.cpu0.itb.misses 3870 # DTB misses +system.cpu0.itb.accesses 36736096 # DTB accesses +system.cpu0.numCycles 162382442 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 113230333 # Number of instructions committed -system.cpu0.committedOps 136910947 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8928789 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1886 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5448949721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.197426 # CPI: cycles per instruction -system.cpu0.ipc 0.455078 # IPC: instructions per cycle +system.cpu0.committedInsts 75583432 # Number of instructions committed +system.cpu0.committedOps 90974289 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 5013155 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 2059 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5135888904 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.148387 # CPI: cycles per instruction +system.cpu0.ipc 0.465466 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed -system.cpu0.tickCycles 199822657 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 48992599 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 758548 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.039628 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41909246 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 759060 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.212033 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 2063 # number of quiesce instructions executed +system.cpu0.tickCycles 121978989 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 40403453 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 680701 # number of replacements +system.cpu0.dcache.tags.tagsinuse 486.682235 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28901777 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 681213 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 42.426931 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.039628 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974687 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.974687 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.682235 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.950551 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.950551 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 345 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 42 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86968977 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86968977 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23338731 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23338731 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17382396 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17382396 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329314 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 329314 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374886 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374886 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370842 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 370842 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40721127 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40721127 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 41050441 # number of overall hits -system.cpu0.dcache.overall_hits::total 41050441 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 492920 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 492920 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 604804 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 604804 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141961 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141961 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21406 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21406 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20501 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20501 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1097724 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1097724 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1239685 # number of overall misses -system.cpu0.dcache.overall_misses::total 1239685 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6985498500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6985498500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12567334500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12567334500 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 329657000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 329657000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 538169500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 538169500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 1008000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1008000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 19552833000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 19552833000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 19552833000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 19552833000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 23831651 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 23831651 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17987200 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17987200 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 471275 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 396292 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396292 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391343 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391343 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41818851 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41818851 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42290126 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42290126 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020683 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020683 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033624 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033624 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301228 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301228 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054016 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054016 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052386 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052386 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026250 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026250 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029314 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029314 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14171.667816 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14171.667816 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20779.185488 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 20779.185488 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15400.214893 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15400.214893 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26250.890200 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26250.890200 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 60666006 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 60666006 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 14995152 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 14995152 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12778726 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12778726 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 305913 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 305913 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 356785 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 356785 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351877 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 351877 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27773878 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27773878 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 28079791 # number of overall hits +system.cpu0.dcache.overall_hits::total 28079791 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 443645 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 443645 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 558771 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 558771 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 131921 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 131921 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 20933 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 20933 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21449 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21449 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1002416 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1002416 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1134337 # number of overall misses +system.cpu0.dcache.overall_misses::total 1134337 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6380347500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 6380347500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 11838491500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 11838491500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330148000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 330148000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 572278500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 572278500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 490000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 490000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 18218839000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 18218839000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 18218839000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 18218839000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 15438797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 15438797 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13337497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13337497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437834 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 437834 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 377718 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 377718 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 373326 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 373326 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 28776294 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 28776294 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 29214128 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 29214128 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028736 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028736 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.041895 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.041895 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301304 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301304 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.055420 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.055420 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.057454 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.057454 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.034835 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.034835 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.038828 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.038828 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14381.650870 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14381.650870 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 21186.660546 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 21186.660546 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15771.652415 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15771.652415 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26680.894214 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26680.894214 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17812.157701 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17812.157701 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15772.420413 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15772.420413 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 18174.928373 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18174.928373 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16061.222547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16061.222547 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -653,149 +655,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 758548 # number of writebacks -system.cpu0.dcache.writebacks::total 758548 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75935 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 75935 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266250 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 266250 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14874 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14874 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 342185 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 342185 # 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number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 995000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 995000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403434500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12403434500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14213533000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14213533000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6701732000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6701732000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452636000 # 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mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016483 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052386 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052386 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018067 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018067 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020429 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020429 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12686.046261 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12686.046261 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21011.547641 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21011.547641 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16697.555463 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16697.555463 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.542560 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.542560 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25251.524316 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25251.524316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 680701 # number of writebacks +system.cpu0.dcache.writebacks::total 680701 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 70219 # 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number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 313850 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 99342 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 99342 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6089 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6089 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21449 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 687276 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 687276 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 786618 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 786618 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17966 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17966 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16715 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16715 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34681 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34681 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4799499000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4799499000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6708842500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6708842500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1708183000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1708183000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 97000000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 97000000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 550839500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 550839500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 480000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 480000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11508341500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 11508341500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 13216524500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13216524500 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3964655000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3964655000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 3079216000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 3079216000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 7043871000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 7043871000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024188 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024188 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023531 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023531 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.226894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.226894 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016120 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016120 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.057454 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.057454 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023883 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023883 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026926 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026926 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12852.610691 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12852.610691 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21375.951888 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21375.951888 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 17194.972922 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 17194.972922 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15930.366234 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15930.366234 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25681.360436 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25681.360436 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16416.670086 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16416.670086 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16451.914707 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16451.914707 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.193951 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.193951 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189841.793747 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189841.793747 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200035.680782 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200035.680782 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16744.861599 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16744.861599 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16801.706165 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16801.706165 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 220675.442503 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 220675.442503 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 184218.725695 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184218.725695 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 203104.610594 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 203104.610594 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 2044571 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.728044 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69390799 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 2045083 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 33.930554 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1875262 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.707229 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 34848846 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1875774 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.578382 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728044 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999469 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999469 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.707229 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999428 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999428 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 177 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 226 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 109 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 144916894 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 144916894 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69390799 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69390799 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69390799 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69390799 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69390799 # number of overall hits -system.cpu0.icache.overall_hits::total 69390799 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 2045099 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2045099 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 2045099 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2045099 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 2045099 # number of overall misses -system.cpu0.icache.overall_misses::total 2045099 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20582559000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20582559000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20582559000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20582559000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20582559000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20582559000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 71435898 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 71435898 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 71435898 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 71435898 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 71435898 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 71435898 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028628 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028628 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028628 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028628 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028628 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028628 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.333805 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.333805 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10064.333805 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10064.333805 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 75325070 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 75325070 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 34848846 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 34848846 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 34848846 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 34848846 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 34848846 # number of overall hits +system.cpu0.icache.overall_hits::total 34848846 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1875793 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1875793 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1875793 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1875793 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1875793 # number of overall misses +system.cpu0.icache.overall_misses::total 1875793 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 18730135500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 18730135500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 18730135500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 18730135500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 18730135500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 18730135500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36724639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36724639 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36724639 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36724639 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36724639 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36724639 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.051077 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.051077 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.051077 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.051077 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.051077 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.051077 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9985.182533 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9985.182533 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9985.182533 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9985.182533 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9985.182533 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9985.182533 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -804,336 +806,335 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 2044571 # number of writebacks -system.cpu0.icache.writebacks::total 2044571 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2045099 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 2045099 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 2045099 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 2045099 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 2045099 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 2045099 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1875262 # number of writebacks +system.cpu0.icache.writebacks::total 1875262 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1875793 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1875793 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1875793 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1875793 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1875793 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1875793 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19560010000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19560010000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19560010000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19560010000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19560010000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19560010000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 17792239500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 17792239500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 17792239500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 17792239500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 17792239500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 17792239500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028628 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028628 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028628 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.334049 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.051077 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.051077 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.051077 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.051077 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9485.182800 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9485.182800 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9485.182800 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9485.182800 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927519 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1927689 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 149 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1759572 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1759695 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 108 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 245495 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 305066 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16110.532476 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4906564 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 321213 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.275110 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 223393 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 281012 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16001.828165 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4472083 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 297133 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.050779 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14727.121799 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.543151 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067969 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1324.799556 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.898872 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003573 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 15118.800161 # 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Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15166 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 11 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 324 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 411 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 226 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 95 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4092 # 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average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 59786.314915 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 27498.028017 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 27498.028017 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 43034.348579 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 36727.099237 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17288.793103 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 59786.314915 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 35989.317324 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 81971.291951 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64380.460217 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201169.028372 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193883.482590 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182323.863241 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182323.863241 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 212665.896694 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 198637.092720 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 176687.885133 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 176687.885133 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192260.833429 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188750.123690 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 195325.783570 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 189131.910980 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 5762889 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2904395 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 45067 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 350664 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 143133 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2769477 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 745212 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2295997 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 245518 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 331271 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87260 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42942 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114488 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 300512 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 297211 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2045099 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606063 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3097 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6142602 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2764050 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13802 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 189783 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 9110237 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261989504 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104964478 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23152 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 362636 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 367339770 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1076533 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4071717 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104210 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.309410 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 5267322 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2655927 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 41328 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 334158 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 329304 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4854 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 119336 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2522924 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 16715 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 16715 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 692222 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2091812 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 222834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 309300 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 91686 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43805 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 115698 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 4 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 274549 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 271267 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1875793 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 569005 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3104 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 5634681 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2479031 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 12447 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 171956 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 8298115 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 240318144 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 94807159 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 20040 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 327916 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 335473259 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1039321 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3754204 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.107024 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.313298 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3652260 89.70% 89.70% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 414602 10.18% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4855 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3357269 89.43% 89.43% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 392081 10.44% 99.87% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4854 0.13% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4071717 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5772987994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3754204 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5255285493 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116128992 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113846370 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3074216608 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 2820178266 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1306190305 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1169961199 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 8023481 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7446481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 99154439 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 90008437 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3635973 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2046610 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 209049 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2276641 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1455770 # Number of BTB hits +system.cpu1.branchPred.lookups 20449244 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7039055 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 963225 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 10410340 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 7679577 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.943766 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 756757 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 55280 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.768743 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 8836366 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 692168 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1292,57 +1293,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 23538 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 23538 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19270 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4268 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 23538 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 23538 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 23538 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1839 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11777.052746 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10980.884481 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6685.927584 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1677 91.19% 91.19% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 150 8.16% 99.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.38% 99.73% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1839 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 30868 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 30868 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 23108 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 7760 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 30868 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 30868 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 30868 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 2696 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11992.210682 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10915.827455 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 8355.113227 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2479 91.95% 91.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 196 7.27% 99.22% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 12 0.45% 99.67% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.11% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 3 0.11% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 2696 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1325 72.05% 72.05% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 514 27.95% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1839 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23538 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1974 73.22% 73.22% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 722 26.78% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2696 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 30868 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23538 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1839 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 30868 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2696 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1839 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 25377 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2696 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 33564 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3603943 # DTB read hits -system.cpu1.dtb.read_misses 21681 # DTB read misses -system.cpu1.dtb.write_hits 2994136 # DTB write hits -system.cpu1.dtb.write_misses 1857 # DTB write misses +system.cpu1.dtb.read_hits 12117944 # DTB read hits +system.cpu1.dtb.read_misses 28100 # DTB read misses +system.cpu1.dtb.write_hits 7719144 # DTB write hits +system.cpu1.dtb.write_misses 2768 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 128 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2067 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 330 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 545 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3625624 # DTB read accesses -system.cpu1.dtb.write_accesses 2995993 # DTB write accesses +system.cpu1.dtb.perms_faults 280 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 12146044 # DTB read accesses +system.cpu1.dtb.write_accesses 7721912 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6598079 # DTB hits -system.cpu1.dtb.misses 23538 # DTB misses -system.cpu1.dtb.accesses 6621617 # DTB accesses +system.cpu1.dtb.hits 19837088 # DTB hits +system.cpu1.dtb.misses 30868 # DTB misses +system.cpu1.dtb.accesses 19867956 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1372,44 +1374,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1941 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1941 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1790 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1941 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1941 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1941 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 844 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11680.687204 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11150.609492 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4460.342613 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 146 17.30% 17.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 544 64.45% 81.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.27% 95.02% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 21 2.49% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.17% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 844 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 2320 # Table walker walks requested +system.cpu1.itb.walker.walksShort 2320 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 184 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2136 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 2320 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 2320 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 2320 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1123 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12081.032947 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11456.275098 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4603.593303 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 188 16.74% 16.74% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 645 57.44% 74.18% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 209 18.61% 92.79% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 49 4.36% 97.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 1 0.09% 97.24% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 15 1.34% 98.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.27% 98.84% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.09% 98.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 10 0.89% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1123 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 705 83.53% 83.53% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 139 16.47% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 844 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 953 84.86% 84.86% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 15.14% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1123 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1941 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1941 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 2320 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 2320 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 844 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 844 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2785 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 6953743 # ITB inst hits -system.cpu1.itb.inst_misses 1941 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1123 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1123 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 3443 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 41835871 # ITB inst hits +system.cpu1.itb.inst_misses 2320 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1418,130 +1420,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 908 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1161 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1049 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1837 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6955684 # ITB inst accesses -system.cpu1.itb.hits 6953743 # DTB hits -system.cpu1.itb.misses 1941 # DTB misses -system.cpu1.itb.accesses 6955684 # DTB accesses -system.cpu1.numCycles 40734093 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 41838191 # ITB inst accesses +system.cpu1.itb.hits 41835871 # DTB hits +system.cpu1.itb.misses 2320 # DTB misses +system.cpu1.itb.accesses 41838191 # DTB accesses +system.cpu1.numCycles 128464441 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 14107719 # Number of instructions committed -system.cpu1.committedOps 17288156 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1387486 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2746 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5656373541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.887362 # CPI: cycles per instruction -system.cpu1.ipc 0.346337 # IPC: instructions per cycle +system.cpu1.committedInsts 51881050 # Number of instructions committed +system.cpu1.committedOps 63376562 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 5336781 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2726 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5169132523 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.476134 # CPI: cycles per instruction +system.cpu1.ipc 0.403855 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2746 # number of quiesce instructions executed -system.cpu1.tickCycles 27498026 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 13236067 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 156251 # number of replacements -system.cpu1.dcache.tags.tagsinuse 474.671754 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6246920 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 156599 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.891187 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91622282000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.671754 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927093 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.927093 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13254229 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13254229 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3282688 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3282688 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2748164 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2748164 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42687 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42687 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70657 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70657 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61986 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61986 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6030852 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6030852 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6073539 # number of overall hits -system.cpu1.dcache.overall_hits::total 6073539 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 134600 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 134600 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 121570 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 121570 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24420 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24420 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16487 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16487 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23399 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23399 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 256170 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 256170 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 280590 # number of overall misses -system.cpu1.dcache.overall_misses::total 280590 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2183210000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2183210000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4500084500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4500084500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 318001000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 318001000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633995000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 633995000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 321000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 321000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6683294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6683294500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6683294500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6683294500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3417288 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3417288 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2869734 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2869734 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67107 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 67107 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87144 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87144 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85385 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85385 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6287022 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6287022 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6354129 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6354129 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039388 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039388 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042363 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.042363 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.363896 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.363896 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189193 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189193 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274041 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274041 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040746 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040746 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044159 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044159 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16219.985141 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16219.985141 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37016.406186 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37016.406186 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19287.984473 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19287.984473 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27094.961323 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27094.961323 # average StoreCondReq miss latency +system.cpu1.kern.inst.quiesce 2733 # number of quiesce instructions executed +system.cpu1.tickCycles 105981069 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 22483372 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 234073 # number of replacements +system.cpu1.dcache.tags.tagsinuse 481.612157 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 19315800 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 234411 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 82.401423 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91649523000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 481.612157 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.940649 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.940649 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 338 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 295 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 43 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.660156 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 39692249 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 39692249 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 11657958 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11657958 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 7379701 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 7379701 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 66326 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 66326 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88715 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 88715 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80616 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 80616 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 19037659 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 19037659 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 19103985 # number of overall hits +system.cpu1.dcache.overall_hits::total 19103985 # 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number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 106480 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104178 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 104178 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 19393206 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 19393206 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 19494563 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 19494563 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.015760 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.015760 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.022371 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.022371 # 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average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15719.654480 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31561.596949 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 31561.596949 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18840.247678 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18840.247678 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 26892.008318 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 26892.008318 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26089.294219 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26089.294219 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23818.719484 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23818.719484 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23244.005715 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23244.005715 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21159.247321 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21159.247321 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1550,149 +1552,148 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # 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number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 5710028500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6295227500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6295227500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 3132437500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 3132437500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2631383000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2631383000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5763820500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5763820500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014196 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.014196 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014071 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014071 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.331206 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.331206 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051381 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051381 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.226171 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.226171 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014147 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014147 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015796 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015796 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14706.332780 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14706.332780 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 30477.513439 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 30477.513439 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17432.201370 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17432.201370 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18112.136721 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18112.136721 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 25892.093201 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 25892.093201 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22802.005977 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22802.005977 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22390.688933 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22390.688933 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130846.606183 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130846.606183 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109013.624567 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 109013.624567 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121300.869894 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121300.869894 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20812.175609 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20812.175609 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20443.696619 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20443.696619 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 182436.662784 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 182436.662784 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 182102.629758 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 182102.629758 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 182284.013283 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 182284.013283 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # 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Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 1045806 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 39.001537 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73317918000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.164820 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.972978 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.972978 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 50 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14768686 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14768686 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6088925 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6088925 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6088925 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6088925 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6088925 # number of overall hits -system.cpu1.icache.overall_hits::total 6088925 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 863612 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 863612 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 863612 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 863612 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 863612 # number of overall misses -system.cpu1.icache.overall_misses::total 863612 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7643358500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7643358500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7643358500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7643358500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7643358500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7643358500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 6952537 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 6952537 # 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average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8850.454255 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8850.454255 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8850.454255 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 84713500 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 84713500 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 40788041 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 40788041 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 40788041 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 40788041 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 40788041 # 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miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.024999 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.024999 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9329.081111 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9329.081111 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9329.081111 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9329.081111 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9329.081111 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1701,453 +1702,453 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # 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number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124215 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124215 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124215 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8350.454255 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8350.454255 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8350.454255 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.024999 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.024999 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.024999 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.024999 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8829.081111 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8829.081111 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8829.081111 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8829.081111 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 119510 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 119557 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 274967 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 275055 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 76 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 49379 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 38013 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15156.094149 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1857838 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53311 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 34.849056 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 69809 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 70327 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15561.407713 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 2301234 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 85126 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 27.033268 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14713.350805 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.823499 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.085233 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 414.834611 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.898032 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001698 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025319 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.925055 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 902 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14305 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 862 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14349.457044 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 61.253461 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.124525 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1150.572683 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.875821 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.003739 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000008 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.070225 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.949793 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1105 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 65 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13629 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 296 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 805 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 347 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1969 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 11989 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.055054 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005554 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.873108 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 34476802 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 34476802 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24946 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2423 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 27369 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 94733 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 94733 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 906332 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 906332 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18144 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 18144 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 850574 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 850574 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 83387 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 83387 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24946 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2423 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 850574 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 101531 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 979474 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24946 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2423 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 850574 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 101531 # number of overall hits -system.cpu1.l2cache.overall_hits::total 979474 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 682 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 240 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 922 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29216 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29216 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23399 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23399 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32397 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32397 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 13038 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 13038 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 66978 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 66978 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 682 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 240 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 13038 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 99375 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 113335 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 682 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 240 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 13038 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 99375 # number of overall misses -system.cpu1.l2cache.overall_misses::total 113335 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 15377500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4827500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 20205000 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 64165000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 64165000 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 56569500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 56569500 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 308500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 308500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1725053500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1725053500 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 743147000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 743147000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1610450996 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1610450996 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 15377500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4827500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 743147000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3335504496 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4098856496 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 15377500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4827500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 743147000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3335504496 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4098856496 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 25628 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2663 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 28291 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::writebacks 94733 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackDirty_accesses::total 94733 # number of WritebackDirty accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::writebacks 906332 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.WritebackClean_accesses::total 906332 # number of WritebackClean accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29216 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 29216 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23399 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23399 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 50541 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 50541 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 863612 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadCleanReq_accesses::total 863612 # number of ReadCleanReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 150365 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.ReadSharedReq_accesses::total 150365 # number of ReadSharedReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 25628 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2663 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 863612 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 200906 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1092809 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 25628 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2663 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 863612 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 200906 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1092809 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.026612 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.090124 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.032590 # miss rate for ReadReq accesses +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 20 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 302 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 5169 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 8158 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.067444 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.003967 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.831848 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 43062781 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 43062781 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 34599 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2926 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 37525 # 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average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32777.297974 # average overall mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 45897.697672 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 45897.697672 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 48734.253283 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 20354.413270 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 20354.413270 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 32532.103899 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 22538.567493 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14465.116279 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 48734.253283 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28657.067862 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 46108.401788 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 35510.022313 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122826.444892 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123052.461140 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101459.558824 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101459.558824 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174430.984275 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 174136.934383 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174593.944637 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 174593.944637 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113484.493192 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113807.500000 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 174505.455408 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 174345.046010 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 2143691 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1079194 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 177461 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175960 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1501 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 34625 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1085487 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2312 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 125339 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 924619 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 97697 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 24084 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71468 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41763 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 84759 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57626 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55185 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 863612 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 234129 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 33 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2590548 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 747561 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6394 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 53434 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3397937 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 110516736 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25535556 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 102512 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 136165456 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 380835 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1457969 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.140235 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.350184 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 2671947 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1344357 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 22211 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 212012 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 209828 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2184 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 60366 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1353600 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 14450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 14450 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 179270 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 1143304 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 137947 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 47540 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 74191 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43096 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89660 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 82906 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 80697 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 1045806 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 295809 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 50 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 3137130 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 1052074 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 7597 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 73953 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 4270754 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 133837568 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 36094549 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 12564 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 141300 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 170085981 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 473244 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1845377 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.133426 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.343498 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1255011 86.08% 86.08% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 201457 13.82% 99.90% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1501 0.10% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1601339 86.78% 86.78% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 241854 13.11% 99.88% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2184 0.12% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1457969 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2107221995 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1845377 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2655073991 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78416105 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 86773438 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1295704762 # Layer occupancy (ticks) -system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 333278550 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1569094564 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) +system.cpu1.toL2Bus.respLayer1.occupancy 476141581 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3731000 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 4456000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 27832447 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 38655445 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 31009 # Transaction distribution -system.iobus.trans_dist::ReadResp 31009 # Transaction distribution -system.iobus.trans_dist::WriteReq 59425 # Transaction distribution -system.iobus.trans_dist::WriteResp 59425 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::ReadReq 31014 # Transaction distribution +system.iobus.trans_dist::ReadResp 31014 # Transaction distribution +system.iobus.trans_dist::WriteReq 59421 # Transaction distribution +system.iobus.trans_dist::WriteResp 59421 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 850 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 846 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -2160,17 +2161,17 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107910 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72960 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 180870 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71544 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 449 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 447 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -2183,25 +2184,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51092500 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 162792 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2484072 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 51031501 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 336000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 29000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 576000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 565500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19000 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) @@ -2209,66 +2210,66 @@ system.iobus.reqLayer14.occupancy 8500 # La system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 46000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6104500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6103500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32859000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32838000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187096728 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187160706 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84713000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36784000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.469909 # Cycle average of tags in use +system.iocache.tags.replacements 36462 # number of replacements +system.iocache.tags.tagsinuse 14.353695 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36478 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272427086000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.469909 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904369 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904369 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272566004000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.353695 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.897106 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.897106 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 328203 # Number of tag accesses -system.iocache.tags.data_accesses 328203 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 243 # number of ReadReq misses -system.iocache.ReadReq_misses::total 243 # number of ReadReq misses +system.iocache.tags.tag_accesses 328320 # Number of tag accesses +system.iocache.tags.data_accesses 328320 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 256 # number of ReadReq misses +system.iocache.ReadReq_misses::total 256 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses -system.iocache.demand_misses::realview.ide 243 # number of demand (read+write) misses -system.iocache.demand_misses::total 243 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 243 # number of overall misses -system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 31652377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 31652377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4575926351 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4575926351 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 31652377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 31652377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 31652377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 31652377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 256 # number of demand (read+write) misses +system.iocache.demand_misses::total 256 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 256 # number of overall misses +system.iocache.overall_misses::total 256 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 33038877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 33038877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4577477829 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4577477829 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 33038877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 33038877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 33038877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 33038877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 256 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 256 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 243 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 243 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 243 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 243 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 256 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 256 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 256 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 256 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses @@ -2277,40 +2278,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 130256.695473 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 130256.695473 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126323.055184 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 126323.055184 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 130256.695473 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 130256.695473 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129058.113281 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129058.113281 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126365.885297 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126365.885297 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 129058.113281 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 129058.113281 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 129058.113281 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 12 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 243 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 243 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 256 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 256 # number of ReadReq MSHR misses system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 243 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19502377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19502377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763035342 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2763035342 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19502377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19502377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19502377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19502377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 256 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 256 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 256 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 256 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20238877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20238877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2764566568 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2764566568 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20238877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20238877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20238877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20238877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2319,575 +2320,576 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80256.695473 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 80256.695473 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76276.373178 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76276.373178 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79058.113281 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79058.113281 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76318.644214 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76318.644214 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 79058.113281 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 79058.113281 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 79058.113281 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 79058.113281 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 132173 # number of replacements -system.l2c.tags.tagsinuse 63220.230545 # Cycle average of tags in use -system.l2c.tags.total_refs 476061 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196324 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.424874 # Average number of references to valid blocks. +system.l2c.tags.replacements 134245 # number of replacements +system.l2c.tags.tagsinuse 63310.759075 # Cycle average of tags in use +system.l2c.tags.total_refs 474981 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 198059 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.398179 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13508.269285 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.219026 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9248.082270 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2930.331388 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33200.975902 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.874579 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1907.881821 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 574.003662 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1760.558132 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.206120 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001270 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.141115 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044713 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506607 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000105 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029112 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008759 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026864 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964664 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29038 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 35051 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23744 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 14231.075006 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 68.949164 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.999781 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 7026.716381 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2024.667607 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 30360.457538 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 27.102838 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 4106.821272 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1547.963396 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3916.006093 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.217149 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001052 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.107219 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.030894 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.463264 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000414 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.062665 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.023620 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.059754 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.966046 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 27725 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 35997 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 133 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4285 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23307 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 61 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 91 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 489 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3341 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31190 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.443085 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.534836 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6395223 # Number of tag accesses -system.l2c.tags.data_accesses 6395223 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 266844 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121040.090759 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133317.539645 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140684.178928 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 129412.500000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122469.112521 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124118.079453 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 156673.498705 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 137191.647062 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.232654 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 194664.561616 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104928.524050 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169983.978587 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165318.379779 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84456.099481 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159294.225881 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 156457.826411 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169529.646596 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 159680.317200 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 157593.287266 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 158712.642484 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174730.526324 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 177803.408668 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95972.564617 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 165249.825387 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 156976.769048 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 164736.154294 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 39041 # Transaction distribution -system.membus.trans_dist::ReadResp 215941 # Transaction distribution -system.membus.trans_dist::WriteReq 31034 # Transaction distribution -system.membus.trans_dist::WriteResp 31034 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138436 # Transaction distribution -system.membus.trans_dist::CleanEvict 18070 # Transaction distribution -system.membus.trans_dist::UpgradeReq 73582 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40721 # Transaction distribution +system.membus.trans_dist::ReadReq 39162 # Transaction distribution +system.membus.trans_dist::ReadResp 215417 # Transaction distribution +system.membus.trans_dist::WriteReq 31165 # Transaction distribution +system.membus.trans_dist::WriteResp 31165 # Transaction distribution +system.membus.trans_dist::WritebackDirty 139900 # Transaction distribution +system.membus.trans_dist::CleanEvict 18801 # Transaction distribution +system.membus.trans_dist::UpgradeReq 78213 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41798 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40108 # Transaction distribution -system.membus.trans_dist::ReadExResp 19531 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176900 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 40189 # Transaction distribution +system.membus.trans_dist::ReadExResp 19404 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176255 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107910 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14216 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664933 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 787125 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 860056 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14740 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 671466 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 794158 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72957 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 867115 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162792 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28432 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19353628 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19546218 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 29480 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19397092 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19590708 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21864362 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120262 # Total snoops (count) -system.membus.snoop_fanout::samples 594139 # Request fanout histogram +system.membus.pkt_size::total 21908852 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125573 # Total snoops (count) +system.membus.snoop_fanout::samples 601741 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 594139 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 601741 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 594139 # Request fanout histogram -system.membus.reqLayer0.occupancy 91324000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 601741 # Request fanout histogram +system.membus.reqLayer0.occupancy 91242999 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12307500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12732000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1010896317 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1019564727 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1147679286 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1144074788 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1341127 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1412877 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2930,52 +2932,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1042334 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 562614 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 153410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21132 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 1023 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 500861 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31034 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31034 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 405302 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 139265 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109721 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43882 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153603 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51189 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51189 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 461832 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 1069309 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 577929 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 171835 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21548 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20404 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1144 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 39165 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 514340 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31165 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31165 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 409596 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 144328 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 114559 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 44999 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 159558 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 12 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51602 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51602 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 475191 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1332417 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274320 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1606737 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36835698 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4378808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41214506 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 447707 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 941615 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.339048 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.475676 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1207299 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 435215 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1642514 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34510571 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 7361417 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41871988 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 461244 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 963683 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.359503 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.482323 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 623385 66.20% 66.20% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 317207 33.69% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 1023 0.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 618380 64.17% 64.17% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 344159 35.71% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1144 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 941615 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 901922668 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 963683 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 919452336 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 360123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 690834076 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 640437781 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 214047025 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 288270065 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal index 03b467a01..263610058 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/system.terminal @@ -158,8 +158,8 @@ ata1.00: 1048320 sectors, multi 0: LBA ata1.00: configured for UDMA/33
scsi 0:0:0:0: Direct-Access ATA M5 IDE Disk n/a PQ: 0 ANSI: 5
sd 0:0:0:0: [sda] 1048320 512-byte logical blocks: (536 MB/511 MiB)
-sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Write Protect is off
+sd 0:0:0:0: Attached scsi generic sg0 type 0
sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
sda: sda1
|