diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-02-10 04:08:27 -0500 |
| commit | c6cede244b431c167ac0213d89ad2bd7a0abbd96 (patch) | |
| tree | fb0e63d4172746d5b1a8edeb859f7ee68cfe13a6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual | |
| parent | 83a5977481d55916b200740cf03748a20777bdf1 (diff) | |
| download | gem5-c6cede244b431c167ac0213d89ad2bd7a0abbd96.tar.xz | |
stats: Update stats to reflect changes to cache and crossbar
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 4577 |
1 files changed, 2281 insertions, 2296 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index a63afd969..e7604208d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,157 +1,157 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.848979 # Number of seconds simulated -sim_ticks 2848979128500 # Number of ticks simulated -final_tick 2848979128500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.848869 # Number of seconds simulated +sim_ticks 2848869082500 # Number of ticks simulated +final_tick 2848869082500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 154282 # Simulator instruction rate (inst/s) -host_op_rate 186830 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3456392917 # Simulator tick rate (ticks/s) -host_mem_usage 618280 # Number of bytes of host memory used -host_seconds 824.26 # Real time elapsed on the host -sim_insts 127169330 # Number of instructions simulated -sim_ops 153997543 # Number of ops (including micro ops) simulated +host_inst_rate 198569 # Simulator instruction rate (inst/s) +host_op_rate 240456 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4442491449 # Simulator tick rate (ticks/s) +host_mem_usage 621364 # Number of bytes of host memory used +host_seconds 641.28 # Real time elapsed on the host +sim_insts 127338052 # Number of instructions simulated +sim_ops 154199103 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 8448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 8704 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1698560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1348800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8516160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 208256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 632788 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 357568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1697856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1350060 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8564736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 206784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 630484 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 333888 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12772244 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1698560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 208256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1906816 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8849024 # Number of bytes written to this memory +system.physmem.bytes_read::total 12794304 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1697856 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 206784 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1904640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8859904 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8866588 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 132 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8877468 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 136 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 26540 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21601 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 3254 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9908 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5587 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26529 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133824 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3231 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9872 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 5217 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 200113 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 138266 # Number of write requests responded to by this memory +system.physmem.num_reads::total 200453 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 138436 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 142657 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 2965 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 142827 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 3055 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 596200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 473433 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2989197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 73098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 222110 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 125507 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 595975 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 473893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3006363 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 72585 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 221310 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 117200 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4483095 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 596200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 73098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 669298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3106033 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4491012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 595975 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 72585 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 668560 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3109972 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6151 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3112198 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3106033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 2965 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3116138 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3109972 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 3055 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 596200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 479584 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2989197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 225 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 73098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 222124 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 125507 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 595975 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 480045 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3006363 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 72585 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 221324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 117200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7595293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 200113 # Number of read requests accepted -system.physmem.writeReqs 142657 # Number of write requests accepted -system.physmem.readBursts 200113 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 142657 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12798592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8640 # Total number of bytes read from write queue -system.physmem.bytesWritten 8879168 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12772244 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8866588 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 135 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7607149 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 200453 # Number of read requests accepted +system.physmem.writeReqs 142827 # Number of write requests accepted +system.physmem.readBursts 200453 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 142827 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12818368 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue +system.physmem.bytesWritten 8890624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12794304 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8877468 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3895 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 69084 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12287 # Per bank write bursts -system.physmem.perBankRdBursts::1 12592 # Per bank write bursts -system.physmem.perBankRdBursts::2 13485 # Per bank write bursts -system.physmem.perBankRdBursts::3 12796 # Per bank write bursts -system.physmem.perBankRdBursts::4 15663 # Per bank write bursts -system.physmem.perBankRdBursts::5 12764 # Per bank write bursts -system.physmem.perBankRdBursts::6 12615 # Per bank write bursts -system.physmem.perBankRdBursts::7 12815 # Per bank write bursts -system.physmem.perBankRdBursts::8 11998 # Per bank write bursts -system.physmem.perBankRdBursts::9 12140 # Per bank write bursts -system.physmem.perBankRdBursts::10 11596 # Per bank write bursts -system.physmem.perBankRdBursts::11 10685 # Per bank write bursts -system.physmem.perBankRdBursts::12 11914 # Per bank write bursts -system.physmem.perBankRdBursts::13 12844 # Per bank write bursts -system.physmem.perBankRdBursts::14 12075 # Per bank write bursts -system.physmem.perBankRdBursts::15 11709 # Per bank write bursts -system.physmem.perBankWrBursts::0 8805 # Per bank write bursts -system.physmem.perBankWrBursts::1 9189 # Per bank write bursts -system.physmem.perBankWrBursts::2 9797 # Per bank write bursts -system.physmem.perBankWrBursts::3 9112 # Per bank write bursts -system.physmem.perBankWrBursts::4 8303 # Per bank write bursts -system.physmem.perBankWrBursts::5 8892 # Per bank write bursts -system.physmem.perBankWrBursts::6 8866 # Per bank write bursts -system.physmem.perBankWrBursts::7 8915 # Per bank write bursts -system.physmem.perBankWrBursts::8 8401 # Per bank write bursts -system.physmem.perBankWrBursts::9 8590 # Per bank write bursts -system.physmem.perBankWrBursts::10 8283 # Per bank write bursts -system.physmem.perBankWrBursts::11 7752 # Per bank write bursts -system.physmem.perBankWrBursts::12 8566 # Per bank write bursts -system.physmem.perBankWrBursts::13 8822 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12269 # Per bank write bursts +system.physmem.perBankRdBursts::1 12614 # Per bank write bursts +system.physmem.perBankRdBursts::2 13475 # Per bank write bursts +system.physmem.perBankRdBursts::3 12831 # Per bank write bursts +system.physmem.perBankRdBursts::4 15664 # Per bank write bursts +system.physmem.perBankRdBursts::5 12720 # Per bank write bursts +system.physmem.perBankRdBursts::6 12662 # Per bank write bursts +system.physmem.perBankRdBursts::7 12956 # Per bank write bursts +system.physmem.perBankRdBursts::8 12071 # Per bank write bursts +system.physmem.perBankRdBursts::9 12246 # Per bank write bursts +system.physmem.perBankRdBursts::10 11615 # Per bank write bursts +system.physmem.perBankRdBursts::11 10653 # Per bank write bursts +system.physmem.perBankRdBursts::12 11883 # Per bank write bursts +system.physmem.perBankRdBursts::13 12836 # Per bank write bursts +system.physmem.perBankRdBursts::14 12055 # Per bank write bursts +system.physmem.perBankRdBursts::15 11737 # Per bank write bursts +system.physmem.perBankWrBursts::0 8758 # Per bank write bursts +system.physmem.perBankWrBursts::1 9183 # Per bank write bursts +system.physmem.perBankWrBursts::2 9791 # Per bank write bursts +system.physmem.perBankWrBursts::3 9102 # Per bank write bursts +system.physmem.perBankWrBursts::4 8279 # Per bank write bursts +system.physmem.perBankWrBursts::5 8882 # Per bank write bursts +system.physmem.perBankWrBursts::6 8907 # Per bank write bursts +system.physmem.perBankWrBursts::7 8993 # Per bank write bursts +system.physmem.perBankWrBursts::8 8509 # Per bank write bursts +system.physmem.perBankWrBursts::9 8693 # Per bank write bursts +system.physmem.perBankWrBursts::10 8248 # Per bank write bursts +system.physmem.perBankWrBursts::11 7749 # Per bank write bursts +system.physmem.perBankWrBursts::12 8519 # Per bank write bursts +system.physmem.perBankWrBursts::13 8825 # Per bank write bursts system.physmem.perBankWrBursts::14 8545 # Per bank write bursts -system.physmem.perBankWrBursts::15 7899 # Per bank write bursts +system.physmem.perBankWrBursts::15 7933 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 18 # Number of times write queue was full causing retry -system.physmem.totGap 2848978583000 # Total gap between requests +system.physmem.numWrRetry 22 # Number of times write queue was full causing retry +system.physmem.totGap 2848868537000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 557 # Read request sizes (log2) +system.physmem.readPktSize::2 552 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 199528 # Read request sizes (log2) +system.physmem.readPktSize::6 199873 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 138266 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 88817 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 60985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9494 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7806 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 6286 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 4625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3738 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 202 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 136 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 138436 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 88840 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 61310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 11776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 7786 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 6277 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5178 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 4618 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3736 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 132 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -184,161 +184,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2866 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4983 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5998 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6540 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 7779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7940 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8957 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 9084 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 9291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10972 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9017 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 8688 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7869 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7517 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 557 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 414 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 324 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 124 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 95 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 74 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 76 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 52 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 35 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 39 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 61 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92122 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 235.314387 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 133.718922 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 297.822907 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 49981 54.26% 54.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17852 19.38% 73.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6274 6.81% 80.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3559 3.86% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2993 3.25% 87.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1358 1.47% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 900 0.98% 90.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 994 1.08% 91.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8211 8.91% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92122 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6829 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.283204 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.566486 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6828 99.99% 99.99% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2746 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3761 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6227 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6320 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6684 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7381 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 8854 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9840 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8372 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 8119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1314 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 323 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 253 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 176 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 84 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 112 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 83 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 87 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 79 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92557 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 234.543816 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.254652 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 297.662523 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50344 54.39% 54.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17979 19.42% 73.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6295 6.80% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3544 3.83% 84.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2825 3.05% 87.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1428 1.54% 89.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 907 0.98% 90.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1020 1.10% 91.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8215 8.88% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92557 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6759 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 29.632490 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 567.452985 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6758 99.99% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6829 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6829 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.315859 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.777431 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.379766 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5626 82.38% 82.38% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 466 6.82% 89.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 97 1.42% 90.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 149 2.18% 92.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 29 0.42% 93.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 128 1.87% 95.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 35 0.51% 95.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 17 0.25% 95.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.37% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 23 0.34% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 7 0.10% 96.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 8 0.12% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 138 2.02% 98.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.12% 98.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 4 0.06% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 26 0.38% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.06% 99.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.01% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 1 0.01% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 2 0.03% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.21% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6829 # Writes before turning the bus around for reads -system.physmem.totQLat 5270639949 # Total ticks spent queuing -system.physmem.totMemAccLat 9020227449 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 999890000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26356.10 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6759 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6759 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.552744 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.790179 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 13.439026 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5671 83.90% 83.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 455 6.73% 90.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 79 1.17% 91.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 48 0.71% 92.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 32 0.47% 92.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 21 0.31% 93.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 53 0.78% 94.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 14 0.21% 94.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 132 1.95% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 15 0.22% 96.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 4 0.06% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 13 0.19% 96.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 74 1.09% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 97.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 97.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 26 0.38% 98.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 85 1.26% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 6 0.09% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 2 0.03% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 6 0.09% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 4 0.06% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6759 # Writes before turning the bus around for reads +system.physmem.totQLat 5409044047 # Total ticks spent queuing +system.physmem.totMemAccLat 9164425297 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1001435000 # Total ticks spent in databus transfers +system.physmem.avgQLat 27006.47 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 45106.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 45756.47 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.50 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.48 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.11 # Average system write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.49 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.06 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.71 # Average write queue length when enqueuing -system.physmem.readRowHits 166028 # Number of row buffer hits during reads -system.physmem.writeRowHits 80563 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.02 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.06 # Row buffer hit rate for writes -system.physmem.avgGap 8311633.41 # Average gap between requests -system.physmem.pageHitRate 72.80 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 367945200 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 200763750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 819124800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 465775920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186081086880 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 85063480605 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1634767041000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1907765218155 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.632478 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2719452348147 # Time in different power states -system.physmem_0.memoryStateTime::REF 95133480000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.87 # Average write queue length when enqueuing +system.physmem.readRowHits 166261 # Number of row buffer hits during reads +system.physmem.writeRowHits 80380 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.01 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.86 # Row buffer hit rate for writes +system.physmem.avgGap 8298964.51 # Average gap between requests +system.physmem.pageHitRate 72.71 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 368829720 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 201246375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 820489800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 465801840 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 85113851220 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1634657451750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1907701637745 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.635783 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2719265528725 # Time in different power states +system.physmem_0.memoryStateTime::REF 95129840000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 34391644853 # Time in different power states +system.physmem_0.memoryStateTime::ACT 34469380775 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 328497120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 179239500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 740688000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 433239840 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186081086880 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 83753939520 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1635915761250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1907432452110 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.515676 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2721369982715 # Time in different power states -system.physmem_1.memoryStateTime::REF 95133480000 # Time in different power states +system.physmem_1.actEnergy 330840720 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 180518250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 741741000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 434257200 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186073967040 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 83792356380 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1635816657750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1907370338340 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.519491 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2721199868682 # Time in different power states +system.physmem_1.memoryStateTime::REF 95129840000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 32475502785 # Time in different power states +system.physmem_1.memoryStateTime::ACT 32535082068 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 832 # Number of bytes read from this memory @@ -364,15 +361,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 36411615 # Number of BP lookups -system.cpu0.branchPred.condPredicted 17748077 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1698439 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 20740706 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 15063288 # Number of BTB hits +system.cpu0.branchPred.lookups 36420174 # Number of BP lookups +system.cpu0.branchPred.condPredicted 17682232 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1669191 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 20721489 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 15026104 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 72.626689 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 11337600 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 822333 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.514596 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 11397312 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 800928 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -403,57 +400,57 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 73296 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 73296 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47393 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25903 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walkWaitTime::samples 73296 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 73296 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 73296 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 7538 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 12243.300610 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 11373.544979 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7165.218707 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 7499 99.48% 99.48% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 33 0.44% 99.92% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walks 73306 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 73306 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 47488 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 25818 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walkWaitTime::samples 73306 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 73306 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 73306 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 7529 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 12317.505645 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 11403.047410 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7148.063589 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 7474 99.27% 99.27% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 46 0.61% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::163840-196607 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 7538 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 7529 # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walksPending::samples 581987000 # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::0 581987000 100.00% 100.00% # Table walker pending requests distribution system.cpu0.dtb.walker.walksPending::total 581987000 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5846 77.55% 77.55% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1692 22.45% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7538 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73296 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkPageSizes::4K 5847 77.66% 77.66% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1682 22.34% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7529 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 73306 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73296 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7538 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 73306 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7529 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7538 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 80834 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7529 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 80835 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24914388 # DTB read hits -system.cpu0.dtb.read_misses 66763 # DTB read misses -system.cpu0.dtb.write_hits 18539888 # DTB write hits -system.cpu0.dtb.write_misses 6533 # DTB write misses +system.cpu0.dtb.read_hits 24946697 # DTB read hits +system.cpu0.dtb.read_misses 66576 # DTB read misses +system.cpu0.dtb.write_hits 18555175 # DTB write hits +system.cpu0.dtb.write_misses 6730 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3822 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1461 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2016 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1386 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2027 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 633 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24981151 # DTB read accesses -system.cpu0.dtb.write_accesses 18546421 # DTB write accesses +system.cpu0.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 25013273 # DTB read accesses +system.cpu0.dtb.write_accesses 18561905 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 43454276 # DTB hits -system.cpu0.dtb.misses 73296 # DTB misses -system.cpu0.dtb.accesses 43527572 # DTB accesses +system.cpu0.dtb.hits 43501872 # DTB hits +system.cpu0.dtb.misses 73306 # DTB misses +system.cpu0.dtb.accesses 43575178 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -483,37 +480,38 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 4166 # Table walker walks requested -system.cpu0.itb.walker.walksShort 4166 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walks 4169 # Table walker walks requested +system.cpu0.itb.walker.walksShort 4169 # Table walker walks initiated with short descriptors system.cpu0.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3842 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walkWaitTime::samples 4166 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 4166 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 4166 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2675 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 12725.794393 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12032.430474 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5005.050560 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2427 90.73% 90.73% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 233 8.71% 99.44% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 14 0.52% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 3845 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walkWaitTime::samples 4169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 4169 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 4169 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2671 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12688.506177 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11997.245115 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5018.704234 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2423 90.72% 90.72% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 228 8.54% 99.25% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 18 0.67% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.04% 99.96% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2675 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2671 # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walksPending::samples 581277500 # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::0 581277500 100.00% 100.00% # Table walker pending requests distribution system.cpu0.itb.walker.walksPending::total 581277500 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2356 88.07% 88.07% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 319 11.93% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2675 # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::4K 2352 88.06% 88.06% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 319 11.94% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2671 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4166 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4166 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 4169 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 4169 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2675 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2675 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 6841 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 71495102 # ITB inst hits -system.cpu0.itb.inst_misses 4166 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2671 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2671 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 6840 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 71444406 # ITB inst hits +system.cpu0.itb.inst_misses 4169 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -522,131 +520,131 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2450 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2449 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 8197 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 8126 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 71499268 # ITB inst accesses -system.cpu0.itb.hits 71495102 # DTB hits -system.cpu0.itb.misses 4166 # DTB misses -system.cpu0.itb.accesses 71499268 # DTB accesses -system.cpu0.numCycles 248928104 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 71448575 # ITB inst accesses +system.cpu0.itb.hits 71444406 # DTB hits +system.cpu0.itb.misses 4169 # DTB misses +system.cpu0.itb.accesses 71448575 # DTB accesses +system.cpu0.numCycles 248815256 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 113059938 # Number of instructions committed -system.cpu0.committedOps 136701894 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 8937139 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 1889 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5449058014 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.201736 # CPI: cycles per instruction -system.cpu0.ipc 0.454187 # IPC: instructions per cycle +system.cpu0.committedInsts 113230333 # Number of instructions committed +system.cpu0.committedOps 136910947 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 8928789 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 1886 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5448949721 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.197426 # CPI: cycles per instruction +system.cpu0.ipc 0.455078 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1892 # number of quiesce instructions executed -system.cpu0.tickCycles 199965513 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 48962591 # Total number of cycles that the object has spent stopped -system.cpu0.dcache.tags.replacements 758556 # number of replacements -system.cpu0.dcache.tags.tagsinuse 498.399366 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 41853464 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 759068 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.137964 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 1891 # number of quiesce instructions executed +system.cpu0.tickCycles 199822657 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 48992599 # Total number of cycles that the object has spent stopped +system.cpu0.dcache.tags.replacements 758548 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.039628 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 41909246 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 759060 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.212033 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 600550000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 498.399366 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.973436 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.973436 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.039628 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.974687 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.974687 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 60 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 136 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 307 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 69 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 86857605 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 86857605 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 23301250 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 23301250 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 17363998 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 17363998 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 329371 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 329371 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 374920 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 374920 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370784 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 370784 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 40665248 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 40665248 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 40994619 # number of overall hits -system.cpu0.dcache.overall_hits::total 40994619 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 492930 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 492930 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 604783 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 604783 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 142057 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 142057 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 21393 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 21393 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20582 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20582 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1097713 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1097713 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1239770 # number of overall misses -system.cpu0.dcache.overall_misses::total 1239770 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6978123000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 6978123000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 12569253000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 12569253000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 330022000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 330022000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 544680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 544680500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 637500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 637500 # 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number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 396313 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 391366 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 391366 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 41762961 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 41762961 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 42234389 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 42234389 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.020716 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.020716 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.033657 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.033657 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301333 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301333 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053980 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053980 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052590 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052590 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026284 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.026284 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029355 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.029355 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14156.417747 # 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miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.301228 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.301228 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.054016 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.054016 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052386 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052386 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026250 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.026250 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029314 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029314 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14171.667816 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14171.667816 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 20779.185488 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 20779.185488 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15400.214893 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15400.214893 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26250.890200 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26250.890200 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17807.364949 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17807.364949 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15766.937416 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 15766.937416 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17812.157701 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17812.157701 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 15772.420413 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 15772.420413 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -655,149 +653,149 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 758556 # number of writebacks -system.cpu0.dcache.writebacks::total 758556 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75954 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 75954 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266286 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 266286 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14845 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14845 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 342240 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 342240 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 342240 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 342240 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416976 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 416976 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 338497 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 338497 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108439 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 108439 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6548 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6548 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20582 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20582 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 755473 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 755473 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 863912 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 863912 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32047 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32047 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28724 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28724 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60771 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60771 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5288189500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5288189500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7115551000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7115551000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1805226500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1805226500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104756500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104756500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 524110500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 524110500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 625500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 625500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403740500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12403740500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14208967000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14208967000 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6702515500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6702515500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452693000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452693000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12155208500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12155208500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017524 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017524 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018838 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018838 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230022 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230022 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016522 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016522 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052590 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052590 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018090 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018090 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020455 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020455 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12682.239505 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12682.239505 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21021.016434 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21021.016434 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16647.391621 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16647.391621 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15998.243739 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15998.243739 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25464.507822 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25464.507822 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 758548 # number of writebacks +system.cpu0.dcache.writebacks::total 758548 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 75935 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 75935 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 266250 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 266250 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 14874 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 14874 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 342185 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 342185 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 342185 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 342185 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 416985 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 416985 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 338554 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 338554 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 108405 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 108405 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6532 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6532 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20501 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20501 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 755539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 755539 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 863944 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 863944 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 32039 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 32039 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28722 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28722 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60761 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60761 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5289891000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5289891000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7113543500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7113543500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1810098500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1810098500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104404500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104404500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 517681500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 517681500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 995000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 995000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12403434500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12403434500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14213533000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 14213533000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6701732000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6701732000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5452636000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5452636000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12154368000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12154368000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017497 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.018822 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.018822 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.230025 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.230025 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016483 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016483 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052386 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052386 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018067 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018067 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020429 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020429 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12686.046261 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12686.046261 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 21011.547641 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 21011.547641 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16697.555463 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16697.555463 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15983.542560 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15983.542560 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25251.524316 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25251.524316 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16418.509331 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16418.509331 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16447.238839 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16447.238839 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209146.425562 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209146.425562 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189830.559811 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189830.559811 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200016.595086 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200016.595086 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 16416.670086 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16416.670086 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 16451.914707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16451.914707 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 209174.193951 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 209174.193951 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189841.793747 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189841.793747 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 200035.680782 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 200035.680782 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 2041160 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.728196 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 69444830 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 2041672 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 34.013705 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 2044571 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.728044 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69390799 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 2045083 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 33.930554 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 6975539000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728196 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728044 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999469 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999469 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 94 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 241 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 103 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 145014717 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 145014717 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 69444830 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 69444830 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 69444830 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 69444830 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 69444830 # number of overall hits -system.cpu0.icache.overall_hits::total 69444830 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 2041686 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 2041686 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 2041686 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 2041686 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 2041686 # number of overall misses -system.cpu0.icache.overall_misses::total 2041686 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20560339500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 20560339500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 20560339500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 20560339500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 20560339500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 20560339500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 71486516 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 71486516 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 71486516 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 71486516 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 71486516 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 71486516 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028560 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.028560 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028560 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.028560 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028560 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.028560 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10070.275008 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10070.275008 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10070.275008 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10070.275008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10070.275008 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10070.275008 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 144916894 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 144916894 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69390799 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69390799 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69390799 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69390799 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69390799 # number of overall hits +system.cpu0.icache.overall_hits::total 69390799 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 2045099 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 2045099 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 2045099 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 2045099 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 2045099 # number of overall misses +system.cpu0.icache.overall_misses::total 2045099 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 20582559000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 20582559000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 20582559000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 20582559000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 20582559000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 20582559000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 71435898 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 71435898 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 71435898 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 71435898 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 71435898 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 71435898 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.028628 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.028628 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.028628 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.028628 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.028628 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.028628 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10064.333805 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10064.333805 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10064.333805 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10064.333805 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10064.333805 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -806,337 +804,336 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 2041160 # number of writebacks -system.cpu0.icache.writebacks::total 2041160 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2041686 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 2041686 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 2041686 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 2041686 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 2041686 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 2041686 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 2044571 # number of writebacks +system.cpu0.icache.writebacks::total 2044571 # number of writebacks +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 2045099 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 2045099 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 2045099 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 2045099 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 2045099 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 2045099 # number of overall MSHR misses system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3917 # number of ReadReq MSHR uncacheable system.cpu0.icache.ReadReq_mshr_uncacheable::total 3917 # number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3917 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3917 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19539497000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 19539497000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19539497000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 19539497000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19539497000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 19539497000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 19560010000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 19560010000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 19560010000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 19560010000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 19560010000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 19560010000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 557356500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 557356500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 557356500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028560 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.028560 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028560 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.028560 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9570.275253 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9570.275253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9570.275253 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9570.275253 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.028628 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.028628 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.028628 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.028628 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9564.334049 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9564.334049 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9564.334049 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 142291.677304 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 142291.677304 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1926179 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1926371 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 166 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1927519 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1927689 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 149 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 244645 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 305884 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16117.392846 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 4898605 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 322066 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 15.209941 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 245495 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 305066 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16110.532476 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 4906564 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 321213 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 15.275110 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14778.459491 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 60.434424 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.065090 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1278.433841 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.902006 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003689 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_blocks::writebacks 14727.121799 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.543151 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.067969 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1324.799556 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.898872 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003573 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.078029 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983728 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 978 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15192 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 14 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 328 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 421 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 213 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::1 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 98 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 403 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4034 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 8338 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2319 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059692 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927246 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 93368748 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 93368748 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 90396 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5742 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 96138 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 507659 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 507659 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 2247535 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 2247535 # number of WritebackClean hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 233006 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 233006 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1971438 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1971438 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 430811 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 430811 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 90396 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5742 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1971438 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 663817 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 2731393 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 90396 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5742 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1971438 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 663817 # number of overall hits -system.cpu0.l2cache.overall_hits::total 2731393 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 708 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 94 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 802 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 57006 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 57006 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20580 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20580 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 48494 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 48494 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 70248 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 70248 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 101145 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 101145 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 708 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 94 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 70248 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 149639 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 220689 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 708 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 94 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 70248 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 149639 # number of overall misses -system.cpu0.l2cache.overall_misses::total 220689 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 33565000 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2328500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 35893500 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 209633000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 209633000 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 49175500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 49175500 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 605000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 605000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 3197349498 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 3197349498 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 4517158000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 4517158000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 3550453498 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 3550453498 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 33565000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2328500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 4517158000 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 6747802996 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 11300854496 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 33565000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2328500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 4517158000 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 6747802996 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 11300854496 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 91104 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 5836 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 96940 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.WritebackDirty_accesses::writebacks 507659 # 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mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 11681960500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 12207980500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008533 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for UpgradeReq accesses @@ -1145,127 +1142,127 @@ system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.153762 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.153762 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034373 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034373 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.189068 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.189068 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007771 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.016107 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034373 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.176850 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072776 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007771 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.016107 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034373 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.176850 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150881 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150881 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.034109 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.188585 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.188585 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.175536 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.072206 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007986 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.017104 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.034109 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.175536 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.162267 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38754.987531 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 78993.821493 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 27034.645476 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 27034.645476 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17929.494655 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17929.494655 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 266500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 266500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 56728.710378 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 56728.710378 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58335.427977 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58335.427977 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28958.752565 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28958.752565 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58335.427977 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37314.062269 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44186.186519 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41408.192090 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18771.276596 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58335.427977 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37314.062269 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78993.821493 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 63382.754233 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.161419 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 38675.577157 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 79986.785842 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26729.206845 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26729.206845 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17715.195122 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17715.195122 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 897500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 897500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57576.770958 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57576.770958 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 58591.927576 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 29095.821954 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 29095.821954 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44445.898363 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 41370.165746 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18969.696970 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 58591.927576 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37568.419587 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 79986.785842 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 64088.648483 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201141.323681 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193860.415972 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182312.630553 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182312.630553 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 201169.028372 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 193883.482590 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 182323.863241 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 182323.863241 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 134291.549655 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192241.760050 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188732.747959 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 192260.833429 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188750.123690 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 5755750 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2900650 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 44518 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 351752 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 347037 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4715 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 143210 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2766468 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28724 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 746011 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 2247535 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 246533 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 331594 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 87502 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43040 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 300476 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 297107 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2041686 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606504 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3118 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6096444 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2755852 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13844 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 190303 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 9056443 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 259253824 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104429286 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23344 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 364416 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 364070870 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1078661 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 4070756 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.104237 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.309335 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 5762889 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2904395 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 45067 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 350664 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 345809 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 143133 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2769477 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28722 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 745212 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 2295997 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 245518 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 331271 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87260 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42942 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114488 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 6 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 300512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 297211 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 2045099 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 606063 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3097 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 6142602 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2764050 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13802 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 189783 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 9110237 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 261989504 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 104964478 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 23152 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 362636 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 367339770 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1076533 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 4071717 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.104210 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.309410 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 3651149 89.69% 89.69% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 414892 10.19% 99.88% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4715 0.12% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 3652260 89.70% 89.70% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 414602 10.18% 99.88% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4855 0.12% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 4070756 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 5766247494 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 4071717 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 5772987994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 116466956 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 116128992 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 3069095112 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 3074216608 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1306223847 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1306190305 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 8018479 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 8023481 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 99225447 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 99154439 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 3641195 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2056746 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 213596 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2171070 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1462919 # Number of BTB hits +system.cpu1.branchPred.lookups 3635973 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2046610 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 209049 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2276641 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1455770 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 67.382397 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 753966 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 56559 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 63.943766 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 756757 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 55280 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1295,57 +1292,57 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 23130 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 23130 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 18836 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4294 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 23130 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 23130 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 23130 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1830 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11932.513661 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11127.774947 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 7404.648675 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 1668 91.15% 91.15% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 148 8.09% 99.23% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 8 0.44% 99.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 3 0.16% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1830 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 23538 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 23538 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 19270 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 4268 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 23538 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 23538 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 23538 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1839 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11777.052746 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10980.884481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6685.927584 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 1677 91.19% 91.19% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 150 8.16% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 7 0.38% 99.73% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.16% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1839 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples -1558893032 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 -1558893032 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total -1558893032 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1322 72.24% 72.24% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 508 27.76% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1830 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23130 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 1325 72.05% 72.05% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 514 27.95% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1839 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 23538 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23130 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1830 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 23538 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1839 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1830 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24960 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1839 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 25377 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3607725 # DTB read hits -system.cpu1.dtb.read_misses 21408 # DTB read misses -system.cpu1.dtb.write_hits 2997772 # DTB write hits -system.cpu1.dtb.write_misses 1722 # DTB write misses +system.cpu1.dtb.read_hits 3603943 # DTB read hits +system.cpu1.dtb.read_misses 21681 # DTB read misses +system.cpu1.dtb.write_hits 2994136 # DTB write hits +system.cpu1.dtb.write_misses 1857 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1725 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 120 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 261 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 128 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3629133 # DTB read accesses -system.cpu1.dtb.write_accesses 2999494 # DTB write accesses +system.cpu1.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3625624 # DTB read accesses +system.cpu1.dtb.write_accesses 2995993 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6605497 # DTB hits -system.cpu1.dtb.misses 23130 # DTB misses -system.cpu1.dtb.accesses 6628627 # DTB accesses +system.cpu1.dtb.hits 6598079 # DTB hits +system.cpu1.dtb.misses 23538 # DTB misses +system.cpu1.dtb.accesses 6621617 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1375,44 +1372,44 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1936 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1936 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 152 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1784 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1936 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1936 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 845 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11855.029586 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11358.377652 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 4391.934541 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 130 15.38% 15.38% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 557 65.92% 81.30% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.25% 94.56% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 22 2.60% 97.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.36% 97.51% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.70% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 2 0.24% 98.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 6 0.71% 99.76% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.12% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.12% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 845 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walks 1941 # Table walker walks requested +system.cpu1.itb.walker.walksShort 1941 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 151 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 1790 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 1941 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 1941 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 1941 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 844 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11680.687204 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11150.609492 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 4460.342613 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-8191 146 17.30% 17.30% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-12287 544 64.45% 81.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-16383 112 13.27% 95.02% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-20479 21 2.49% 97.51% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::20480-24575 2 0.24% 97.75% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-28671 10 1.18% 98.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::28672-32767 1 0.12% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.12% 99.17% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.59% 99.76% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-53247 1 0.12% 99.88% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::57344-61439 1 0.12% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 844 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples -1559948532 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 -1559948532 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total -1559948532 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 705 83.43% 83.43% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 140 16.57% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 845 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 705 83.53% 83.53% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 139 16.47% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 844 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1936 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1936 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1941 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1941 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 845 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 845 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 2781 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 6961088 # ITB inst hits -system.cpu1.itb.inst_misses 1936 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 844 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 844 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 2785 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 6953743 # ITB inst hits +system.cpu1.itb.inst_misses 1941 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1421,130 +1418,130 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 909 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 908 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1058 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1049 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 6963024 # ITB inst accesses -system.cpu1.itb.hits 6961088 # DTB hits -system.cpu1.itb.misses 1936 # DTB misses -system.cpu1.itb.accesses 6963024 # DTB accesses -system.cpu1.numCycles 40816703 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 6955684 # ITB inst accesses +system.cpu1.itb.hits 6953743 # DTB hits +system.cpu1.itb.misses 1941 # DTB misses +system.cpu1.itb.accesses 6955684 # DTB accesses +system.cpu1.numCycles 40734093 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 14109392 # Number of instructions committed -system.cpu1.committedOps 17295649 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 1386756 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 2772 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 5656506173 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 2.892875 # CPI: cycles per instruction -system.cpu1.ipc 0.345677 # IPC: instructions per cycle +system.cpu1.committedInsts 14107719 # Number of instructions committed +system.cpu1.committedOps 17288156 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 1387486 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 2746 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 5656373541 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 2.887362 # CPI: cycles per instruction +system.cpu1.ipc 0.346337 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2772 # number of quiesce instructions executed -system.cpu1.tickCycles 27557255 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 13259448 # Total number of cycles that the object has spent stopped -system.cpu1.dcache.tags.replacements 157096 # number of replacements -system.cpu1.dcache.tags.tagsinuse 475.586306 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6254726 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 157444 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 39.726671 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 91652045000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 475.586306 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.928880 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.928880 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 2746 # number of quiesce instructions executed +system.cpu1.tickCycles 27498026 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 13236067 # Total number of cycles that the object has spent stopped +system.cpu1.dcache.tags.replacements 156251 # number of replacements +system.cpu1.dcache.tags.tagsinuse 474.671754 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6246920 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 156599 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 39.891187 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 91622282000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 474.671754 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.927093 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.927093 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 283 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 65 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 286 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 62 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.679688 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 13266107 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 13266107 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3282974 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3282974 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2751908 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2751908 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42647 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42647 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70687 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70687 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 62029 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 62029 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6034882 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6034882 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6077529 # number of overall hits -system.cpu1.dcache.overall_hits::total 6077529 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 135266 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 135266 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 122118 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 122118 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24580 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 24580 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16502 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 16502 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23395 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23395 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 257384 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 257384 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 281964 # number of overall misses -system.cpu1.dcache.overall_misses::total 281964 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2192537500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2192537500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4529521000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4529521000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 318889500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 318889500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 637518000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 637518000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1095000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1095000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6722058500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6722058500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6722058500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 6722058500 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3418240 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3418240 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2874026 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2874026 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67227 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 67227 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87189 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87189 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85424 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85424 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6292266 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6292266 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6359493 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6359493 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039572 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.039572 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042490 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.042490 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.365627 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.365627 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189267 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189267 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.273869 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.273869 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040905 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.040905 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044337 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.044337 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16209.080626 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16209.080626 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37091.346075 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 37091.346075 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19324.294025 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19324.294025 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27250.181663 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27250.181663 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 13254229 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 13254229 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3282688 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3282688 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2748164 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2748164 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42687 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42687 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70657 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70657 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61986 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61986 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6030852 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6030852 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6073539 # number of overall hits +system.cpu1.dcache.overall_hits::total 6073539 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 134600 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 134600 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 121570 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 121570 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 24420 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 24420 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 16487 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 16487 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23399 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23399 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 256170 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 256170 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 280590 # number of overall misses +system.cpu1.dcache.overall_misses::total 280590 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2183210000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 2183210000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4500084500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 4500084500 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 318001000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 318001000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 633995000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 633995000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 321000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 321000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6683294500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 6683294500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6683294500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 6683294500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3417288 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3417288 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2869734 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2869734 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 67107 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 67107 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87144 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87144 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85385 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 85385 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6287022 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6287022 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6354129 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6354129 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.039388 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.039388 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.042363 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.042363 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.363896 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.363896 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.189193 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.189193 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274041 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274041 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.040746 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.040746 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044159 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.044159 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16219.985141 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16219.985141 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37016.406186 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37016.406186 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19287.984473 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19287.984473 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27094.961323 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27094.961323 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26116.846813 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 26116.846813 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23840.130300 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 23840.130300 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 26089.294219 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 26089.294219 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23818.719484 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23818.719484 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1553,149 +1550,149 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 157097 # number of writebacks -system.cpu1.dcache.writebacks::total 157097 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12921 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 12921 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 42016 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 42016 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11695 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11695 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 54937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 54937 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 54937 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 54937 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 122345 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 122345 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 80102 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 80102 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 24073 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 24073 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4807 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4807 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23395 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23395 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 202447 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 202447 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 226520 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 226520 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2973 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2973 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2311 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2311 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5284 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5284 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1862537500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1862537500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2760870000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2760870000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 453287500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 453287500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86939500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86939500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 614134000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 614134000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1084000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1084000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4623407500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4623407500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5076695000 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5076695000 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389226500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389226500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 251720500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 251720500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 640947000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 640947000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035792 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035792 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027871 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027871 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.358085 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.358085 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055133 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055133 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.273869 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.273869 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032174 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.032174 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035619 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035619 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15223.650333 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15223.650333 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34466.929665 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34466.929665 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18829.705479 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18829.705479 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18086.020387 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18086.020387 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26250.651849 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26250.651849 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 156252 # number of writebacks +system.cpu1.dcache.writebacks::total 156252 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 12906 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 12906 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 41816 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 41816 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 11699 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 11699 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 54722 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 54722 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 54722 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 54722 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 121694 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 121694 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 79754 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 79754 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23886 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 23886 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4788 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4788 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23399 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 201448 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 201448 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 225334 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 225334 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 2976 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 2976 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2312 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2312 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5288 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5288 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1855487000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1855487000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2737931500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2737931500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 451965000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 451965000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 86630500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 86630500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 610601000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 610601000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 316000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 316000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4593418500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4593418500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5045383500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5045383500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 389399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 389399500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 252039500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 252039500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 641439000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 641439000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035611 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035611 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027791 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.355939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.355939 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054944 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054944 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274041 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274041 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032042 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032042 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035463 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035463 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15247.152694 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15247.152694 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34329.707601 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34329.707601 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18921.753328 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 18921.753328 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18093.253968 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18093.253968 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26095.175007 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26095.175007 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22837.619229 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22837.619229 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22411.685502 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22411.685502 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130920.450723 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130920.450723 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 108922.760710 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 108922.760710 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121299.583649 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121299.583649 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22802.005977 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 22802.005977 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22390.688933 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22390.688933 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 130846.606183 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 130846.606183 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 109013.624567 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 109013.624567 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 121300.869894 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 121300.869894 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 864194 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.135415 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6095160 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 864706 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 7.048824 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 73316283000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.135415 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974874 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974874 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 863100 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.134862 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6088925 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 863612 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 7.050533 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 73321501000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.134862 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974873 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974873 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 460 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 51 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 464 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 47 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14784438 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14784438 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6095160 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6095160 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6095160 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6095160 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6095160 # number of overall hits -system.cpu1.icache.overall_hits::total 6095160 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 864706 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 864706 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 864706 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 864706 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 864706 # number of overall misses -system.cpu1.icache.overall_misses::total 864706 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7648423000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7648423000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7648423000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7648423000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7648423000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7648423000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 6959866 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 6959866 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 6959866 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 6959866 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 6959866 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 6959866 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.124242 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.124242 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.124242 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.124242 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.124242 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.124242 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8845.113831 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8845.113831 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8845.113831 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8845.113831 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8845.113831 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8845.113831 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 14768686 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 14768686 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6088925 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6088925 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6088925 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6088925 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6088925 # number of overall hits +system.cpu1.icache.overall_hits::total 6088925 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 863612 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 863612 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 863612 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 863612 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 863612 # number of overall misses +system.cpu1.icache.overall_misses::total 863612 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8850.454255 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8850.454255 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1704,457 +1701,447 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 864194 # number of writebacks -system.cpu1.icache.writebacks::total 864194 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 864706 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 864706 # 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number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7211552500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7211552500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7211552500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7211552500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7211552500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7211552500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 15350500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 15350500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 15350500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 15350500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124242 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.124242 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124242 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.124242 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8345.113831 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8345.113831 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8345.113831 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8345.113831 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.124215 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.124215 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.124215 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.124215 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8350.454255 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8350.454255 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8350.454255 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8350.454255 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137058.035714 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137058.035714 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 119025 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 119084 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 52 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 119510 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 119557 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 41 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 48684 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 38075 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15173.951540 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1858742 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 53288 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 34.881061 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 49379 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 38013 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15156.094149 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1857838 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 53311 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 34.849056 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14749.353983 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 37.286789 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.078849 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 387.231918 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.900229 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.002276 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_blocks::writebacks 14713.350805 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 27.823499 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.085233 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 414.834611 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.898032 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001698 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000005 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.023635 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.926145 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 919 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 92 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14202 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 5 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 50 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 864 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 18 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.025319 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.925055 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 902 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 91 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 14305 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 1 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 39 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 862 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 13 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 18 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 56 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 337 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 1786 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 12079 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.056091 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.005615 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.866821 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 34538889 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 34538889 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 24515 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2453 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 26968 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 95201 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 95201 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 907759 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 907759 # number of WritebackClean hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 18142 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 18142 # number of ReadExReq hits -system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 851797 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadCleanReq_hits::total 851797 # number of ReadCleanReq hits -system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 83849 # number of ReadSharedReq hits -system.cpu1.l2cache.ReadSharedReq_hits::total 83849 # number of ReadSharedReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 24515 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2453 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 851797 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 101991 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 980756 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 24515 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2453 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 851797 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 101991 # number of overall hits -system.cpu1.l2cache.overall_hits::total 980756 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 708 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 242 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 950 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29444 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29444 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23394 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23394 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 32519 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 32519 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 12909 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 12909 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 67373 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 67373 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 708 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 242 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 12909 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 99892 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 113751 # 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mshr miss rate for ReadReq accesses +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 600106000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 614560500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.026612 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.090124 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032590 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.637236 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.637236 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.014918 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.014918 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.445292 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.445292 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.028070 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.089796 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.014918 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.493459 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103673 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.028070 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.089796 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.014918 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.493459 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.636374 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.636374 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.015090 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.015090 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.445190 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.445190 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026612 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.090124 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.015090 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.493285 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103456 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026612 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.090124 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.015090 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.493285 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.122021 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15743.157895 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 50954.308834 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20506.622741 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20506.622741 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18685.581773 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18685.581773 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1000999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1000999 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46952.080042 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46952.080042 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51190.852713 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51190.852713 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17954.290237 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17954.290237 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51190.852713 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27351.261240 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29964.290400 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16322.740113 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14047.520661 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51190.852713 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27351.261240 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 50954.308834 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 33120.502168 # average overall mshr miss latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.121556 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15914.316703 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 48657.133070 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20320.868702 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20320.868702 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 18534.253601 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18534.253601 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 46804.355937 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 46804.355937 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 51000.767342 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 18030.280336 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 18030.280336 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 29999.190646 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16547.653959 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14114.583333 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 51000.767342 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 27368.557233 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 48657.133070 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 32777.297974 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122897.914564 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123121.555916 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101369.104284 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101369.104284 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 122826.444892 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 123052.461140 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 101459.558824 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 101459.558824 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129058.035714 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113482.115821 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113805.411416 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 113484.493192 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 113807.500000 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 2148021 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1081444 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18331 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 178235 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 177001 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1234 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 34229 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 1087159 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2311 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 125656 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 907759 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 98212 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 24432 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 72484 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41782 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85083 # Transaction distribution +system.cpu1.toL2Bus.snoop_filter.tot_requests 2143691 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 1079194 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 18287 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 177461 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 175960 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1501 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 34625 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 1085487 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2312 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 125339 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 924619 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 97697 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 24084 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71468 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41763 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 84759 # Transaction distribution system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57811 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 55294 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 864706 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 235840 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 36 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2577500 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 749010 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6415 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 52647 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 3385572 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 109611648 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25531190 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10780 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 100892 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 135254510 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 383471 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1462314 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.140260 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.349678 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57626 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 55185 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 863612 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 234129 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 33 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 2590548 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 747561 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 6394 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 53434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3397937 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 110516736 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 25535556 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 10652 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 102512 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 136165456 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 380835 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1457969 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.140235 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.350184 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1258444 86.06% 86.06% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 202636 13.86% 99.92% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1234 0.08% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1255011 86.08% 86.08% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 201457 13.82% 99.90% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1501 0.10% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1462314 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2111082490 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1457969 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2107221995 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 78627228 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 78416105 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1297343267 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1295704762 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 334901961 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 333278550 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 3720499 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 3731000 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 27451445 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 27832447 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31009 # Transaction distribution system.iobus.trans_dist::ReadResp 31009 # Transaction distribution -system.iobus.trans_dist::WriteReq 59424 # Transaction distribution -system.iobus.trans_dist::WriteResp 59424 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) +system.iobus.trans_dist::WriteReq 59425 # Transaction distribution +system.iobus.trans_dist::WriteResp 59425 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56620 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2173,11 +2160,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 107934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72934 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72934 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 180866 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 180868 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71564 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) @@ -2196,63 +2183,63 @@ system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 162814 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321176 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321176 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2483988 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 51120500 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2483990 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 51092500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 109500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 320500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 322000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 30500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 12500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 14000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 84500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 84000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 571500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 576000 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 20500 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 19500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 45500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 8500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 8500 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6117000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6104500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 32846500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 32859000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 186337026 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187096728 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 84733000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36758000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36449 # number of replacements -system.iocache.tags.tagsinuse 14.469949 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.469909 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36465 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 272430408000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.469949 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.904372 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.904372 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 272427086000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.469909 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.904369 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.904369 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2266,14 +2253,14 @@ system.iocache.demand_misses::realview.ide 243 # system.iocache.demand_misses::total 243 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 243 # number of overall misses system.iocache.overall_misses::total 243 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32247375 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32247375 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4733187651 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4733187651 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32247375 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32247375 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32247375 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32247375 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 31652377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 31652377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4575926351 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4575926351 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 31652377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 31652377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 31652377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 31652377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 243 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 243 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2290,19 +2277,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 132705.246914 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 132705.246914 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130664.411744 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130664.411744 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 132705.246914 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 132705.246914 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 132705.246914 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 132705.246914 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 621 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130256.695473 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130256.695473 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 126323.055184 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 126323.055184 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130256.695473 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130256.695473 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130256.695473 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 9 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 79 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 2 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.860759 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 4.500000 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2316,14 +2303,14 @@ system.iocache.demand_mshr_misses::realview.ide 243 system.iocache.demand_mshr_misses::total 243 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 243 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 243 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20097375 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20097375 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2921987651 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2921987651 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20097375 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20097375 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20097375 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20097375 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19502377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19502377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2763035342 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2763035342 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19502377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19502377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19502377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19502377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -2332,304 +2319,304 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 82705.246914 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 82705.246914 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80664.411744 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80664.411744 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 82705.246914 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 82705.246914 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 82705.246914 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 82705.246914 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80256.695473 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80256.695473 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 76276.373178 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 76276.373178 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80256.695473 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80256.695473 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 131701 # number of replacements -system.l2c.tags.tagsinuse 63232.493895 # Cycle average of tags in use -system.l2c.tags.total_refs 477114 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195835 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.436306 # Average number of references to valid blocks. +system.l2c.tags.replacements 132173 # number of replacements +system.l2c.tags.tagsinuse 63220.230545 # Cycle average of tags in use +system.l2c.tags.total_refs 476061 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 196324 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.424874 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13499.183462 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 81.189305 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.030804 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 9276.099032 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2886.907500 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33207.909394 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.955383 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1918.551839 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 583.845643 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1772.821532 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.205981 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001239 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.141542 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.044051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000091 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.029275 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.008909 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.027051 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964851 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 28913 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 59 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 35162 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4903 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23890 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 59 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 5 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 22 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 486 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 3361 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 31288 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.441177 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000900 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.536530 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6403013 # Number of tag accesses -system.l2c.tags.data_accesses 6403013 # Number of data accesses -system.l2c.WritebackDirty_hits::writebacks 266916 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 266916 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 34147 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2219 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 36366 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2260 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 929 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3189 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4341 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1335 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5676 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 425 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 47541 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 51775 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49659 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 78 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 12 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 9744 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 5530 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3532 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 168385 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 425 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 47541 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 56116 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 49659 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 78 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 12 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 9744 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6865 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 3532 # number of demand (read+write) hits -system.l2c.demand_hits::total 174061 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 425 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits -system.l2c.overall_hits::cpu0.inst 47541 # number of overall hits -system.l2c.overall_hits::cpu0.data 56116 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 49659 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 78 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 12 # number of overall hits -system.l2c.overall_hits::cpu1.inst 9744 # number of overall hits -system.l2c.overall_hits::cpu1.data 6865 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 3532 # number of overall hits -system.l2c.overall_hits::total 174061 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 10466 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2461 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12927 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 842 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1269 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2111 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11510 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8279 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19789 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 132 # number of ReadSharedReq misses +system.l2c.tags.occ_blocks::writebacks 13508.269285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 83.219026 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.034479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9248.082270 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2930.331388 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33200.975902 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.874579 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1907.881821 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 574.003662 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1760.558132 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.206120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001270 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.141115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044713 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.506607 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.029112 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008759 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.026864 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.964664 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 29038 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 62 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 35051 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5162 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 23744 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 61 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 28 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 489 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 3341 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 31190 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.443085 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000946 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.534836 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 6395223 # Number of tag accesses +system.l2c.tags.data_accesses 6395223 # Number of data accesses +system.l2c.WritebackDirty_hits::writebacks 266844 # number of WritebackDirty hits +system.l2c.WritebackDirty_hits::total 266844 # number of WritebackDirty hits +system.l2c.UpgradeReq_hits::cpu0.data 34054 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 2186 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 36240 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 2212 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 949 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3161 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 4419 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1324 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5743 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 427 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 96 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 47128 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 51485 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 49241 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 65 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 16 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 9897 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 5499 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 3682 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 167536 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 427 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 96 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 47128 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 55904 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 49241 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 65 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 16 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 9897 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 6823 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 3682 # number of demand (read+write) hits +system.l2c.demand_hits::total 173279 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 427 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 96 # number of overall hits +system.l2c.overall_hits::cpu0.inst 47128 # number of overall hits +system.l2c.overall_hits::cpu0.data 55904 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 49241 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 65 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 16 # number of overall hits +system.l2c.overall_hits::cpu1.inst 9897 # number of overall hits +system.l2c.overall_hits::cpu1.data 6823 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 3682 # number of overall hits +system.l2c.overall_hits::total 173279 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 10558 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2446 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13004 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 813 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1268 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2081 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11436 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8196 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 19632 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 136 # number of ReadSharedReq misses system.l2c.ReadSharedReq_misses::cpu0.itb.walker 1 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.inst 22638 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.data 9815 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133222 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 10 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.inst 3156 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.data 1620 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5587 # number of ReadSharedReq misses -system.l2c.ReadSharedReq_misses::total 176181 # number of ReadSharedReq misses -system.l2c.demand_misses::cpu0.dtb.walker 132 # number of demand (read+write) misses +system.l2c.ReadSharedReq_misses::cpu0.inst 22627 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 9886 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 133981 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 12 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 3135 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 1669 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 5217 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 176664 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 136 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 22638 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 21325 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 133222 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 3156 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 9899 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 5587 # number of demand (read+write) misses -system.l2c.demand_misses::total 195970 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 132 # number of overall misses +system.l2c.demand_misses::cpu0.inst 22627 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 21322 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 133981 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 3135 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9865 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 5217 # number of demand (read+write) misses +system.l2c.demand_misses::total 196296 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 136 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 22638 # number of overall misses -system.l2c.overall_misses::cpu0.data 21325 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 133222 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses -system.l2c.overall_misses::cpu1.inst 3156 # number of overall misses -system.l2c.overall_misses::cpu1.data 9899 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 5587 # number of overall misses -system.l2c.overall_misses::total 195970 # number of overall misses -system.l2c.UpgradeReq_miss_latency::cpu0.data 30632500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 6192500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 36825000 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 4484000 # number of SCUpgradeReq miss cycles +system.l2c.overall_misses::cpu0.inst 22627 # number of overall misses +system.l2c.overall_misses::cpu0.data 21322 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 133981 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu1.inst 3135 # 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mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 72833.870051 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 72392.681930 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 72750.884343 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 74662.976630 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 73882.886435 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 74187.650168 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 138043.153987 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 122120.487067 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 131395.732529 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127460.264901 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 129241.975309 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137039.470064 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 127634.534999 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 127863.691432 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 137674.636844 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 132369.214537 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 122955.601576 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 136364.055714 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 128424.242424 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 133217.171091 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 127419.117647 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 123000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 120956.790669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 132369.214537 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 139988.067129 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 132600 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 122321.077655 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 122955.601576 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159498.997494 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 136364.055714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 121018.389250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 133217.171091 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 140844.755115 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 123958.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 123400.391124 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123092.145261 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 159524.463676 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 137046.647250 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183140.762006 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 183168.232654 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 105001.010101 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169974.645290 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165307.861022 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84366.724362 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159280.634767 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 104928.524050 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 169983.978587 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165318.379779 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 84456.099481 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159294.225881 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 113291.549655 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174711.869148 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 174730.526324 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 108053.571429 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95971.312251 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 165238.859320 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 95972.564617 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 165249.825387 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 39046 # Transaction distribution -system.membus.trans_dist::ReadResp 215465 # Transaction distribution -system.membus.trans_dist::WriteReq 31035 # Transaction distribution -system.membus.trans_dist::WriteResp 31035 # Transaction distribution -system.membus.trans_dist::WritebackDirty 138266 # Transaction distribution -system.membus.trans_dist::CleanEvict 17702 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74461 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40765 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15160 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40157 # Transaction distribution -system.membus.trans_dist::ReadExResp 19667 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 176419 # Transaction distribution +system.membus.trans_dist::ReadReq 39041 # Transaction distribution +system.membus.trans_dist::ReadResp 215941 # Transaction distribution +system.membus.trans_dist::WriteReq 31034 # Transaction distribution +system.membus.trans_dist::WriteResp 31034 # Transaction distribution +system.membus.trans_dist::WritebackDirty 138436 # Transaction distribution +system.membus.trans_dist::CleanEvict 18070 # Transaction distribution +system.membus.trans_dist::UpgradeReq 73582 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40721 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 40108 # Transaction distribution +system.membus.trans_dist::ReadExResp 19531 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 176900 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 42 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 679941 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 802135 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108925 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 911060 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14216 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 664933 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 787125 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 72931 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860056 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162814 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 1344 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19320688 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19513284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28432 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19353628 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19546218 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21831428 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 121126 # Total snoops (count) -system.membus.snoop_fanout::samples 594326 # Request fanout histogram +system.membus.pkt_size::total 21864362 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 120262 # Total snoops (count) +system.membus.snoop_fanout::samples 594139 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 594326 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 594139 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 594326 # Request fanout histogram -system.membus.reqLayer0.occupancy 91340500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 594139 # Request fanout histogram +system.membus.reqLayer0.occupancy 91324000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 23828 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12352499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 12307500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1009821404 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1010896317 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1176071579 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1147679286 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64144132 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1341127 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -2945,52 +2930,52 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 1045963 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 564632 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 154673 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20991 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19997 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 994 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 39049 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 502457 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 405200 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 105572 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 110705 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43954 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 154659 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51324 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51324 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 463423 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 1042334 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 562614 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 153410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21132 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1023 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 39044 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 500861 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31034 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31034 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 405302 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 139265 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109721 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43882 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153603 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 18 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 18 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 51189 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 51189 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 461832 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1306764 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270016 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1576780 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36870810 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4377514 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 41248324 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 449455 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 943932 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.340597 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.476127 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1332417 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 274320 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1606737 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36835698 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4378808 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 41214506 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 447707 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 941615 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.339048 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.475676 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 623426 66.05% 66.05% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 319512 33.85% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 994 0.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 623385 66.20% 66.20% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 317207 33.69% 99.89% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1023 0.11% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 943932 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 904213819 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 941615 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 901922668 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 343121 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 342123 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 693007025 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 690834076 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 215048953 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 214047025 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- |