diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-01-04 13:02:12 -0600 |
| commit | e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb (patch) | |
| tree | 553bace58f742b4c98ac52d600a1103901011b8b /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual | |
| parent | 0d8d6e44419e2c5464012b66abc62aaad433026b (diff) | |
| download | gem5-e979e8d75e12caee2b4b1ab3512d7f2fdba4fcdb.tar.xz | |
stats: changes due to recent changesets.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 1070 |
1 files changed, 614 insertions, 456 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 16f8b652d..f1c3d0229 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -4,21 +4,23 @@ sim_seconds 2.845843 # Nu sim_ticks 2845842660500 # Number of ticks simulated final_tick 2845842660500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 164712 # Simulator instruction rate (inst/s) -host_op_rate 199442 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3743328799 # Simulator tick rate (ticks/s) -host_mem_usage 646452 # Number of bytes of host memory used -host_seconds 760.24 # Real time elapsed on the host +host_inst_rate 92448 # Simulator instruction rate (inst/s) +host_op_rate 111941 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2101025547 # Simulator tick rate (ticks/s) +host_mem_usage 635156 # Number of bytes of host memory used +host_seconds 1354.50 # Real time elapsed on the host sim_insts 125221621 # Number of instructions simulated sim_ops 151624712 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 10368 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 3007420 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1722304 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1285116 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.l2cache.prefetcher 8732480 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 768 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 774240 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 153024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 621216 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.l2cache.prefetcher 399936 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory system.physmem.bytes_read::total 12926236 # Number of bytes read from this memory @@ -26,28 +28,32 @@ system.physmem.bytes_inst_read::cpu0.inst 1722304 # N system.physmem.bytes_inst_read::cpu1.inst 153024 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 1875328 # Number of instructions bytes read from this memory system.physmem.bytes_written::writebacks 8977344 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.inst 17704 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.inst 40 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17704 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory system.physmem.bytes_written::total 8995088 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 162 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 47516 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 26911 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 20605 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.l2cache.prefetcher 136445 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 12 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 12121 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9730 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.l2cache.prefetcher 6249 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory system.physmem.num_reads::total 202521 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 140271 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.inst 4426 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.inst 10 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 4426 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory system.physmem.num_writes::total 144707 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 3643 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 1056777 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 605200 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 451577 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.l2cache.prefetcher 3068504 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 270 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 272060 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 53771 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 218289 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.l2cache.prefetcher 140533 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 4542147 # Total read bandwidth from this memory (bytes/s) @@ -55,16 +61,18 @@ system.physmem.bw_inst_read::cpu0.inst 605200 # In system.physmem.bw_inst_read::cpu1.inst 53771 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 658971 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_write::writebacks 3154547 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.inst 6221 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 14 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6221 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::total 3160782 # Write bandwidth from this memory (bytes/s) system.physmem.bw_total::writebacks 3154547 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 3643 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 1062998 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 605200 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 457798 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.l2cache.prefetcher 3068504 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 270 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 272074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 53771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 218303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.l2cache.prefetcher 140533 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 7702929 # Total bandwidth to/from this memory (bytes/s) @@ -544,8 +552,8 @@ system.cpu0.dcache.tags.total_refs 40476936 # To system.cpu0.dcache.tags.sampled_refs 719053 # Sample count of references to valid blocks. system.cpu0.dcache.tags.avg_refs 56.292006 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 306903000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 494.305697 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.965441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.305697 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.965441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id @@ -554,81 +562,81 @@ system.cpu0.dcache.tags.age_task_id_blocks_1024::2 68 system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id system.cpu0.dcache.tags.tag_accesses 83802985 # Number of tag accesses system.cpu0.dcache.tags.data_accesses 83802985 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.inst 22808347 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu0.data 22808347 # number of ReadReq hits system.cpu0.dcache.ReadReq_hits::total 22808347 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.inst 16863099 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 16863099 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 16863099 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 381264 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 381264 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 381264 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 362825 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 362825 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 362825 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.inst 39671446 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu0.data 39671446 # number of demand (read+write) hits system.cpu0.dcache.demand_hits::total 39671446 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.inst 39671446 # number of overall hits +system.cpu0.dcache.overall_hits::cpu0.data 39671446 # number of overall hits system.cpu0.dcache.overall_hits::total 39671446 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.inst 540080 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu0.data 540080 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 540080 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.inst 532227 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 532227 # number of WriteReq misses system.cpu0.dcache.WriteReq_misses::total 532227 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.inst 6489 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6489 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6489 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.inst 19898 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 19898 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 19898 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.inst 1072307 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu0.data 1072307 # number of demand (read+write) misses system.cpu0.dcache.demand_misses::total 1072307 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.inst 1072307 # number of overall misses +system.cpu0.dcache.overall_misses::cpu0.data 1072307 # number of overall misses system.cpu0.dcache.overall_misses::total 1072307 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.inst 6648434719 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 6648434719 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 6648434719 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.inst 8319872197 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 8319872197 # number of WriteReq miss cycles system.cpu0.dcache.WriteReq_miss_latency::total 8319872197 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.inst 104923750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 104923750 # number of LoadLockedReq miss cycles system.cpu0.dcache.LoadLockedReq_miss_latency::total 104923750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.inst 438142885 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 438142885 # number of StoreCondReq miss cycles system.cpu0.dcache.StoreCondReq_miss_latency::total 438142885 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 309000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 309000 # number of StoreCondFailReq miss cycles system.cpu0.dcache.StoreCondFailReq_miss_latency::total 309000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.inst 14968306916 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 14968306916 # number of demand (read+write) miss cycles system.cpu0.dcache.demand_miss_latency::total 14968306916 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.inst 14968306916 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 14968306916 # number of overall miss cycles system.cpu0.dcache.overall_miss_latency::total 14968306916 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.inst 23348427 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu0.data 23348427 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.ReadReq_accesses::total 23348427 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.inst 17395326 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17395326 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 17395326 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 387753 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 387753 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 387753 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 382723 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 382723 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 382723 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.inst 40743753 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu0.data 40743753 # number of demand (read+write) accesses system.cpu0.dcache.demand_accesses::total 40743753 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.inst 40743753 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40743753 # number of overall (read+write) accesses system.cpu0.dcache.overall_accesses::total 40743753 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.023131 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023131 # miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_miss_rate::total 0.023131 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.030596 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.030596 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.030596 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.016735 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016735 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.016735 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.051991 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051991 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051991 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.026318 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026318 # miss rate for demand accesses system.cpu0.dcache.demand_miss_rate::total 0.026318 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.026318 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026318 # miss rate for overall accesses system.cpu0.dcache.overall_miss_rate::total 0.026318 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 12310.092429 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 12310.092429 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 12310.092429 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15632.187388 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15632.187388 # average WriteReq miss latency system.cpu0.dcache.WriteReq_avg_miss_latency::total 15632.187388 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16169.479119 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16169.479119 # average LoadLockedReq miss latency system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16169.479119 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 22019.443411 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22019.443411 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22019.443411 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency +system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency system.cpu0.dcache.demand_avg_miss_latency::total 13958.975290 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13958.975290 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13958.975290 # average overall miss latency system.cpu0.dcache.overall_avg_miss_latency::total 13958.975290 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -640,77 +648,77 @@ system.cpu0.dcache.fast_writes 0 # nu system.cpu0.dcache.cache_copies 0 # number of cache copies performed system.cpu0.dcache.writebacks::writebacks 523102 # number of writebacks system.cpu0.dcache.writebacks::total 523102 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 42658 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 42658 # number of ReadReq MSHR hits system.cpu0.dcache.ReadReq_mshr_hits::total 42658 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 230433 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 230433 # number of WriteReq MSHR hits system.cpu0.dcache.WriteReq_mshr_hits::total 230433 # number of WriteReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 273091 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 273091 # number of demand (read+write) MSHR hits system.cpu0.dcache.demand_mshr_hits::total 273091 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 273091 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 273091 # number of overall MSHR hits system.cpu0.dcache.overall_mshr_hits::total 273091 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 497422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 497422 # number of ReadReq MSHR misses system.cpu0.dcache.ReadReq_mshr_misses::total 497422 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 301794 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 301794 # number of WriteReq MSHR misses system.cpu0.dcache.WriteReq_mshr_misses::total 301794 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 6489 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6489 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6489 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 19898 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 19898 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 19898 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 799216 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 799216 # number of demand (read+write) MSHR misses system.cpu0.dcache.demand_mshr_misses::total 799216 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 799216 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 799216 # number of overall MSHR misses system.cpu0.dcache.overall_mshr_misses::total 799216 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 5149793898 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5149793898 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5149793898 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 4423706193 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4423706193 # number of WriteReq MSHR miss cycles system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4423706193 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 91926250 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91926250 # number of LoadLockedReq MSHR miss cycles system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91926250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 397751115 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 397751115 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 397751115 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 291000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 291000 # number of StoreCondFailReq MSHR miss cycles system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 291000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 9573500091 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9573500091 # number of demand (read+write) MSHR miss cycles system.cpu0.dcache.demand_mshr_miss_latency::total 9573500091 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 9573500091 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9573500091 # number of overall MSHR miss cycles system.cpu0.dcache.overall_mshr_miss_latency::total 9573500091 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6190990749 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6190990749 # number of ReadReq MSHR uncacheable cycles system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6190990749 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4804555500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4804555500 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4804555500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 10995546249 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 10995546249 # number of overall MSHR uncacheable cycles system.cpu0.dcache.overall_mshr_uncacheable_latency::total 10995546249 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.021304 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.021304 # mshr miss rate for ReadReq accesses system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.021304 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.017349 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.017349 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.017349 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.016735 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016735 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016735 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.051991 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051991 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051991 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.019616 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.019616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.019616 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.019616 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10352.967697 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 10352.967697 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 10352.967697 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14658.032277 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 14658.032277 # average WriteReq mshr miss latency system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14658.032277 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14166.474033 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14166.474033 # average LoadLockedReq mshr miss latency system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14166.474033 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 19989.502211 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 19989.502211 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 19989.502211 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11978.614156 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 11978.614156 # average overall mshr miss latency system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11978.614156 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.icache.tags.replacements 1982441 # number of replacements @@ -821,12 +829,14 @@ system.cpu0.l2cache.tags.warmup_cycle 2825848630000 # C system.cpu0.l2cache.tags.occ_blocks::writebacks 6310.295058 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 58.412646 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.063392 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 7791.524761 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 5929.101601 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1862.423160 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1981.430976 # Average occupied blocks per requestor system.cpu0.l2cache.tags.occ_percent::writebacks 0.385150 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.003565 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.475557 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.361884 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.113673 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.120937 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_percent::total 0.985213 # Average percentage of cache occupancy system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1941 # Occupied blocks per task id @@ -851,125 +861,143 @@ system.cpu0.l2cache.tags.tag_accesses 55347065 # Nu system.cpu0.l2cache.tags.data_accesses 55347065 # Number of data accesses system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 80493 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 4332 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 2344344 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1910084 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.data 434260 # number of ReadReq hits system.cpu0.l2cache.ReadReq_hits::total 2429169 # number of ReadReq hits system.cpu0.l2cache.Writeback_hits::writebacks 523100 # number of Writeback hits system.cpu0.l2cache.Writeback_hits::total 523100 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 4781 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 4781 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 4781 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 1890 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1890 # number of SCUpgradeReq hits system.cpu0.l2cache.SCUpgradeReq_hits::total 1890 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 226532 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 226532 # number of ReadExReq hits system.cpu0.l2cache.ReadExReq_hits::total 226532 # number of ReadExReq hits system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 80493 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::cpu0.itb.walker 4332 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 2570876 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1910084 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 660792 # number of demand (read+write) hits system.cpu0.l2cache.demand_hits::total 2655701 # number of demand (read+write) hits system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 80493 # number of overall hits system.cpu0.l2cache.overall_hits::cpu0.itb.walker 4332 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 2570876 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1910084 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 660792 # number of overall hits system.cpu0.l2cache.overall_hits::total 2655701 # number of overall hits system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 854 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 113 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 142527 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.inst 72883 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.data 69644 # number of ReadReq misses system.cpu0.l2cache.ReadReq_misses::total 143494 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.inst 26406 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 26406 # number of UpgradeReq misses system.cpu0.l2cache.UpgradeReq_misses::total 26406 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.inst 18006 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 18006 # number of SCUpgradeReq misses system.cpu0.l2cache.SCUpgradeReq_misses::total 18006 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.inst 2 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.inst 44082 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 44082 # number of ReadExReq misses system.cpu0.l2cache.ReadExReq_misses::total 44082 # number of ReadExReq misses system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 854 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::cpu0.itb.walker 113 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 186609 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 72883 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 113726 # number of demand (read+write) misses system.cpu0.l2cache.demand_misses::total 187576 # number of demand (read+write) misses system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 854 # number of overall misses system.cpu0.l2cache.overall_misses::cpu0.itb.walker 113 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 186609 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 72883 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 113726 # number of overall misses system.cpu0.l2cache.overall_misses::total 187576 # number of overall misses system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 30085500 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 2495499 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 5310554679 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 3197828979 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2112725700 # number of ReadReq miss cycles system.cpu0.l2cache.ReadReq_miss_latency::total 5343135678 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 462181513 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 462181513 # number of UpgradeReq miss cycles system.cpu0.l2cache.UpgradeReq_miss_latency::total 462181513 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 354964789 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 354964789 # number of SCUpgradeReq miss cycles system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 354964789 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.inst 282000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 282000 # number of SCUpgradeFailReq miss cycles system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 282000 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.inst 2099231484 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2099231484 # number of ReadExReq miss cycles system.cpu0.l2cache.ReadExReq_miss_latency::total 2099231484 # number of ReadExReq miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 30085500 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 2495499 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 7409786163 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 3197828979 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 4211957184 # number of demand (read+write) miss cycles system.cpu0.l2cache.demand_miss_latency::total 7442367162 # number of demand (read+write) miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 30085500 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 2495499 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 7409786163 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 3197828979 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 4211957184 # number of overall miss cycles system.cpu0.l2cache.overall_miss_latency::total 7442367162 # number of overall miss cycles system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 81347 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 4445 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 2486871 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1982967 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.data 503904 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.ReadReq_accesses::total 2572663 # number of ReadReq accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::writebacks 523100 # number of Writeback accesses(hits+misses) system.cpu0.l2cache.Writeback_accesses::total 523100 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.inst 31187 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 31187 # number of UpgradeReq accesses(hits+misses) system.cpu0.l2cache.UpgradeReq_accesses::total 31187 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.inst 19896 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 19896 # number of SCUpgradeReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeReq_accesses::total 19896 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.inst 2 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.inst 270614 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 270614 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.ReadExReq_accesses::total 270614 # number of ReadExReq accesses(hits+misses) system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 81347 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 4445 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 2757485 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1982967 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 774518 # number of demand (read+write) accesses system.cpu0.l2cache.demand_accesses::total 2843277 # number of demand (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 81347 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 4445 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 2757485 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1982967 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 774518 # number of overall (read+write) accesses system.cpu0.l2cache.overall_accesses::total 2843277 # number of overall (read+write) accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.025422 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.057312 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.036755 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.138209 # miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_miss_rate::total 0.055776 # miss rate for ReadReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.846699 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.846699 # miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.846699 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.905006 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.905006 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.905006 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.inst 1 # miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.inst 0.162896 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.162896 # miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_miss_rate::total 0.162896 # miss rate for ReadExReq accesses system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.025422 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.067674 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.036755 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.146835 # miss rate for demand accesses system.cpu0.l2cache.demand_miss_rate::total 0.065972 # miss rate for demand accesses system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.010498 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.025422 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.067674 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.036755 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.146835 # miss rate for overall accesses system.cpu0.l2cache.overall_miss_rate::total 0.065972 # miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 22084.061947 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 37259.990591 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 43876.198551 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 30336.076331 # average ReadReq miss latency system.cpu0.l2cache.ReadReq_avg_miss_latency::total 37235.951873 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.inst 17502.897561 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 17502.897561 # average UpgradeReq miss latency system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 17502.897561 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.inst 19713.694824 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 19713.694824 # average SCUpgradeReq miss latency system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 19713.694824 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.inst 141000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 141000 # average SCUpgradeFailReq miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 141000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.inst 47621.058119 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 47621.058119 # average ReadExReq miss latency system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 47621.058119 # average ReadExReq miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 39707.549813 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency system.cpu0.l2cache.demand_avg_miss_latency::total 39676.542639 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 35228.922717 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 22084.061947 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 39707.549813 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 43876.198551 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37036.009215 # average overall miss latency system.cpu0.l2cache.overall_avg_miss_latency::total 39676.542639 # average overall miss latency system.cpu0.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -982,119 +1010,138 @@ system.cpu0.l2cache.cache_copies 0 # nu system.cpu0.l2cache.writebacks::writebacks 201133 # number of writebacks system.cpu0.l2cache.writebacks::total 201133 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 511 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 65 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 446 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::total 512 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.inst 3265 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 3265 # number of ReadExReq MSHR hits system.cpu0.l2cache.ReadExReq_mshr_hits::total 3265 # number of ReadExReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 3776 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 65 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 3711 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::total 3777 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 3776 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 65 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 3711 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::total 3777 # number of overall MSHR hits system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 854 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 112 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 142016 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 72818 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 69198 # number of ReadReq MSHR misses system.cpu0.l2cache.ReadReq_mshr_misses::total 142982 # number of ReadReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of HardPFReq MSHR misses system.cpu0.l2cache.HardPFReq_mshr_misses::total 280772 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.inst 26406 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 26406 # number of UpgradeReq MSHR misses system.cpu0.l2cache.UpgradeReq_mshr_misses::total 26406 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.inst 18006 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 18006 # number of SCUpgradeReq MSHR misses system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 18006 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.inst 2 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.inst 40817 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40817 # number of ReadExReq MSHR misses system.cpu0.l2cache.ReadExReq_mshr_misses::total 40817 # number of ReadExReq MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 854 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 112 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 182833 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 72818 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 110015 # number of demand (read+write) MSHR misses system.cpu0.l2cache.demand_mshr_misses::total 183799 # number of demand (read+write) MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 854 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 112 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 182833 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 72818 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 110015 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 280772 # number of overall MSHR misses system.cpu0.l2cache.overall_mshr_misses::total 464571 # number of overall MSHR misses system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 1685499 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 4279514975 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2677133771 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 1602381204 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4305290474 # number of ReadReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of HardPFReq MSHR miss cycles system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15488924735 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.inst 449600763 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 449600763 # number of UpgradeReq MSHR miss cycles system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 449600763 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.inst 240569359 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 240569359 # number of SCUpgradeReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 240569359 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.inst 219000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 219000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 219000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.inst 1467254248 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1467254248 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1467254248 # number of ReadExReq MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 1685499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 5746769223 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2677133771 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3069635452 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.demand_mshr_miss_latency::total 5772544722 # number of demand (read+write) MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 24090000 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 1685499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 5746769223 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2677133771 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3069635452 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15488924735 # number of overall MSHR miss cycles system.cpu0.l2cache.overall_mshr_miss_latency::total 21261469457 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 6177076991 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 242870500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5934206491 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6177076991 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.inst 4588309497 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4588309497 # number of WriteReq MSHR uncacheable cycles system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4588309497 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 10765386488 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 242870500 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 10522515988 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 10765386488 # number of overall MSHR uncacheable cycles system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.057106 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.137324 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.055577 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.inst 0.846699 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.846699 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.846699 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.905006 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.905006 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.905006 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.inst 1 # mshr miss rate for SCUpgradeFailReq accesses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.inst 0.150831 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.150831 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.150831 # mshr miss rate for ReadExReq accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for demand accesses system.cpu0.l2cache.demand_mshr_miss_rate::total 0.064643 # mshr miss rate for demand accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.010498 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.025197 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.066304 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.036722 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.142043 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::total 0.163393 # mshr miss rate for overall accesses system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 30134.034017 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 23156.467008 # average ReadReq mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 30110.716552 # average ReadReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average HardPFReq mshr miss latency system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 55165.489205 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 17026.462281 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17026.462281 # average UpgradeReq mshr miss latency system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.462281 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 13360.510885 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 13360.510885 # average SCUpgradeReq mshr miss latency system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13360.510885 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 109500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 109500 # average SCUpgradeFailReq mshr miss latency system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 109500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 35947.135948 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 35947.135948 # average ReadExReq mshr miss latency system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 35947.135948 # average ReadExReq mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31406.834216 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 28208.430913 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 15049.098214 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 31431.794167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 36764.725356 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27901.972022 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 55165.489205 # average overall mshr miss latency system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 45765.812883 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.toL2Bus.trans_dist::ReadReq 2726808 # Transaction distribution @@ -1343,8 +1390,8 @@ system.cpu1.dcache.tags.total_refs 7034054 # To system.cpu1.dcache.tags.sampled_refs 188124 # Sample count of references to valid blocks. system.cpu1.dcache.tags.avg_refs 37.390519 # Average number of references to valid blocks. system.cpu1.dcache.tags.warmup_cycle 108317904000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 478.493571 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.934558 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.493571 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934558 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_percent::total 0.934558 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 366 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 291 # Occupied blocks per task id @@ -1352,81 +1399,81 @@ system.cpu1.dcache.tags.age_task_id_blocks_1024::3 75 system.cpu1.dcache.tags.occ_task_id_percent::1024 0.714844 # Percentage of cache occupancy per task id system.cpu1.dcache.tags.tag_accesses 14914460 # Number of tag accesses system.cpu1.dcache.tags.data_accesses 14914460 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.inst 3762812 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 3762812 # number of ReadReq hits system.cpu1.dcache.ReadReq_hits::total 3762812 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.inst 3070723 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3070723 # number of WriteReq hits system.cpu1.dcache.WriteReq_hits::total 3070723 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.inst 89288 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 89288 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 89288 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.inst 69262 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 69262 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 69262 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.inst 6833535 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::cpu1.data 6833535 # number of demand (read+write) hits system.cpu1.dcache.demand_hits::total 6833535 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.inst 6833535 # number of overall hits +system.cpu1.dcache.overall_hits::cpu1.data 6833535 # number of overall hits system.cpu1.dcache.overall_hits::total 6833535 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.inst 181434 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::cpu1.data 181434 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 181434 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.inst 139542 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 139542 # number of WriteReq misses system.cpu1.dcache.WriteReq_misses::total 139542 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.inst 5058 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 5058 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 5058 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.inst 23425 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23425 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 23425 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.inst 320976 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::cpu1.data 320976 # number of demand (read+write) misses system.cpu1.dcache.demand_misses::total 320976 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.inst 320976 # number of overall misses +system.cpu1.dcache.overall_misses::cpu1.data 320976 # number of overall misses system.cpu1.dcache.overall_misses::total 320976 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.inst 2698134351 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 2698134351 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 2698134351 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.inst 3673411367 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3673411367 # number of WriteReq miss cycles system.cpu1.dcache.WriteReq_miss_latency::total 3673411367 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.inst 91654251 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 91654251 # number of LoadLockedReq miss cycles system.cpu1.dcache.LoadLockedReq_miss_latency::total 91654251 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.inst 540931813 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 540931813 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 540931813 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.inst 185500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 185500 # number of StoreCondFailReq miss cycles system.cpu1.dcache.StoreCondFailReq_miss_latency::total 185500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.inst 6371545718 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 6371545718 # number of demand (read+write) miss cycles system.cpu1.dcache.demand_miss_latency::total 6371545718 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.inst 6371545718 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 6371545718 # number of overall miss cycles system.cpu1.dcache.overall_miss_latency::total 6371545718 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.inst 3944246 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3944246 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 3944246 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.inst 3210265 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3210265 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::total 3210265 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.inst 94346 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 94346 # number of LoadLockedReq accesses(hits+misses) system.cpu1.dcache.LoadLockedReq_accesses::total 94346 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.inst 92687 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 92687 # number of StoreCondReq accesses(hits+misses) system.cpu1.dcache.StoreCondReq_accesses::total 92687 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.inst 7154511 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 7154511 # number of demand (read+write) accesses system.cpu1.dcache.demand_accesses::total 7154511 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.inst 7154511 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7154511 # number of overall (read+write) accesses system.cpu1.dcache.overall_accesses::total 7154511 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.inst 0.046000 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.046000 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.046000 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.inst 0.043467 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.043467 # miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_miss_rate::total 0.043467 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.inst 0.053611 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.053611 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.053611 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.inst 0.252732 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.252732 # miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::total 0.252732 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.inst 0.044863 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.044863 # miss rate for demand accesses system.cpu1.dcache.demand_miss_rate::total 0.044863 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.inst 0.044863 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.044863 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.044863 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.inst 14871.161695 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14871.161695 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 14871.161695 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.inst 26324.772233 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 26324.772233 # average WriteReq miss latency system.cpu1.dcache.WriteReq_avg_miss_latency::total 26324.772233 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.inst 18120.650652 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 18120.650652 # average LoadLockedReq miss latency system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 18120.650652 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.inst 23092.073127 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23092.073127 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23092.073127 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.inst inf # average StoreCondFailReq miss latency +system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency system.cpu1.dcache.demand_avg_miss_latency::total 19850.536233 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.inst 19850.536233 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19850.536233 # average overall miss latency system.cpu1.dcache.overall_avg_miss_latency::total 19850.536233 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1438,77 +1485,77 @@ system.cpu1.dcache.fast_writes 0 # nu system.cpu1.dcache.cache_copies 0 # number of cache copies performed system.cpu1.dcache.writebacks::writebacks 113901 # number of writebacks system.cpu1.dcache.writebacks::total 113901 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.inst 15137 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 15137 # number of ReadReq MSHR hits system.cpu1.dcache.ReadReq_mshr_hits::total 15137 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.inst 49794 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49794 # number of WriteReq MSHR hits system.cpu1.dcache.WriteReq_mshr_hits::total 49794 # number of WriteReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.inst 64931 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 64931 # number of demand (read+write) MSHR hits system.cpu1.dcache.demand_mshr_hits::total 64931 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.inst 64931 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 64931 # number of overall MSHR hits system.cpu1.dcache.overall_mshr_hits::total 64931 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.inst 166297 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 166297 # number of ReadReq MSHR misses system.cpu1.dcache.ReadReq_mshr_misses::total 166297 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.inst 89748 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89748 # number of WriteReq MSHR misses system.cpu1.dcache.WriteReq_mshr_misses::total 89748 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 5058 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5058 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5058 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 23425 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23425 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 23425 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.inst 256045 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 256045 # number of demand (read+write) MSHR misses system.cpu1.dcache.demand_mshr_misses::total 256045 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.inst 256045 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256045 # number of overall MSHR misses system.cpu1.dcache.overall_mshr_misses::total 256045 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2162409829 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2162409829 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2162409829 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2163633710 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2163633710 # number of WriteReq MSHR miss cycles system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2163633710 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 81526749 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 81526749 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 81526749 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 492905187 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 492905187 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 492905187 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 177500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 177500 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 177500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4326043539 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326043539 # number of demand (read+write) MSHR miss cycles system.cpu1.dcache.demand_mshr_miss_latency::total 4326043539 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4326043539 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4326043539 # number of overall MSHR miss cycles system.cpu1.dcache.overall_mshr_miss_latency::total 4326043539 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 330271000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 330271000 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 330271000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 203208500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 203208500 # number of WriteReq MSHR uncacheable cycles system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 203208500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 533479500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 533479500 # number of overall MSHR uncacheable cycles system.cpu1.dcache.overall_mshr_uncacheable_latency::total 533479500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.042162 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.042162 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.042162 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.027957 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027957 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027957 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.053611 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.053611 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.053611 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.252732 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.252732 # mshr miss rate for StoreCondReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.252732 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for demand accesses system.cpu1.dcache.demand_mshr_miss_rate::total 0.035788 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.035788 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035788 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.035788 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13003.300294 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13003.300294 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13003.300294 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 24107.876610 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 24107.876610 # average WriteReq mshr miss latency system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 24107.876610 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16118.376631 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 16118.376631 # average LoadLockedReq mshr miss latency system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16118.376631 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 21041.843629 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21041.843629 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21041.843629 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 16895.637638 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16895.637638 # average overall mshr miss latency system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16895.637638 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.icache.tags.replacements 908016 # number of replacements @@ -1618,12 +1665,14 @@ system.cpu1.l2cache.tags.warmup_cycle 0 # Cy system.cpu1.l2cache.tags.occ_blocks::writebacks 8763.818423 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 26.824644 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 0.109281 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 5323.780218 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 3126.745417 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2197.034801 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1213.252936 # Average occupied blocks per requestor system.cpu1.l2cache.tags.occ_percent::writebacks 0.534901 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001637 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000007 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.324938 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.190841 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.134096 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.074051 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_percent::total 0.935534 # Average percentage of cache occupancy system.cpu1.l2cache.tags.occ_task_id_blocks::1022 2056 # Occupied blocks per task id @@ -1645,119 +1694,137 @@ system.cpu1.l2cache.tags.tag_accesses 21629208 # Nu system.cpu1.l2cache.tags.data_accesses 21629208 # Number of data accesses system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 28145 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 2626 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 993919 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 889570 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.data 104349 # number of ReadReq hits system.cpu1.l2cache.ReadReq_hits::total 1024690 # number of ReadReq hits system.cpu1.l2cache.Writeback_hits::writebacks 113900 # number of Writeback hits system.cpu1.l2cache.Writeback_hits::total 113900 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1602 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1602 # number of UpgradeReq hits system.cpu1.l2cache.UpgradeReq_hits::total 1602 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 885 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 885 # number of SCUpgradeReq hits system.cpu1.l2cache.SCUpgradeReq_hits::total 885 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 24979 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 24979 # number of ReadExReq hits system.cpu1.l2cache.ReadExReq_hits::total 24979 # number of ReadExReq hits system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 28145 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::cpu1.itb.walker 2626 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1018898 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 889570 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 129328 # number of demand (read+write) hits system.cpu1.l2cache.demand_hits::total 1049669 # number of demand (read+write) hits system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 28145 # number of overall hits system.cpu1.l2cache.overall_hits::cpu1.itb.walker 2626 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1018898 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 889570 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 129328 # number of overall hits system.cpu1.l2cache.overall_hits::total 1049669 # number of overall hits system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 614 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 219 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 85964 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.inst 18958 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.data 67006 # number of ReadReq misses system.cpu1.l2cache.ReadReq_misses::total 86797 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 28133 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 28133 # number of UpgradeReq misses system.cpu1.l2cache.UpgradeReq_misses::total 28133 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 22540 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22540 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeReq_misses::total 22540 # number of SCUpgradeReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 35034 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35034 # number of ReadExReq misses system.cpu1.l2cache.ReadExReq_misses::total 35034 # number of ReadExReq misses system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 614 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::cpu1.itb.walker 219 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 120998 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 18958 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 102040 # number of demand (read+write) misses system.cpu1.l2cache.demand_misses::total 121831 # number of demand (read+write) misses system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 614 # number of overall misses system.cpu1.l2cache.overall_misses::cpu1.itb.walker 219 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 120998 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 18958 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 102040 # number of overall misses system.cpu1.l2cache.overall_misses::total 121831 # number of overall misses system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 13117250 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 4335498 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 2028659662 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 588499240 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1440160422 # number of ReadReq miss cycles system.cpu1.l2cache.ReadReq_miss_latency::total 2046112410 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 524558345 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 524558345 # number of UpgradeReq miss cycles system.cpu1.l2cache.UpgradeReq_miss_latency::total 524558345 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 440871540 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 440871540 # number of SCUpgradeReq miss cycles system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 440871540 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 173000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 173000 # number of SCUpgradeFailReq miss cycles system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 173000 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1316941950 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1316941950 # number of ReadExReq miss cycles system.cpu1.l2cache.ReadExReq_miss_latency::total 1316941950 # number of ReadExReq miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 13117250 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 4335498 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 3345601612 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 588499240 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 2757102372 # number of demand (read+write) miss cycles system.cpu1.l2cache.demand_miss_latency::total 3363054360 # number of demand (read+write) miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 13117250 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 4335498 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 3345601612 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 588499240 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 2757102372 # number of overall miss cycles system.cpu1.l2cache.overall_miss_latency::total 3363054360 # number of overall miss cycles system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 28759 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 2845 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 1079883 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 908528 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.data 171355 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.ReadReq_accesses::total 1111487 # number of ReadReq accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::writebacks 113900 # number of Writeback accesses(hits+misses) system.cpu1.l2cache.Writeback_accesses::total 113900 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 29735 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 29735 # number of UpgradeReq accesses(hits+misses) system.cpu1.l2cache.UpgradeReq_accesses::total 29735 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 23425 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23425 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeReq_accesses::total 23425 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 60013 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 60013 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.ReadExReq_accesses::total 60013 # number of ReadExReq accesses(hits+misses) system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 28759 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 2845 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1139896 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 908528 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 231368 # number of demand (read+write) accesses system.cpu1.l2cache.demand_accesses::total 1171500 # number of demand (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 28759 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 2845 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1139896 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 908528 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 231368 # number of overall (read+write) accesses system.cpu1.l2cache.overall_accesses::total 1171500 # number of overall (read+write) accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.076977 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.079605 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.020867 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.391036 # miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_miss_rate::total 0.078091 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.946124 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.946124 # miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.946124 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.962220 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.962220 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.962220 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.inst 0.583774 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.583774 # miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_miss_rate::total 0.583774 # miss rate for ReadExReq accesses system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.076977 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.106148 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.020867 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.441029 # miss rate for demand accesses system.cpu1.l2cache.demand_miss_rate::total 0.103996 # miss rate for demand accesses system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021350 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.076977 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.106148 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.020867 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.441029 # miss rate for overall accesses system.cpu1.l2cache.overall_miss_rate::total 0.103996 # miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 19796.794521 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 23598.944465 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 31042.263952 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 21493.006925 # average ReadReq miss latency system.cpu1.l2cache.ReadReq_avg_miss_latency::total 23573.538371 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.inst 18645.659723 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18645.659723 # average UpgradeReq miss latency system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18645.659723 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.inst 19559.518190 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19559.518190 # average SCUpgradeReq miss latency system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19559.518190 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.inst inf # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data inf # average SCUpgradeFailReq miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total inf # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.inst 37590.396472 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 37590.396472 # average ReadExReq miss latency system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 37590.396472 # average ReadExReq miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 27650.057125 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency system.cpu1.l2cache.demand_avg_miss_latency::total 27604.258030 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21363.599349 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 19796.794521 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 27650.057125 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 31042.263952 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 27019.819404 # average overall miss latency system.cpu1.l2cache.overall_avg_miss_latency::total 27604.258030 # average overall miss latency system.cpu1.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -1769,113 +1836,132 @@ system.cpu1.l2cache.fast_writes 0 # nu system.cpu1.l2cache.cache_copies 0 # number of cache copies performed system.cpu1.l2cache.writebacks::writebacks 33019 # number of writebacks system.cpu1.l2cache.writebacks::total 33019 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 106 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 18 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 88 # number of ReadReq MSHR hits system.cpu1.l2cache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.inst 284 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 284 # number of ReadExReq MSHR hits system.cpu1.l2cache.ReadExReq_mshr_hits::total 284 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 390 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 18 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 372 # number of demand (read+write) MSHR hits system.cpu1.l2cache.demand_mshr_hits::total 390 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 390 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 18 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 372 # number of overall MSHR hits system.cpu1.l2cache.overall_mshr_hits::total 390 # number of overall MSHR hits system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 614 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 219 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 85858 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 18940 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 66918 # number of ReadReq MSHR misses system.cpu1.l2cache.ReadReq_mshr_misses::total 86691 # number of ReadReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of HardPFReq MSHR misses system.cpu1.l2cache.HardPFReq_mshr_misses::total 25785 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.inst 28133 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 28133 # number of UpgradeReq MSHR misses system.cpu1.l2cache.UpgradeReq_mshr_misses::total 28133 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.inst 22540 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22540 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22540 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.inst 34750 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34750 # number of ReadExReq MSHR misses system.cpu1.l2cache.ReadExReq_mshr_misses::total 34750 # number of ReadExReq MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 614 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 219 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 120608 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 18940 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 101668 # number of demand (read+write) MSHR misses system.cpu1.l2cache.demand_mshr_misses::total 121441 # number of demand (read+write) MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 614 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 219 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 120608 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 18940 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 101668 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 25785 # number of overall MSHR misses system.cpu1.l2cache.overall_mshr_misses::total 147226 # number of overall MSHR misses system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 2802498 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 1423893692 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 454726510 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 969167182 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1435514940 # number of ReadReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of HardPFReq MSHR miss cycles system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1025770621 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.inst 399929245 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 399929245 # number of UpgradeReq MSHR miss cycles system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 399929245 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.inst 306606785 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 306606785 # number of SCUpgradeReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 306606785 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.inst 145000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 145000 # number of SCUpgradeFailReq MSHR miss cycles system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 145000 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.inst 1042779776 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1042779776 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1042779776 # number of ReadExReq MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 2802498 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 2466673468 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 454726510 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2011946958 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.demand_mshr_miss_latency::total 2478294716 # number of demand (read+write) MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 8818750 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 2802498 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 2466673468 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 454726510 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2011946958 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1025770621 # number of overall MSHR miss cycles system.cpu1.l2cache.overall_mshr_miss_latency::total 3504065337 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 316947250 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9029750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 307917500 # number of ReadReq MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 316947250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.inst 187186000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 187186000 # number of WriteReq MSHR uncacheable cycles system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 187186000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 504133250 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 9029750 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 495103500 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 504133250 # number of overall MSHR uncacheable cycles system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.079507 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.390523 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.077996 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.inst 0.946124 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.946124 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.946124 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.962220 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.962220 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.962220 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.inst 0.579041 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.579041 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.579041 # mshr miss rate for ReadExReq accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for demand accesses system.cpu1.l2cache.demand_mshr_miss_rate::total 0.103663 # mshr miss rate for demand accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021350 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.076977 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.105806 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.020847 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.439421 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::total 0.125673 # mshr miss rate for overall accesses system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 16584.286753 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 14482.907170 # average ReadReq mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 16558.984670 # average ReadReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average HardPFReq mshr miss latency system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 39781.680085 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 14215.662923 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 14215.662923 # average UpgradeReq mshr miss latency system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 14215.662923 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 13602.785492 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 13602.785492 # average SCUpgradeReq mshr miss latency system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 13602.785492 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 30008.051108 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 30008.051108 # average ReadExReq mshr miss latency system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 30008.051108 # average ReadExReq mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20407.397139 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 14362.785016 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 12796.794521 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20451.988823 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 24008.791447 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 19789.382677 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 39781.680085 # average overall mshr miss latency system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 23800.587783 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.toL2Bus.trans_dist::ReadReq 1492249 # Transaction distribution @@ -2139,18 +2225,22 @@ system.l2c.tags.warmup_cycle 0 # Cy system.l2c.tags.occ_blocks::writebacks 11502.485032 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 90.401142 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.038214 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 12425.194881 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 9505.348435 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2919.846446 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 36413.661117 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.683124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1856.879628 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1274.245745 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 582.633884 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1880.036266 # Average occupied blocks per requestor system.l2c.tags.occ_percent::writebacks 0.175514 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.001379 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000001 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.189593 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.145040 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.044553 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.555628 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000117 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.028334 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.019443 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.008890 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.028687 # Average percentage of cache occupancy system.l2c.tags.occ_percent::total 0.979254 # Average percentage of cache occupancy system.l2c.tags.occ_task_id_blocks::1022 31795 # Occupied blocks per task id @@ -2173,210 +2263,246 @@ system.l2c.tags.tag_accesses 5313847 # Nu system.l2c.tags.data_accesses 5313847 # Number of data accesses system.l2c.ReadReq_hits::cpu0.dtb.walker 426 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 63 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 70654 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 48963 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 21691 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 75814 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.dtb.walker 118 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 32 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 24007 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 16648 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 7359 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7439 # number of ReadReq hits system.l2c.ReadReq_hits::total 178553 # number of ReadReq hits system.l2c.Writeback_hits::writebacks 234152 # number of Writeback hits system.l2c.Writeback_hits::total 234152 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 2938 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 658 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu0.data 2938 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 658 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 3596 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 142 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.inst 176 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 142 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 176 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 318 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 3842 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 1332 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 3842 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1332 # number of ReadExReq hits system.l2c.ReadExReq_hits::total 5174 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 426 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 63 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 74496 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 48963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 25533 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.l2cache.prefetcher 75814 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 118 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 32 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 25339 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 16648 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 8691 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.l2cache.prefetcher 7439 # number of demand (read+write) hits system.l2c.demand_hits::total 183727 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 426 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 63 # number of overall hits -system.l2c.overall_hits::cpu0.inst 74496 # number of overall hits +system.l2c.overall_hits::cpu0.inst 48963 # number of overall hits +system.l2c.overall_hits::cpu0.data 25533 # number of overall hits system.l2c.overall_hits::cpu0.l2cache.prefetcher 75814 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 118 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 32 # number of overall hits -system.l2c.overall_hits::cpu1.inst 25339 # number of overall hits +system.l2c.overall_hits::cpu1.inst 16648 # number of overall hits +system.l2c.overall_hits::cpu1.data 8691 # number of overall hits system.l2c.overall_hits::cpu1.l2cache.prefetcher 7439 # number of overall hits system.l2c.overall_hits::total 183727 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 162 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 32548 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 23855 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 8693 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 12 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3333 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 2292 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1041 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq misses system.l2c.ReadReq_misses::total 178995 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 8970 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 2734 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu0.data 8970 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 2734 # number of UpgradeReq misses system.l2c.UpgradeReq_misses::total 11704 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 618 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1189 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 618 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1189 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1807 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 11575 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 8676 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 11575 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 8676 # number of ReadExReq misses system.l2c.ReadExReq_misses::total 20251 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 162 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 44123 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 23855 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 20268 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 12 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 12009 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 2292 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 9717 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) misses system.l2c.demand_misses::total 199246 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 162 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu0.inst 44123 # number of overall misses +system.l2c.overall_misses::cpu0.inst 23855 # number of overall misses +system.l2c.overall_misses::cpu0.data 20268 # number of overall misses system.l2c.overall_misses::cpu0.l2cache.prefetcher 136690 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 12 # number of overall misses -system.l2c.overall_misses::cpu1.inst 12009 # number of overall misses +system.l2c.overall_misses::cpu1.inst 2292 # number of overall misses +system.l2c.overall_misses::cpu1.data 9717 # number of overall misses system.l2c.overall_misses::cpu1.l2cache.prefetcher 6249 # number of overall misses system.l2c.overall_misses::total 199246 # number of overall misses system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 12996250 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.itb.walker 75000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 2445317489 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 1747991991 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 697325498 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 960250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 258262249 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 172995499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 85266750 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 17612731920 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.inst 7054791 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.inst 1587933 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 7054791 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 1587933 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 8642724 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.inst 937466 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.inst 512978 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 937466 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 512978 # number of SCUpgradeReq miss cycles system.l2c.SCUpgradeReq_miss_latency::total 1450444 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.inst 952737665 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.inst 639334486 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 952737665 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 639334486 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_latency::total 1592072151 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu0.dtb.walker 12996250 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.itb.walker 75000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 3398055154 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1747991991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1650063163 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 960250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 897596735 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 172995499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 724601236 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::total 19204804071 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu0.dtb.walker 12996250 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.itb.walker 75000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 3398055154 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1747991991 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1650063163 # number of overall miss cycles system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14069068891 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 960250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 897596735 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 172995499 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 724601236 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 826051791 # number of overall miss cycles system.l2c.overall_miss_latency::total 19204804071 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.dtb.walker 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 64 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 103202 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 72818 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 30384 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 212504 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.dtb.walker 130 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.itb.walker 32 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 27340 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 18940 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 8400 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 13688 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 357548 # number of ReadReq accesses(hits+misses) system.l2c.Writeback_accesses::writebacks 234152 # number of Writeback accesses(hits+misses) system.l2c.Writeback_accesses::total 234152 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.inst 11908 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.inst 3392 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 11908 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 3392 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 15300 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.inst 760 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.inst 1365 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 760 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1365 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 2125 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.inst 15417 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.inst 10008 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15417 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10008 # number of ReadExReq accesses(hits+misses) system.l2c.ReadExReq_accesses::total 25425 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.dtb.walker 588 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.itb.walker 64 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 118619 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 72818 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 45801 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu0.l2cache.prefetcher 212504 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.dtb.walker 130 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.itb.walker 32 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 37348 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 18940 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 18408 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.l2cache.prefetcher 13688 # number of demand (read+write) accesses system.l2c.demand_accesses::total 382973 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.dtb.walker 588 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.itb.walker 64 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 118619 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 72818 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 45801 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu0.l2cache.prefetcher 212504 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.dtb.walker 130 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.itb.walker 32 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 37348 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 18940 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 18408 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.l2cache.prefetcher 13688 # number of overall (read+write) accesses system.l2c.overall_accesses::total 382973 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.015625 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.315381 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.327598 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.286105 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.121909 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.121014 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.123929 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::total 0.500618 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.inst 0.753275 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.inst 0.806014 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.753275 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.806014 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 0.764967 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.inst 0.813158 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.inst 0.871062 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.813158 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.871062 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.850353 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.inst 0.750795 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.inst 0.866906 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.750795 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.866906 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 0.796500 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.015625 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.371972 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.327598 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.442523 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.321543 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.121014 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.527868 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for demand accesses system.l2c.demand_miss_rate::total 0.520261 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.275510 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.015625 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.371972 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.327598 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.442523 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.643235 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.092308 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.321543 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.121014 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.527868 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.456531 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.520261 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 75000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 75129.577516 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 73275.707022 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 80216.898424 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 77486.423342 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 75477.966405 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 81908.501441 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 98397.898936 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.inst 786.487291 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.inst 580.809437 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 786.487291 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 580.809437 # average UpgradeReq miss latency system.l2c.UpgradeReq_avg_miss_latency::total 738.441900 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.inst 1516.935275 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.inst 431.436501 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1516.935275 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 431.436501 # average SCUpgradeReq miss latency system.l2c.SCUpgradeReq_avg_miss_latency::total 802.680686 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.inst 82309.949460 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.inst 73690.005302 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 82309.949460 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 73690.005302 # average ReadExReq miss latency system.l2c.ReadExReq_avg_miss_latency::total 78616.964644 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 77013.239218 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 74743.670164 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency system.l2c.demand_avg_miss_latency::total 96387.400856 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 80223.765432 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.itb.walker 75000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 77013.239218 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 73275.707022 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 81412.234212 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 102926.833645 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 80020.833333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 74743.670164 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 75477.966405 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 74570.467840 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132189.436870 # average overall miss latency system.l2c.overall_avg_miss_latency::total 96387.400856 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked @@ -2400,153 +2526,185 @@ system.l2c.overall_mshr_hits::cpu1.inst 3 # nu system.l2c.overall_mshr_hits::total 11 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 162 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 32540 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 23847 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 8693 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 12 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 3330 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 2289 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1041 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 178984 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.inst 8970 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.inst 2734 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8970 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 2734 # number of UpgradeReq MSHR misses system.l2c.UpgradeReq_mshr_misses::total 11704 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.inst 618 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.inst 1189 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 618 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1189 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::total 1807 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.inst 11575 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.inst 8676 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11575 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 8676 # number of ReadExReq MSHR misses system.l2c.ReadExReq_mshr_misses::total 20251 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu0.dtb.walker 162 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 44115 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 23847 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 20268 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 12 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 12006 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 2289 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 9717 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::total 199235 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu0.dtb.walker 162 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 44115 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 23847 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 20268 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 136690 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 12 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 12006 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 2289 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 9717 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 6249 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 199235 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 62500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 2034453239 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1445321741 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 589131498 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 810750 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 216209999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 143882249 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72327750 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 15392098420 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.inst 91762404 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.inst 27532715 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 91762404 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 27532715 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 119295119 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.inst 6310115 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.inst 11917186 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6310115 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 11917186 # number of SCUpgradeReq MSHR miss cycles system.l2c.SCUpgradeReq_mshr_miss_latency::total 18227301 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.inst 807808323 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.inst 530171012 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 807808323 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 530171012 # number of ReadExReq MSHR miss cycles system.l2c.ReadExReq_mshr_miss_latency::total 1337979335 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 62500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 2842261562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1445321741 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1396939821 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 810750 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 746381011 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 143882249 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 602498762 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::total 16730077755 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 10991250 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 62500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 2842261562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1445321741 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1396939821 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12379828891 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 810750 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 746381011 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 143882249 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 602498762 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 749741791 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::total 16730077755 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5519244498 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 263262750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 163590000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 5355654498 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 6093250 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 257169500 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 5782507248 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 4096891000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 150604000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 4096891000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 150604000 # number of WriteReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::total 4247495000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 9616135498 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 413866750 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 163590000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 9452545498 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 6093250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 407773500 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 10030002248 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.315304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.286105 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.121800 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.123929 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::total 0.500587 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.753275 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.806014 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.753275 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.806014 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.764967 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.813158 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.871062 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.813158 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.871062 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.850353 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.750795 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.866906 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750795 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.866906 # mshr miss rate for ReadExReq accesses system.l2c.ReadExReq_mshr_miss_rate::total 0.796500 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::total 0.520232 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.275510 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.015625 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.371905 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.327488 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.442523 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.643235 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.092308 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.321463 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.120855 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.527868 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.456531 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.520232 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 62521.611524 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 67770.792362 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64927.927628 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 69479.106628 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 85997.063536 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10229.922408 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10070.488296 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10229.922408 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10070.488296 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10192.679340 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10210.542071 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10022.864592 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10210.542071 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.864592 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10087.050913 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 69789.055983 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61107.769940 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 69789.055983 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 61107.769940 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::total 66069.790875 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67847.222222 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 64428.461113 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60608.115947 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 68923.417259 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 90568.650896 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 67562.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62167.333916 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62858.125382 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62004.606566 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 119977.883021 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::total 83971.580069 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 217279 # Transaction distribution |