diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-28 16:53:48 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-09-28 16:53:48 -0400 |
| commit | ff2d58f935c434e89a499474d3bda76f476e6d25 (patch) | |
| tree | 3d895dc40952ec47b3388dded8072bf988b3c49c /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual | |
| parent | ec41000dadd5256fd90f0bfdc97264946e50a3aa (diff) | |
| download | gem5-ff2d58f935c434e89a499474d3bda76f476e6d25.tar.xz | |
stats: Update stats to reflect ARM fixes
As a result of the fixes, the full-system dual-core ARM regressions
are slightly changed. Hopefully this also means there will no longer
be any discrepancies between the results observed on different hosts.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt | 3651 |
1 files changed, 1817 insertions, 1834 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt index 59143a518..e666b7d0c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor-dual/stats.txt @@ -1,168 +1,164 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.658500 # Number of seconds simulated -sim_ticks 2658500429500 # Number of ticks simulated -final_tick 2658500429500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.658488 # Number of seconds simulated +sim_ticks 2658488068000 # Number of ticks simulated +final_tick 2658488068000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 100914 # Simulator instruction rate (inst/s) -host_op_rate 121517 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4256503307 # Simulator tick rate (ticks/s) -host_mem_usage 437672 # Number of bytes of host memory used -host_seconds 624.57 # Real time elapsed on the host -sim_insts 63028509 # Number of instructions simulated -sim_ops 75896503 # Number of ops (including micro ops) simulated +host_inst_rate 84054 # Simulator instruction rate (inst/s) +host_op_rate 101215 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3545231727 # Simulator tick rate (ticks/s) +host_mem_usage 436668 # Number of bytes of host memory used +host_seconds 749.88 # Real time elapsed on the host +sim_insts 63030433 # Number of instructions simulated +sim_ops 75898814 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 670652 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 5012160 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 503736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 5163008 # Number of bytes read from this memory -system.physmem.bytes_read::total 134034100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 219584 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 61824 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 281408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4338816 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 674300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 5028416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 495096 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 5148352 # Number of bytes read from this memory +system.physmem.bytes_read::total 134030836 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 219456 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 61376 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 280832 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4344000 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.inst 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.inst 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7367952 # Number of bytes written to this memory +system.physmem.bytes_written::total 7373136 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 10538 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 78315 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 7889 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 80672 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15512856 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 67794 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 10595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 78569 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 7754 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 80443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15512805 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 67875 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.inst 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.inst 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 825078 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46147592 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 120 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 825159 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46147806 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 96 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 48 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 252267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 1885334 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 241 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 189481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 1942075 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50417182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 82597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 23255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 105852 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1632054 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 253640 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 1891457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 337 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 186232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 1936571 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50416189 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 82549 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 23087 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 105636 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1634011 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.inst 6395 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.inst 1133021 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2771469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1632054 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46147592 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 120 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.inst 1133026 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2773432 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1634011 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46147806 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 96 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 48 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 258662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 1885334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 241 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 1322502 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 1942075 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53188651 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15512856 # Number of read requests accepted -system.physmem.writeReqs 825078 # Number of write requests accepted -system.physmem.readBursts 15512856 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 825078 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 992706816 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 115968 # Total number of bytes read from write queue -system.physmem.bytesWritten 7383872 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 134034100 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7367952 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 1812 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 709689 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 15707 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 969471 # Per bank write bursts -system.physmem.perBankRdBursts::1 969246 # Per bank write bursts -system.physmem.perBankRdBursts::2 969043 # Per bank write bursts -system.physmem.perBankRdBursts::3 969564 # Per bank write bursts -system.physmem.perBankRdBursts::4 971813 # Per bank write bursts -system.physmem.perBankRdBursts::5 969510 # Per bank write bursts -system.physmem.perBankRdBursts::6 969103 # Per bank write bursts -system.physmem.perBankRdBursts::7 968972 # Per bank write bursts -system.physmem.perBankRdBursts::8 969597 # Per bank write bursts -system.physmem.perBankRdBursts::9 969588 # Per bank write bursts -system.physmem.perBankRdBursts::10 969467 # Per bank write bursts -system.physmem.perBankRdBursts::11 968939 # Per bank write bursts -system.physmem.perBankRdBursts::12 969138 # Per bank write bursts -system.physmem.perBankRdBursts::13 969444 # Per bank write bursts -system.physmem.perBankRdBursts::14 969295 # Per bank write bursts -system.physmem.perBankRdBursts::15 968854 # Per bank write bursts -system.physmem.perBankWrBursts::0 7363 # Per bank write bursts -system.physmem.perBankWrBursts::1 7345 # Per bank write bursts -system.physmem.perBankWrBursts::2 6989 # Per bank write bursts -system.physmem.perBankWrBursts::3 7254 # Per bank write bursts -system.physmem.perBankWrBursts::4 7419 # Per bank write bursts -system.physmem.perBankWrBursts::5 7425 # Per bank write bursts +system.physmem.bw_total::cpu0.inst 260035 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 1891457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 337 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 1319258 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 1936571 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53189621 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15512805 # Number of read requests accepted +system.physmem.writeReqs 825159 # Number of write requests accepted +system.physmem.readBursts 15512805 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 825159 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 992712960 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 106560 # Total number of bytes read from write queue +system.physmem.bytesWritten 7389248 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 134030836 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7373136 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 1665 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 709677 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 15674 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 969393 # Per bank write bursts +system.physmem.perBankRdBursts::1 969270 # Per bank write bursts +system.physmem.perBankRdBursts::2 969024 # Per bank write bursts +system.physmem.perBankRdBursts::3 969581 # Per bank write bursts +system.physmem.perBankRdBursts::4 971912 # Per bank write bursts +system.physmem.perBankRdBursts::5 969565 # Per bank write bursts +system.physmem.perBankRdBursts::6 969152 # Per bank write bursts +system.physmem.perBankRdBursts::7 969036 # Per bank write bursts +system.physmem.perBankRdBursts::8 969555 # Per bank write bursts +system.physmem.perBankRdBursts::9 969606 # Per bank write bursts +system.physmem.perBankRdBursts::10 969469 # Per bank write bursts +system.physmem.perBankRdBursts::11 968910 # Per bank write bursts +system.physmem.perBankRdBursts::12 969137 # Per bank write bursts +system.physmem.perBankRdBursts::13 969414 # Per bank write bursts +system.physmem.perBankRdBursts::14 969294 # Per bank write bursts +system.physmem.perBankRdBursts::15 968822 # Per bank write bursts +system.physmem.perBankWrBursts::0 7303 # Per bank write bursts +system.physmem.perBankWrBursts::1 7359 # Per bank write bursts +system.physmem.perBankWrBursts::2 6981 # Per bank write bursts +system.physmem.perBankWrBursts::3 7260 # Per bank write bursts +system.physmem.perBankWrBursts::4 7486 # Per bank write bursts +system.physmem.perBankWrBursts::5 7442 # Per bank write bursts system.physmem.perBankWrBursts::6 7374 # Per bank write bursts -system.physmem.perBankWrBursts::7 7152 # Per bank write bursts -system.physmem.perBankWrBursts::8 7408 # Per bank write bursts -system.physmem.perBankWrBursts::9 7360 # Per bank write bursts -system.physmem.perBankWrBursts::10 7357 # Per bank write bursts -system.physmem.perBankWrBursts::11 7062 # Per bank write bursts -system.physmem.perBankWrBursts::12 6947 # Per bank write bursts -system.physmem.perBankWrBursts::13 7077 # Per bank write bursts -system.physmem.perBankWrBursts::14 7057 # Per bank write bursts -system.physmem.perBankWrBursts::15 6784 # Per bank write bursts +system.physmem.perBankWrBursts::7 7195 # Per bank write bursts +system.physmem.perBankWrBursts::8 7413 # Per bank write bursts +system.physmem.perBankWrBursts::9 7378 # Per bank write bursts +system.physmem.perBankWrBursts::10 7327 # Per bank write bursts +system.physmem.perBankWrBursts::11 7067 # Per bank write bursts +system.physmem.perBankWrBursts::12 6951 # Per bank write bursts +system.physmem.perBankWrBursts::13 7051 # Per bank write bursts +system.physmem.perBankWrBursts::14 7072 # Per bank write bursts +system.physmem.perBankWrBursts::15 6798 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2658500409000 # Total gap between requests +system.physmem.totGap 2658486560500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 59 # Read request sizes (log2) system.physmem.readPktSize::3 15335449 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 177348 # Read request sizes (log2) +system.physmem.readPktSize::6 177297 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 757284 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 67794 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1046196 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1019688 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 986842 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1094338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 993106 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1055542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2738032 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2641383 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3439999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 128528 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 110050 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 101603 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 98027 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 19641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 18942 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 18731 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 149 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 29 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 21 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::22 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::23 12 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::24 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::25 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::26 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::27 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::28 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::29 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 67875 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1046149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1019751 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 986849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1098941 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 993476 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1059379 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2733951 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2632980 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3427107 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 133098 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 114256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 105608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 102115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19625 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 18867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 18633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 143 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 86 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 34 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 28 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 20 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 12 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 10 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see @@ -180,32 +176,32 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 4092 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4702 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5210 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6495 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6634 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 6762 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6877 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 7199 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7541 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7039 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 28 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4048 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 4083 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4691 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5205 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 6785 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7580 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7259 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7006 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 166 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 31 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 6 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see @@ -229,54 +225,55 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 1037696 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 963.760762 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 885.523874 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 219.463963 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 32040 3.09% 3.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 21332 2.06% 5.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9404 0.91% 6.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2470 0.24% 6.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3075 0.30% 6.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2164 0.21% 6.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 8825 0.85% 7.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1075 0.10% 7.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 957311 92.25% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 1037696 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6640 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 2336.000602 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 97357.467769 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-262143 6632 99.88% 99.88% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.91% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::524288-786431 3 0.05% 99.95% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::786432-1.04858e+06 1 0.02% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::7.60218e+06-7.86432e+06 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6640 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6640 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 17.375452 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.330517 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.281391 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 2518 37.92% 37.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 36 0.54% 38.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 3683 55.47% 93.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 190 2.86% 96.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 92 1.39% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 40 0.60% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 30 0.45% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 20 0.30% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 15 0.23% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 13 0.20% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 1037609 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 963.852673 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 885.641044 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 219.370096 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 32112 3.09% 3.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 21277 2.05% 5.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9254 0.89% 6.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2543 0.25% 6.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 3048 0.29% 6.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2181 0.21% 6.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 8654 0.83% 7.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1069 0.10% 7.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 957471 92.28% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 1037609 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6645 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 2334.257336 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 73724.534105 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-262143 6636 99.86% 99.86% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::262144-524287 2 0.03% 99.89% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::524288-786431 2 0.03% 99.92% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::786432-1.04858e+06 2 0.03% 99.95% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.04858e+06-1.31072e+06 1 0.02% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2.62144e+06-2.88358e+06 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::4.71859e+06-4.98074e+06 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6645 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6645 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 17.375019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.329909 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 1.281758 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 2539 38.21% 38.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 27 0.41% 38.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 3660 55.08% 93.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 195 2.93% 96.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 85 1.28% 97.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 57 0.86% 98.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 40 0.60% 99.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 18 0.27% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 11 0.17% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 9 0.14% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 1 0.02% 99.98% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::30 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6640 # Writes before turning the bus around for reads -system.physmem.totQLat 403478953250 # Total ticks spent queuing -system.physmem.totMemAccLat 694311028250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 77555220000 # Total ticks spent in databus transfers -system.physmem.avgQLat 26012.37 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::total 6645 # Writes before turning the bus around for reads +system.physmem.totQLat 404032545000 # Total ticks spent queuing +system.physmem.totMemAccLat 694866420000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 77555700000 # Total ticks spent in databus transfers +system.physmem.avgQLat 26047.89 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44762.37 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 44797.89 # Average memory access latency per DRAM burst system.physmem.avgRdBW 373.41 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.78 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 50.42 # Average system read bandwidth in MiByte/s @@ -285,18 +282,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.94 # Data bus utilization in percentage system.physmem.busUtilRead 2.92 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 6.07 # Average read queue length when enqueuing -system.physmem.avgWrQLen 26.23 # Average write queue length when enqueuing -system.physmem.readRowHits 14503444 # Number of row buffer hits during reads -system.physmem.writeRowHits 85277 # Number of row buffer hits during writes +system.physmem.avgRdQLen 6.34 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 14503540 # Number of row buffer hits during reads +system.physmem.writeRowHits 85448 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.50 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 73.90 # Row buffer hit rate for writes -system.physmem.avgGap 162719.50 # Average gap between requests +system.physmem.writeRowHitRate 73.99 # Row buffer hit rate for writes +system.physmem.avgGap 162718.35 # Average gap between requests system.physmem.pageHitRate 93.36 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2316371594000 # Time in different power states -system.physmem.memoryStateTime::REF 88773100000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2316452257000 # Time in different power states +system.physmem.memoryStateTime::REF 88772580000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 253353834750 # Time in different power states +system.physmem.memoryStateTime::ACT 253258119250 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 256 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 448 # Number of bytes read from this memory @@ -316,498 +313,475 @@ system.realview.nvmem.bw_inst_read::total 265 # I system.realview.nvmem.bw_total::cpu0.inst 96 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 169 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 265 # Total bandwidth to/from this memory (bytes/s) -system.membus.trans_dist::ReadReq 16692425 # Transaction distribution -system.membus.trans_dist::ReadResp 16692425 # Transaction distribution -system.membus.trans_dist::WriteReq 768873 # Transaction distribution -system.membus.trans_dist::WriteResp 768873 # Transaction distribution -system.membus.trans_dist::Writeback 67794 # Transaction distribution -system.membus.trans_dist::UpgradeReq 55379 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 22285 # Transaction distribution -system.membus.trans_dist::UpgradeResp 15707 # Transaction distribution -system.membus.trans_dist::ReadExReq 15268 # Transaction distribution +system.membus.trans_dist::ReadReq 16692376 # Transaction distribution +system.membus.trans_dist::ReadResp 16692376 # Transaction distribution +system.membus.trans_dist::WriteReq 768869 # Transaction distribution +system.membus.trans_dist::WriteResp 768869 # Transaction distribution +system.membus.trans_dist::Writeback 67875 # Transaction distribution +system.membus.trans_dist::UpgradeReq 55188 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 22300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 15674 # Transaction distribution +system.membus.trans_dist::ReadExReq 15293 # Transaction distribution system.membus.trans_dist::ReadExResp 8420 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384472 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2384484 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 22 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12568 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 12552 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 2090 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037445 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4436601 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 2037240 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4436392 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 35107449 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392888 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 35107240 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 2392912 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 704 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 25104 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 4180 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18718660 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 21141576 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18720580 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 21143488 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 143824968 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 68805 # Total snoops (count) -system.membus.snoop_fanout::samples 327203 # Request fanout histogram +system.membus.pkt_size::total 143826880 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 68687 # Total snoops (count) +system.membus.snoop_fanout::samples 327086 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 327203 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 327086 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 327203 # Request fanout histogram -system.membus.reqLayer0.occupancy 1769123496 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 327086 # Request fanout histogram +system.membus.reqLayer0.occupancy 1769125500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 12000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 11500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 10983499 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11055000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1597500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1598500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17876588998 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17877285000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 5004631688 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 5004493562 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 37937018429 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 37922455685 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 92212 # number of replacements -system.l2c.tags.tagsinuse 55213.567741 # Cycle average of tags in use -system.l2c.tags.total_refs 396364 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 156868 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.526736 # Average number of references to valid blocks. +system.l2c.tags.replacements 92119 # number of replacements +system.l2c.tags.tagsinuse 55174.117162 # Cycle average of tags in use +system.l2c.tags.total_refs 396231 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 156723 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.528225 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 8088.192516 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 3.706191 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029154 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 2502.443827 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29448.913538 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.609197 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.004438 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 2039.532288 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13124.136592 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.123416 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000057 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 8029.027858 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.830738 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.029129 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 2503.920237 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 29498.221526 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.298488 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 2007.480710 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 13123.308478 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.122513 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000043 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.038184 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.449355 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000086 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.031121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200258 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.842492 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 53217 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 9 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 11430 # Occupied blocks per task id +system.l2c.tags.occ_percent::cpu0.inst 0.038207 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.450107 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000127 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.030632 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.200246 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.841890 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 53228 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 14 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 11362 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1022::1 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 151 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 4758 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 48307 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 10 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 265 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 1757 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 9394 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.812027 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000137 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.174408 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5122526 # Number of tag accesses -system.l2c.tags.data_accesses 5122526 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 183 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 37 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 15214 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88074 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 233 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 50 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 19471 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76181 # number of ReadReq hits -system.l2c.ReadReq_hits::total 199443 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 215065 # number of Writeback hits -system.l2c.Writeback_hits::total 215065 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.inst 3153 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.inst 2020 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 5173 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.inst 94 # number of SCUpgradeReq hits +system.l2c.tags.age_task_id_blocks_1022::2 137 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 4763 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 48327 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 12 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 290 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 1719 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 9346 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.812195 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000214 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.173370 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5120698 # Number of tag accesses +system.l2c.tags.data_accesses 5120698 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 193 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 42 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 14931 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 88016 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 59 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 19686 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 76288 # number of ReadReq hits +system.l2c.ReadReq_hits::total 199452 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 215010 # number of Writeback hits +system.l2c.Writeback_hits::total 215010 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.inst 3051 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.inst 2025 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 5076 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.inst 100 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.inst 213 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 307 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.inst 2198 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.inst 2398 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 4596 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 183 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 37 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 17412 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 88074 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 233 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 21869 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 76181 # number of demand (read+write) hits -system.l2c.demand_hits::total 204039 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 183 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu0.inst 17412 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 88074 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 233 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits -system.l2c.overall_hits::cpu1.inst 21869 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 76181 # number of overall hits -system.l2c.overall_hits::total 204039 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 5 # number of ReadReq misses +system.l2c.SCUpgradeReq_hits::total 313 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.inst 2211 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.inst 2397 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 4608 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 193 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 42 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 17142 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 88016 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 59 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 22083 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 76288 # number of demand (read+write) hits +system.l2c.demand_hits::total 204060 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 193 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 42 # number of overall hits +system.l2c.overall_hits::cpu0.inst 17142 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 88016 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 237 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 59 # number of overall hits +system.l2c.overall_hits::cpu1.inst 22083 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 76288 # number of overall hits +system.l2c.overall_hits::total 204060 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 4198 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78315 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 10 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 3275 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80672 # number of ReadReq misses -system.l2c.ReadReq_misses::total 166478 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.inst 7866 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.inst 5570 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 13436 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.inst 1047 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.inst 1097 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2144 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.inst 3980 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.inst 4567 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 8547 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 5 # number of demand (read+write) misses +system.l2c.ReadReq_misses::cpu0.inst 4222 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 78569 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 3178 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 80451 # number of ReadReq misses +system.l2c.ReadReq_misses::total 166440 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.inst 7948 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.inst 5460 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 13408 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.inst 1046 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.inst 1101 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 2147 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.inst 4019 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.inst 4520 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 8539 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 8178 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 78315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 7842 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 80672 # number of demand (read+write) misses -system.l2c.demand_misses::total 175025 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 5 # number of overall misses +system.l2c.demand_misses::cpu0.inst 8241 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 78569 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 7698 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 80451 # number of demand (read+write) misses +system.l2c.demand_misses::total 174979 # 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mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.917616 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837405 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.874745 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.644221 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.655707 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.650308 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.461727 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.026596 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.051282 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.319578 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.470674 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.041152 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.019608 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.263909 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.514316 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.461727 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average ReadReq mshr miss latency +system.l2c.overall_mshr_miss_latency::cpu0.inst 514472081 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 6168945444 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 936250 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 491423537 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 7758902888 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 14935012700 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 12573700750 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 155061349748 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167635050498 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.inst 1125597500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.inst 15721355858 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 16846953358 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 13699298250 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 170782705606 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184482003856 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.220435 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.138908 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.454861 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.inst 0.722611 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.inst 0.729459 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.725384 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.inst 0.912740 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.inst 0.837900 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.872764 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.inst 0.645104 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.inst 0.653462 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.649502 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.461612 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.020305 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.045455 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.324666 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.471645 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.055777 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.258420 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.513229 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.461612 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 65232.134350 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 68533.903482 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 86576.788866 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.786168 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10076.575404 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10073.186142 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10146.641834 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10021.960802 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10082.847481 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 58574.829899 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 61446.364353 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60109.204282 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 64842.491710 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 67938.837846 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 86634.956624 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 10068.053347 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 10063.995604 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10066.400955 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 10070.299235 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 10030.968211 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10050.129949 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.inst 59892.281911 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.inst 60984.466372 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60470.414451 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 51875 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 61992.213622 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78194.936321 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66625 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 130500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64405.757684 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96561.277668 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 85284.289292 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 62428.355903 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 78516.277972 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66875 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63854.409693 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 96452.182141 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 85358.050283 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -824,48 +798,48 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.trans_dist::ReadReq 1655769 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1655769 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 768873 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 768873 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 215065 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 60425 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 22592 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 83017 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 53 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 22828 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 22828 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 802487 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302639 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 5105126 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20032432 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23601176 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 43633608 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 171019 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 786212 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 1655552 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1655552 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 768869 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 768869 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 215010 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 60145 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 22613 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 82758 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 60 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 22833 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 22833 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 801778 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4302678 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 5104456 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 20000696 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 23627528 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 43628224 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 170698 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 785697 # Request fanout histogram system.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram system.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 786212 100.00% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 785697 100.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 786212 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2618569936 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 785697 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2618065998 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1234710374 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1234480729 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 2607103376 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 2606264414 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 16519576 # Transaction distribution -system.iobus.trans_dist::ReadResp 16519576 # Transaction distribution +system.iobus.trans_dist::ReadReq 16519582 # Transaction distribution +system.iobus.trans_dist::ReadResp 16519582 # Transaction distribution system.iobus.trans_dist::WriteReq 8084 # Transaction distribution system.iobus.trans_dist::WriteResp 8084 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30946 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8928 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8940 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) @@ -887,12 +861,12 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2384472 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2384484 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 33055320 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 33055332 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 40715 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17856 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 17880 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) @@ -914,13 +888,13 @@ system.iobus.pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 2392888 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 2392912 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 125076280 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 125076304 # Cumulative packet size per connected master and slave (bytes) system.iobus.reqLayer0.occupancy 21715000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4470000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4476000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -966,19 +940,19 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 15335424000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2376388000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2376400000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 38667942571 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 38686704315 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 7247667 # Number of BP lookups -system.cpu0.branchPred.condPredicted 5145194 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 425040 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 4677323 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 3357189 # Number of BTB hits +system.cpu0.branchPred.lookups 7252165 # Number of BP lookups +system.cpu0.branchPred.condPredicted 5142285 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 425056 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4634449 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 3350199 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 71.775864 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 942424 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 64273 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 72.289047 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 946301 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 66428 # Number of incorrect RAS predictions. system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1002,25 +976,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 6449421 # DTB read hits -system.cpu0.dtb.read_misses 22629 # DTB read misses -system.cpu0.dtb.write_hits 5803237 # DTB write hits -system.cpu0.dtb.write_misses 1880 # DTB write misses +system.cpu0.dtb.read_hits 6449087 # DTB read hits +system.cpu0.dtb.read_misses 22394 # DTB read misses +system.cpu0.dtb.write_hits 5803603 # DTB write hits +system.cpu0.dtb.write_misses 1784 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1731 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1649 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 155 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1724 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1623 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 268 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 6472050 # DTB read accesses -system.cpu0.dtb.write_accesses 5805117 # DTB write accesses +system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 6471481 # DTB read accesses +system.cpu0.dtb.write_accesses 5805387 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12252658 # DTB hits -system.cpu0.dtb.misses 24509 # DTB misses -system.cpu0.dtb.accesses 12277167 # DTB accesses +system.cpu0.dtb.hits 12252690 # DTB hits +system.cpu0.dtb.misses 24178 # DTB misses +system.cpu0.dtb.accesses 12276868 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1042,8 +1016,8 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 13306402 # ITB inst hits -system.cpu0.itb.inst_misses 3981 # ITB inst misses +system.cpu0.itb.inst_hits 13302311 # ITB inst hits +system.cpu0.itb.inst_misses 3954 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1052,83 +1026,83 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1196 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1195 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 3606 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 3570 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 13310383 # ITB inst accesses -system.cpu0.itb.hits 13306402 # DTB hits -system.cpu0.itb.misses 3981 # DTB misses -system.cpu0.itb.accesses 13310383 # DTB accesses -system.cpu0.numCycles 86779776 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 13306265 # ITB inst accesses +system.cpu0.itb.hits 13302311 # DTB hits +system.cpu0.itb.misses 3954 # DTB misses +system.cpu0.itb.accesses 13306265 # DTB accesses +system.cpu0.numCycles 86799146 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 29469177 # Number of instructions committed -system.cpu0.committedOps 35692469 # Number of ops (including micro ops) committed -system.cpu0.discardedOps 1968048 # Number of ops (including micro ops) which were discarded before commit -system.cpu0.numFetchSuspends 41085 # Number of times Execute suspended instruction fetching -system.cpu0.quiesceCycles 5234632408 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.cpi 2.944764 # CPI: cycles per instruction -system.cpu0.ipc 0.339586 # IPC: instructions per cycle +system.cpu0.committedInsts 29471412 # Number of instructions committed +system.cpu0.committedOps 35693999 # Number of ops (including micro ops) committed +system.cpu0.discardedOps 1972340 # Number of ops (including micro ops) which were discarded before commit +system.cpu0.numFetchSuspends 41075 # Number of times Execute suspended instruction fetching +system.cpu0.quiesceCycles 5234564326 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.cpi 2.945198 # CPI: cycles per instruction +system.cpu0.ipc 0.339536 # IPC: instructions per cycle system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 47499 # number of quiesce instructions executed -system.cpu0.tickCycles 68210329 # Number of cycles that the object actually ticked -system.cpu0.idleCycles 18569447 # Total number of cycles that the object has spent stopped -system.cpu0.icache.tags.replacements 669895 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.780265 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 12632215 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 670407 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 18.842606 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6077782000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780265 # Average occupied blocks per requestor +system.cpu0.kern.inst.quiesce 47489 # number of quiesce instructions executed +system.cpu0.tickCycles 68192545 # Number of cycles that the object actually ticked +system.cpu0.idleCycles 18606601 # Total number of cycles that the object has spent stopped +system.cpu0.icache.tags.replacements 670908 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.780495 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 12627162 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 671420 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 18.806652 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6076833000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.780495 # Average occupied blocks per requestor system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999571 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_percent::total 0.999571 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 172 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 216 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 124 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 173 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 225 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 114 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 27275662 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 27275662 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 12632215 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 12632215 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 12632215 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 12632215 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 12632215 # number of overall hits -system.cpu0.icache.overall_hits::total 12632215 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 670411 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 670411 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 670411 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 670411 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 670411 # number of overall misses -system.cpu0.icache.overall_misses::total 670411 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5588337897 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5588337897 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5588337897 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5588337897 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5588337897 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5588337897 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 13302626 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 13302626 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 13302626 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 13302626 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 13302626 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 13302626 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050397 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.050397 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050397 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.050397 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050397 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.050397 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8335.689446 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 8335.689446 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 8335.689446 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8335.689446 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 8335.689446 # average overall miss latency +system.cpu0.icache.tags.tag_accesses 27268595 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 27268595 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 12627162 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 12627162 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 12627162 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 12627162 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 12627162 # number of overall hits +system.cpu0.icache.overall_hits::total 12627162 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 671424 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 671424 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 671424 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 671424 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 671424 # number of overall misses +system.cpu0.icache.overall_misses::total 671424 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5600052378 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5600052378 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5600052378 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5600052378 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5600052378 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5600052378 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 13298586 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 13298586 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 13298586 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 13298586 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 13298586 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 13298586 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.050488 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.050488 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.050488 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.050488 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.050488 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.050488 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 8340.560328 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 8340.560328 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 8340.560328 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 8340.560328 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 8340.560328 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1137,365 +1111,375 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 670411 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 670411 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 670411 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 670411 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 670411 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 670411 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4581839103 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4581839103 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4581839103 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4581839103 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4581839103 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4581839103 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 215199250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 215199250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 215199250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 215199250 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050397 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.050397 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050397 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.050397 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6834.373396 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6834.373396 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 6834.373396 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 671424 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 671424 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 671424 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 671424 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 671424 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 671424 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4592017122 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4592017122 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4592017122 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4592017122 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4592017122 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4592017122 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 214843000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 214843000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 214843000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 214843000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.050488 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.050488 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.050488 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.050488 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 6839.221002 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 6839.221002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 6839.221002 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1297449 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1098949 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 10915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 10915 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 277394 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 309853 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 48681 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23393 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 54656 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 145161 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 136933 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1345495 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1384854 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13521 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 67392 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 2811262 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43053120 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45712112 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 22348 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 121316 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 88908896 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 663093 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 2014813 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 5.294791 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.455949 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 1296970 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1098887 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 10913 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 10913 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 275708 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 308200 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 48588 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 23370 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 54742 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 144812 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 136646 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 1347493 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 1381165 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 13298 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 66487 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 2808443 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 43116416 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 45547448 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 21688 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119336 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 88804888 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 661783 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 2010538 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 5.294459 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.455799 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::5 1420865 70.52% 70.52% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::6 593948 29.48% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::5 1418517 70.55% 70.55% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::6 592021 29.45% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 2014813 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1042501632 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 2010538 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 1039622669 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 66915000 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 67426500 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1010138647 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1011659878 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 706064108 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 704346240 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 7935497 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 7877498 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 37067990 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 36655495 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6505286 # number of hwpf identified -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 197873 # number of hwpf that were already in mshr -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6075585 # number of hwpf that were already in the cache -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2087 # number of hwpf that were already in the prefetch queue +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_identified 6510276 # number of hwpf identified +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 198706 # number of hwpf that were already in mshr +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6081219 # number of hwpf that were already in the cache +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2295 # number of hwpf that were already in the prefetch queue system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2097 # number of hwpf removed because MSHR allocated -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 227641 # number of hwpf issued -system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 451994 # number of hwpf spanning a virtual page +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2119 # number of hwpf removed because MSHR allocated +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_issued 225934 # number of hwpf issued +system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_span_page 452636 # number of hwpf spanning a virtual page system.cpu0.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu0.l2cache.tags.replacements 185568 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16045.943959 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 1211197 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 201780 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 6.002562 # Average number of references to valid blocks. -system.cpu0.l2cache.tags.warmup_cycle 5120960000 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 4785.288649 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 15.661304 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.175022 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 2150.935803 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 9093.883182 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.292071 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000956 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000011 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.131283 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.555047 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.979367 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 8308 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 18 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 7886 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::0 36 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 61 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 933 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 5734 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 1544 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 9 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 59 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 187 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 1527 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 5465 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 648 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.507080 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.001099 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.481323 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 22965812 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 22965812 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 29822 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 5414 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 885726 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 920962 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 277394 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 277394 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.inst 1852 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1852 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.inst 771 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 771 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.inst 107990 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 107990 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 29822 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 5414 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 993716 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1028952 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 29822 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 5414 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 993716 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1028952 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 507 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 173 # 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number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 507 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 173 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 73035 # number of overall misses -system.cpu0.l2cache.overall_misses::total 73715 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10873500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3613500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 1326942681 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 1341429681 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.inst 312233020 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 312233020 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.inst 200699599 # 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number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 29834 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 5422 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1066545 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 1101801 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.017396 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.031538 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.052564 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.051365 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.inst 0.912748 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.912748 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.inst 0.932891 # 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average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 25844.133976 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 25844.133976 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22170.951644 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14446.745562 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 13887.283237 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22248.094604 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 37725.512862 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34066.458345 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.268264 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 20484.507832 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20392.651232 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 38217.275591 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.inst 18077.305991 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 18077.305991 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.inst 14407.583975 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14407.583975 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.inst 192583.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 192583.333333 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.inst 26330.353335 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 26330.353335 # average ReadExReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 22330.845434 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 14266.859345 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 14157.900585 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 22411.813996 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 38217.275591 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 34474.271337 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1503,99 +1487,99 @@ system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 363620 # number of replacements -system.cpu0.dcache.tags.tagsinuse 473.092728 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 11412864 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 364132 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 31.342656 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 362294 # number of replacements +system.cpu0.dcache.tags.tagsinuse 472.891448 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 11414416 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 362806 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 31.461486 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 243086500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.inst 473.092728 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.924009 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.924009 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.inst 472.891448 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.inst 0.923616 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.923616 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 47 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 153 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 41 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # 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miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069147 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050278 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.050278 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050278 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.050278 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11955.328076 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 11955.328076 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15140.583677 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15140.583677 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16392.161782 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16392.161782 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23380.494353 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23380.494353 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 24357333 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 24357333 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.inst 5805631 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5805631 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.inst 5275579 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5275579 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.inst 147422 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147422 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.inst 146630 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 146630 # 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number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.inst 1495500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 1495500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.inst 7891036708 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 7891036708 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.inst 7891036708 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 7891036708 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.inst 6113960 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6113960 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.inst 5551965 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5551965 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.inst 157613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157613 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.inst 157499 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157499 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.inst 11665925 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11665925 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.inst 11665925 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11665925 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.inst 0.050430 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.050430 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.inst 0.049782 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.049782 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.inst 0.064658 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064658 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.inst 0.069010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.069010 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.inst 0.050122 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.050122 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.inst 0.050122 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.050122 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.inst 11938.327692 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 11938.327692 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.inst 15232.696551 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15232.696551 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.inst 16434.182220 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16434.182220 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.inst 23422.758763 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23422.758763 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.inst inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 13459.308511 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13459.308511 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13459.308511 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 13495.526381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.inst 13495.526381 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13495.526381 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1604,76 +1588,76 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 277395 # number of writebacks -system.cpu0.dcache.writebacks::total 277395 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54934 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 54934 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124546 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 124546 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 275708 # number of writebacks +system.cpu0.dcache.writebacks::total 275708 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.inst 54553 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 54553 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.inst 124298 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 124298 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.inst 74 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 74 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.inst 179480 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 179480 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.inst 179480 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 179480 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 254665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 254665 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152405 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 152405 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10094 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10094 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10891 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 10891 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.inst 407070 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 407070 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.inst 407070 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 407070 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2527058296 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2527058296 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2131958823 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2131958823 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 145779499 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 145779499 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231881036 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231881036 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1299500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1299500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4659017119 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4659017119 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4659017119 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4659017119 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14650509239 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14650509239 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394876998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394876998 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16045386237 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16045386237 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041653 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041653 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027450 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027450 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064036 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069147 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069147 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.034893 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034893 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.034893 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9923.068722 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9923.068722 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 13988.772173 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 13988.772173 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14442.193283 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14442.193283 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21291.069323 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21291.069323 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_mshr_hits::cpu0.inst 178851 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 178851 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.inst 178851 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 178851 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.inst 253776 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 253776 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.inst 152088 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 152088 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.inst 10117 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 10117 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.inst 10869 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 10869 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.inst 405864 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 405864 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.inst 405864 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 405864 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.inst 2514607539 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2514607539 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.inst 2141849701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2141849701 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.inst 146522249 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146522249 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.inst 231876035 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 231876035 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.inst 1427500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1427500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.inst 4656457240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4656457240 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.inst 4656457240 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4656457240 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.inst 14652229736 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 14652229736 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.inst 1394826498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1394826498 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.inst 16047056234 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 16047056234 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.inst 0.041508 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.041508 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.inst 0.027394 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027394 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.inst 0.064189 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.064189 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.inst 0.069010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.069010 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.034791 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.inst 0.034791 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.034791 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9908.768122 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 9908.768122 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.inst 14082.963159 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 14082.963159 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.inst 14482.776416 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14482.776416 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.inst 21333.704573 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21333.704573 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.inst inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11445.248038 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11445.248038 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.inst 11472.949658 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 11472.949658 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average WriteReq mshr uncacheable latency @@ -1681,15 +1665,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 7015971 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5101339 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 682515 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5021553 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3808301 # Number of BTB hits +system.cpu1.branchPred.lookups 7012649 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5102138 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 681212 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4956162 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3806104 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 75.839108 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 855690 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 72942 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 76.795391 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 854817 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 71801 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1713,25 +1697,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 7897430 # DTB read hits -system.cpu1.dtb.read_misses 21135 # DTB read misses -system.cpu1.dtb.write_hits 6047519 # DTB write hits -system.cpu1.dtb.write_misses 2176 # DTB write misses +system.cpu1.dtb.read_hits 7899300 # DTB read hits +system.cpu1.dtb.read_misses 20789 # DTB read misses +system.cpu1.dtb.write_hits 6047693 # DTB write hits +system.cpu1.dtb.write_misses 2209 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1928 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 3376 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 148 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1917 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3619 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 7918565 # DTB read accesses -system.cpu1.dtb.write_accesses 6049695 # DTB write accesses +system.cpu1.dtb.perms_faults 329 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7920089 # DTB read accesses +system.cpu1.dtb.write_accesses 6049902 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 13944949 # DTB hits -system.cpu1.dtb.misses 23311 # DTB misses -system.cpu1.dtb.accesses 13968260 # DTB accesses +system.cpu1.dtb.hits 13946993 # DTB hits +system.cpu1.dtb.misses 22998 # DTB misses +system.cpu1.dtb.accesses 13969991 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1753,8 +1737,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 14225149 # ITB inst hits -system.cpu1.itb.inst_misses 5020 # ITB inst misses +system.cpu1.itb.inst_hits 14215184 # ITB inst hits +system.cpu1.itb.inst_misses 5010 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1763,81 +1747,81 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1294 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1291 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 3363 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 3360 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 14230169 # ITB inst accesses -system.cpu1.itb.hits 14225149 # DTB hits -system.cpu1.itb.misses 5020 # DTB misses -system.cpu1.itb.accesses 14230169 # DTB accesses -system.cpu1.numCycles 502333604 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 14220194 # ITB inst accesses +system.cpu1.itb.hits 14215184 # DTB hits +system.cpu1.itb.misses 5010 # DTB misses +system.cpu1.itb.accesses 14220194 # DTB accesses +system.cpu1.numCycles 502294457 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 33559332 # Number of instructions committed -system.cpu1.committedOps 40204034 # Number of ops (including micro ops) committed -system.cpu1.discardedOps 2027525 # Number of ops (including micro ops) which were discarded before commit -system.cpu1.numFetchSuspends 40422 # Number of times Execute suspended instruction fetching -system.cpu1.quiesceCycles 4816582490 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.cpi 14.968522 # CPI: cycles per instruction -system.cpu1.ipc 0.066807 # IPC: instructions per cycle +system.cpu1.committedInsts 33559021 # Number of instructions committed +system.cpu1.committedOps 40204815 # Number of ops (including micro ops) committed +system.cpu1.discardedOps 2028180 # Number of ops (including micro ops) which were discarded before commit +system.cpu1.numFetchSuspends 40425 # Number of times Execute suspended instruction fetching +system.cpu1.quiesceCycles 4816571571 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.cpi 14.967494 # CPI: cycles per instruction +system.cpu1.ipc 0.066811 # IPC: instructions per cycle system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 45430 # number of quiesce instructions executed -system.cpu1.tickCycles 438569606 # Number of cycles that the object actually ticked -system.cpu1.idleCycles 63763998 # Total number of cycles that the object has spent stopped -system.cpu1.icache.tags.replacements 776883 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.132911 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 13444222 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 777395 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 17.293939 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 68940011500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.132911 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974869 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.974869 # Average percentage of cache occupancy +system.cpu1.kern.inst.quiesce 45433 # number of quiesce instructions executed +system.cpu1.tickCycles 438597056 # Number of cycles that the object actually ticked +system.cpu1.idleCycles 63697401 # Total number of cycles that the object has spent stopped +system.cpu1.icache.tags.replacements 777492 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.131548 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 13433657 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 778004 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 17.266823 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 71929000500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.131548 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.974866 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.974866 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 512 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 29220629 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 29220629 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 13444222 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 13444222 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 13444222 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 13444222 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 13444222 # number of overall hits -system.cpu1.icache.overall_hits::total 13444222 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 777395 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 777395 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 777395 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 777395 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 777395 # number of overall misses -system.cpu1.icache.overall_misses::total 777395 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6473834509 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6473834509 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6473834509 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6473834509 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6473834509 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6473834509 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 14221617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 14221617 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 14221617 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 14221617 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 14221617 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 14221617 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054663 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.054663 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054663 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.054663 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054663 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.054663 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8327.599880 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8327.599880 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8327.599880 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8327.599880 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8327.599880 # average overall miss latency +system.cpu1.icache.tags.tag_accesses 29201326 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 29201326 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 13433657 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 13433657 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 13433657 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 13433657 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 13433657 # number of overall hits +system.cpu1.icache.overall_hits::total 13433657 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 778004 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 778004 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 778004 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 778004 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 778004 # number of overall misses +system.cpu1.icache.overall_misses::total 778004 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6472911750 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6472911750 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6472911750 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6472911750 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6472911750 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6472911750 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 14211661 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 14211661 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 14211661 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 14211661 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 14211661 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 14211661 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.054744 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.054744 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.054744 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.054744 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.054744 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.054744 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8319.895206 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8319.895206 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8319.895206 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8319.895206 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8319.895206 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1846,371 +1830,370 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 777395 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 777395 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 777395 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 777395 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 777395 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 777395 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5306001991 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5306001991 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5306001991 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5306001991 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5306001991 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5306001991 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7443500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7443500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7443500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 7443500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054663 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.054663 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054663 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.054663 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6825.361613 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6825.361613 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 6825.361613 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 778004 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 778004 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 778004 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 778004 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 778004 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 778004 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5304159248 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5304159248 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5304159248 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5304159248 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5304159248 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5304159248 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 7302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 7302500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 7302500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.054744 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.054744 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.054744 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.054744 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 6817.650357 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 6817.650357 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 6817.650357 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 2372884 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 2161619 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadRespWithInvalidate 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 757958 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 757958 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 242023 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 269237 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 52848 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23732 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 50462 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 31 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 53 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 145739 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 137938 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1554692 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4766762 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17488 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 67601 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 6406543 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49741696 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44501144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30140 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 121260 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 94394240 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 607829 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 2003123 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 5.277710 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.447870 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 2373135 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 2161912 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 757956 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 757956 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 242084 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 267987 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 52917 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 23794 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 50912 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 37 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 60 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 145700 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 137856 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1555984 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 4768118 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17545 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 66434 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 6408081 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 49785408 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 44521800 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30416 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 119152 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94456776 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 606235 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2002284 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 5.277104 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.447568 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::5 1446836 72.23% 72.23% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::6 556287 27.77% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::5 1447444 72.29% 72.29% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::6 554840 27.71% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 2003123 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 2275243689 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2002284 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 2275579743 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 46353997 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 46369000 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1167104009 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 1168020751 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 2025335762 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 2025918980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9955994 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9945491 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 37292239 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 36649244 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6843055 # number of hwpf identified -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163843 # number of hwpf that were already in mshr -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6478033 # number of hwpf that were already in the cache -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2741 # number of hwpf that were already in the prefetch queue +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_identified 6850018 # number of hwpf identified +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_mshr 163294 # number of hwpf that were already in mshr +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_cache 6486593 # number of hwpf that were already in the cache +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_already_in_prefetcher 2687 # number of hwpf that were already in the prefetch queue system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2015 # number of hwpf removed because MSHR allocated -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 196423 # number of hwpf issued -system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 563857 # number of hwpf spanning a virtual page +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_removed_MSHR_hit 2014 # number of hwpf removed because MSHR allocated +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_issued 195430 # number of hwpf issued +system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_span_page 564382 # number of hwpf spanning a virtual page system.cpu1.l2cache.prefetcher.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time -system.cpu1.l2cache.tags.replacements 179577 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15624.309787 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1195829 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 195022 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 6.131765 # Average number of references to valid blocks. -system.cpu1.l2cache.tags.warmup_cycle 2581358397500 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 4477.438103 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 22.594175 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.081575 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2724.649779 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8398.546154 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.273281 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001379 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000066 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.166299 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.512607 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.953632 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9457 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5975 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2071 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1611 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5775 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 7 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2329 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 929 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2717 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.577209 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.364685 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 23391503 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 23391503 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29831 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7391 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 925413 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 962635 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 242023 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 242023 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1810 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1810 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1118 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1118 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112181 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 112181 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 29831 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7391 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 1037594 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 1074816 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 29831 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7391 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 1037594 # number of overall hits -system.cpu1.l2cache.overall_hits::total 1074816 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 484 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 144 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 61489 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 62117 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.inst 18553 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 18553 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.inst 12524 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 12524 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.inst 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.inst 24216 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 24216 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 484 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 144 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 85705 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 86333 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 484 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 144 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 85705 # number of overall misses -system.cpu1.l2cache.overall_misses::total 86333 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 10993750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 3129500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 1532483424 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 1546606674 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.inst 310148223 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 310148223 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.inst 250854673 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 250854673 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.inst 743500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 743500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.inst 1014040211 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1014040211 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 10993750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 3129500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 2546523635 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 2560646885 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 10993750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 3129500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 2546523635 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 2560646885 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 30315 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7535 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 986902 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 1024752 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 242023 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 242023 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.inst 20363 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 20363 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.inst 13642 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 13642 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.inst 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.inst 136397 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 136397 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 30315 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7535 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 1123299 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 1161149 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 30315 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7535 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 1123299 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 1161149 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.015966 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.019111 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.062305 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.060617 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.inst 0.911113 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.911113 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.inst 0.918047 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.918047 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.tags.replacements 179644 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15634.197458 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1195685 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 195044 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 6.130335 # Average number of references to valid blocks. +system.cpu1.l2cache.tags.warmup_cycle 2581359096500 # Cycle when the warmup percentage was hit. +system.cpu1.l2cache.tags.occ_blocks::writebacks 4491.320198 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 23.341759 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 1.933743 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 2764.115946 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 8353.485812 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.274128 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.001425 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000118 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.168708 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.509856 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.954236 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 9491 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 11 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 5898 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 2061 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 1580 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 5850 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 7 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 2269 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 2711 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.579285 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.000671 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.359985 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 23405517 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 23405517 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 29293 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7458 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.inst 926354 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 963105 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 242084 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 242084 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.inst 1948 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 1948 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.inst 1158 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1158 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.inst 112338 # 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mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.071626 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.239153 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14732.638889 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18350.000710 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 18319.212175 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51600.781700 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 51600.781700 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.inst 16479.950574 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16479.950574 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.inst 14246.957921 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14246.957921 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 582500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 582500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27863.315348 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27863.315348 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15711.260331 # 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average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14248.954190 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.inst 218166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 218166.666667 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.inst 27725.903639 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 27725.903639 # average ReadExReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 20832.172258 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16426.767677 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13835.616438 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 20871.936966 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 51692.257084 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 42636.251006 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2218,96 +2201,96 @@ system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.tags.replacements 322636 # number of replacements -system.cpu1.dcache.tags.tagsinuse 491.144142 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 11399665 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 322979 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.295375 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 72461169500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.inst 491.144142 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.inst 0.959266 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.959266 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 343 # 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number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.inst 11867 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11867 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.inst 13691 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 13691 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.inst 355207 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 355207 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.inst 355207 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 355207 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.inst 2202163297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2202163297 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.inst 2284592028 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2284592028 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.inst 190117000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 190117000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.inst 286543590 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 286543590 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.inst 863000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 863000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.inst 4486755325 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4486755325 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.inst 4486755325 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4486755325 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.inst 183747450747 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 183747450747 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.inst 34481854358 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34481854358 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.inst 218229305105 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 218229305105 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.inst 0.029992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.029992 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.inst 0.030726 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030726 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.inst 0.124526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.124526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.inst 0.143793 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.143793 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030312 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.inst 0.030312 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.030312 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11106.835074 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11106.835074 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.inst 14557.475837 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14557.475837 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.inst 16020.645487 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16020.645487 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.inst 20929.339712 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 20929.339712 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.inst inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12669.344115 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12669.344115 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.inst 12631.382053 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12631.382053 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average WriteReq mshr uncacheable latency @@ -2409,10 +2392,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1759208062571 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759208062571 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1759208062571 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1759755743315 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1759755743315 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1759755743315 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |