diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-12-23 09:31:20 -0500 |
| commit | df8df4fd0a95763cb0658cbe77615e7deac391d3 (patch) | |
| tree | 0c8776db2ef482a4f6e5db099133105f9af799d7 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | |
| parent | b2342c5d9aea0b732f6d5a5b6c9c3961940ed8e7 (diff) | |
| download | gem5-df8df4fd0a95763cb0658cbe77615e7deac391d3.tar.xz | |
stats: Bump stats for decoder, TLB, prefetcher and DRAM changes
Changes due to speculative execution of an unaligned PC, introduction
of TLB stats, changes and re-work of the prefetcher, and the
introduction of rank-wise refresh in the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1574 |
1 files changed, 827 insertions, 747 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 1c98029fc..8068ce076 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,116 +1,116 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852850 # Number of seconds simulated -sim_ticks 2852849954000 # Number of ticks simulated -final_tick 2852849954000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.852858 # Number of seconds simulated +sim_ticks 2852857543000 # Number of ticks simulated +final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 160685 # Simulator instruction rate (inst/s) -host_op_rate 194286 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4092855045 # Simulator tick rate (ticks/s) -host_mem_usage 562916 # Number of bytes of host memory used -host_seconds 697.03 # Real time elapsed on the host -sim_insts 112002684 # Number of instructions simulated -sim_ops 135423332 # Number of ops (including micro ops) simulated +host_inst_rate 169259 # Simulator instruction rate (inst/s) +host_op_rate 204656 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4303403710 # Simulator tick rate (ticks/s) +host_mem_usage 619600 # Number of bytes of host memory used +host_seconds 662.93 # Real time elapsed on the host +sim_insts 112207125 # Number of instructions simulated +sim_ops 135672670 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 10823844 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 10837924 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10832740 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1658560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1658560 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7967296 # Number of bytes written to this memory +system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory system.physmem.bytes_written::cpu.inst 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7984820 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 169642 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 169862 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 169781 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124489 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.inst 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128870 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2759 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 3794046 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 3798971 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3797164 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 581370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 581370 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2792750 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.inst 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2798892 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2792750 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 3800189 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 3805114 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6596057 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 169781 # Number of read requests accepted -system.physmem.writeReqs 165094 # Number of write requests accepted -system.physmem.readBursts 169781 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165094 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10858880 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7104 # Total number of bytes read from write queue -system.physmem.bytesWritten 10194112 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10832740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10303156 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 111 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5787 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4592 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10675 # Per bank write bursts -system.physmem.perBankRdBursts::1 10570 # Per bank write bursts -system.physmem.perBankRdBursts::2 10940 # Per bank write bursts -system.physmem.perBankRdBursts::3 10884 # Per bank write bursts -system.physmem.perBankRdBursts::4 12996 # Per bank write bursts +system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170006 # Number of read requests accepted +system.physmem.writeReqs 165023 # Number of write requests accepted +system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue +system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10656 # Per bank write bursts +system.physmem.perBankRdBursts::1 10651 # Per bank write bursts +system.physmem.perBankRdBursts::2 10704 # Per bank write bursts +system.physmem.perBankRdBursts::3 10614 # Per bank write bursts +system.physmem.perBankRdBursts::4 13356 # Per bank write bursts system.physmem.perBankRdBursts::5 10666 # Per bank write bursts -system.physmem.perBankRdBursts::6 11098 # Per bank write bursts -system.physmem.perBankRdBursts::7 10877 # Per bank write bursts -system.physmem.perBankRdBursts::8 10287 # Per bank write bursts -system.physmem.perBankRdBursts::9 10457 # Per bank write bursts -system.physmem.perBankRdBursts::10 10268 # Per bank write bursts -system.physmem.perBankRdBursts::11 9318 # Per bank write bursts -system.physmem.perBankRdBursts::12 10425 # Per bank write bursts -system.physmem.perBankRdBursts::13 10908 # Per bank write bursts -system.physmem.perBankRdBursts::14 9678 # Per bank write bursts -system.physmem.perBankRdBursts::15 9623 # Per bank write bursts -system.physmem.perBankWrBursts::0 10097 # Per bank write bursts -system.physmem.perBankWrBursts::1 10006 # Per bank write bursts -system.physmem.perBankWrBursts::2 10747 # Per bank write bursts -system.physmem.perBankWrBursts::3 10511 # Per bank write bursts -system.physmem.perBankWrBursts::4 9282 # Per bank write bursts -system.physmem.perBankWrBursts::5 9914 # Per bank write bursts -system.physmem.perBankWrBursts::6 10247 # Per bank write bursts -system.physmem.perBankWrBursts::7 10166 # Per bank write bursts -system.physmem.perBankWrBursts::8 10178 # Per bank write bursts -system.physmem.perBankWrBursts::9 10302 # Per bank write bursts -system.physmem.perBankWrBursts::10 10037 # Per bank write bursts -system.physmem.perBankWrBursts::11 9553 # Per bank write bursts -system.physmem.perBankWrBursts::12 10068 # Per bank write bursts -system.physmem.perBankWrBursts::13 10279 # Per bank write bursts -system.physmem.perBankWrBursts::14 8984 # Per bank write bursts -system.physmem.perBankWrBursts::15 8912 # Per bank write bursts +system.physmem.perBankRdBursts::6 11042 # Per bank write bursts +system.physmem.perBankRdBursts::7 10972 # Per bank write bursts +system.physmem.perBankRdBursts::8 10208 # Per bank write bursts +system.physmem.perBankRdBursts::9 10672 # Per bank write bursts +system.physmem.perBankRdBursts::10 10509 # Per bank write bursts +system.physmem.perBankRdBursts::11 9657 # Per bank write bursts +system.physmem.perBankRdBursts::12 10109 # Per bank write bursts +system.physmem.perBankRdBursts::13 10747 # Per bank write bursts +system.physmem.perBankRdBursts::14 9757 # Per bank write bursts +system.physmem.perBankRdBursts::15 9582 # Per bank write bursts +system.physmem.perBankWrBursts::0 10072 # Per bank write bursts +system.physmem.perBankWrBursts::1 10092 # Per bank write bursts +system.physmem.perBankWrBursts::2 10491 # Per bank write bursts +system.physmem.perBankWrBursts::3 10304 # Per bank write bursts +system.physmem.perBankWrBursts::4 9538 # Per bank write bursts +system.physmem.perBankWrBursts::5 9899 # Per bank write bursts +system.physmem.perBankWrBursts::6 10133 # Per bank write bursts +system.physmem.perBankWrBursts::7 10134 # Per bank write bursts +system.physmem.perBankWrBursts::8 10091 # Per bank write bursts +system.physmem.perBankWrBursts::9 10380 # Per bank write bursts +system.physmem.perBankWrBursts::10 10169 # Per bank write bursts +system.physmem.perBankWrBursts::11 9697 # Per bank write bursts +system.physmem.perBankWrBursts::12 9799 # Per bank write bursts +system.physmem.perBankWrBursts::13 10201 # Per bank write bursts +system.physmem.perBankWrBursts::14 9040 # Per bank write bursts +system.physmem.perBankWrBursts::15 8946 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2852849531000 # Total gap between requests +system.physmem.totGap 2852857119000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169226 # Read request sizes (log2) +system.physmem.readPktSize::6 169451 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160713 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 162999 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6619 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160642 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -155,134 +155,134 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3867 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7745 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8889 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9235 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 9997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11185 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11099 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11636 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10861 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10486 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9441 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7752 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7274 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 275 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 203 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 174 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 110 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 87 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 67 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 45 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 11037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 11618 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10744 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10251 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9284 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 7662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7362 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7081 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62892 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.747313 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 194.220308 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.895470 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22415 35.64% 35.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14531 23.10% 58.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6612 10.51% 69.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3482 5.54% 74.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2506 3.98% 78.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1581 2.51% 81.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1054 1.68% 82.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1133 1.80% 84.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9578 15.23% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62892 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6668 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.444061 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 561.318574 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6666 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6668 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6668 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.887672 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.937507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.272912 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5557 83.34% 83.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 39 0.58% 83.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 24 0.36% 84.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 223 3.34% 87.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 119 1.78% 89.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 51 0.76% 90.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 29 0.43% 90.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 45 0.67% 91.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 120 1.80% 93.09% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.18% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 15 0.22% 93.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.21% 93.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 30 0.45% 94.15% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 8 0.12% 94.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 35 0.52% 95.08% # Writes before turning the bus around for reads +system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 9 0.13% 96.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 6 0.09% 96.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 100 1.50% 97.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 4 0.06% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 13 0.19% 98.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 8 0.12% 98.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 22 0.33% 98.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.15% 98.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.04% 98.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 27 0.40% 99.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 9 0.13% 99.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.12% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.01% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 3 0.04% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 3 0.04% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::216-219 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::220-223 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::252-255 2 0.03% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6668 # Writes before turning the bus around for reads -system.physmem.totQLat 1702635750 # Total ticks spent queuing -system.physmem.totMemAccLat 4883948250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 848350000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10034.98 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads +system.physmem.totQLat 1659710000 # Total ticks spent queuing +system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28784.98 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s @@ -291,37 +291,42 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 23.42 # Average write queue length when enqueuing -system.physmem.readRowHits 139924 # Number of row buffer hits during reads -system.physmem.writeRowHits 126136 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.47 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.18 # Row buffer hit rate for writes -system.physmem.avgGap 8519147.54 # Average gap between requests -system.physmem.pageHitRate 80.87 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2713515031250 # Time in different power states -system.physmem.memoryStateTime::REF 95262700000 # Time in different power states -system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 44072132750 # Time in different power states -system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem.actEnergy::0 246765960 # Energy for activate commands per rank (pJ) -system.physmem.actEnergy::1 228697560 # Energy for activate commands per rank (pJ) -system.physmem.preEnergy::0 134644125 # Energy for precharge commands per rank (pJ) -system.physmem.preEnergy::1 124785375 # Energy for precharge commands per rank (pJ) -system.physmem.readEnergy::0 691906800 # Energy for read commands per rank (pJ) -system.physmem.readEnergy::1 631511400 # Energy for read commands per rank (pJ) -system.physmem.writeEnergy::0 524685600 # Energy for write commands per rank (pJ) -system.physmem.writeEnergy::1 507468240 # Energy for write commands per rank (pJ) -system.physmem.refreshEnergy::0 186333841200 # Energy for refresh commands per rank (pJ) -system.physmem.refreshEnergy::1 186333841200 # Energy for refresh commands per rank (pJ) -system.physmem.actBackEnergy::0 83199782385 # Energy for active background per rank (pJ) -system.physmem.actBackEnergy::1 82045768365 # Energy for active background per rank (pJ) -system.physmem.preBackEnergy::0 1638723732000 # Energy for precharge background per rank (pJ) -system.physmem.preBackEnergy::1 1639736025000 # Energy for precharge background per rank (pJ) -system.physmem.totalEnergy::0 1909855358070 # Total energy per rank (pJ) -system.physmem.totalEnergy::1 1909608097140 # Total energy per rank (pJ) -system.physmem.averagePower::0 669.456797 # Core power per rank (mW) -system.physmem.averagePower::1 669.370126 # Core power per rank (mW) +system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing +system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing +system.physmem.readRowHits 140084 # Number of row buffer hits during reads +system.physmem.writeRowHits 125841 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes +system.physmem.avgGap 8515254.26 # Average gap between requests +system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.469106 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.371033 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states +system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states +system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 448 # Number of instructions bytes read from this memory @@ -340,16 +345,24 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31051775 # Number of BP lookups -system.cpu.branchPred.condPredicted 16857996 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2519060 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18534749 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13337392 # Number of BTB hits +system.cpu.branchPred.lookups 31058702 # Number of BP lookups +system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 71.958849 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7856975 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1512712 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -371,27 +384,65 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 66845 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24746159 # DTB read hits -system.cpu.dtb.read_misses 60199 # DTB read misses -system.cpu.dtb.write_hits 19443156 # DTB write hits -system.cpu.dtb.write_misses 6950 # DTB write misses +system.cpu.dtb.read_hits 24793006 # DTB read hits +system.cpu.dtb.read_misses 59858 # DTB read misses +system.cpu.dtb.write_hits 19468400 # DTB write hits +system.cpu.dtb.write_misses 6987 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4352 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1783 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 751 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24806358 # DTB read accesses -system.cpu.dtb.write_accesses 19450106 # DTB write accesses +system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24852864 # DTB read accesses +system.cpu.dtb.write_accesses 19475387 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44189315 # DTB hits -system.cpu.dtb.misses 67149 # DTB misses -system.cpu.dtb.accesses 44256464 # DTB accesses +system.cpu.dtb.hits 44261406 # DTB hits +system.cpu.dtb.misses 66845 # DTB misses +system.cpu.dtb.accesses 44328251 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -413,8 +464,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.inst_hits 57672689 # ITB inst hits -system.cpu.itb.inst_misses 5411 # ITB inst misses +system.cpu.itb.walker.walks 5440 # Table walker walks requested +system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57692911 # ITB inst hits +system.cpu.itb.inst_misses 5440 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -423,119 +503,119 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2970 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8383 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57678100 # ITB inst accesses -system.cpu.itb.hits 57672689 # DTB hits -system.cpu.itb.misses 5411 # DTB misses -system.cpu.itb.accesses 57678100 # DTB accesses -system.cpu.numCycles 314966932 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57698351 # ITB inst accesses +system.cpu.itb.hits 57692911 # DTB hits +system.cpu.itb.misses 5440 # DTB misses +system.cpu.itb.accesses 57698351 # DTB accesses +system.cpu.numCycles 314937774 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112002684 # Number of instructions committed -system.cpu.committedOps 135423332 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7762811 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3036 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390780993 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.812137 # CPI: cycles per instruction -system.cpu.ipc 0.355601 # IPC: instructions per cycle +system.cpu.committedInsts 112207125 # Number of instructions committed +system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.806754 # CPI: cycles per instruction +system.cpu.ipc 0.356283 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3036 # number of quiesce instructions executed -system.cpu.tickCycles 228185661 # Number of cycles that the object actually ticked -system.cpu.idleCycles 86781271 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 843230 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953176 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42691062 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 843742 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.597294 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed +system.cpu.tickCycles 228221487 # Number of cycles that the object actually ticked +system.cpu.idleCycles 86716287 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 841983 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.953279 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42762284 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953176 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.inst 511.953279 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.inst 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 97 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176134397 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176134397 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.inst 23488260 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23488260 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.inst 18281937 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18281937 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457712 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457712 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.inst 460238 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460238 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.inst 41770197 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41770197 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.inst 41770197 # number of overall hits -system.cpu.dcache.overall_hits::total 41770197 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.inst 584617 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 584617 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.inst 541532 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541532 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8359 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8359 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.inst 23536274 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.inst 18304900 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.inst 457909 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.inst 460268 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.inst 41841174 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.inst 41841174 # number of overall hits +system.cpu.dcache.overall_hits::total 41841174 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.inst 583393 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.inst 541748 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.inst 8195 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.inst 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.inst 1126149 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1126149 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.inst 1126149 # number of overall misses -system.cpu.dcache.overall_misses::total 1126149 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8658802092 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8658802092 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21460434801 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21460434801 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 117977250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 117977250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 152000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 152000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.inst 30119236893 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30119236893 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.inst 30119236893 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30119236893 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.inst 24072877 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24072877 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.inst 18823469 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18823469 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466071 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 466071 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.inst 460240 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460240 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.inst 42896346 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 42896346 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.inst 42896346 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 42896346 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.inst 0.024285 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.024285 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.inst 0.028769 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.028769 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst 0.017935 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017935 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_misses::cpu.inst 1125141 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.inst 1125141 # number of overall misses +system.cpu.dcache.overall_misses::total 1125141 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.inst 8651014339 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.inst 21393186307 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst 116036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.inst 30044200646 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.inst 30044200646 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.inst 24119667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.inst 18846648 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 18846648 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.inst 466104 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18108129299 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18108129299 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790997000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439577500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439577500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230574500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230574500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022410 # 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number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst 11166823654 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11166823654 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst 99620500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 99620500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst 146500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.inst 18060007796 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.inst 18060007796 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst 5790998000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst 4439562500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439562500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst 10230560500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230560500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst 0.022316 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022316 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst 0.015860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst 0.017582 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017582 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019541 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019541 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019541 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019541 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12783.424482 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12783.424482 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37528.549107 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37528.549107 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12110.389999 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12110.389999 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 74000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 74000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21602.868550 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21602.868550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21602.868550 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21602.868550 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.inst 0.019484 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.inst 0.019484 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12806.801640 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37357.981406 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.253813 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst 73250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21572.997924 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21572.997924 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -615,58 +695,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2898546 # number of replacements -system.cpu.icache.tags.tagsinuse 511.424366 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54764882 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2899058 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.890578 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15302672250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.424366 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 2900110 # number of replacements +system.cpu.icache.tags.tagsinuse 511.424371 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54783568 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2900622 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.886835 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15309705250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.424371 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 110 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 198 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652352500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652352500 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010758 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010560 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.982612 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982612 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9796383317 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 9805087067 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 5545301250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5545301250 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst 4107025000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4107025000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 9652326250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9652326250 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010806 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.010611 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst 0.981285 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.981285 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443071 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044077 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001717 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044940 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044077 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst 0.443005 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443005 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044136 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001799 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000226 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.044993 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044136 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 62500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61532.254585 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61543.946887 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10066.727700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10066.727700 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 61000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 61000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57558.304584 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57558.304584 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61636.248926 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10068.290392 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57182.821397 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 65060.975610 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58434.353561 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58439.219923 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58167.770978 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst inf # average WriteReq mshr uncacheable latency @@ -946,54 +1026,54 @@ system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3581708 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3581608 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 699279 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2818 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2820 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 295941 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 295941 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804102 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2510082 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14997 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161563 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8490744 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185730048 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98946845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17972 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 286516 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284981381 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 60946 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4581834 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007957 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088847 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61311 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4545376 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4581834 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3016682672 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4358543218 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1342977701 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10504000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89938750 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30195 # Transaction distribution system.iobus.trans_dist::ReadResp 30195 # Transaction distribution @@ -1090,23 +1170,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347024164 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804504 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033420 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270180945000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033420 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064589 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064589 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1122,8 +1202,8 @@ system.iocache.overall_misses::realview.ide 234 # system.iocache.overall_misses::total 234 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9603131283 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9603131283 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles @@ -1146,17 +1226,17 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265104.110065 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265104.110065 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56022 # number of cycles access was blocked +system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7210 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.770042 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1172,8 +1252,8 @@ system.iocache.overall_mshr_misses::realview.ide 234 system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7719475291 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7719475291 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles @@ -1188,64 +1268,64 @@ system.iocache.overall_mshr_miss_rate::realview.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213103.889438 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213103.889438 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71576 # Transaction distribution -system.membus.trans_dist::ReadResp 71576 # Transaction distribution +system.membus.trans_dist::ReadReq 71749 # Transaction distribution +system.membus.trans_dist::ReadResp 71749 # Transaction distribution system.membus.trans_dist::WriteReq 27607 # Transaction distribution system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 124489 # Transaction distribution +system.membus.trans_dist::Writeback 124418 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4592 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4594 # Transaction distribution -system.membus.trans_dist::ReadExReq 129300 # Transaction distribution -system.membus.trans_dist::ReadExResp 129300 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution +system.membus.trans_dist::ReadExReq 129351 # Transaction distribution +system.membus.trans_dist::ReadExResp 129351 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446065 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 553697 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662584 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16500440 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16664221 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21299677 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 507 # Total snoops (count) -system.membus.snoop_fanout::samples 332045 # Request fanout histogram +system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 506 # Total snoops (count) +system.membus.snoop_fanout::samples 332202 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332045 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332045 # Request fanout histogram -system.membus.reqLayer0.occupancy 87455500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332202 # Request fanout histogram +system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1699000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1675329000 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1688631909 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38334496 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |