diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2016-04-09 12:13:40 -0400 |
| commit | d9193d1b2039739ef4fb264c742d37f9803817e5 (patch) | |
| tree | 7904829173102a8d8f654873d5cefb790e148298 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | |
| parent | 1d61224a8ba60a2c8cb06e9877b7e548d47bb99a (diff) | |
| download | gem5-d9193d1b2039739ef4fb264c742d37f9803817e5.tar.xz | |
stats: Match current behaviour
Small changes to the branch predictor and BTB caused stats changes
throughout.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1926 |
1 files changed, 984 insertions, 942 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 11bd5dafc..cc9440c8e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.858536 # Number of seconds simulated -sim_ticks 2858536032500 # Number of ticks simulated -final_tick 2858536032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.858505 # Number of seconds simulated +sim_ticks 2858505242500 # Number of ticks simulated +final_tick 2858505242500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 177299 # Simulator instruction rate (inst/s) -host_op_rate 214372 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 4522420422 # Simulator tick rate (ticks/s) -host_mem_usage 585260 # Number of bytes of host memory used -host_seconds 632.08 # Real time elapsed on the host -sim_insts 112067614 # Number of instructions simulated -sim_ops 135500271 # Number of ops (including micro ops) simulated +host_inst_rate 194204 # Simulator instruction rate (inst/s) +host_op_rate 234807 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4961098243 # Simulator tick rate (ticks/s) +host_mem_usage 583728 # Number of bytes of host memory used +host_seconds 576.18 # Real time elapsed on the host +sim_insts 111897168 # Number of instructions simulated +sim_ops 135292215 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1708096 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9152172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1705984 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9156972 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10869356 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1708096 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1708096 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7939328 # Number of bytes written to this memory +system.physmem.bytes_read::total 10871852 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1705984 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1705984 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7955328 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7956852 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 125 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 26689 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143524 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7972852 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 123 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26656 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143599 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170355 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124052 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170394 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124302 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128433 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2799 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 597542 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3201699 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128683 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2754 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 596810 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3203413 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 597542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 597542 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2777411 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3803335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 596810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 596810 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2783038 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 6130 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783541 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2777411 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2799 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 597542 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3207829 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2789168 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2783038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 596810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3209543 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6585961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170355 # Number of read requests accepted -system.physmem.writeReqs 128433 # Number of write requests accepted -system.physmem.readBursts 170355 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 128433 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10894592 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8128 # Total number of bytes read from write queue -system.physmem.bytesWritten 7969344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10869356 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7956852 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 127 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6592503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170394 # Number of read requests accepted +system.physmem.writeReqs 128683 # Number of write requests accepted +system.physmem.readBursts 170394 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 128683 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10896320 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8896 # Total number of bytes read from write queue +system.physmem.bytesWritten 7985280 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10871852 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 7972852 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 139 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3887 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10771 # Per bank write bursts -system.physmem.perBankRdBursts::1 10790 # Per bank write bursts -system.physmem.perBankRdBursts::2 10898 # Per bank write bursts -system.physmem.perBankRdBursts::3 10736 # Per bank write bursts -system.physmem.perBankRdBursts::4 14068 # Per bank write bursts -system.physmem.perBankRdBursts::5 10207 # Per bank write bursts -system.physmem.perBankRdBursts::6 11005 # Per bank write bursts -system.physmem.perBankRdBursts::7 10952 # Per bank write bursts -system.physmem.perBankRdBursts::8 9928 # Per bank write bursts -system.physmem.perBankRdBursts::9 10232 # Per bank write bursts -system.physmem.perBankRdBursts::10 9939 # Per bank write bursts -system.physmem.perBankRdBursts::11 9163 # Per bank write bursts -system.physmem.perBankRdBursts::12 10281 # Per bank write bursts -system.physmem.perBankRdBursts::13 11195 # Per bank write bursts -system.physmem.perBankRdBursts::14 10251 # Per bank write bursts -system.physmem.perBankRdBursts::15 9812 # Per bank write bursts -system.physmem.perBankWrBursts::0 8074 # Per bank write bursts -system.physmem.perBankWrBursts::1 8145 # Per bank write bursts -system.physmem.perBankWrBursts::2 8532 # Per bank write bursts -system.physmem.perBankWrBursts::3 8274 # Per bank write bursts -system.physmem.perBankWrBursts::4 7651 # Per bank write bursts -system.physmem.perBankWrBursts::5 7419 # Per bank write bursts -system.physmem.perBankWrBursts::6 7942 # Per bank write bursts -system.physmem.perBankWrBursts::7 8023 # Per bank write bursts -system.physmem.perBankWrBursts::8 7561 # Per bank write bursts -system.physmem.perBankWrBursts::9 7722 # Per bank write bursts -system.physmem.perBankWrBursts::10 7504 # Per bank write bursts -system.physmem.perBankWrBursts::11 7050 # Per bank write bursts -system.physmem.perBankWrBursts::12 7678 # Per bank write bursts -system.physmem.perBankWrBursts::13 8296 # Per bank write bursts -system.physmem.perBankWrBursts::14 7536 # Per bank write bursts -system.physmem.perBankWrBursts::15 7114 # Per bank write bursts +system.physmem.perBankRdBursts::0 10648 # Per bank write bursts +system.physmem.perBankRdBursts::1 11113 # Per bank write bursts +system.physmem.perBankRdBursts::2 10810 # Per bank write bursts +system.physmem.perBankRdBursts::3 10613 # Per bank write bursts +system.physmem.perBankRdBursts::4 13551 # Per bank write bursts +system.physmem.perBankRdBursts::5 10292 # Per bank write bursts +system.physmem.perBankRdBursts::6 10857 # Per bank write bursts +system.physmem.perBankRdBursts::7 10932 # Per bank write bursts +system.physmem.perBankRdBursts::8 10292 # Per bank write bursts +system.physmem.perBankRdBursts::9 10622 # Per bank write bursts +system.physmem.perBankRdBursts::10 10100 # Per bank write bursts +system.physmem.perBankRdBursts::11 9078 # Per bank write bursts +system.physmem.perBankRdBursts::12 10356 # Per bank write bursts +system.physmem.perBankRdBursts::13 10810 # Per bank write bursts +system.physmem.perBankRdBursts::14 10110 # Per bank write bursts +system.physmem.perBankRdBursts::15 10071 # Per bank write bursts +system.physmem.perBankWrBursts::0 7962 # Per bank write bursts +system.physmem.perBankWrBursts::1 8429 # Per bank write bursts +system.physmem.perBankWrBursts::2 8465 # Per bank write bursts +system.physmem.perBankWrBursts::3 8172 # Per bank write bursts +system.physmem.perBankWrBursts::4 7181 # Per bank write bursts +system.physmem.perBankWrBursts::5 7509 # Per bank write bursts +system.physmem.perBankWrBursts::6 7876 # Per bank write bursts +system.physmem.perBankWrBursts::7 8019 # Per bank write bursts +system.physmem.perBankWrBursts::8 7862 # Per bank write bursts +system.physmem.perBankWrBursts::9 8101 # Per bank write bursts +system.physmem.perBankWrBursts::10 7665 # Per bank write bursts +system.physmem.perBankWrBursts::11 6948 # Per bank write bursts +system.physmem.perBankWrBursts::12 7780 # Per bank write bursts +system.physmem.perBankWrBursts::13 8006 # Per bank write bursts +system.physmem.perBankWrBursts::14 7432 # Per bank write bursts +system.physmem.perBankWrBursts::15 7363 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 10 # Number of times write queue was full causing retry -system.physmem.totGap 2858535588000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2858504798000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 543 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169798 # Read request sizes (log2) +system.physmem.readPktSize::6 169837 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 124052 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163475 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6450 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 291 # What read queue length does an incoming req see +system.physmem.writePktSize::6 124302 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 162916 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 7039 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 288 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,155 +159,158 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2999 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 6966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6332 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6386 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6374 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6606 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 7201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7506 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8488 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7336 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7586 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 8729 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7393 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 326 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 153 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 129 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 106 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 143 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 132 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 80 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 29 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 25 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 61427 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 307.093102 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 182.837118 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.066728 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22431 36.52% 36.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14913 24.28% 60.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6673 10.86% 71.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3644 5.93% 77.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2598 4.23% 81.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2007 3.27% 85.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1018 1.66% 86.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1090 1.77% 88.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 7053 11.48% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 61427 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6076 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.016458 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 575.560734 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6075 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2986 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 7027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 7111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6931 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7511 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8551 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8849 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7178 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 111 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 116 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 74 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 47 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 80 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 23 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 27 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61459 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 307.217495 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 182.591879 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.526171 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22578 36.74% 36.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14767 24.03% 60.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6693 10.89% 71.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3646 5.93% 77.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2555 4.16% 81.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2031 3.30% 85.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1005 1.64% 86.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1119 1.82% 88.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7065 11.50% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61459 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6091 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.951896 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 574.936120 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6090 99.98% 99.98% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6076 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6075 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.495967 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.543257 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 14.157568 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5370 88.40% 88.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 94 1.55% 89.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 44 0.72% 90.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 49 0.81% 91.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 46 0.76% 92.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 25 0.41% 92.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 47 0.77% 93.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 10 0.16% 93.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 146 2.40% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 3 0.05% 96.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.13% 96.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 10 0.16% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 76 1.25% 97.58% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.07% 97.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 97.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 24 0.40% 98.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 88 1.45% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 8 0.13% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 8 0.13% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6075 # Writes before turning the bus around for reads -system.physmem.totQLat 1806632250 # Total ticks spent queuing -system.physmem.totMemAccLat 4998407250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 851140000 # Total ticks spent in databus transfers -system.physmem.avgQLat 10613.01 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6091 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6090 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.486535 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.508732 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 14.308920 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5400 88.67% 88.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 109 1.79% 90.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 32 0.53% 90.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 43 0.71% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 35 0.57% 92.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 14 0.23% 92.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 47 0.77% 93.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 15 0.25% 93.51% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 145 2.38% 95.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 5 0.08% 95.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.08% 96.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.23% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 63 1.03% 97.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.15% 97.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 5 0.08% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.44% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 95 1.56% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 1 0.02% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 1 0.02% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.02% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 8 0.13% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.02% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 7 0.11% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 3 0.05% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::188-191 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6090 # Writes before turning the bus around for reads +system.physmem.totQLat 1821948750 # Total ticks spent queuing +system.physmem.totMemAccLat 5014230000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 851275000 # Total ticks spent in databus transfers +system.physmem.avgQLat 10701.29 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 29363.01 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 29451.29 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.79 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 2.78 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 21.23 # Average write queue length when enqueuing -system.physmem.readRowHits 139599 # Number of row buffer hits during reads -system.physmem.writeRowHits 93721 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.01 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 75.25 # Row buffer hit rate for writes -system.physmem.avgGap 9567103.06 # Average gap between requests -system.physmem.pageHitRate 79.15 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 242282880 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 132198000 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 697530600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 415063440 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 87013655235 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638793270500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1913999599215 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.573595 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2726118833250 # Time in different power states -system.physmem_0.memoryStateTime::REF 95452760000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 25.82 # Average write queue length when enqueuing +system.physmem.readRowHits 139699 # Number of row buffer hits during reads +system.physmem.writeRowHits 93863 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.05 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 75.21 # Row buffer hit rate for writes +system.physmem.avgGap 9557755.35 # Average gap between requests +system.physmem.pageHitRate 79.16 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 240408000 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 131175000 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692764800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 412173360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 86549850225 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1639181430000 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1913911365705 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.550023 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726766742000 # Time in different power states +system.physmem_0.memoryStateTime::REF 95451720000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 36964415750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 36286757000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 222075000 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 121171875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 630240000 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 391780800 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186705598560 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 85155956550 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1640422830750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1913649653535 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.451174 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2728842952750 # Time in different power states -system.physmem_1.memoryStateTime::REF 95452760000 # Time in different power states +system.physmem_1.actEnergy 224214480 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122339250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 635216400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 396290880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186703564320 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 85109194890 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1640445162750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1913635982970 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.453685 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2728879759500 # Time in different power states +system.physmem_1.memoryStateTime::REF 95451720000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 34240173750 # Time in different power states +system.physmem_1.memoryStateTime::ACT 34173617000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 512 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 512 # Number of bytes read from this memory @@ -327,15 +330,19 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31018850 # Number of BP lookups -system.cpu.branchPred.condPredicted 16837096 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2510697 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18467994 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13332341 # Number of BTB hits +system.cpu.branchPred.lookups 30988279 # Number of BP lookups +system.cpu.branchPred.condPredicted 16810499 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2467893 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18543680 # Number of BTB lookups +system.cpu.branchPred.BTBHits 10372624 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.191603 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7836957 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1518082 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 55.936168 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7863209 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1506080 # Number of incorrect RAS predictions. +system.cpu.branchPred.indirectLookups 3044381 # Number of indirect predictor lookups. +system.cpu.branchPred.indirectHits 2857246 # Number of indirect target hits. +system.cpu.branchPred.indirectMisses 187135 # Number of indirect misses. +system.cpu.branchPredindirectMispredicted 108257 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -366,55 +373,55 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66340 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66340 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43350 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22990 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66340 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66340 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66340 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7812 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 12842.037890 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 10664.293591 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 8573.106392 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7804 99.90% 99.90% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 7 0.09% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7812 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walks 66151 # Table walker walks requested +system.cpu.dtb.walker.walksShort 66151 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43510 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22641 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 66151 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 66151 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 66151 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7866 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12681.604373 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 10478.068683 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 8425.510925 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-32767 7859 99.91% 99.91% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::131072-163839 6 0.08% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::262144-294911 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7866 # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walksPending::samples 517922000 # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::0 517922000 100.00% 100.00% # Table walker pending requests distribution system.cpu.dtb.walker.walksPending::total 517922000 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6422 82.21% 82.21% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1390 17.79% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7812 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66340 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkPageSizes::4K 6508 82.74% 82.74% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1358 17.26% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7866 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66151 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66340 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7812 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66151 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7866 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7812 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74152 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7866 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 74017 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24767530 # DTB read hits -system.cpu.dtb.read_misses 59359 # DTB read misses -system.cpu.dtb.write_hits 19448397 # DTB write hits -system.cpu.dtb.write_misses 6981 # DTB write misses +system.cpu.dtb.read_hits 24710832 # DTB read hits +system.cpu.dtb.read_misses 59358 # DTB read misses +system.cpu.dtb.write_hits 19424403 # DTB write hits +system.cpu.dtb.write_misses 6793 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4358 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1306 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1806 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4350 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 1526 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1789 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 756 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24826889 # DTB read accesses -system.cpu.dtb.write_accesses 19455378 # DTB write accesses +system.cpu.dtb.perms_faults 754 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24770190 # DTB read accesses +system.cpu.dtb.write_accesses 19431196 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44215927 # DTB hits -system.cpu.dtb.misses 66340 # DTB misses -system.cpu.dtb.accesses 44282267 # DTB accesses +system.cpu.dtb.hits 44135235 # DTB hits +system.cpu.dtb.misses 66151 # DTB misses +system.cpu.dtb.accesses 44201386 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -444,36 +451,36 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5454 # Table walker walks requested -system.cpu.itb.walker.walksShort 5454 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 321 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5133 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5454 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5454 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5454 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3187 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 13010.982115 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 10938.412651 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7360.815983 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-16383 2457 77.09% 77.09% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-32767 729 22.87% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walks 5761 # Table walker walks requested +system.cpu.itb.walker.walksShort 5761 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 327 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5434 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5761 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5761 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5761 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3206 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12829.694323 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10737.941546 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7417.860411 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-16383 2464 76.86% 76.86% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-32767 741 23.11% 99.97% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3187 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3206 # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walksPending::samples 517267500 # Table walker pending requests distribution system.cpu.itb.walker.walksPending::0 517267500 100.00% 100.00% # Table walker pending requests distribution system.cpu.itb.walker.walksPending::total 517267500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2877 90.27% 90.27% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 310 9.73% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3187 # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::4K 2896 90.33% 90.33% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 310 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3206 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5454 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5454 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5761 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5761 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3187 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3187 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8641 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57568551 # ITB inst hits -system.cpu.itb.inst_misses 5454 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3206 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3206 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8967 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57333922 # ITB inst hits +system.cpu.itb.inst_misses 5761 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -482,274 +489,309 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2975 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2992 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8464 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8365 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57574005 # ITB inst accesses -system.cpu.itb.hits 57568551 # DTB hits -system.cpu.itb.misses 5454 # DTB misses -system.cpu.itb.accesses 57574005 # DTB accesses -system.cpu.numCycles 333181944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57339683 # ITB inst accesses +system.cpu.itb.hits 57333922 # DTB hits +system.cpu.itb.misses 5761 # DTB misses +system.cpu.itb.accesses 57339683 # DTB accesses +system.cpu.numCycles 332822103 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112067614 # Number of instructions committed -system.cpu.committedOps 135500271 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7782146 # Number of ops (including micro ops) which were discarded before commit -system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5383950822 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.973044 # CPI: cycles per instruction -system.cpu.ipc 0.336356 # IPC: instructions per cycle +system.cpu.committedInsts 111897168 # Number of instructions committed +system.cpu.committedOps 135292215 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7734017 # Number of ops (including micro ops) which were discarded before commit +system.cpu.numFetchSuspends 3033 # Number of times Execute suspended instruction fetching +system.cpu.quiesceCycles 5384249089 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.974357 # CPI: cycles per instruction +system.cpu.ipc 0.336207 # IPC: instructions per cycle +system.cpu.op_class_0::No_OpClass 2337 0.00% 0.00% # Class of committed instruction +system.cpu.op_class_0::IntAlu 90691008 67.03% 67.04% # Class of committed instruction +system.cpu.op_class_0::IntMult 113025 0.08% 67.12% # Class of committed instruction +system.cpu.op_class_0::IntDiv 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatAdd 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatCmp 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatCvt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatMult 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatDiv 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::FloatSqrt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdAdd 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdAddAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdAlu 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdCmp 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdCvt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdMisc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdMult 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdMultAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdShift 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdShiftAcc 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdSqrt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAdd 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatAlu 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCmp 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatCvt 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatDiv 0 0.00% 67.12% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMisc 8533 0.01% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMult 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 67.13% # Class of committed instruction +system.cpu.op_class_0::MemRead 24225299 17.91% 85.03% # Class of committed instruction +system.cpu.op_class_0::MemWrite 20252013 14.97% 100.00% # Class of committed instruction +system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction +system.cpu.op_class_0::total 135292215 # Class of committed instruction system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228532556 # Number of cycles that the object actually ticked -system.cpu.idleCycles 104649388 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 842951 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.899807 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42615127 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 843463 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.524003 # Average number of references to valid blocks. +system.cpu.kern.inst.quiesce 3033 # number of quiesce instructions executed +system.cpu.tickCycles 228131430 # Number of cycles that the object actually ticked +system.cpu.idleCycles 104690673 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842468 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.899803 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42541757 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842980 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.465915 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 594757500 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.899807 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 511.899803 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999804 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 53 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 102 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 361 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 49 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176233418 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176233418 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23069734 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23069734 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18281775 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18281775 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 356571 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 356571 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 443857 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 443857 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460299 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460299 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41351509 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41351509 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41708080 # number of overall hits -system.cpu.dcache.overall_hits::total 41708080 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 494516 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 494516 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 548690 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 548690 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 169778 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 169778 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 22259 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 22259 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 175934547 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 175934547 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23016254 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23016254 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18262412 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18262412 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 356302 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 356302 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 443705 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 443705 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460205 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460205 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41278666 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41278666 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41634968 # number of overall hits +system.cpu.dcache.overall_hits::total 41634968 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 493842 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 493842 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 547981 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 547981 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 169870 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 169870 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 22311 # 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number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 293366000 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1041823 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1041823 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1211693 # number of overall misses +system.cpu.dcache.overall_misses::total 1211693 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8047572500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8047572500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 35605363979 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 35605363979 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 292635500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 292635500 # 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average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14010.401548 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016922 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016922 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019548 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019548 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 15678.536537 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 15678.536537 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 64252.477354 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 64252.477354 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 14091.447796 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 14091.447796 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13885.436893 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13885.436893 # average LoadLockedReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 82500 # average StoreCondReq mshr miss latency system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 82500 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35878.189726 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35878.189726 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32725.315061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 32725.315061 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201663.363315 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201663.363315 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184295.805539 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184295.805539 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193504.036516 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193504.036516 # average overall mshr uncacheable latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35925.580551 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 35925.580551 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 32760.298800 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 32760.298800 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 201679.548959 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 201679.548959 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 184357.303412 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 184357.303412 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 193541.389177 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 193541.389177 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2897049 # number of replacements -system.cpu.icache.tags.tagsinuse 511.208859 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54662046 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2897561 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.864847 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 18409362500 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.208859 # Average occupied blocks per requestor +system.cpu.icache.tags.replacements 2894371 # number of replacements +system.cpu.icache.tags.tagsinuse 511.208818 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54430342 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2894883 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.802260 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 18407091500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.208818 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.998455 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.998455 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 206 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 201 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 199 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60457191 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60457191 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54662046 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54662046 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54662046 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54662046 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 54662046 # number of overall hits -system.cpu.icache.overall_hits::total 54662046 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 2897573 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 2897573 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 2897573 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 2897573 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 2897573 # number of overall misses -system.cpu.icache.overall_misses::total 2897573 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 40485768000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 40485768000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 40485768000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 40485768000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 40485768000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 40485768000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 57559619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 57559619 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 57559619 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 57559619 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 57559619 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 57559619 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050340 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.050340 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.050340 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.050340 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.050340 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.050340 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13972.303027 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13972.303027 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13972.303027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13972.303027 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13972.303027 # average overall miss latency +system.cpu.icache.tags.tag_accesses 60220131 # Number of tag accesses +system.cpu.icache.tags.data_accesses 60220131 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 54430342 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 54430342 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 54430342 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 54430342 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 54430342 # number of overall hits +system.cpu.icache.overall_hits::total 54430342 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 2894895 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 2894895 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 2894895 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 2894895 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 2894895 # number of overall misses +system.cpu.icache.overall_misses::total 2894895 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 40452971500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 40452971500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 40452971500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 40452971500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 40452971500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 40452971500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57325237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57325237 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57325237 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57325237 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57325237 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57325237 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050499 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.050499 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.050499 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.050499 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.050499 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.050499 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13973.899399 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13973.899399 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13973.899399 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13973.899399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13973.899399 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13973.899399 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -758,218 +800,218 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 2897049 # number of writebacks -system.cpu.icache.writebacks::total 2897049 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2897573 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2897573 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2897573 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2897573 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2897573 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 2897573 # number of overall MSHR misses +system.cpu.icache.writebacks::writebacks 2894371 # number of writebacks +system.cpu.icache.writebacks::total 2894371 # number of writebacks +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2894895 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 2894895 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 2894895 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 2894895 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 2894895 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 2894895 # number of overall MSHR misses system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3763 # number of ReadReq MSHR uncacheable system.cpu.icache.ReadReq_mshr_uncacheable::total 3763 # number of ReadReq MSHR uncacheable system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3763 # number of overall MSHR uncacheable misses system.cpu.icache.overall_mshr_uncacheable_misses::total 3763 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37588196000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 37588196000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37588196000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 37588196000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37588196000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 37588196000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37558077500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37558077500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37558077500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37558077500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37558077500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37558077500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 485921500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 485921500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 485921500 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 485921500 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050340 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.050340 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050340 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.050340 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12972.303373 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12972.303373 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12972.303373 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12972.303373 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12972.303373 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12972.303373 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050499 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050499 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050499 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050499 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050499 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050499 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12973.899744 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12973.899744 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12973.899744 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12973.899744 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 129131.411108 # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 129131.411108 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96446 # 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mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001651 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982765 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982765 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 10656594000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 11083812000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.001612 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.982361 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.982361 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442303 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442303 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007916 # mshr miss rate for ReadCleanReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.025777 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.025777 # mshr miss rate for ReadSharedReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.044049 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001731 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000426 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007916 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172040 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.044049 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 129500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 131854.330709 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68005.115090 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68005.115090 # average UpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.442730 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.442730 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.007912 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026032 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026032 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172211 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.044093 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.001706 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000208 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.007912 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.172211 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.044093 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 122500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 129786.290323 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 68029.497985 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 68029.497985 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 71000 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 71000 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118120.405780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118120.405780 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120379.278022 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120379.278022 # average ReadCleanReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122132.052736 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122132.052736 # average ReadSharedReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 131892 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 129500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120379.278022 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118510.415877 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118775.376236 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 118139.858244 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 118139.858244 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 120589.285714 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 120589.285714 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 122700.989682 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 122700.989682 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 129845.528455 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 122500 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 120589.285714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 118587.469692 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 118868.308720 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189161.612592 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181005.330582 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172794.663573 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172794.663573 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189177.171678 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 181018.744089 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 172855.998260 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 172855.998260 # average WriteReq mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 113531.225086 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181472.374561 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177380.267939 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 181509.325339 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 177414.796555 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.snoop_filter.tot_requests 7513127 # Total number of requests made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_requests 3772095 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58799 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.snoop_filter.tot_snoops 590 # Total number of snoops made to the snoop filter. -system.cpu.toL2Bus.snoop_filter.hit_single_snoops 590 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_requests 7506242 # Total number of requests made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_requests 3768367 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu.toL2Bus.snoop_filter.hit_multi_requests 58373 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu.toL2Bus.snoop_filter.tot_snoops 592 # Total number of snoops made to the snoop filter. +system.cpu.toL2Bus.snoop_filter.hit_single_snoops 592 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu.toL2Bus.trans_dist::ReadReq 134810 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3579896 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackDirty 824175 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WritebackClean 2897049 # Transaction distribution -system.cpu.toL2Bus.trans_dist::CleanEvict 151656 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2785 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 134878 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3577264 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackDirty 823992 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WritebackClean 2894371 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 151399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2778 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296193 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296193 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadCleanReq 2897573 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadSharedReq 547535 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2780 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295731 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 2894895 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 547514 # Transaction distribution system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8699695 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2653154 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15282 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 161550 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 11529681 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 371094976 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98987561 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 18780 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288880 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 470390197 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 192578 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4075586 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 0.021763 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.145909 # Request fanout histogram +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 8691656 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2651684 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 16008 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160884 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 11520232 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 370751872 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98928925 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 19252 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 288368 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 469988417 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 192705 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4072528 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 0.021538 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.145168 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::0 3986889 97.82% 97.82% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 88697 2.18% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::0 3984815 97.85% 97.85% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 87713 2.15% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4075586 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 7434078000 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 4072528 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 7427836500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.3 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 380377 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 378877 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4352565871 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4348460548 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1311717177 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1310984681 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10589994 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 11196996 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89368907 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88824919 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30183 # Transaction distribution system.iobus.trans_dist::ReadResp 30183 # Transaction distribution @@ -1212,59 +1254,59 @@ system.iobus.pkt_size_system.bridge.master::total 159125 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 46502500 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 46452000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 106500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 104000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 331500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 30000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 28500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 14500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 13500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 85500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 612500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 21000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 21500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) +system.iobus.reqLayer16.occupancy 49000 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 10500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer21.occupancy 10500 # Layer occupancy (ticks) +system.iobus.reqLayer21.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6064500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6139500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33518500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34107000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187144507 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187147502 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36740000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.036750 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.037066 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 274891170000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.036750 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064797 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064797 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 274806935000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.037066 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064817 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064817 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1278,14 +1320,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 29054877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 29054877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4549676630 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4549676630 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 29054877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 29054877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 29054877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 29054877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29059377 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29059377 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4548977125 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4548977125 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29059377 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29059377 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29059377 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29059377 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -1302,14 +1344,14 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 124166.141026 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 124166.141026 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125598.405201 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 125598.405201 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 124166.141026 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 124166.141026 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 124166.141026 # average overall miss latency +system.iocache.ReadReq_avg_miss_latency::realview.ide 124185.371795 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124185.371795 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 125579.094661 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 125579.094661 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124185.371795 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124185.371795 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124185.371795 # average overall miss latency system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1328,14 +1370,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 17354877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 17354877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2737053618 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2737053618 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 17354877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 17354877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 17354877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 17354877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17359377 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17359377 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2736351620 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2736351620 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17359377 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17359377 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17359377 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17359377 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -1344,67 +1386,67 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74166.141026 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 74166.141026 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75559.121522 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75559.121522 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 74166.141026 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 74166.141026 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 74185.371795 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 74185.371795 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 75539.742160 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 75539.742160 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 74185.371795 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 74185.371795 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 34893 # Transaction distribution -system.membus.trans_dist::ReadResp 72299 # Transaction distribution -system.membus.trans_dist::WriteReq 27584 # Transaction distribution -system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::WritebackDirty 124052 # Transaction distribution -system.membus.trans_dist::CleanEvict 8818 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution +system.membus.trans_dist::ReadReq 34891 # Transaction distribution +system.membus.trans_dist::ReadResp 72400 # Transaction distribution +system.membus.trans_dist::WriteReq 27583 # Transaction distribution +system.membus.trans_dist::WriteResp 27583 # Transaction distribution +system.membus.trans_dist::WritebackDirty 124302 # Transaction distribution +system.membus.trans_dist::CleanEvict 8612 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4581 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 129140 # Transaction distribution -system.membus.trans_dist::ReadExResp 129140 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 37406 # Transaction distribution +system.membus.trans_dist::ReadExReq 129077 # Transaction distribution +system.membus.trans_dist::ReadExResp 129077 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 37509 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2074 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450778 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558346 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 450878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 558440 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72897 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72897 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 631243 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 631337 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 512 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4148 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16509088 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16672873 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16527584 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16691357 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 18989993 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 505 # Total snoops (count) -system.membus.snoop_fanout::samples 402733 # Request fanout histogram +system.membus.pkt_size::total 19008477 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 506 # Total snoops (count) +system.membus.snoop_fanout::samples 402790 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 402733 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 402790 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 402733 # Request fanout histogram -system.membus.reqLayer0.occupancy 87415500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 402790 # Request fanout histogram +system.membus.reqLayer0.occupancy 87987000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 8500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1703000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1702000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 878266116 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 879699870 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 990100000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 990225250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1264123 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1263123 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks |