stats: update and fix e273e86a873d

1 files changed, 31 insertions, 31 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index c94a5f66f..9c380c00f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.858505                       # Nu
 sim_ticks                                2858505242500                       # Number of ticks simulated
 final_tick                               2858505242500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 171882                       # Simulator instruction rate (inst/s)
-host_op_rate                                   207819                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4390877747                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 578076                       # Number of bytes of host memory used
-host_seconds                                   651.01                       # Real time elapsed on the host
+host_inst_rate                                 125507                       # Simulator instruction rate (inst/s)
+host_op_rate                                   151748                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             3206183180                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 578080                       # Number of bytes of host memory used
+host_seconds                                   891.56                       # Real time elapsed on the host
 sim_insts                                   111897168                       # Number of instructions simulated
 sim_ops                                     135292215                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -403,9 +403,9 @@ system.cpu.dtb.walker.walkRequestOrigin_Completed::total         7866
 system.cpu.dtb.walker.walkRequestOrigin::total        74017                       # Table walker requests started/completed, data/inst
 system.cpu.dtb.inst_hits                            0                       # ITB inst hits
 system.cpu.dtb.inst_misses                          0                       # ITB inst misses
-system.cpu.dtb.read_hits                     24710832                       # DTB read hits
+system.cpu.dtb.read_hits                     24710833                       # DTB read hits
 system.cpu.dtb.read_misses                      59358                       # DTB read misses
-system.cpu.dtb.write_hits                    19424403                       # DTB write hits
+system.cpu.dtb.write_hits                    19424404                       # DTB write hits
 system.cpu.dtb.write_misses                      6793                       # DTB write misses
 system.cpu.dtb.flush_tlb                           64                       # Number of times complete TLB was flushed
 system.cpu.dtb.flush_tlb_mva                      917                       # Number of times TLB was flushed by MVA
@@ -416,12 +416,12 @@ system.cpu.dtb.align_faults                      1526                       # Nu
 system.cpu.dtb.prefetch_faults                   1789                       # Number of TLB faults due to prefetch
 system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
 system.cpu.dtb.perms_faults                       754                       # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses                 24770190                       # DTB read accesses
-system.cpu.dtb.write_accesses                19431196                       # DTB write accesses
+system.cpu.dtb.read_accesses                 24770191                       # DTB read accesses
+system.cpu.dtb.write_accesses                19431197                       # DTB write accesses
 system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
-system.cpu.dtb.hits                          44135235                       # DTB hits
+system.cpu.dtb.hits                          44135237                       # DTB hits
 system.cpu.dtb.misses                           66151                       # DTB misses
-system.cpu.dtb.accesses                      44201386                       # DTB accesses
+system.cpu.dtb.accesses                      44201388                       # DTB accesses
 system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
 system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
@@ -551,9 +551,9 @@ system.cpu.tickCycles                       228131430                       # Nu
 system.cpu.idleCycles                       104690673                       # Total number of cycles that the object has spent stopped
 system.cpu.dcache.tags.replacements            842468                       # number of replacements
 system.cpu.dcache.tags.tagsinuse           511.899803                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs            42541757                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.total_refs            42541759                       # Total number of references to valid blocks.
 system.cpu.dcache.tags.sampled_refs            842980                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs             50.465915                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             50.465917                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         594757500                       # Cycle when the warmup percentage was hit.
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.899803                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999804                       # Average percentage of cache occupancy
@@ -563,22 +563,22 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::0          102
 system.cpu.dcache.tags.age_task_id_blocks_1024::1          361                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::2           49                       # Occupied blocks per task id
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses         175934547                       # Number of tag accesses
-system.cpu.dcache.tags.data_accesses        175934547                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.data     23016254                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total        23016254                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data     18262412                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total       18262412                       # number of WriteReq hits
+system.cpu.dcache.tags.tag_accesses         175934555                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        175934555                       # Number of data accesses
+system.cpu.dcache.ReadReq_hits::cpu.data     23016255                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::total        23016255                       # number of ReadReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18262413                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::total       18262413                       # number of WriteReq hits
 system.cpu.dcache.SoftPFReq_hits::cpu.data       356302                       # number of SoftPFReq hits
 system.cpu.dcache.SoftPFReq_hits::total        356302                       # number of SoftPFReq hits
 system.cpu.dcache.LoadLockedReq_hits::cpu.data       443705                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       443705                       # number of LoadLockedReq hits
 system.cpu.dcache.StoreCondReq_hits::cpu.data       460205                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       460205                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.data      41278666                       # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total         41278666                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data     41634968                       # number of overall hits
-system.cpu.dcache.overall_hits::total        41634968                       # number of overall hits
+system.cpu.dcache.demand_hits::cpu.data      41278668                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::total         41278668                       # number of demand (read+write) hits
+system.cpu.dcache.overall_hits::cpu.data     41634970                       # number of overall hits
+system.cpu.dcache.overall_hits::total        41634970                       # number of overall hits
 system.cpu.dcache.ReadReq_misses::cpu.data       493842                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        493842                       # number of ReadReq misses
 system.cpu.dcache.WriteReq_misses::cpu.data       547981                       # number of WriteReq misses
@@ -605,20 +605,20 @@ system.cpu.dcache.demand_miss_latency::cpu.data  43652936479
 system.cpu.dcache.demand_miss_latency::total  43652936479                       # number of demand (read+write) miss cycles
 system.cpu.dcache.overall_miss_latency::cpu.data  43652936479                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  43652936479                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data     23510096                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total     23510096                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data     18810393                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total     18810393                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     23510097                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::total     23510097                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18810394                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::total     18810394                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::cpu.data       526172                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.SoftPFReq_accesses::total       526172                       # number of SoftPFReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466016                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       466016                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::cpu.data       460207                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       460207                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data     42320489                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total     42320489                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data     42846661                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_accesses::total     42846661                       # number of overall (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     42320491                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::total     42320491                       # number of demand (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42846663                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::total     42846663                       # number of overall (read+write) accesses
 system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.021006                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.021006                       # miss rate for ReadReq accesses
 system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.029132                       # miss rate for WriteReq accesses