stats: changes due to recent changesets.

1 files changed, 195 insertions, 152 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
index 8068ce076..6a8c865e1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt
@@ -4,47 +4,51 @@ sim_seconds                                  2.852858                       # Nu
 sim_ticks                                2852857543000                       # Number of ticks simulated
 final_tick                               2852857543000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 169259                       # Simulator instruction rate (inst/s)
-host_op_rate                                   204656                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4303403710                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 619600                       # Number of bytes of host memory used
-host_seconds                                   662.93                       # Real time elapsed on the host
+host_inst_rate                                 109881                       # Simulator instruction rate (inst/s)
+host_op_rate                                   132861                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2793727953                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 608784                       # Number of bytes of host memory used
+host_seconds                                  1021.17                       # Real time elapsed on the host
 sim_insts                                   112207125                       # Number of instructions simulated
 sim_ops                                     135672670                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
 system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::cpu.dtb.walker         8192                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker           64                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst          10837924                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.inst           1662912                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data           9175012                       # Number of bytes read from this memory
 system.physmem.bytes_read::realview.ide           960                       # Number of bytes read from this memory
 system.physmem.bytes_read::total             10847140                       # Number of bytes read from this memory
 system.physmem.bytes_inst_read::cpu.inst      1662912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::total         1662912                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::writebacks      7962752                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu.inst          17524                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu.data          17524                       # Number of bytes written to this memory
 system.physmem.bytes_written::total           7980276                       # Number of bytes written to this memory
 system.physmem.num_reads::cpu.dtb.walker          128                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu.itb.walker            1                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst             169862                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.inst              25983                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data             143879                       # Number of read requests responded to by this memory
 system.physmem.num_reads::realview.ide             15                       # Number of read requests responded to by this memory
 system.physmem.num_reads::total                170006                       # Number of read requests responded to by this memory
 system.physmem.num_writes::writebacks          124418                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu.inst              4381                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu.data              4381                       # Number of write requests responded to by this memory
 system.physmem.num_writes::total               128799                       # Number of write requests responded to by this memory
 system.physmem.bw_read::cpu.dtb.walker           2872                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu.itb.walker             22                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst              3798971                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst               582893                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data              3216078                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::realview.ide              337                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::total                 3802202                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu.inst          582893                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::total             582893                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::writebacks           2791150                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.inst                6143                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data                6143                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total                2797292                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::writebacks           2791150                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.dtb.walker          2872                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu.itb.walker            22                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst             3805114                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst              582893                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data             3222220                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::realview.ide             337                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::total                6599494                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                        170006                       # Number of read requests accepted
@@ -534,8 +538,8 @@ system.cpu.dcache.tags.total_refs            42762284                       # To
 system.cpu.dcache.tags.sampled_refs            842495                       # Sample count of references to valid blocks.
 system.cpu.dcache.tags.avg_refs             50.756721                       # Average number of references to valid blocks.
 system.cpu.dcache.tags.warmup_cycle         281436250                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.inst   511.953279                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.inst     0.999909                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.953279                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999909                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999909                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
 system.cpu.dcache.tags.age_task_id_blocks_1024::0          100                       # Occupied blocks per task id
@@ -544,77 +548,77 @@ system.cpu.dcache.tags.age_task_id_blocks_1024::2           57
 system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
 system.cpu.dcache.tags.tag_accesses         176413277                       # Number of tag accesses
 system.cpu.dcache.tags.data_accesses        176413277                       # Number of data accesses
-system.cpu.dcache.ReadReq_hits::cpu.inst     23536274                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_hits::cpu.data     23536274                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        23536274                       # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.inst     18304900                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_hits::cpu.data     18304900                       # number of WriteReq hits
 system.cpu.dcache.WriteReq_hits::total       18304900                       # number of WriteReq hits
-system.cpu.dcache.LoadLockedReq_hits::cpu.inst       457909                       # number of LoadLockedReq hits
+system.cpu.dcache.LoadLockedReq_hits::cpu.data       457909                       # number of LoadLockedReq hits
 system.cpu.dcache.LoadLockedReq_hits::total       457909                       # number of LoadLockedReq hits
-system.cpu.dcache.StoreCondReq_hits::cpu.inst       460268                       # number of StoreCondReq hits
+system.cpu.dcache.StoreCondReq_hits::cpu.data       460268                       # number of StoreCondReq hits
 system.cpu.dcache.StoreCondReq_hits::total       460268                       # number of StoreCondReq hits
-system.cpu.dcache.demand_hits::cpu.inst      41841174                       # number of demand (read+write) hits
+system.cpu.dcache.demand_hits::cpu.data      41841174                       # number of demand (read+write) hits
 system.cpu.dcache.demand_hits::total         41841174                       # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.inst     41841174                       # number of overall hits
+system.cpu.dcache.overall_hits::cpu.data     41841174                       # number of overall hits
 system.cpu.dcache.overall_hits::total        41841174                       # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.inst       583393                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_misses::cpu.data       583393                       # number of ReadReq misses
 system.cpu.dcache.ReadReq_misses::total        583393                       # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.inst       541748                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_misses::cpu.data       541748                       # number of WriteReq misses
 system.cpu.dcache.WriteReq_misses::total       541748                       # number of WriteReq misses
-system.cpu.dcache.LoadLockedReq_misses::cpu.inst         8195                       # number of LoadLockedReq misses
+system.cpu.dcache.LoadLockedReq_misses::cpu.data         8195                       # number of LoadLockedReq misses
 system.cpu.dcache.LoadLockedReq_misses::total         8195                       # number of LoadLockedReq misses
-system.cpu.dcache.StoreCondReq_misses::cpu.inst            2                       # number of StoreCondReq misses
+system.cpu.dcache.StoreCondReq_misses::cpu.data            2                       # number of StoreCondReq misses
 system.cpu.dcache.StoreCondReq_misses::total            2                       # number of StoreCondReq misses
-system.cpu.dcache.demand_misses::cpu.inst      1125141                       # number of demand (read+write) misses
+system.cpu.dcache.demand_misses::cpu.data      1125141                       # number of demand (read+write) misses
 system.cpu.dcache.demand_misses::total        1125141                       # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.inst      1125141                       # number of overall misses
+system.cpu.dcache.overall_misses::cpu.data      1125141                       # number of overall misses
 system.cpu.dcache.overall_misses::total       1125141                       # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.inst   8651014339                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_latency::cpu.data   8651014339                       # number of ReadReq miss cycles
 system.cpu.dcache.ReadReq_miss_latency::total   8651014339                       # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.inst  21393186307                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_latency::cpu.data  21393186307                       # number of WriteReq miss cycles
 system.cpu.dcache.WriteReq_miss_latency::total  21393186307                       # number of WriteReq miss cycles
-system.cpu.dcache.LoadLockedReq_miss_latency::cpu.inst    116036500                       # number of LoadLockedReq miss cycles
+system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data    116036500                       # number of LoadLockedReq miss cycles
 system.cpu.dcache.LoadLockedReq_miss_latency::total    116036500                       # number of LoadLockedReq miss cycles
-system.cpu.dcache.StoreCondReq_miss_latency::cpu.inst       150500                       # number of StoreCondReq miss cycles
+system.cpu.dcache.StoreCondReq_miss_latency::cpu.data       150500                       # number of StoreCondReq miss cycles
 system.cpu.dcache.StoreCondReq_miss_latency::total       150500                       # number of StoreCondReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.inst  30044200646                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_latency::cpu.data  30044200646                       # number of demand (read+write) miss cycles
 system.cpu.dcache.demand_miss_latency::total  30044200646                       # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.inst  30044200646                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_latency::cpu.data  30044200646                       # number of overall miss cycles
 system.cpu.dcache.overall_miss_latency::total  30044200646                       # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.inst     24119667                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_accesses::cpu.data     24119667                       # number of ReadReq accesses(hits+misses)
 system.cpu.dcache.ReadReq_accesses::total     24119667                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.inst     18846648                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_accesses::cpu.data     18846648                       # number of WriteReq accesses(hits+misses)
 system.cpu.dcache.WriteReq_accesses::total     18846648                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.LoadLockedReq_accesses::cpu.inst       466104                       # number of LoadLockedReq accesses(hits+misses)
+system.cpu.dcache.LoadLockedReq_accesses::cpu.data       466104                       # number of LoadLockedReq accesses(hits+misses)
 system.cpu.dcache.LoadLockedReq_accesses::total       466104                       # number of LoadLockedReq accesses(hits+misses)
-system.cpu.dcache.StoreCondReq_accesses::cpu.inst       460270                       # number of StoreCondReq accesses(hits+misses)
+system.cpu.dcache.StoreCondReq_accesses::cpu.data       460270                       # number of StoreCondReq accesses(hits+misses)
 system.cpu.dcache.StoreCondReq_accesses::total       460270                       # number of StoreCondReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.inst     42966315                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_accesses::cpu.data     42966315                       # number of demand (read+write) accesses
 system.cpu.dcache.demand_accesses::total     42966315                       # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.inst     42966315                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_accesses::cpu.data     42966315                       # number of overall (read+write) accesses
 system.cpu.dcache.overall_accesses::total     42966315                       # number of overall (read+write) accesses
-system.cpu.dcache.ReadReq_miss_rate::cpu.inst     0.024187                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.024187                       # miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_miss_rate::total     0.024187                       # miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_miss_rate::cpu.inst     0.028745                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.028745                       # miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_miss_rate::total     0.028745                       # miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_miss_rate::cpu.inst     0.017582                       # miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.017582                       # miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_miss_rate::total     0.017582                       # miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_miss_rate::cpu.inst     0.000004                       # miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_miss_rate::cpu.data     0.000004                       # miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_miss_rate::total     0.000004                       # miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_miss_rate::cpu.inst     0.026187                       # miss rate for demand accesses
+system.cpu.dcache.demand_miss_rate::cpu.data     0.026187                       # miss rate for demand accesses
 system.cpu.dcache.demand_miss_rate::total     0.026187                       # miss rate for demand accesses
-system.cpu.dcache.overall_miss_rate::cpu.inst     0.026187                       # miss rate for overall accesses
+system.cpu.dcache.overall_miss_rate::cpu.data     0.026187                       # miss rate for overall accesses
 system.cpu.dcache.overall_miss_rate::total     0.026187                       # miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_miss_latency::cpu.inst 14828.793522                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522                       # average ReadReq miss latency
 system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522                       # average ReadReq miss latency
-system.cpu.dcache.WriteReq_avg_miss_latency::cpu.inst 39489.183729                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729                       # average WriteReq miss latency
 system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729                       # average WriteReq miss latency
-system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.inst 14159.426480                       # average LoadLockedReq miss latency
+system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480                       # average LoadLockedReq miss latency
 system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480                       # average LoadLockedReq miss latency
-system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.inst        75250                       # average StoreCondReq miss latency
+system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data        75250                       # average StoreCondReq miss latency
 system.cpu.dcache.StoreCondReq_avg_miss_latency::total        75250                       # average StoreCondReq miss latency
-system.cpu.dcache.demand_avg_miss_latency::cpu.inst 26702.609403                       # average overall miss latency
+system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403                       # average overall miss latency
 system.cpu.dcache.demand_avg_miss_latency::total 26702.609403                       # average overall miss latency
-system.cpu.dcache.overall_avg_miss_latency::cpu.inst 26702.609403                       # average overall miss latency
+system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403                       # average overall miss latency
 system.cpu.dcache.overall_avg_miss_latency::total 26702.609403                       # average overall miss latency
 system.cpu.dcache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.dcache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -626,73 +630,73 @@ system.cpu.dcache.fast_writes                       0                       # nu
 system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
 system.cpu.dcache.writebacks::writebacks       698310                       # number of writebacks
 system.cpu.dcache.writebacks::total            698310                       # number of writebacks
-system.cpu.dcache.ReadReq_mshr_hits::cpu.inst        45149                       # number of ReadReq MSHR hits
+system.cpu.dcache.ReadReq_mshr_hits::cpu.data        45149                       # number of ReadReq MSHR hits
 system.cpu.dcache.ReadReq_mshr_hits::total        45149                       # number of ReadReq MSHR hits
-system.cpu.dcache.WriteReq_mshr_hits::cpu.inst       242834                       # number of WriteReq MSHR hits
+system.cpu.dcache.WriteReq_mshr_hits::cpu.data       242834                       # number of WriteReq MSHR hits
 system.cpu.dcache.WriteReq_mshr_hits::total       242834                       # number of WriteReq MSHR hits
-system.cpu.dcache.demand_mshr_hits::cpu.inst       287983                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data       287983                       # number of demand (read+write) MSHR hits
 system.cpu.dcache.demand_mshr_hits::total       287983                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.overall_mshr_hits::cpu.inst       287983                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data       287983                       # number of overall MSHR hits
 system.cpu.dcache.overall_mshr_hits::total       287983                       # number of overall MSHR hits
-system.cpu.dcache.ReadReq_mshr_misses::cpu.inst       538244                       # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data       538244                       # number of ReadReq MSHR misses
 system.cpu.dcache.ReadReq_mshr_misses::total       538244                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_mshr_misses::cpu.inst       298914                       # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data       298914                       # number of WriteReq MSHR misses
 system.cpu.dcache.WriteReq_mshr_misses::total       298914                       # number of WriteReq MSHR misses
-system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.inst         8195                       # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data         8195                       # number of LoadLockedReq MSHR misses
 system.cpu.dcache.LoadLockedReq_mshr_misses::total         8195                       # number of LoadLockedReq MSHR misses
-system.cpu.dcache.StoreCondReq_mshr_misses::cpu.inst            2                       # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data            2                       # number of StoreCondReq MSHR misses
 system.cpu.dcache.StoreCondReq_mshr_misses::total            2                       # number of StoreCondReq MSHR misses
-system.cpu.dcache.demand_mshr_misses::cpu.inst       837158                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data       837158                       # number of demand (read+write) MSHR misses
 system.cpu.dcache.demand_mshr_misses::total       837158                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.overall_mshr_misses::cpu.inst       837158                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data       837158                       # number of overall MSHR misses
 system.cpu.dcache.overall_mshr_misses::total       837158                       # number of overall MSHR misses
-system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.inst   6893184142                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data   6893184142                       # number of ReadReq MSHR miss cycles
 system.cpu.dcache.ReadReq_mshr_miss_latency::total   6893184142                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.inst  11166823654                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data  11166823654                       # number of WriteReq MSHR miss cycles
 system.cpu.dcache.WriteReq_mshr_miss_latency::total  11166823654                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.inst     99620500                       # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data     99620500                       # number of LoadLockedReq MSHR miss cycles
 system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total     99620500                       # number of LoadLockedReq MSHR miss cycles
-system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.inst       146500                       # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data       146500                       # number of StoreCondReq MSHR miss cycles
 system.cpu.dcache.StoreCondReq_mshr_miss_latency::total       146500                       # number of StoreCondReq MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_latency::cpu.inst  18060007796                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data  18060007796                       # number of demand (read+write) MSHR miss cycles
 system.cpu.dcache.demand_mshr_miss_latency::total  18060007796                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_latency::cpu.inst  18060007796                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data  18060007796                       # number of overall MSHR miss cycles
 system.cpu.dcache.overall_mshr_miss_latency::total  18060007796                       # number of overall MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.inst   5790998000                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data   5790998000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total   5790998000                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.inst   4439562500                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data   4439562500                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total   4439562500                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.inst  10230560500                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data  10230560500                       # number of overall MSHR uncacheable cycles
 system.cpu.dcache.overall_mshr_uncacheable_latency::total  10230560500                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.inst     0.022316                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.022316                       # mshr miss rate for ReadReq accesses
 system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.022316                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.inst     0.015860                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.015860                       # mshr miss rate for WriteReq accesses
 system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.015860                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.inst     0.017582                       # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data     0.017582                       # mshr miss rate for LoadLockedReq accesses
 system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total     0.017582                       # mshr miss rate for LoadLockedReq accesses
-system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.inst     0.000004                       # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data     0.000004                       # mshr miss rate for StoreCondReq accesses
 system.cpu.dcache.StoreCondReq_mshr_miss_rate::total     0.000004                       # mshr miss rate for StoreCondReq accesses
-system.cpu.dcache.demand_mshr_miss_rate::cpu.inst     0.019484                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.019484                       # mshr miss rate for demand accesses
 system.cpu.dcache.demand_mshr_miss_rate::total     0.019484                       # mshr miss rate for demand accesses
-system.cpu.dcache.overall_mshr_miss_rate::cpu.inst     0.019484                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.019484                       # mshr miss rate for overall accesses
 system.cpu.dcache.overall_mshr_miss_rate::total     0.019484                       # mshr miss rate for overall accesses
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.inst 12806.801640                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640                       # average ReadReq mshr miss latency
 system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640                       # average ReadReq mshr miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.inst 37357.981406                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406                       # average WriteReq mshr miss latency
 system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406                       # average WriteReq mshr miss latency
-system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.inst 12156.253813                       # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12156.253813                       # average LoadLockedReq mshr miss latency
 system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813                       # average LoadLockedReq mshr miss latency
-system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.inst        73250                       # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data        73250                       # average StoreCondReq mshr miss latency
 system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total        73250                       # average StoreCondReq mshr miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.inst 21572.997924                       # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21572.997924                       # average overall mshr miss latency
 system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.inst 21572.997924                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924                       # average overall mshr miss latency
 system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924                       # average overall mshr miss latency
-system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
 system.cpu.icache.tags.replacements           2900110                       # number of replacements
@@ -797,11 +801,13 @@ system.cpu.l2cache.tags.warmup_cycle                0                       # Cy
 system.cpu.l2cache.tags.occ_blocks::writebacks 47498.508165                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker    71.489031                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.000365                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst 17501.014446                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst 12194.784847                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  5306.229599                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.724770                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.001091                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::cpu.inst     0.267044                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.inst     0.186078                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::cpu.data     0.080967                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.992905                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_task_id_blocks::1023           37                       # Occupied blocks per task id
 system.cpu.l2cache.tags.occ_task_id_blocks::1024        65211                       # Occupied blocks per task id
@@ -817,113 +823,131 @@ system.cpu.l2cache.tags.tag_accesses         36621683                       # Nu
 system.cpu.l2cache.tags.data_accesses        36621683                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        71038                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         4429                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_hits::cpu.inst      3409631                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.inst      2877594                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_hits::cpu.data       532037                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        3485098                       # number of ReadReq hits
 system.cpu.l2cache.Writeback_hits::writebacks       698310                       # number of Writeback hits
 system.cpu.l2cache.Writeback_hits::total       698310                       # number of Writeback hits
-system.cpu.l2cache.UpgradeReq_hits::cpu.inst           53                       # number of UpgradeReq hits
+system.cpu.l2cache.UpgradeReq_hits::cpu.data           53                       # number of UpgradeReq hits
 system.cpu.l2cache.UpgradeReq_hits::total           53                       # number of UpgradeReq hits
-system.cpu.l2cache.ReadExReq_hits::cpu.inst       164919                       # number of ReadExReq hits
+system.cpu.l2cache.ReadExReq_hits::cpu.data       164919                       # number of ReadExReq hits
 system.cpu.l2cache.ReadExReq_hits::total       164919                       # number of ReadExReq hits
 system.cpu.l2cache.demand_hits::cpu.dtb.walker        71038                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::cpu.itb.walker         4429                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_hits::cpu.inst      3574550                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.inst      2877594                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_hits::cpu.data       696956                       # number of demand (read+write) hits
 system.cpu.l2cache.demand_hits::total         3650017                       # number of demand (read+write) hits
 system.cpu.l2cache.overall_hits::cpu.dtb.walker        71038                       # number of overall hits
 system.cpu.l2cache.overall_hits::cpu.itb.walker         4429                       # number of overall hits
-system.cpu.l2cache.overall_hits::cpu.inst      3574550                       # number of overall hits
+system.cpu.l2cache.overall_hits::cpu.inst      2877594                       # number of overall hits
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 system.cpu.l2cache.overall_hits::total        3650017                       # number of overall hits
 system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker          128                       # number of ReadReq misses
 system.cpu.l2cache.ReadReq_misses::cpu.itb.walker            1                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_misses::cpu.inst        37410                       # number of ReadReq misses
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 system.cpu.l2cache.ReadReq_misses::total        37539                       # number of ReadReq misses
-system.cpu.l2cache.UpgradeReq_misses::cpu.inst         2779                       # number of UpgradeReq misses
+system.cpu.l2cache.UpgradeReq_misses::cpu.data         2779                       # number of UpgradeReq misses
 system.cpu.l2cache.UpgradeReq_misses::total         2779                       # number of UpgradeReq misses
-system.cpu.l2cache.SCUpgradeReq_misses::cpu.inst            2                       # number of SCUpgradeReq misses
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 system.cpu.l2cache.SCUpgradeReq_misses::total            2                       # number of SCUpgradeReq misses
-system.cpu.l2cache.ReadExReq_misses::cpu.inst       131168                       # number of ReadExReq misses
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 system.cpu.l2cache.ReadExReq_misses::total       131168                       # number of ReadExReq misses
 system.cpu.l2cache.demand_misses::cpu.dtb.walker          128                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::cpu.itb.walker            1                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_misses::cpu.inst       168578                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.inst        23013                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_misses::cpu.data       145565                       # number of demand (read+write) misses
 system.cpu.l2cache.demand_misses::total        168707                       # number of demand (read+write) misses
 system.cpu.l2cache.overall_misses::cpu.dtb.walker          128                       # number of overall misses
 system.cpu.l2cache.overall_misses::cpu.itb.walker            1                       # number of overall misses
-system.cpu.l2cache.overall_misses::cpu.inst       168578                       # number of overall misses
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 system.cpu.l2cache.overall_misses::total       168707                       # number of overall misses
 system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker     10214250                       # number of ReadReq miss cycles
 system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker        74500                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   2773098000                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_latency::cpu.inst   1672158250                       # number of ReadReq miss cycles
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 system.cpu.l2cache.ReadReq_miss_latency::total   2783386750                       # number of ReadReq miss cycles
-system.cpu.l2cache.UpgradeReq_miss_latency::cpu.inst       790966                       # number of UpgradeReq miss cycles
+system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data       790966                       # number of UpgradeReq miss cycles
 system.cpu.l2cache.UpgradeReq_miss_latency::total       790966                       # number of UpgradeReq miss cycles
-system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.inst       144500                       # number of SCUpgradeReq miss cycles
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 system.cpu.l2cache.SCUpgradeReq_miss_latency::total       144500                       # number of SCUpgradeReq miss cycles
-system.cpu.l2cache.ReadExReq_miss_latency::cpu.inst   9154216683                       # number of ReadExReq miss cycles
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 system.cpu.l2cache.ReadExReq_miss_latency::total   9154216683                       # number of ReadExReq miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker     10214250                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.demand_miss_latency::cpu.itb.walker        74500                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_latency::cpu.inst  11927314683                       # number of demand (read+write) miss cycles
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 system.cpu.l2cache.demand_miss_latency::total  11937603433                       # number of demand (read+write) miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker     10214250                       # number of overall miss cycles
 system.cpu.l2cache.overall_miss_latency::cpu.itb.walker        74500                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_latency::cpu.inst  11927314683                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_latency::cpu.inst   1672158250                       # number of overall miss cycles
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 system.cpu.l2cache.overall_miss_latency::total  11937603433                       # number of overall miss cycles
 system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker        71166                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker         4430                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_accesses::cpu.inst      3447041                       # number of ReadReq accesses(hits+misses)
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 system.cpu.l2cache.ReadReq_accesses::total      3522637                       # number of ReadReq accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::writebacks       698310                       # number of Writeback accesses(hits+misses)
 system.cpu.l2cache.Writeback_accesses::total       698310                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.UpgradeReq_accesses::cpu.inst         2832                       # number of UpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.UpgradeReq_accesses::total         2832                       # number of UpgradeReq accesses(hits+misses)
-system.cpu.l2cache.SCUpgradeReq_accesses::cpu.inst            2                       # number of SCUpgradeReq accesses(hits+misses)
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 system.cpu.l2cache.SCUpgradeReq_accesses::total            2                       # number of SCUpgradeReq accesses(hits+misses)
-system.cpu.l2cache.ReadExReq_accesses::cpu.inst       296087                       # number of ReadExReq accesses(hits+misses)
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 system.cpu.l2cache.ReadExReq_accesses::total       296087                       # number of ReadExReq accesses(hits+misses)
 system.cpu.l2cache.demand_accesses::cpu.dtb.walker        71166                       # number of demand (read+write) accesses
 system.cpu.l2cache.demand_accesses::cpu.itb.walker         4430                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_accesses::cpu.inst      3743128                       # number of demand (read+write) accesses
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 system.cpu.l2cache.demand_accesses::total      3818724                       # number of demand (read+write) accesses
 system.cpu.l2cache.overall_accesses::cpu.dtb.walker        71166                       # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_accesses::cpu.inst      3743128                       # number of overall (read+write) accesses
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 system.cpu.l2cache.overall_accesses::total      3818724                       # number of overall (read+write) accesses
 system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker     0.001799                       # miss rate for ReadReq accesses
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-system.cpu.l2cache.ReadReq_miss_rate::cpu.inst     0.010853                       # miss rate for ReadReq accesses
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 system.cpu.l2cache.ReadReq_miss_rate::total     0.010657                       # miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_miss_rate::cpu.inst     0.981285                       # miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data     0.981285                       # miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_miss_rate::total     0.981285                       # miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.inst            1                       # miss rate for SCUpgradeReq accesses
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 system.cpu.l2cache.SCUpgradeReq_miss_rate::total            1                       # miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_miss_rate::cpu.inst     0.443005                       # miss rate for ReadExReq accesses
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 system.cpu.l2cache.ReadExReq_miss_rate::total     0.443005                       # miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker     0.001799                       # miss rate for demand accesses
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-system.cpu.l2cache.demand_miss_rate::cpu.inst     0.045037                       # miss rate for demand accesses
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-system.cpu.l2cache.overall_miss_rate::cpu.inst     0.045037                       # miss rate for overall accesses
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+system.cpu.l2cache.overall_miss_rate::cpu.data     0.172773                       # miss rate for overall accesses
 system.cpu.l2cache.overall_miss_rate::total     0.044179                       # miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 79798.828125                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker        74500                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74127.185245                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 72661.463086                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76470.080572                       # average ReadReq miss latency
 system.cpu.l2cache.ReadReq_avg_miss_latency::total 74146.534271                       # average ReadReq miss latency
-system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.inst   284.622526                       # average UpgradeReq miss latency
+system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data   284.622526                       # average UpgradeReq miss latency
 system.cpu.l2cache.UpgradeReq_avg_miss_latency::total   284.622526                       # average UpgradeReq miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.inst        72250                       # average SCUpgradeReq miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data        72250                       # average SCUpgradeReq miss latency
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-system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.inst 69790.014966                       # average ReadExReq miss latency
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 system.cpu.l2cache.ReadExReq_avg_miss_latency::total 69790.014966                       # average ReadExReq miss latency
 system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 79798.828125                       # average overall miss latency
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-system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70752.498446                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 72661.463086                       # average overall miss latency
+system.cpu.l2cache.demand_avg_miss_latency::cpu.data 70450.701975                       # average overall miss latency
 system.cpu.l2cache.demand_avg_miss_latency::total 70759.384216                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 79798.828125                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker        74500                       # average overall miss latency
-system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70752.498446                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 72661.463086                       # average overall miss latency
+system.cpu.l2cache.overall_avg_miss_latency::cpu.data 70450.701975                       # average overall miss latency
 system.cpu.l2cache.overall_avg_miss_latency::total 70759.384216                       # average overall miss latency
 system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
 system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
@@ -935,95 +959,114 @@ system.cpu.l2cache.fast_writes                      0                       # nu
 system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
 system.cpu.l2cache.writebacks::writebacks        88228                       # number of writebacks
 system.cpu.l2cache.writebacks::total            88228                       # number of writebacks
-system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst          162                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst           20                       # number of ReadReq MSHR hits
+system.cpu.l2cache.ReadReq_mshr_hits::cpu.data          142                       # number of ReadReq MSHR hits
 system.cpu.l2cache.ReadReq_mshr_hits::total          162                       # number of ReadReq MSHR hits
-system.cpu.l2cache.demand_mshr_hits::cpu.inst          162                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.inst           20                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_hits::cpu.data          142                       # number of demand (read+write) MSHR hits
 system.cpu.l2cache.demand_mshr_hits::total          162                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.overall_mshr_hits::cpu.inst          162                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.inst           20                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_hits::cpu.data          142                       # number of overall MSHR hits
 system.cpu.l2cache.overall_mshr_hits::total          162                       # number of overall MSHR hits
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker          128                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker            1                       # number of ReadReq MSHR misses
-system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        37248                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst        22993                       # number of ReadReq MSHR misses
+system.cpu.l2cache.ReadReq_mshr_misses::cpu.data        14255                       # number of ReadReq MSHR misses
 system.cpu.l2cache.ReadReq_mshr_misses::total        37377                       # number of ReadReq MSHR misses
-system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.inst         2779                       # number of UpgradeReq MSHR misses
+system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data         2779                       # number of UpgradeReq MSHR misses
 system.cpu.l2cache.UpgradeReq_mshr_misses::total         2779                       # number of UpgradeReq MSHR misses
-system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.inst            2                       # number of SCUpgradeReq MSHR misses
+system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data            2                       # number of SCUpgradeReq MSHR misses
 system.cpu.l2cache.SCUpgradeReq_mshr_misses::total            2                       # number of SCUpgradeReq MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_misses::cpu.inst       131168                       # number of ReadExReq MSHR misses
+system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data       131168                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.ReadExReq_mshr_misses::total       131168                       # number of ReadExReq MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker          128                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker            1                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.demand_mshr_misses::cpu.inst       168416                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.inst        22993                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.demand_mshr_misses::cpu.data       145423                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.demand_mshr_misses::total       168545                       # number of demand (read+write) MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker          128                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker            1                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::cpu.inst       168416                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.inst        22993                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_misses::cpu.data       145423                       # number of overall MSHR misses
 system.cpu.l2cache.overall_mshr_misses::total       168545                       # number of overall MSHR misses
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker      8641250                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker        62500                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   2295827000                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst   1382505500                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data    913321500                       # number of ReadReq MSHR miss cycles
 system.cpu.l2cache.ReadReq_mshr_miss_latency::total   2304530750                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.inst     27979779                       # number of UpgradeReq MSHR miss cycles
+system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data     27979779                       # number of UpgradeReq MSHR miss cycles
 system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total     27979779                       # number of UpgradeReq MSHR miss cycles
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.inst       120500                       # number of SCUpgradeReq MSHR miss cycles
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data       120500                       # number of SCUpgradeReq MSHR miss cycles
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total       120500                       # number of SCUpgradeReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.inst   7500556317                       # number of ReadExReq MSHR miss cycles
+system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data   7500556317                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.ReadExReq_mshr_miss_latency::total   7500556317                       # number of ReadExReq MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker      8641250                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker        62500                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   9796383317                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst   1382505500                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_latency::cpu.data   8413877817                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.demand_mshr_miss_latency::total   9805087067                       # number of demand (read+write) MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker      8641250                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker        62500                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   9796383317                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst   1382505500                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_latency::cpu.data   8413877817                       # number of overall MSHR miss cycles
 system.cpu.l2cache.overall_mshr_miss_latency::total   9805087067                       # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst   5545301250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst    159586250                       # number of ReadReq MSHR uncacheable cycles
+system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data   5385715000                       # number of ReadReq MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total   5545301250                       # number of ReadReq MSHR uncacheable cycles
-system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.inst   4107025000                       # number of WriteReq MSHR uncacheable cycles
+system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data   4107025000                       # number of WriteReq MSHR uncacheable cycles
 system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total   4107025000                       # number of WriteReq MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst   9652326250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst    159586250                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data   9492740000                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.overall_mshr_uncacheable_latency::total   9652326250                       # number of overall MSHR uncacheable cycles
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker     0.001799                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker     0.000226                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.010806                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst     0.007927                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data     0.026087                       # mshr miss rate for ReadReq accesses
 system.cpu.l2cache.ReadReq_mshr_miss_rate::total     0.010611                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.inst     0.981285                       # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data     0.981285                       # mshr miss rate for UpgradeReq accesses
 system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total     0.981285                       # mshr miss rate for UpgradeReq accesses
-system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.inst            1                       # mshr miss rate for SCUpgradeReq accesses
+system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data            1                       # mshr miss rate for SCUpgradeReq accesses
 system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total            1                       # mshr miss rate for SCUpgradeReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.inst     0.443005                       # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.443005                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.443005                       # mshr miss rate for ReadExReq accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker     0.001799                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker     0.000226                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.044993                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.007927                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.172605                       # mshr miss rate for demand accesses
 system.cpu.l2cache.demand_mshr_miss_rate::total     0.044136                       # mshr miss rate for demand accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker     0.001799                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker     0.000226                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.044993                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.007927                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.172605                       # mshr miss rate for overall accesses
 system.cpu.l2cache.overall_mshr_miss_rate::total     0.044136                       # mshr miss rate for overall accesses
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61636.248926                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60127.234376                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64070.256051                       # average ReadReq mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61656.386280                       # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.inst 10068.290392                       # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10068.290392                       # average UpgradeReq mshr miss latency
 system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10068.290392                       # average UpgradeReq mshr miss latency
-system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.inst        60250                       # average SCUpgradeReq mshr miss latency
+system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data        60250                       # average SCUpgradeReq mshr miss latency
 system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total        60250                       # average SCUpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.inst 57182.821397                       # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397                       # average ReadExReq mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58167.770978                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376                       # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937                       # average overall mshr miss latency
 system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker        62500                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58167.770978                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937                       # average overall mshr miss latency
 system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376                       # average overall mshr miss latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average ReadReq mshr uncacheable latency
+system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average ReadReq mshr uncacheable latency
 system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total          inf                       # average ReadReq mshr uncacheable latency
-system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average WriteReq mshr uncacheable latency
+system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total          inf                       # average WriteReq mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst          inf                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
 system.cpu.toL2Bus.trans_dist::ReadReq        3581727                       # Transaction distribution