diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor | |
parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt | 1832 |
1 files changed, 908 insertions, 924 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt index 6a8c865e1..6dd28da03 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-minor/stats.txt @@ -1,120 +1,120 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.852858 # Number of seconds simulated -sim_ticks 2852857543000 # Number of ticks simulated -final_tick 2852857543000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.853442 # Number of seconds simulated +sim_ticks 2853442108500 # Number of ticks simulated +final_tick 2853442108500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 109881 # Simulator instruction rate (inst/s) -host_op_rate 132861 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2793727953 # Simulator tick rate (ticks/s) -host_mem_usage 608784 # Number of bytes of host memory used -host_seconds 1021.17 # Real time elapsed on the host -sim_insts 112207125 # Number of instructions simulated -sim_ops 135672670 # Number of ops (including micro ops) simulated +host_inst_rate 171765 # Simulator instruction rate (inst/s) +host_op_rate 207684 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4374009836 # Simulator tick rate (ticks/s) +host_mem_usage 619996 # Number of bytes of host memory used +host_seconds 652.36 # Real time elapsed on the host +sim_insts 112053421 # Number of instructions simulated +sim_ops 135485276 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 8192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 7296 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1662912 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9175012 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1671680 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9169380 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10847140 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1662912 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1662912 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 7962752 # Number of bytes written to this memory +system.physmem.bytes_read::total 10849380 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1671680 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1671680 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 7972992 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 7980276 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 128 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 7990516 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 114 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 25983 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 143879 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 26120 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 143791 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 170006 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 124418 # Number of write requests responded to by this memory +system.physmem.num_reads::total 170041 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 124578 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 128799 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 2872 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 128959 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 2557 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 22 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 582893 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3216078 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3802202 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 582893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 582893 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2791150 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6143 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2797292 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2791150 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 2872 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 585847 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3213445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 336 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3802208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 585847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 585847 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2794166 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6141 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2800308 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2794166 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 2557 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 22 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 582893 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3222220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 337 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6599494 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 170006 # Number of read requests accepted -system.physmem.writeReqs 165023 # Number of write requests accepted -system.physmem.readBursts 170006 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 165023 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10873728 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 6656 # Total number of bytes read from write queue -system.physmem.bytesWritten 10175104 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10847140 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10298612 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 104 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 6006 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4596 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 10656 # Per bank write bursts -system.physmem.perBankRdBursts::1 10651 # Per bank write bursts -system.physmem.perBankRdBursts::2 10704 # Per bank write bursts -system.physmem.perBankRdBursts::3 10614 # Per bank write bursts -system.physmem.perBankRdBursts::4 13356 # Per bank write bursts -system.physmem.perBankRdBursts::5 10666 # Per bank write bursts -system.physmem.perBankRdBursts::6 11042 # Per bank write bursts -system.physmem.perBankRdBursts::7 10972 # Per bank write bursts -system.physmem.perBankRdBursts::8 10208 # Per bank write bursts -system.physmem.perBankRdBursts::9 10672 # Per bank write bursts -system.physmem.perBankRdBursts::10 10509 # Per bank write bursts -system.physmem.perBankRdBursts::11 9657 # Per bank write bursts -system.physmem.perBankRdBursts::12 10109 # Per bank write bursts -system.physmem.perBankRdBursts::13 10747 # Per bank write bursts -system.physmem.perBankRdBursts::14 9757 # Per bank write bursts -system.physmem.perBankRdBursts::15 9582 # Per bank write bursts -system.physmem.perBankWrBursts::0 10072 # Per bank write bursts -system.physmem.perBankWrBursts::1 10092 # Per bank write bursts -system.physmem.perBankWrBursts::2 10491 # Per bank write bursts -system.physmem.perBankWrBursts::3 10304 # Per bank write bursts -system.physmem.perBankWrBursts::4 9538 # Per bank write bursts -system.physmem.perBankWrBursts::5 9899 # Per bank write bursts -system.physmem.perBankWrBursts::6 10133 # Per bank write bursts -system.physmem.perBankWrBursts::7 10134 # Per bank write bursts -system.physmem.perBankWrBursts::8 10091 # Per bank write bursts -system.physmem.perBankWrBursts::9 10380 # Per bank write bursts -system.physmem.perBankWrBursts::10 10169 # Per bank write bursts -system.physmem.perBankWrBursts::11 9697 # Per bank write bursts -system.physmem.perBankWrBursts::12 9799 # Per bank write bursts -system.physmem.perBankWrBursts::13 10201 # Per bank write bursts -system.physmem.perBankWrBursts::14 9040 # Per bank write bursts -system.physmem.perBankWrBursts::15 8946 # Per bank write bursts +system.physmem.bw_total::cpu.inst 585847 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3219587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 336 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 6602516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 170041 # Number of read requests accepted +system.physmem.writeReqs 165183 # Number of write requests accepted +system.physmem.readBursts 170041 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 165183 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 10875008 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 7616 # Total number of bytes read from write queue +system.physmem.bytesWritten 9072064 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 10849380 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10308852 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 119 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23407 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4604 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 10431 # Per bank write bursts +system.physmem.perBankRdBursts::1 10779 # Per bank write bursts +system.physmem.perBankRdBursts::2 11040 # Per bank write bursts +system.physmem.perBankRdBursts::3 10735 # Per bank write bursts +system.physmem.perBankRdBursts::4 13061 # Per bank write bursts +system.physmem.perBankRdBursts::5 10390 # Per bank write bursts +system.physmem.perBankRdBursts::6 11080 # Per bank write bursts +system.physmem.perBankRdBursts::7 11267 # Per bank write bursts +system.physmem.perBankRdBursts::8 10153 # Per bank write bursts +system.physmem.perBankRdBursts::9 10232 # Per bank write bursts +system.physmem.perBankRdBursts::10 10264 # Per bank write bursts +system.physmem.perBankRdBursts::11 9394 # Per bank write bursts +system.physmem.perBankRdBursts::12 10277 # Per bank write bursts +system.physmem.perBankRdBursts::13 10799 # Per bank write bursts +system.physmem.perBankRdBursts::14 10090 # Per bank write bursts +system.physmem.perBankRdBursts::15 9930 # Per bank write bursts +system.physmem.perBankWrBursts::0 8676 # Per bank write bursts +system.physmem.perBankWrBursts::1 9067 # Per bank write bursts +system.physmem.perBankWrBursts::2 9547 # Per bank write bursts +system.physmem.perBankWrBursts::3 9319 # Per bank write bursts +system.physmem.perBankWrBursts::4 8434 # Per bank write bursts +system.physmem.perBankWrBursts::5 8678 # Per bank write bursts +system.physmem.perBankWrBursts::6 9214 # Per bank write bursts +system.physmem.perBankWrBursts::7 9423 # Per bank write bursts +system.physmem.perBankWrBursts::8 8918 # Per bank write bursts +system.physmem.perBankWrBursts::9 8886 # Per bank write bursts +system.physmem.perBankWrBursts::10 8752 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8824 # Per bank write bursts +system.physmem.perBankWrBursts::13 8894 # Per bank write bursts +system.physmem.perBankWrBursts::14 8297 # Per bank write bursts +system.physmem.perBankWrBursts::15 8373 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2852857119000 # Total gap between requests +system.physmem.numWrRetry 40 # Number of times write queue was full causing retry +system.physmem.totGap 2853441702500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 169451 # Read request sizes (log2) +system.physmem.readPktSize::6 169486 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 160642 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 163533 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 6320 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 37 # What read queue length does an incoming req see +system.physmem.writePktSize::6 160802 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 163468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 6406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -159,177 +159,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3913 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7826 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10066 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10452 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11037 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11618 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10744 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9284 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7662 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7187 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7081 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 369 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 334 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 264 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 218 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 201 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 139 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 126 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 115 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 73 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 56 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 7 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 62962 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 334.308059 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 193.690406 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 348.894179 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 22562 35.83% 35.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14454 22.96% 58.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6551 10.40% 69.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3518 5.59% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2542 4.04% 78.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1533 2.43% 81.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1128 1.79% 83.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1127 1.79% 84.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9547 15.16% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 62962 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6648 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.554603 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 562.154464 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6646 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6648 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6648 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.914862 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.938842 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.611148 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5537 83.29% 83.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 45 0.68% 83.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 19 0.29% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 242 3.64% 87.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 123 1.85% 89.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 53 0.80% 90.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 26 0.39% 90.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 33 0.50% 91.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 114 1.71% 93.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 19 0.29% 93.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 14 0.21% 93.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.17% 93.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 33 0.50% 94.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 20 0.30% 94.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 22 0.33% 95.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 60 0.90% 95.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 16 0.24% 96.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.11% 96.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 13 0.20% 96.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 84 1.26% 97.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 5 0.08% 97.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 9 0.14% 98.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 9 0.14% 98.13% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.23% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.05% 98.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 10 0.15% 98.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 3 0.05% 98.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 37 0.56% 99.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.28% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 4 0.06% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 9 0.14% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.08% 99.55% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 4 0.06% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.06% 99.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 5 0.08% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 1 0.02% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.02% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 2 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.02% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-195 1 0.02% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::196-199 1 0.02% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 4 0.06% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6648 # Writes before turning the bus around for reads -system.physmem.totQLat 1659710000 # Total ticks spent queuing -system.physmem.totMemAccLat 4845372500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 849510000 # Total ticks spent in databus transfers -system.physmem.avgQLat 9768.63 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1516 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1813 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6027 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6324 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 7720 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6542 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 6696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 7845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 6904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8673 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7583 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 6877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6843 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1218 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 1028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2241 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 1757 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2628 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 2085 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1791 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1847 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1817 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1327 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1020 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 280 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 187 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 175 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 121 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 53 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 100 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 61793 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 322.802648 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 189.147121 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 338.470119 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 22296 36.08% 36.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 14465 23.41% 59.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6637 10.74% 70.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3539 5.73% 75.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2616 4.23% 80.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1600 2.59% 82.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1149 1.86% 84.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1212 1.96% 86.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8279 13.40% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 61793 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 5874 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.927818 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 584.509202 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 5873 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 5874 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 5873 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 24.134684 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.418054 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 43.798135 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5542 94.36% 94.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 90 1.53% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.29% 96.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 15 0.26% 96.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 16 0.27% 96.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 28 0.48% 97.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 28 0.48% 97.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 13 0.22% 97.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 10 0.17% 98.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 8 0.14% 98.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 17 0.29% 98.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 16 0.27% 98.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 10 0.17% 98.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::224-239 6 0.10% 99.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 3 0.05% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 5 0.09% 99.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 7 0.12% 99.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 1 0.02% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 5 0.09% 99.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 11 0.19% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 8 0.14% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::416-431 1 0.02% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 1 0.02% 99.83% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 3 0.05% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::544-559 1 0.02% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::560-575 1 0.02% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::592-607 1 0.02% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::672-687 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::688-703 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 5873 # Writes before turning the bus around for reads +system.physmem.totQLat 1685079736 # Total ticks spent queuing +system.physmem.totMemAccLat 4871117236 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 849610000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9916.78 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 28518.63 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 28666.78 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.81 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.57 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.80 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 3.61 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.33 # Average write queue length when enqueuing -system.physmem.readRowHits 140084 # Number of row buffer hits during reads -system.physmem.writeRowHits 125841 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.45 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 79.14 # Row buffer hit rate for writes -system.physmem.avgGap 8515254.26 # Average gap between requests -system.physmem.pageHitRate 80.85 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 246909600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 134722500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 691555800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 522696240 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 83503223595 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1638462219000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1909895676495 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.469106 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2725585905000 # Time in different power states -system.physmem_0.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.37 # Average write queue length when enqueuing +system.physmem.readRowHits 140217 # Number of row buffer hits during reads +system.physmem.writeRowHits 109661 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.52 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 77.35 # Row buffer hit rate for writes +system.physmem.avgGap 8512044.79 # Average gap between requests +system.physmem.pageHitRate 80.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 242267760 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 132189750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 692507400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 468860400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 83617160895 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1638712655250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1910238133215 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.452112 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2726011845150 # Time in different power states +system.physmem_0.memoryStateTime::REF 95282460000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 32002250000 # Time in different power states +system.physmem_0.memoryStateTime::ACT 32147776350 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 229083120 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 124995750 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 633664200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 507533040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 186334349760 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 82044200295 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1639742072250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1909615898415 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.371033 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2727729306000 # Time in different power states -system.physmem_1.memoryStateTime::REF 95262960000 # Time in different power states +system.physmem_1.actEnergy 224857080 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 122689875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 632876400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 449634240 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 186372491760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 82395435150 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1639784344500 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1909982329005 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.362464 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2727805815350 # Time in different power states +system.physmem_1.memoryStateTime::REF 95282460000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 29860939000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 30353736650 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 448 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -349,15 +334,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 31058702 # Number of BP lookups -system.cpu.branchPred.condPredicted 16880390 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 2530392 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 18557624 # Number of BTB lookups -system.cpu.branchPred.BTBHits 13376459 # Number of BTB hits +system.cpu.branchPred.lookups 31053109 # Number of BP lookups +system.cpu.branchPred.condPredicted 16852863 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 2525514 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 18620216 # Number of BTB lookups +system.cpu.branchPred.BTBHits 13364906 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.080666 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 7810096 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 1523796 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 71.776321 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 7853668 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 1516989 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -388,57 +373,58 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 66845 # Table walker walks requested -system.cpu.dtb.walker.walksShort 66845 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43967 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22878 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walkWaitTime::samples 66845 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0 66845 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 66845 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 7791 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 10107.303299 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7513.505454 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7923.201613 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 7786 99.94% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 2 0.03% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::131072-163839 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::294912-327679 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 7791 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 234495500 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0 234495500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 234495500 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6429 82.52% 82.52% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1362 17.48% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7791 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 66845 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walks 65844 # Table walker walks requested +system.cpu.dtb.walker.walksShort 65844 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 43330 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22514 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walkWaitTime::samples 65844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0 65844 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 65844 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11086.116106 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 8821.657087 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7338.018596 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 6073 78.00% 78.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 1707 21.92% 99.92% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 1 0.01% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 3 0.04% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::163840-180223 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 7786 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 262515000 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0 262515000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 262515000 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6400 82.20% 82.20% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1386 17.80% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7786 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 65844 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 66845 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7791 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 65844 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7786 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7791 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 74636 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7786 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 73630 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 24793006 # DTB read hits -system.cpu.dtb.read_misses 59858 # DTB read misses -system.cpu.dtb.write_hits 19468400 # DTB write hits -system.cpu.dtb.write_misses 6987 # DTB write misses +system.cpu.dtb.read_hits 24757406 # DTB read hits +system.cpu.dtb.read_misses 59085 # DTB read misses +system.cpu.dtb.write_hits 19449348 # DTB write hits +system.cpu.dtb.write_misses 6759 # DTB write misses system.cpu.dtb.flush_tlb 64 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4357 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 1289 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 1775 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 1268 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 1766 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 757 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 24852864 # DTB read accesses -system.cpu.dtb.write_accesses 19475387 # DTB write accesses +system.cpu.dtb.perms_faults 739 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 24816491 # DTB read accesses +system.cpu.dtb.write_accesses 19456107 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 44261406 # DTB hits -system.cpu.dtb.misses 66845 # DTB misses -system.cpu.dtb.accesses 44328251 # DTB accesses +system.cpu.dtb.hits 44206754 # DTB hits +system.cpu.dtb.misses 65844 # DTB misses +system.cpu.dtb.accesses 44272598 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -468,37 +454,37 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 5440 # Table walker walks requested -system.cpu.itb.walker.walksShort 5440 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 316 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 5124 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walkWaitTime::samples 5440 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0 5440 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 5440 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10236.198243 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7641.069075 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7067.497935 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1310 41.09% 41.09% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1157 36.29% 77.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 720 22.58% 99.97% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3188 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 234126500 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 234126500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 234126500 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 2879 90.31% 90.31% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 309 9.69% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3188 # Table walker page sizes translated +system.cpu.itb.walker.walks 5446 # Table walker walks requested +system.cpu.itb.walker.walksShort 5446 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 324 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 5122 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walkWaitTime::samples 5446 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0 5446 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 5446 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 11253.454774 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 8989.562910 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7050.042435 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1281 40.23% 40.23% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1185 37.22% 77.45% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 717 22.52% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 1 0.03% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3184 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 262109500 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 262109500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 262109500 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 2875 90.30% 90.30% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 309 9.70% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3184 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5440 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 5440 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 5446 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 5446 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3188 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3188 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 8628 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 57692911 # ITB inst hits -system.cpu.itb.inst_misses 5440 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3184 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 8630 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 57726188 # ITB inst hits +system.cpu.itb.inst_misses 5446 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -507,119 +493,119 @@ system.cpu.itb.flush_tlb 64 # Nu system.cpu.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2976 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2973 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 8340 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 8450 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 57698351 # ITB inst accesses -system.cpu.itb.hits 57692911 # DTB hits -system.cpu.itb.misses 5440 # DTB misses -system.cpu.itb.accesses 57698351 # DTB accesses -system.cpu.numCycles 314937774 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 57731634 # ITB inst accesses +system.cpu.itb.hits 57726188 # DTB hits +system.cpu.itb.misses 5446 # DTB misses +system.cpu.itb.accesses 57731634 # DTB accesses +system.cpu.numCycles 317415724 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 112207125 # Number of instructions committed -system.cpu.committedOps 135672670 # Number of ops (including micro ops) committed -system.cpu.discardedOps 7783589 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 112053421 # Number of instructions committed +system.cpu.committedOps 135485276 # Number of ops (including micro ops) committed +system.cpu.discardedOps 7764036 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 3035 # Number of times Execute suspended instruction fetching -system.cpu.quiesceCycles 5390825701 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.cpi 2.806754 # CPI: cycles per instruction -system.cpu.ipc 0.356283 # IPC: instructions per cycle +system.cpu.quiesceCycles 5389516808 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.cpi 2.832718 # CPI: cycles per instruction +system.cpu.ipc 0.353018 # IPC: instructions per cycle system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 3035 # number of quiesce instructions executed -system.cpu.tickCycles 228221487 # Number of cycles that the object actually ticked -system.cpu.idleCycles 86716287 # Total number of cycles that the object has spent stopped -system.cpu.dcache.tags.replacements 841983 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.953279 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 42762284 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 842495 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 50.756721 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 281436250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.953279 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999909 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999909 # Average percentage of cache occupancy +system.cpu.tickCycles 228406815 # Number of cycles that the object actually ticked +system.cpu.idleCycles 89008909 # Total number of cycles that the object has spent stopped +system.cpu.dcache.tags.replacements 842109 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.947879 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 42706608 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 842621 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 50.683057 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 313221250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.947879 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999898 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999898 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 100 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 355 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 57 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 99 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 357 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 56 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 176413277 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 176413277 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23536274 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23536274 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 18304900 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 18304900 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 457909 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 457909 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 460268 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 460268 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 41841174 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 41841174 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 41841174 # number of overall hits -system.cpu.dcache.overall_hits::total 41841174 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 583393 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 583393 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 541748 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 541748 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 8195 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 8195 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 176191359 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 176191359 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23499832 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23499832 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 18286134 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 18286134 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 457571 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 457571 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 460116 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 460116 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 41785966 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 41785966 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 41785966 # number of overall hits +system.cpu.dcache.overall_hits::total 41785966 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 583874 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 583874 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 541283 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 541283 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 8366 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 8366 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 2 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 1125141 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1125141 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1125141 # number of overall misses -system.cpu.dcache.overall_misses::total 1125141 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8651014339 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 21393186307 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 116036500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 150500 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 30044200646 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 30044200646 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 30044200646 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 30044200646 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24119667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24119667 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 18846648 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 18846648 # 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miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.028750 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.017955 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.017955 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000004 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000004 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026187 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026187 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026187 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026187 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14828.793522 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14828.793522 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 39489.183729 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 39489.183729 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14159.426480 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14159.426480 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 75250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 75250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26702.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26702.609403 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26702.609403 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.026221 # 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average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 28506.405573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 28506.405573 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 28506.405573 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -628,70 +614,70 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 698310 # number of writebacks -system.cpu.dcache.writebacks::total 698310 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 45149 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 45149 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 242834 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 242834 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 287983 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 287983 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 287983 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 287983 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 538244 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 538244 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 298914 # 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number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18060007796 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18060007796 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18060007796 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5790998000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5790998000 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4439562500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4439562500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10230560500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10230560500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022316 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022316 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015860 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017582 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017582 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 837137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 837137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 837137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 837137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7251218502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7251218502 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 12288582898 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 12288582898 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 107501250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 107501250 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 162500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19539801400 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19539801400 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 19539801400 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 19539801400 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5836783750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5836783750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4510033500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4510033500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10346817250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10346817250 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.022367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.022367 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015852 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017955 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017955 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000004 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000004 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.019484 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019484 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019484 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12806.801640 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12806.801640 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 37357.981406 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 37357.981406 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12156.253813 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12156.253813 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 73250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21572.997924 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21572.997924 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.019509 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019509 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019509 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13461.112280 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13461.112280 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41173.575170 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41173.575170 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 12849.778867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 12849.778867 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 81250 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23341.223002 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23341.223002 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -699,58 +685,58 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 2900110 # number of replacements -system.cpu.icache.tags.tagsinuse 511.424371 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 54783568 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 2900622 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.886835 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 15309705250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.424371 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998876 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998876 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 2898605 # number of replacements +system.cpu.icache.tags.tagsinuse 511.397830 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 54818221 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 2899117 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.908592 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 15715014250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.397830 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998824 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998824 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 111 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 204 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 197 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 195 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 60584835 # Number of tag accesses -system.cpu.icache.tags.data_accesses 60584835 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 54783568 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 54783568 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 54783568 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 54783568 # 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number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 39309012875 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 39309012875 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 39309012875 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 39309012875 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 57717350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 57717350 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 57717350 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 57717350 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 57717350 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 57717350 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.050230 # 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average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,196 +745,196 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 2900634 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 2900634 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 2900634 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 2900634 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 2900634 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 34950907125 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 34950907125 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 34950907125 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 34950907125 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 247386750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 247386750 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 247386750 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 247386750 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.050230 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.050230 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.050230 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.050230 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12055.657794 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12055.657794 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12055.657794 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12055.657794 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 96921 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65071.012008 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 4047776 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 162169 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 24.960233 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 96782 # 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Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001091 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 47373.506796 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 67.256900 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000383 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 12244.945403 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5373.703806 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.722862 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.001026 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.186078 # 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Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 36621683 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 36621683 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 71038 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 4429 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 2877594 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 532037 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 3485098 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 698310 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 698310 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 53 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 53 # number of UpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 164919 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 164919 # 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average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 60250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 57182.821397 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 57182.821397 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 67509.765625 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 62500 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 60127.234376 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 57857.957937 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58174.891376 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.443805 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.443805 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.001627 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000223 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.007919 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.172448 # 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average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 72850.877193 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 70000 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67515.739524 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65630.369857 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65892.338336 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1069,61 +1055,59 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 3581727 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 3581627 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27607 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 698310 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2832 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 3579627 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 3579531 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27583 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 697919 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36254 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2856 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2834 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296087 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296087 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5807240 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506645 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 14994 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 160889 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 8489768 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185830784 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98804957 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17720 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 284664 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 284938125 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 61311 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 4581044 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 5.007958 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.088854 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2858 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 295607 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 295607 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5804583 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2506486 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 15045 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 158423 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8484537 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 185746048 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98788181 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 17908 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 280260 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 284832397 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 61029 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 4577967 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 3.007970 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.088920 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 4544586 99.20% 99.20% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 36458 0.80% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::3 4541479 99.20% 99.20% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::4 36488 0.80% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 4581044 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 3015323412 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 4 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 4577967 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3013390750 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 202500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 208500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 4360848041 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 4358889625 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1341145704 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1341438850 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 10564000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 10568000 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 89727250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 88362250 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30195 # Transaction distribution -system.iobus.trans_dist::ReadResp 30195 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30183 # Transaction distribution +system.iobus.trans_dist::ReadResp 30183 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1144,11 +1128,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72916 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72916 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178466 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 178394 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1169,11 +1153,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321104 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321104 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480301 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size::total 2480229 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1213,23 +1197,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347055145 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198914708 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36804505 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36809505 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36424 # number of replacements -system.iocache.tags.tagsinuse 1.033413 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.032937 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36440 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 270192614000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.033413 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.064588 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.064588 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 270823051000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.032937 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.064559 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.064559 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1243,14 +1227,14 @@ system.iocache.demand_misses::realview.ide 234 # system.iocache.demand_misses::total 234 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 234 # number of overall misses system.iocache.overall_misses::total 234 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 27950377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 27950377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9592588263 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9592588263 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 27950377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 27950377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 27950377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 27950377 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 29244877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 29244877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652334326 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6652334326 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 29244877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 29244877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 29244877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 29244877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 234 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 234 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) @@ -1267,19 +1251,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 119446.055556 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 119446.055556 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 264813.059381 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 264813.059381 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 119446.055556 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 119446.055556 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 55542 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 124978.106838 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 124978.106838 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183644.388417 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183644.388417 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 124978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 124978.106838 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 124978.106838 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22952 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7161 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3496 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.756179 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.565217 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1293,14 +1277,14 @@ system.iocache.demand_mshr_misses::realview.ide 234 system.iocache.demand_mshr_misses::total 234 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 234 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 234 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 15781377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 15781377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7708930273 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7708930273 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 15781377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 15781377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 15781377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 15781377 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16937877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16937877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768676336 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768676336 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16937877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16937877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16937877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16937877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1309,66 +1293,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 67441.782051 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 67441.782051 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 212812.783597 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 212812.783597 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 67441.782051 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 67441.782051 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 72384.089744 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 72384.089744 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131644.112633 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131644.112633 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 72384.089744 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 72384.089744 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 71749 # Transaction distribution -system.membus.trans_dist::ReadResp 71749 # Transaction distribution -system.membus.trans_dist::WriteReq 27607 # Transaction distribution -system.membus.trans_dist::WriteResp 27607 # Transaction distribution -system.membus.trans_dist::Writeback 124418 # Transaction distribution +system.membus.trans_dist::ReadReq 71726 # Transaction distribution +system.membus.trans_dist::ReadResp 71726 # Transaction distribution +system.membus.trans_dist::WriteReq 27583 # Transaction distribution +system.membus.trans_dist::WriteResp 27583 # Transaction distribution +system.membus.trans_dist::Writeback 124578 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4596 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4604 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4598 # Transaction distribution -system.membus.trans_dist::ReadExReq 129351 # Transaction distribution -system.membus.trans_dist::ReadExResp 129351 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4606 # Transaction distribution +system.membus.trans_dist::ReadExReq 129395 # Transaction distribution +system.membus.trans_dist::ReadExResp 129395 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2068 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446451 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554083 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 446695 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 554255 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108887 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108887 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 662970 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 663142 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4136 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16510296 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16674077 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16522776 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16686485 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21309533 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 506 # Total snoops (count) -system.membus.snoop_fanout::samples 332202 # Request fanout histogram +system.membus.pkt_size::total 21321941 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 504 # Total snoops (count) +system.membus.snoop_fanout::samples 332271 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 332202 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 332271 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 332202 # Request fanout histogram -system.membus.reqLayer0.occupancy 87413000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 332271 # Request fanout histogram +system.membus.reqLayer0.occupancy 90362500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1709000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1704000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1674431500 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1690391904 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38335495 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1022735199 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 997821410 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37468495 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |