stats: update stats for cache occupancy and clock domain changes

4 files changed, 78 insertions, 35 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 25f2809e1..d2896598b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -12,7 +12,7 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 cache_line_size=64
 clk_domain=system.clk_domain
@@ -23,7 +23,7 @@ eventq_index=0
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -75,7 +75,7 @@ table_size=65536
 [system.cf0.image.child]
 type=RawDiskImage
 eventq_index=0
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/disks/linux-arm-ael.img
 read_only=true
 
 [system.clk_domain]
@@ -288,6 +288,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.dcache.tags
@@ -304,6 +305,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.dtb]
@@ -643,6 +645,7 @@ mshrs=4
 prefetch_on_access=false
 prefetcher=Null
 response_latency=2
+sequential_access=false
 size=32768
 system=system
 tags=system.cpu.icache.tags
@@ -659,6 +662,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=2
+sequential_access=false
 size=32768
 
 [system.cpu.interrupts]
@@ -713,6 +717,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=20
+sequential_access=false
 size=4194304
 system=system
 tags=system.cpu.l2cache.tags
@@ -729,6 +734,7 @@ block_size=64
 clk_domain=system.cpu_clk_domain
 eventq_index=0
 hit_latency=20
+sequential_access=false
 size=4194304
 
 [system.cpu.toL2Bus]
@@ -782,6 +788,7 @@ mshrs=20
 prefetch_on_access=false
 prefetcher=Null
 response_latency=50
+sequential_access=false
 size=1024
 system=system
 tags=system.iocache.tags
@@ -798,6 +805,7 @@ block_size=64
 clk_domain=system.clk_domain
 eventq_index=0
 hit_latency=50
+sequential_access=false
 size=1024
 
 [system.membus]
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index 90faba56d..ccd250823 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
@@ -1,7 +1,6 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
-warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
@@ -11,22 +10,25 @@ warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
-warn: 6117297500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 6125706500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 6160975500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 6176055500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6715294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 6165886500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
+warn: 6172734500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 6181171500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 6216960500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 6232347500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6775306000: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
 warn: LCD dual screen mode not supported
-warn: 51807478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
+warn: 51869237500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 2474714862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2488540668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2489750451500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2510845218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2511359133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2517064152000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2517573704500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2518135055000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2518136146000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
-hack: be nice to actually delete the event here
+warn: 2475417694000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2489281853500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2490491047500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2511643992000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2512158375000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2516381302500: Instruction results do not match! (Values may not actually be integers) Inst: 0xee6b2, checker: 0
+warn: 2516399186500: Instruction results do not match! (Values may not actually be integers) Inst: 0x4001f92c, checker: 0x4001ef10
+warn: 2517881609000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2518389750000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2518949430500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2518950618000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2519498238000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2fc, checker: 0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index 6df74fa42..a9e6de1f3 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -1,12 +1,12 @@
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Oct 16 2013 01:36:42
-gem5 started Oct 16 2013 02:31:27
-gem5 executing on zizzer
+gem5 compiled Jan 22 2014 17:24:06
+gem5 started Jan 23 2014 00:07:43
+gem5 executing on u200540-lin
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2524309551500 because m5_exit instruction encountered
+Exiting @ tick 2525131633500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
index d7c49d42e..e81d47f63 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt
@@ -4,13 +4,15 @@ sim_seconds                                  2.525132                       # Nu
 sim_ticks                                2525131633500                       # Number of ticks simulated
 final_tick                               2525131633500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  41051                       # Simulator instruction rate (inst/s)
-host_op_rate                                    52821                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1718892257                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 447424                       # Number of bytes of host memory used
-host_seconds                                  1469.05                       # Real time elapsed on the host
+host_inst_rate                                  63748                       # Simulator instruction rate (inst/s)
+host_op_rate                                    82026                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2669254242                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 403420                       # Number of bytes of host memory used
+host_seconds                                   946.01                       # Real time elapsed on the host
 sim_insts                                    60305678                       # Number of instructions simulated
 sim_ops                                      77596684                       # Number of ops (including micro ops) simulated
+system.voltage_domain.voltage                       1                       # Voltage in Volts
+system.clk_domain.clock                          1000                       # Clock period in ticks
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker         2688                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
@@ -928,6 +930,7 @@ system.iobus.respLayer0.occupancy          2374785000                       # La
 system.iobus.respLayer0.utilization               0.1                       # Layer utilization (%)
 system.iobus.respLayer1.occupancy         40921719549                       # Layer occupancy (ticks)
 system.iobus.respLayer1.utilization               1.6                       # Layer utilization (%)
+system.cpu_clk_domain.clock                       500                       # Clock period in ticks
 system.cpu.branchPred.lookups                14384927                       # Number of BP lookups
 system.cpu.branchPred.condPredicted          11469310                       # Number of conditional branches predicted
 system.cpu.branchPred.condIncorrect            704177                       # Number of conditional branches incorrect
@@ -958,8 +961,8 @@ system.cpu.checker.dtb.inst_accesses                0                       # IT
 system.cpu.checker.dtb.hits                  26214250                       # DTB hits
 system.cpu.checker.dtb.misses                    9498                       # DTB misses
 system.cpu.checker.dtb.accesses              26223748                       # DTB accesses
-system.cpu.checker.itb.inst_hits             61479663                       # ITB inst hits
-system.cpu.checker.itb.inst_misses               4471                       # ITB inst misses
+system.cpu.checker.itb.inst_hits             61479661                       # ITB inst hits
+system.cpu.checker.itb.inst_misses               4473                       # ITB inst misses
 system.cpu.checker.itb.read_hits                    0                       # DTB read hits
 system.cpu.checker.itb.read_misses                  0                       # DTB read misses
 system.cpu.checker.itb.write_hits                   0                       # DTB write hits
@@ -968,7 +971,7 @@ system.cpu.checker.itb.flush_tlb                    4                       # Nu
 system.cpu.checker.itb.flush_tlb_mva                0                       # Number of times TLB was flushed by MVA
 system.cpu.checker.itb.flush_tlb_mva_asid         2878                       # Number of times TLB was flushed by MVA & ASID
 system.cpu.checker.itb.flush_tlb_asid             126                       # Number of times TLB was flushed by ASID
-system.cpu.checker.itb.flush_entries             4682                       # Number of entries that have been flushed from TLB
+system.cpu.checker.itb.flush_entries             4683                       # Number of entries that have been flushed from TLB
 system.cpu.checker.itb.align_faults                 0                       # Number of TLB faults due to alignment restrictions
 system.cpu.checker.itb.prefetch_faults              0                       # Number of TLB faults due to prefetch
 system.cpu.checker.itb.domain_faults                0                       # Number of TLB faults due to domain restrictions
@@ -976,8 +979,8 @@ system.cpu.checker.itb.perms_faults                 0                       # Nu
 system.cpu.checker.itb.read_accesses                0                       # DTB read accesses
 system.cpu.checker.itb.write_accesses               0                       # DTB write accesses
 system.cpu.checker.itb.inst_accesses         61484134                       # ITB inst accesses
-system.cpu.checker.itb.hits                  61479663                       # DTB hits
-system.cpu.checker.itb.misses                    4471                       # DTB misses
+system.cpu.checker.itb.hits                  61479661                       # DTB hits
+system.cpu.checker.itb.misses                    4473                       # DTB misses
 system.cpu.checker.itb.accesses              61484134                       # DTB accesses
 system.cpu.checker.numCycles                 77882476                       # number of cpu cycles simulated
 system.cpu.checker.numWorkItemsStarted              0                       # number of work items this cpu started
@@ -1332,6 +1335,14 @@ system.cpu.icache.tags.warmup_cycle        6918450250                       # Cy
 system.cpu.icache.tags.occ_blocks::cpu.inst   511.579102                       # Average occupied blocks per requestor
 system.cpu.icache.tags.occ_percent::cpu.inst     0.999178                       # Average percentage of cache occupancy
 system.cpu.icache.tags.occ_percent::total     0.999178                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::0          136                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::1          225                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::2          150                       # Occupied blocks per task id
+system.cpu.icache.tags.age_task_id_blocks_1024::3            1                       # Occupied blocks per task id
+system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.icache.tags.tag_accesses          12500309                       # Number of tag accesses
+system.cpu.icache.tags.data_accesses         12500309                       # Number of data accesses
 system.cpu.icache.ReadReq_hits::cpu.inst     10457750                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        10457750                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      10457750                       # number of demand (read+write) hits
@@ -1432,6 +1443,19 @@ system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000000
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.124721                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.095140                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::total     0.783737                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_task_id_blocks::1023           19                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_blocks::1024        65375                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::3            1                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1023::4           18                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::0           38                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::1          355                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::2         3055                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::3         6962                       # Occupied blocks per task id
+system.cpu.l2cache.tags.age_task_id_blocks_1024::4        54965                       # Occupied blocks per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1023     0.000290                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.occ_task_id_percent::1024     0.997543                       # Percentage of cache occupancy per task id
+system.cpu.l2cache.tags.tag_accesses         18784884                       # Number of tag accesses
+system.cpu.l2cache.tags.data_accesses        18784884                       # Number of data accesses
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker        52523                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker        10409                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       967861                       # number of ReadReq hits
@@ -1687,6 +1711,13 @@ system.cpu.dcache.tags.warmup_cycle          42430250                       # Cy
 system.cpu.dcache.tags.occ_blocks::cpu.data   511.993331                       # Average occupied blocks per requestor
 system.cpu.dcache.tags.occ_percent::cpu.data     0.999987                       # Average percentage of cache occupancy
 system.cpu.dcache.tags.occ_percent::total     0.999987                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::0          192                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::1          302                       # Occupied blocks per task id
+system.cpu.dcache.tags.age_task_id_blocks_1024::2           18                       # Occupied blocks per task id
+system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
+system.cpu.dcache.tags.tag_accesses         101519243                       # Number of tag accesses
+system.cpu.dcache.tags.data_accesses        101519243                       # Number of data accesses
 system.cpu.dcache.ReadReq_hits::cpu.data     13755484                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13755484                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      7258628                       # number of WriteReq hits
@@ -1846,6 +1877,8 @@ system.iocache.tags.total_refs                      0                       # To
 system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
 system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
 system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.tag_accesses                    0                       # Number of tag accesses
+system.iocache.tags.data_accesses                   0                       # Number of data accesses
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked