diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-03-02 05:04:20 -0500 |
commit | 8909843a76c723cb9d8a0b1394eeeba4d7abadb1 (patch) | |
tree | 446fe188000e814cbc7d23075428cab7f44868d1 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker | |
parent | fc315901ff4aaae0f56c4c1b1c50ffe9bd70b4d6 (diff) | |
download | gem5-8909843a76c723cb9d8a0b1394eeeba4d7abadb1.tar.xz |
stats: Update stats to reflect cache and interconnect changes
This is a bulk update of stats to match the changes to cache timing,
interconnect timing, and a few minor changes to the o3 CPU.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 2532 |
1 files changed, 1259 insertions, 1273 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index c276b537b..b7b8c766f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,121 +1,121 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827025 # Number of seconds simulated -sim_ticks 2827025397500 # Number of ticks simulated -final_tick 2827025397500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827616 # Number of seconds simulated +sim_ticks 2827616186000 # Number of ticks simulated +final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 71679 # Simulator instruction rate (inst/s) -host_op_rate 86943 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1789973688 # Simulator tick rate (ticks/s) -host_mem_usage 620632 # Number of bytes of host memory used -host_seconds 1579.37 # Real time elapsed on the host -sim_insts 113206948 # Number of instructions simulated -sim_ops 137314363 # Number of ops (including micro ops) simulated +host_inst_rate 69501 # Simulator instruction rate (inst/s) +host_op_rate 84304 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1736810486 # Simulator tick rate (ticks/s) +host_mem_usage 620504 # Number of bytes of host memory used +host_seconds 1628.05 # Real time elapsed on the host +sim_insts 113151083 # Number of instructions simulated +sim_ops 137250963 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1324240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9499748 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9769956 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10826676 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1324240 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8118016 # Number of bytes written to this memory +system.physmem.bytes_read::total 11098052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8135540 # Number of bytes written to this memory -system.physmem.num_reads::cpu.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22936 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 148953 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153175 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 171931 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 126844 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176172 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 131225 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.dtb.walker 453 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468422 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3360333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3455192 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3829706 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468422 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2871575 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6199 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2877774 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2871575 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3924879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468422 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3366532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3461389 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6707480 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 171932 # Number of read requests accepted -system.physmem.writeReqs 167449 # Number of write requests accepted -system.physmem.readBursts 171932 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 167449 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 10995584 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8064 # Total number of bytes read from write queue -system.physmem.bytesWritten 10340800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 10826740 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10453876 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 126 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 5856 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4542 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11320 # Per bank write bursts -system.physmem.perBankRdBursts::1 10283 # Per bank write bursts -system.physmem.perBankRdBursts::2 11137 # Per bank write bursts -system.physmem.perBankRdBursts::3 11363 # Per bank write bursts -system.physmem.perBankRdBursts::4 13028 # Per bank write bursts -system.physmem.perBankRdBursts::5 10237 # Per bank write bursts -system.physmem.perBankRdBursts::6 10954 # Per bank write bursts -system.physmem.perBankRdBursts::7 11381 # Per bank write bursts -system.physmem.perBankRdBursts::8 10407 # Per bank write bursts -system.physmem.perBankRdBursts::9 11232 # Per bank write bursts -system.physmem.perBankRdBursts::10 10729 # Per bank write bursts -system.physmem.perBankRdBursts::11 9386 # Per bank write bursts -system.physmem.perBankRdBursts::12 9853 # Per bank write bursts -system.physmem.perBankRdBursts::13 10909 # Per bank write bursts -system.physmem.perBankRdBursts::14 9951 # Per bank write bursts -system.physmem.perBankRdBursts::15 9636 # Per bank write bursts -system.physmem.perBankWrBursts::0 10810 # Per bank write bursts -system.physmem.perBankWrBursts::1 10132 # Per bank write bursts -system.physmem.perBankWrBursts::2 10502 # Per bank write bursts -system.physmem.perBankWrBursts::3 10558 # Per bank write bursts -system.physmem.perBankWrBursts::4 9654 # Per bank write bursts -system.physmem.perBankWrBursts::5 9978 # Per bank write bursts -system.physmem.perBankWrBursts::6 10358 # Per bank write bursts -system.physmem.perBankWrBursts::7 10535 # Per bank write bursts -system.physmem.perBankWrBursts::8 10309 # Per bank write bursts -system.physmem.perBankWrBursts::9 10935 # Per bank write bursts -system.physmem.perBankWrBursts::10 10009 # Per bank write bursts -system.physmem.perBankWrBursts::11 9154 # Per bank write bursts -system.physmem.perBankWrBursts::12 9556 # Per bank write bursts -system.physmem.perBankWrBursts::13 10555 # Per bank write bursts -system.physmem.perBankWrBursts::14 9521 # Per bank write bursts -system.physmem.perBankWrBursts::15 9009 # Per bank write bursts +system.physmem.bw_total::total 6897386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176173 # Number of read requests accepted +system.physmem.writeReqs 171661 # Number of write requests accepted +system.physmem.readBursts 176173 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8768 # Total number of bytes read from write queue +system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11098116 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 137 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11334 # Per bank write bursts +system.physmem.perBankRdBursts::1 10890 # Per bank write bursts +system.physmem.perBankRdBursts::2 10732 # Per bank write bursts +system.physmem.perBankRdBursts::3 10393 # Per bank write bursts +system.physmem.perBankRdBursts::4 14045 # Per bank write bursts +system.physmem.perBankRdBursts::5 11531 # Per bank write bursts +system.physmem.perBankRdBursts::6 11498 # Per bank write bursts +system.physmem.perBankRdBursts::7 11674 # Per bank write bursts +system.physmem.perBankRdBursts::8 10645 # Per bank write bursts +system.physmem.perBankRdBursts::9 10993 # Per bank write bursts +system.physmem.perBankRdBursts::10 10307 # Per bank write bursts +system.physmem.perBankRdBursts::11 9597 # Per bank write bursts +system.physmem.perBankRdBursts::12 9956 # Per bank write bursts +system.physmem.perBankRdBursts::13 10908 # Per bank write bursts +system.physmem.perBankRdBursts::14 10689 # Per bank write bursts +system.physmem.perBankRdBursts::15 10844 # Per bank write bursts +system.physmem.perBankWrBursts::0 9257 # Per bank write bursts +system.physmem.perBankWrBursts::1 9346 # Per bank write bursts +system.physmem.perBankWrBursts::2 9336 # Per bank write bursts +system.physmem.perBankWrBursts::3 8962 # Per bank write bursts +system.physmem.perBankWrBursts::4 9705 # Per bank write bursts +system.physmem.perBankWrBursts::5 9746 # Per bank write bursts +system.physmem.perBankWrBursts::6 9125 # Per bank write bursts +system.physmem.perBankWrBursts::7 9630 # Per bank write bursts +system.physmem.perBankWrBursts::8 9307 # Per bank write bursts +system.physmem.perBankWrBursts::9 9634 # Per bank write bursts +system.physmem.perBankWrBursts::10 8942 # Per bank write bursts +system.physmem.perBankWrBursts::11 8449 # Per bank write bursts +system.physmem.perBankWrBursts::12 8881 # Per bank write bursts +system.physmem.perBankWrBursts::13 9361 # Per bank write bursts +system.physmem.perBankWrBursts::14 9018 # Per bank write bursts +system.physmem.perBankWrBursts::15 9072 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2827025186500 # Total gap between requests +system.physmem.numWrRetry 58 # Number of times write queue was full causing retry +system.physmem.totGap 2827615975000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 541 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2993 # Read request sizes (log2) +system.physmem.readPktSize::4 2994 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 168384 # Read request sizes (log2) +system.physmem.readPktSize::6 172624 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 163068 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 151696 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 16122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 3183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 788 # What read queue length does an incoming req see +system.physmem.writePktSize::6 167280 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see @@ -159,175 +159,161 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2205 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 7484 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 8723 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 9349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 10189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 10503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 11230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 11052 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 11509 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10710 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10405 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9400 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 7956 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7712 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7566 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7361 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 564 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 503 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 314 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 244 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 222 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 195 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 112 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 105 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 94 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 81 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 43 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 30 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 15 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 11 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 5 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 4 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 64517 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 330.708495 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 190.901316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 347.828879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 23555 36.51% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 14820 22.97% 59.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6443 9.99% 69.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3645 5.65% 75.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2568 3.98% 79.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1574 2.44% 81.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1131 1.75% 83.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1187 1.84% 85.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9594 14.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 64517 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6820 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 25.190762 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 540.107379 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6818 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6820 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6820 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.691349 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 19.848646 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 22.179127 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5682 83.31% 83.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 64 0.94% 84.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 25 0.37% 84.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 208 3.05% 87.67% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 139 2.04% 89.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 55 0.81% 90.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 46 0.67% 91.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 37 0.54% 91.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 121 1.77% 93.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 14 0.21% 93.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 20 0.29% 94.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 15 0.22% 94.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 20 0.29% 94.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 19 0.28% 94.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.15% 94.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 21 0.31% 95.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 67 0.98% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 14 0.21% 96.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 7 0.10% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 14 0.21% 96.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 85 1.25% 97.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 98.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::104-107 5 0.07% 98.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 2 0.03% 98.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 15 0.22% 98.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::116-119 3 0.04% 98.40% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::120-123 16 0.23% 98.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 5 0.07% 98.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 25 0.37% 99.08% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 8 0.12% 99.19% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 2 0.03% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 7 0.10% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-147 12 0.18% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 5 0.07% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 2 0.03% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 9 0.13% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::172-175 2 0.03% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-179 4 0.06% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::184-187 1 0.01% 99.88% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 4 0.06% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::200-203 1 0.01% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-227 2 0.03% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::232-235 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6820 # Writes before turning the bus around for reads -system.physmem.totQLat 2011805750 # Total ticks spent queuing -system.physmem.totMemAccLat 5233168250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 859030000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11709.75 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads +system.physmem.totQLat 2104910750 # Total ticks spent queuing +system.physmem.totMemAccLat 5405585750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11957.27 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30459.75 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 3.89 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.66 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 3.83 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.70 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30707.27 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.20 # Average write queue length when enqueuing -system.physmem.readRowHits 141825 # Number of row buffer hits during reads -system.physmem.writeRowHits 127038 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.55 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 78.62 # Row buffer hit rate for writes -system.physmem.avgGap 8329945.36 # Average gap between requests -system.physmem.pageHitRate 80.64 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 254462040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 138843375 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 699683400 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 534774960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80304363360 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625772042000 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892351625375 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.379373 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704495478000 # Time in different power states -system.physmem_0.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing +system.physmem.readRowHits 145058 # Number of row buffer hits during reads +system.physmem.writeRowHits 112529 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes +system.physmem.avgGap 8129210.99 # Average gap between requests +system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81488168145 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625088669750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892870659755 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.422846 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703351125494 # Time in different power states +system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28128105750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29844453256 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 233286480 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 127289250 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 640395600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 512231040 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184647456240 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79168609575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626768325500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892097593685 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.289511 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2706163008250 # Time in different power states -system.physmem_1.memoryStateTime::REF 94400540000 # Time in different power states +system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80123989140 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626285318000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892592096975 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.324331 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705354979994 # Time in different power states +system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26461835250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27840892506 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -347,15 +333,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46965884 # Number of BP lookups -system.cpu.branchPred.condPredicted 24051171 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1232760 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29570934 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21375571 # Number of BTB hits +system.cpu.branchPred.lookups 46937284 # Number of BP lookups +system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.285749 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11765533 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33715 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -386,45 +372,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9687 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9687 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9687 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9687 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9687 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 207947000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 207947000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 207947000 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6190 82.28% 82.28% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1333 17.72% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7523 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9687 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 9923 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9923 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9923 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9923 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9923 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 230116500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 230116500 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 230116500 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6339 81.70% 81.70% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1420 18.30% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7759 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9923 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9687 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7523 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7759 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7523 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17210 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7759 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17682 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24601959 # DTB read hits -system.cpu.checker.dtb.read_misses 8249 # DTB read misses -system.cpu.checker.dtb.write_hits 19645805 # DTB write hits -system.cpu.checker.dtb.write_misses 1438 # DTB write misses +system.cpu.checker.dtb.read_hits 24588859 # DTB read hits +system.cpu.checker.dtb.read_misses 8478 # DTB read misses +system.cpu.checker.dtb.write_hits 19638229 # DTB write hits +system.cpu.checker.dtb.write_misses 1445 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.checker.dtb.flush_entries 4297 # Number of entries that have been flushed from TLB +system.cpu.checker.dtb.flush_entries 4321 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1738 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24610208 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19647243 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24597337 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19639674 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44247764 # DTB hits -system.cpu.checker.dtb.misses 9687 # DTB misses -system.cpu.checker.dtb.accesses 44257451 # DTB accesses +system.cpu.checker.dtb.hits 44227088 # DTB hits +system.cpu.checker.dtb.misses 9923 # DTB misses +system.cpu.checker.dtb.accesses 44237011 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -459,9 +445,9 @@ system.cpu.checker.itb.walker.walksShort 4826 # Ta system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 207571000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 207571000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 207571000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::samples 229704000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 229704000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 229704000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated @@ -472,7 +458,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115911347 # ITB inst hits +system.cpu.checker.itb.inst_hits 115853330 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -489,11 +475,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115916173 # ITB inst accesses -system.cpu.checker.itb.hits 115911347 # DTB hits +system.cpu.checker.itb.inst_accesses 115858156 # ITB inst accesses +system.cpu.checker.itb.hits 115853330 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115916173 # DTB accesses -system.cpu.checker.numCycles 139170806 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115858156 # DTB accesses +system.cpu.checker.numCycles 139105254 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -525,81 +511,84 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 69937 # Table walker walks requested -system.cpu.dtb.walker.walksShort 69937 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29497 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22737 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 17703 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 334.025730 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 1986.195905 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50803 97.26% 97.26% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 591 1.13% 98.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 521 1.00% 99.39% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 84 0.16% 99.55% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 102 0.20% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 114 0.22% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 4 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 3 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::40960-45055 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72371 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52234 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 9699.278169 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 7212.227669 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7791.284796 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-32767 16044 99.00% 99.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-65535 159 0.98% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::65536-98303 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::98304-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 16206 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.624364 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.489854 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 116858057224 99.96% 99.96% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 29153000 0.02% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 6015500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 4000000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 926000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 658000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 231500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 5000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 116899920224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6318 82.14% 82.14% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1374 17.86% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7692 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 69937 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 69937 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7692 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7692 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 77629 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25472400 # DTB read hits -system.cpu.dtb.read_misses 60528 # DTB read misses -system.cpu.dtb.write_hits 19920178 # DTB write hits -system.cpu.dtb.write_misses 9409 # DTB write misses +system.cpu.dtb.read_hits 25461870 # DTB read hits +system.cpu.dtb.read_misses 62291 # DTB read misses +system.cpu.dtb.write_hits 19915387 # DTB write hits +system.cpu.dtb.write_misses 10080 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4326 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 345 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2281 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1305 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25532928 # DTB read accesses -system.cpu.dtb.write_accesses 19929587 # DTB write accesses +system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25524161 # DTB read accesses +system.cpu.dtb.write_accesses 19925467 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45392578 # DTB hits -system.cpu.dtb.misses 69937 # DTB misses -system.cpu.dtb.accesses 45462515 # DTB accesses +system.cpu.dtb.hits 45377257 # DTB hits +system.cpu.dtb.misses 72371 # DTB misses +system.cpu.dtb.accesses 45449628 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -629,55 +618,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11957 # Table walker walks requested -system.cpu.itb.walker.walksShort 11957 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 4035 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7756 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 166 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 476.931558 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2426.619854 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11573 98.15% 98.15% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 164 1.39% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 47 0.40% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 2 0.02% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::32768-40959 2 0.02% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11974 # Table walker walks requested +system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11791 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 10252.862049 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 7229.260491 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7922.738250 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1610 46.08% 46.08% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 989 28.31% 74.38% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 844 24.16% 98.54% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 31 0.89% 99.43% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 18 0.52% 99.94% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::73728-81919 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3494 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.982067 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.132922 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 397376500 1.80% 1.80% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 21732921212 98.20% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 44500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 26500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 22130705712 # Table walker pending requests distribution -system.cpu.itb.walker.walkPageSizes::4K 3007 90.35% 90.35% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::1M 321 9.65% 100.00% # Table walker page sizes translated -system.cpu.itb.walker.walkPageSizes::total 3328 # Table walker page sizes translated +system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated +system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11957 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11957 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Completed::total 3328 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15285 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66242388 # ITB inst hits -system.cpu.itb.inst_misses 11957 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66270436 # ITB inst hits +system.cpu.itb.inst_misses 11974 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -686,98 +676,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3096 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66254345 # ITB inst accesses -system.cpu.itb.hits 66242388 # DTB hits -system.cpu.itb.misses 11957 # DTB misses -system.cpu.itb.accesses 66254345 # DTB accesses -system.cpu.numCycles 260505842 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66282410 # ITB inst accesses +system.cpu.itb.hits 66270436 # DTB hits +system.cpu.itb.misses 11974 # DTB misses +system.cpu.itb.accesses 66282410 # DTB accesses +system.cpu.numCycles 263104506 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104910536 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184564437 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46965884 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33141104 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 145523967 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6162316 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 169075 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 8609 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 338609 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 504254 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 106 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66242687 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1039458 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5021 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.884658 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.237297 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 155286067 61.01% 61.01% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29244712 11.49% 72.50% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14083759 5.53% 78.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55921776 21.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 254536314 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.180287 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.708485 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78110854 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 105310937 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64681837 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3829276 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2603410 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422230 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 485999 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157498066 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3692054 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2603410 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83952319 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10018441 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74493030 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62674544 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 20794570 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146849554 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949739 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 436543 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 62719 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 16684 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 18031839 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150536032 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678970726 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164476932 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10967 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141878160 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8657869 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2847901 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2651576 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13851577 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26418729 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21304216 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1685996 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2099557 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143583180 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2120928 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143378875 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 268933 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 6250249 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14652310 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125244 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 254536314 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.563294 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.882192 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74822970 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22677863 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19908146 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143328299 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6274201 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 166156595 65.28% 65.28% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45308451 17.80% 83.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31957183 12.56% 95.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10300315 4.05% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 813737 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168573863 65.62% 65.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45206233 17.60% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -785,44 +775,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 254536314 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7371563 32.63% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 32 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.63% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5632608 24.93% 57.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585974 42.43% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96039761 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 113980 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -846,101 +836,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8594 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26201849 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21012354 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26193107 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143378875 # Type of FU issued -system.cpu.iq.rate 0.550386 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22590177 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157556 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 564117476 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 151959359 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140262857 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35698 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13217 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 11431 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165943337 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23378 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323934 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 143328299 # Type of FU issued +system.cpu.iq.rate 0.544758 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566346239 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 151939321 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13215 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 165879209 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1489912 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 533 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18252 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 700651 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87937 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6369 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87835 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2603410 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 946501 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 282988 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145905073 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26418729 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21304216 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1096059 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17893 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 248042 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18252 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317390 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471834 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 789224 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142436087 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25800504 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 872964 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142382518 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25789726 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 200965 # number of nop insts executed -system.cpu.iew.exec_refs 46683536 # number of memory reference insts executed -system.cpu.iew.exec_branches 26544582 # Number of branches executed -system.cpu.iew.exec_stores 20883032 # Number of stores executed -system.cpu.iew.exec_rate 0.546767 # Inst execution rate -system.cpu.iew.wb_sent 142049013 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140274288 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63301991 # num instructions producing a value -system.cpu.iew.wb_consumers 95888204 # num instructions consuming a value +system.cpu.iew.exec_nop 201053 # number of nop insts executed +system.cpu.iew.exec_refs 46667575 # number of memory reference insts executed +system.cpu.iew.exec_branches 26530134 # Number of branches executed +system.cpu.iew.exec_stores 20877849 # Number of stores executed +system.cpu.iew.exec_rate 0.541163 # Inst execution rate +system.cpu.iew.wb_sent 141996043 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63271750 # num instructions producing a value +system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.538469 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660165 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7591203 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1995684 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755012 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 251600015 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.546380 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.145616 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 178032532 70.76% 70.76% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43398742 17.25% 88.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15483585 6.15% 94.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4358404 1.73% 95.90% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6462138 2.57% 98.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1589340 0.63% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 777430 0.31% 99.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 414440 0.16% 99.57% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1083404 0.43% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 251600015 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113361853 # Number of instructions committed -system.cpu.commit.committedOps 137469268 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113305988 # Number of instructions committed +system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45532382 # Number of memory references committed -system.cpu.commit.loads 24928817 # Number of loads committed -system.cpu.commit.membars 814713 # Number of memory barriers committed -system.cpu.commit.branches 26060941 # Number of branches committed +system.cpu.commit.refs 45511652 # Number of memory references committed +system.cpu.commit.loads 24916104 # Number of loads committed +system.cpu.commit.membars 814017 # Number of memory barriers committed +system.cpu.commit.branches 26045610 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120284813 # Number of committed integer instructions. -system.cpu.commit.function_calls 4896517 # Number of function calls committed. +system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. +system.cpu.commit.function_calls 4892502 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91815303 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 112990 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -964,214 +954,214 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8593 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24928817 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20603565 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137469268 # Class of committed instruction -system.cpu.commit.bw_lim_events 1083404 # number cycles where commit BW limit reached +system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction +system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 373323554 # The number of ROB reads -system.cpu.rob.rob_writes 293054802 # The number of ROB writes -system.cpu.timesIdled 892910 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5969528 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5393544954 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113206948 # Number of Instructions Simulated -system.cpu.committedOps 137314363 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.301147 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.301147 # CPI: Total CPI of All Threads -system.cpu.ipc 0.434566 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.434566 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155872747 # number of integer regfile reads -system.cpu.int_regfile_writes 88664447 # number of integer regfile writes -system.cpu.fp_regfile_reads 9607 # number of floating regfile reads +system.cpu.rob.rob_reads 375672050 # The number of ROB reads +system.cpu.rob.rob_writes 292972268 # The number of ROB writes +system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113151083 # Number of Instructions Simulated +system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155826637 # number of integer regfile reads +system.cpu.int_regfile_writes 88633022 # number of integer regfile writes +system.cpu.fp_regfile_reads 9606 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 503168369 # number of cc regfile reads -system.cpu.cc_regfile_writes 53197006 # number of cc regfile writes -system.cpu.misc_regfile_reads 443775049 # number of misc regfile reads -system.cpu.misc_regfile_writes 1521649 # number of misc regfile writes -system.cpu.dcache.tags.replacements 837844 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.958421 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40169385 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 838356 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.914472 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 244924250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.958421 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999919 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999919 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502981884 # number of cc regfile reads +system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes +system.cpu.misc_regfile_reads 446088161 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839617 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 123 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::2 27 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179425849 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179425849 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23330547 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23330547 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15587007 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15587007 # 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number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3575875 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177079 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177079 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26763 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26763 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 4 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4276498 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4276498 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4453577 # number of overall misses -system.cpu.dcache.overall_misses::total 4453577 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9909110648 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9909110648 # 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number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24031170 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19162882 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523753 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 468737 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 460325 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43194052 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43194052 # 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miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000009 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099007 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099007 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.101871 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.101871 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14143.284831 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14143.284831 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37690.185916 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 37690.185916 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13292.549378 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 44125 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 44125 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 33832.473255 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 33832.473255 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32487.257818 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32487.257818 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 491325 # number of cycles access was blocked +system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # 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average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.680485 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 37149.680485 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.747793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35677.747793 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6982 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7397 # 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number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 11825722463 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1475435001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1475435001 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 109426500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 109426500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 168500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 168500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 17177248878 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 17177248878 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 18652683879 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5792686500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4440468453 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10233154953 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017231 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015627 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.227794 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017731 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000009 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016519 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019050 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019050 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12923.957358 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12923.957358 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39490.289031 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39490.289031 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12366.605768 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12366.605768 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 13166.466129 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13166.466129 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 42125 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 24073.382148 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 24073.382148 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 22396.344913 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 22396.344913 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks +system.cpu.dcache.writebacks::total 696320 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # 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number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235278165 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 18895975323 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458966576 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20458966576 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831900750 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343769701 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # 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average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.042700 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.042700 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.702437 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.702437 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1179,265 +1169,265 @@ system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # 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number of replacements +system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 164 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::2 217 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68134254 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68134254 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64258114 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64258114 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64258114 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64258114 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64258114 # 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number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26765848354 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66239686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66239686 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66239686 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66239686 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66239686 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66239686 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029915 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029915 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029915 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029915 # 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average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1558,65 +1548,61 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2565017 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564966 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteReq 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteResp 27608 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 695426 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2775 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2779 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 296811 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 296811 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3795114 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2495409 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31281 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128693 # 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Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.100630 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::ReadReq 2564423 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2564403 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution +system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499775 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 6455012 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530841 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 220007629 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 62589 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 3563285 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 5.010244 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.100691 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::7 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::8 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::9 3525674 98.98% 98.98% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::10 36444 1.02% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 3526784 98.98% 98.98% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::6 36501 1.02% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::min_value 9 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::max_value 10 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3562118 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2503082512 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::total 3563285 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 2504368234 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.snoopLayer0.occupancy 256500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2849465378 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1334578357 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1338895897 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19552240 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 74992959 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.trans_dist::ReadReq 30181 # Transaction distribution -system.iobus.trans_dist::ReadResp 30181 # Transaction distribution -system.iobus.trans_dist::WriteReq 59038 # Transaction distribution -system.iobus.trans_dist::WriteResp 22814 # Transaction distribution +system.iobus.trans_dist::ReadReq 30182 # Transaction distribution +system.iobus.trans_dist::ReadResp 30182 # Transaction distribution +system.iobus.trans_dist::WriteReq 59014 # Transaction distribution +system.iobus.trans_dist::WriteResp 22790 # Transaction distribution system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54242 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) @@ -1637,11 +1623,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 105550 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.ide.dma::total 72888 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 178438 # Packet count per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67959 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 105478 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.ide.dma::total 72914 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 178392 # Packet count per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67887 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) @@ -1662,11 +1648,11 @@ system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::total 159197 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size::total 2480189 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 38529000 # Layer occupancy (ticks) +system.iobus.pkt_size_system.bridge.master::total 159125 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.realview.ide.dma::total 2321096 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size::total 2480221 # Cumulative packet size per connected master and slave (bytes) +system.iobus.reqLayer0.occupancy 38469000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1706,52 +1692,52 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 347066125 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 82736000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36776514 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.000670 # Cycle average of tags in use +system.iocache.tags.replacements 36423 # number of replacements +system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. +system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 251936772000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000670 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062542 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062542 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id -system.iocache.tags.tag_accesses 327996 # Number of tag accesses -system.iocache.tags.data_accesses 327996 # Number of data accesses -system.iocache.ReadReq_misses::realview.ide 220 # number of ReadReq misses -system.iocache.ReadReq_misses::total 220 # number of ReadReq misses +system.iocache.tags.tag_accesses 328113 # Number of tag accesses +system.iocache.tags.data_accesses 328113 # Number of data accesses +system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses +system.iocache.ReadReq_misses::total 233 # number of ReadReq misses system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses -system.iocache.demand_misses::realview.ide 220 # number of demand (read+write) misses -system.iocache.demand_misses::total 220 # number of demand (read+write) misses -system.iocache.overall_misses::realview.ide 220 # number of overall misses -system.iocache.overall_misses::total 220 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 26427377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 26427377 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 9617153234 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 26427377 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 26427377 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 26427377 # number of overall miss cycles -system.iocache.overall_miss_latency::total 26427377 # number of overall miss cycles -system.iocache.ReadReq_accesses::realview.ide 220 # number of ReadReq accesses(hits+misses) -system.iocache.ReadReq_accesses::total 220 # number of ReadReq accesses(hits+misses) +system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses +system.iocache.demand_misses::total 233 # number of demand (read+write) misses +system.iocache.overall_misses::realview.ide 233 # number of overall misses +system.iocache.overall_misses::total 233 # number of overall misses +system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) +system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.demand_accesses::realview.ide 220 # number of demand (read+write) accesses -system.iocache.demand_accesses::total 220 # number of demand (read+write) accesses -system.iocache.overall_accesses::realview.ide 220 # number of overall (read+write) accesses -system.iocache.overall_accesses::total 220 # number of overall (read+write) accesses +system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses +system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses +system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses +system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses @@ -1760,40 +1746,40 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 120124.440909 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 120124.440909 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 265491.200144 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 120124.440909 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 120124.440909 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 56312 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7225 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 7.794048 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed system.iocache.writebacks::writebacks 36190 # number of writebacks system.iocache.writebacks::total 36190 # number of writebacks -system.iocache.ReadReq_mshr_misses::realview.ide 220 # number of ReadReq MSHR misses -system.iocache.ReadReq_mshr_misses::total 220 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses +system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.demand_mshr_misses::realview.ide 220 # number of demand (read+write) MSHR misses -system.iocache.demand_mshr_misses::total 220 # number of demand (read+write) MSHR misses -system.iocache.overall_mshr_misses::realview.ide 220 # number of overall MSHR misses -system.iocache.overall_mshr_misses::total 220 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 14986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 14986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 7733477262 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 14986377 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 14986377 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 14986377 # number of overall MSHR miss cycles +system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses +system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses +system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses +system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses +system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses @@ -1802,66 +1788,66 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68119.895455 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 68119.895455 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 213490.427948 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68119.895455 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68119.895455 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 67820 # Transaction distribution -system.membus.trans_dist::ReadResp 67819 # Transaction distribution -system.membus.trans_dist::WriteReq 27608 # Transaction distribution -system.membus.trans_dist::WriteResp 27608 # Transaction distribution -system.membus.trans_dist::Writeback 126844 # Transaction distribution +system.membus.trans_dist::ReadReq 68566 # Transaction distribution +system.membus.trans_dist::ReadResp 68565 # Transaction distribution +system.membus.trans_dist::WriteReq 27584 # Transaction distribution +system.membus.trans_dist::WriteResp 27584 # Transaction distribution +system.membus.trans_dist::Writeback 131056 # Transaction distribution system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4542 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4544 # Transaction distribution -system.membus.trans_dist::ReadExReq 135185 # Transaction distribution -system.membus.trans_dist::ReadExResp 135185 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105550 # Packet count per connected master and slave (bytes) +system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution +system.membus.trans_dist::ReadExReq 138681 # Transaction distribution +system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 452612 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 560248 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108873 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 669121 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159197 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465380 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572944 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 681830 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16645096 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 16808561 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186040 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349433 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21444017 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 484 # Total snoops (count) -system.membus.snoop_fanout::samples 336478 # Request fanout histogram +system.membus.pkt_size::total 21984889 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 497 # Total snoops (count) +system.membus.snoop_fanout::samples 345038 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 336478 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 345038 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 336478 # Request fanout histogram -system.membus.reqLayer0.occupancy 94194499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 345038 # Request fanout histogram +system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 10500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1701500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1683962999 # Layer occupancy (ticks) -system.membus.reqLayer5.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 1678430208 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 0.1 # Layer utilization (%) -system.membus.respLayer3.occupancy 38218486 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1057991143 # Layer occupancy (ticks) +system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) +system.membus.respLayer2.occupancy 1020411671 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 0.0 # Layer utilization (%) +system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -1895,6 +1881,6 @@ system.realview.ethernet.coalescedTotal nan # av system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 3039 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 3038 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |