diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt | 2402 |
1 files changed, 1212 insertions, 1190 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt index 2dea4306e..d2ddd8522 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/stats.txt @@ -1,122 +1,122 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.827616 # Number of seconds simulated -sim_ticks 2827616186000 # Number of ticks simulated -final_tick 2827616186000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827546 # Number of seconds simulated +sim_ticks 2827546300000 # Number of ticks simulated +final_tick 2827546300000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70271 # Simulator instruction rate (inst/s) -host_op_rate 85238 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1756065639 # Simulator tick rate (ticks/s) -host_mem_usage 621588 # Number of bytes of host memory used -host_seconds 1610.20 # Real time elapsed on the host -sim_insts 113151083 # Number of instructions simulated -sim_ops 137250963 # Number of ops (including micro ops) simulated +host_inst_rate 69908 # Simulator instruction rate (inst/s) +host_op_rate 84797 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1747497470 # Simulator tick rate (ticks/s) +host_mem_usage 626724 # Number of bytes of host memory used +host_seconds 1618.05 # Real time elapsed on the host +sim_insts 113115023 # Number of instructions simulated +sim_ops 137206411 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.dtb.walker 1344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 1325344 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9769960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 1322768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9763816 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 11098056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 1325344 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1325344 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8387584 # Number of bytes written to this memory +system.physmem.bytes_read::total 11089336 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 1322768 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1322768 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8388544 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8405108 # Number of bytes written to this memory +system.physmem.bytes_written::total 8406068 # Number of bytes written to this memory system.physmem.num_reads::cpu.dtb.walker 21 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 22954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 153176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 22916 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 153080 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 176173 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 131056 # Number of write requests responded to by this memory +system.physmem.num_reads::total 176039 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 131071 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 135437 # Number of write requests responded to by this memory +system.physmem.num_writes::total 135452 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.dtb.walker 475 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 158 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 468714 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3455193 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 467815 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3453106 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3924881 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 468714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 468714 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2966309 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 6197 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2972507 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2966309 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::total 3921894 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 467815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 467815 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2966722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 6198 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2972920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2966722 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 475 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 158 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 468714 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3461391 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 467815 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3459303 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6897387 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 176174 # Number of read requests accepted -system.physmem.writeReqs 171661 # Number of write requests accepted -system.physmem.readBursts 176174 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 171661 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 11266304 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8832 # Total number of bytes read from write queue -system.physmem.bytesWritten 9457344 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 11098120 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10723444 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 138 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23861 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4579 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11334 # Per bank write bursts -system.physmem.perBankRdBursts::1 10890 # Per bank write bursts -system.physmem.perBankRdBursts::2 10732 # Per bank write bursts -system.physmem.perBankRdBursts::3 10393 # Per bank write bursts -system.physmem.perBankRdBursts::4 14045 # Per bank write bursts -system.physmem.perBankRdBursts::5 11531 # Per bank write bursts -system.physmem.perBankRdBursts::6 11498 # Per bank write bursts -system.physmem.perBankRdBursts::7 11674 # Per bank write bursts -system.physmem.perBankRdBursts::8 10645 # Per bank write bursts -system.physmem.perBankRdBursts::9 10993 # Per bank write bursts -system.physmem.perBankRdBursts::10 10307 # Per bank write bursts -system.physmem.perBankRdBursts::11 9597 # Per bank write bursts -system.physmem.perBankRdBursts::12 9956 # Per bank write bursts -system.physmem.perBankRdBursts::13 10908 # Per bank write bursts -system.physmem.perBankRdBursts::14 10689 # Per bank write bursts -system.physmem.perBankRdBursts::15 10844 # Per bank write bursts -system.physmem.perBankWrBursts::0 9257 # Per bank write bursts -system.physmem.perBankWrBursts::1 9346 # Per bank write bursts -system.physmem.perBankWrBursts::2 9336 # Per bank write bursts -system.physmem.perBankWrBursts::3 8962 # Per bank write bursts -system.physmem.perBankWrBursts::4 9705 # Per bank write bursts -system.physmem.perBankWrBursts::5 9746 # Per bank write bursts -system.physmem.perBankWrBursts::6 9125 # Per bank write bursts -system.physmem.perBankWrBursts::7 9630 # Per bank write bursts -system.physmem.perBankWrBursts::8 9307 # Per bank write bursts -system.physmem.perBankWrBursts::9 9634 # Per bank write bursts -system.physmem.perBankWrBursts::10 8942 # Per bank write bursts -system.physmem.perBankWrBursts::11 8449 # Per bank write bursts -system.physmem.perBankWrBursts::12 8881 # Per bank write bursts -system.physmem.perBankWrBursts::13 9361 # Per bank write bursts -system.physmem.perBankWrBursts::14 9018 # Per bank write bursts -system.physmem.perBankWrBursts::15 9072 # Per bank write bursts +system.physmem.bw_total::total 6894813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 176040 # Number of read requests accepted +system.physmem.writeReqs 135452 # Number of write requests accepted +system.physmem.readBursts 176040 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 135452 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 11255936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10624 # Total number of bytes read from write queue +system.physmem.bytesWritten 8418624 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 11089400 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8406068 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 166 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3886 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 40804 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 11283 # Per bank write bursts +system.physmem.perBankRdBursts::1 10909 # Per bank write bursts +system.physmem.perBankRdBursts::2 10879 # Per bank write bursts +system.physmem.perBankRdBursts::3 10544 # Per bank write bursts +system.physmem.perBankRdBursts::4 14049 # Per bank write bursts +system.physmem.perBankRdBursts::5 11359 # Per bank write bursts +system.physmem.perBankRdBursts::6 11255 # Per bank write bursts +system.physmem.perBankRdBursts::7 11497 # Per bank write bursts +system.physmem.perBankRdBursts::8 10572 # Per bank write bursts +system.physmem.perBankRdBursts::9 11295 # Per bank write bursts +system.physmem.perBankRdBursts::10 10218 # Per bank write bursts +system.physmem.perBankRdBursts::11 9589 # Per bank write bursts +system.physmem.perBankRdBursts::12 9979 # Per bank write bursts +system.physmem.perBankRdBursts::13 10701 # Per bank write bursts +system.physmem.perBankRdBursts::14 10842 # Per bank write bursts +system.physmem.perBankRdBursts::15 10903 # Per bank write bursts +system.physmem.perBankWrBursts::0 8346 # Per bank write bursts +system.physmem.perBankWrBursts::1 8306 # Per bank write bursts +system.physmem.perBankWrBursts::2 8514 # Per bank write bursts +system.physmem.perBankWrBursts::3 8219 # Per bank write bursts +system.physmem.perBankWrBursts::4 8602 # Per bank write bursts +system.physmem.perBankWrBursts::5 8561 # Per bank write bursts +system.physmem.perBankWrBursts::6 8053 # Per bank write bursts +system.physmem.perBankWrBursts::7 8529 # Per bank write bursts +system.physmem.perBankWrBursts::8 8073 # Per bank write bursts +system.physmem.perBankWrBursts::9 8804 # Per bank write bursts +system.physmem.perBankWrBursts::10 7852 # Per bank write bursts +system.physmem.perBankWrBursts::11 7407 # Per bank write bursts +system.physmem.perBankWrBursts::12 7747 # Per bank write bursts +system.physmem.perBankWrBursts::13 8181 # Per bank write bursts +system.physmem.perBankWrBursts::14 8268 # Per bank write bursts +system.physmem.perBankWrBursts::15 8079 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 58 # Number of times write queue was full causing retry -system.physmem.totGap 2827615975000 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2827546089000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 542 # Read request sizes (log2) system.physmem.readPktSize::3 14 # Read request sizes (log2) -system.physmem.readPktSize::4 2994 # Read request sizes (log2) +system.physmem.readPktSize::4 2997 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 172624 # Read request sizes (log2) +system.physmem.readPktSize::6 172487 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4381 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 167280 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 154910 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 18105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see +system.physmem.writePktSize::6 131071 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 154804 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 17996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 828 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 1 # What read queue length does an incoming req see @@ -159,161 +159,156 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 6016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 6189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6399 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8194 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 6687 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7233 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 8649 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 7316 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 9234 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 7906 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7485 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 899 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1255 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 2077 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1665 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1476 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1370 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 216 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 196 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 154 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 90 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 104 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 97 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 77 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 87 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 66219 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 312.955255 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 183.034234 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 334.173316 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 24625 37.19% 37.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 15873 23.97% 61.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6865 10.37% 71.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3626 5.48% 77.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2732 4.13% 81.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1677 2.53% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 1136 1.72% 85.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1168 1.76% 87.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8517 12.86% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 66219 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6252 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.154671 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 564.033809 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6251 99.98% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::43008-45055 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6252 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6252 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.635797 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.335011 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 41.227878 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 5914 94.59% 94.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 86 1.38% 95.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 17 0.27% 96.24% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 16 0.26% 96.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 17 0.27% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 30 0.48% 97.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 32 0.51% 97.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 14 0.22% 97.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 17 0.27% 98.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 6 0.10% 98.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 22 0.35% 98.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 18 0.29% 98.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 1 0.02% 99.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 1 0.02% 99.14% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 6 0.10% 99.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 4 0.06% 99.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 4 0.06% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 3 0.05% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 5 0.08% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 16 0.26% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 2 0.03% 99.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 3 0.05% 99.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::400-415 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::448-463 1 0.02% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 3 0.05% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::496-511 1 0.02% 99.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 1 0.02% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::704-719 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::752-767 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::864-879 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6252 # Writes before turning the bus around for reads -system.physmem.totQLat 2104913750 # Total ticks spent queuing -system.physmem.totMemAccLat 5405588750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 880180000 # Total ticks spent in databus transfers -system.physmem.avgQLat 11957.29 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 2635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 6262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 6796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 6764 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6948 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8242 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8550 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 9754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 8859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 7952 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 8201 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 8147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 7161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 7090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 6942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 296 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 134 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 130 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 154 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 110 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 66 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 106 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 76 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 46 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 6 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 11 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 2 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 65199 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 301.760702 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 178.342640 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 324.505125 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 24507 37.59% 37.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 15999 24.54% 62.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6852 10.51% 72.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3716 5.70% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2634 4.04% 82.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1687 2.59% 84.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 1128 1.73% 86.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1089 1.67% 88.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 7587 11.64% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 65199 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6653 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 26.433789 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 560.061521 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6652 99.98% 99.98% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6653 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6653 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.771682 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.345316 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.497785 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5824 87.54% 87.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 71 1.07% 88.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 181 2.72% 91.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 53 0.80% 92.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 64 0.96% 93.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 178 2.68% 95.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 29 0.44% 96.20% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 6 0.09% 96.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.14% 96.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 9 0.14% 96.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 8 0.12% 96.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.09% 96.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 170 2.56% 99.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 6 0.09% 99.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 8 0.12% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.02% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 2 0.03% 99.67% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 4 0.06% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.02% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.02% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.02% 99.77% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 11 0.17% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.02% 99.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.02% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6653 # Writes before turning the bus around for reads +system.physmem.totQLat 2123501000 # Total ticks spent queuing +system.physmem.totMemAccLat 5421138500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 879370000 # Total ticks spent in databus transfers +system.physmem.avgQLat 12073.99 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30707.29 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30823.99 # Average memory access latency per DRAM burst system.physmem.avgRdBW 3.98 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.34 # Average achieved write bandwidth in MiByte/s +system.physmem.avgWrBW 2.98 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 3.92 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.79 # Average system write bandwidth in MiByte/s +system.physmem.avgWrBWSys 2.97 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.06 # Data bus utilization in percentage +system.physmem.busUtil 0.05 # Data bus utilization in percentage system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads -system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes +system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 25.89 # Average write queue length when enqueuing -system.physmem.readRowHits 145058 # Number of row buffer hits during reads -system.physmem.writeRowHits 112529 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.40 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 76.14 # Row buffer hit rate for writes -system.physmem.avgGap 8129187.62 # Average gap between requests -system.physmem.pageHitRate 79.54 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 260517600 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 142147500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 718356600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 486693360 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 81488169855 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625088668250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1892870659965 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.422846 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2703351122494 # Time in different power states -system.physmem_0.memoryStateTime::REF 94420300000 # Time in different power states +system.physmem.avgWrQLen 24.42 # Average write queue length when enqueuing +system.physmem.readRowHits 144861 # Number of row buffer hits during reads +system.physmem.writeRowHits 97354 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.37 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 74.00 # Row buffer hit rate for writes +system.physmem.avgGap 9077427.64 # Average gap between requests +system.physmem.pageHitRate 78.78 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 255989160 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 139676625 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 715845000 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 435002400 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 81048006450 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625432730750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892708780145 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.382186 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2703925000250 # Time in different power states +system.physmem_0.memoryStateTime::REF 94417960000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 29844456256 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29202842250 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 240098040 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 131005875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 654716400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 470862720 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184686106800 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80123990850 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1626285316500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1892592097185 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.324331 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2705354976994 # Time in different power states -system.physmem_1.memoryStateTime::REF 94420300000 # Time in different power states +system.physmem_1.actEnergy 236915280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 129269250 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 655964400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 417383280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184681529760 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80055144540 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626303662250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892479868760 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.301228 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705388162750 # Time in different power states +system.physmem_1.memoryStateTime::REF 94417960000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27840895506 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27740163750 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 128 # Number of bytes read from this memory @@ -333,15 +328,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu.branchPred.lookups 46937284 # Number of BP lookups -system.cpu.branchPred.condPredicted 24041936 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 1233234 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 29553356 # Number of BTB lookups -system.cpu.branchPred.BTBHits 21362007 # Number of BTB hits +system.cpu.branchPred.lookups 46902830 # Number of BP lookups +system.cpu.branchPred.condPredicted 24030897 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 1232795 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 29532360 # Number of BTB lookups +system.cpu.branchPred.BTBHits 21346058 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 72.282847 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 11754741 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 33891 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 72.280231 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 11742213 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 33846 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -372,45 +367,45 @@ system.cpu.checker.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.checker.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.checker.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.checker.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.checker.dtb.walker.walks 9923 # Table walker walks requested -system.cpu.checker.dtb.walker.walksShort 9923 # Table walker walks initiated with short descriptors -system.cpu.checker.dtb.walker.walkWaitTime::samples 9923 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::0 9923 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walkWaitTime::total 9923 # Table walker wait (enqueue to first request) latency -system.cpu.checker.dtb.walker.walksPending::samples 230116500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::0 230116500 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walksPending::total 230116500 # Table walker pending requests distribution -system.cpu.checker.dtb.walker.walkPageSizes::4K 6339 81.70% 81.70% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::1M 1420 18.30% 100.00% # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkPageSizes::total 7759 # Table walker page sizes translated -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9923 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walks 9925 # Table walker walks requested +system.cpu.checker.dtb.walker.walksShort 9925 # Table walker walks initiated with short descriptors +system.cpu.checker.dtb.walker.walkWaitTime::samples 9925 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::0 9925 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walkWaitTime::total 9925 # Table walker wait (enqueue to first request) latency +system.cpu.checker.dtb.walker.walksPending::samples 227240000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::0 227240000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walksPending::total 227240000 # Table walker pending requests distribution +system.cpu.checker.dtb.walker.walkPageSizes::4K 6352 81.85% 81.85% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::1M 1409 18.15% 100.00% # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkPageSizes::total 7761 # Table walker page sizes translated +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Data 9925 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9923 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7759 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Requested::total 9925 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Data 7761 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7759 # Table walker requests started/completed, data/inst -system.cpu.checker.dtb.walker.walkRequestOrigin::total 17682 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin_Completed::total 7761 # Table walker requests started/completed, data/inst +system.cpu.checker.dtb.walker.walkRequestOrigin::total 17686 # Table walker requests started/completed, data/inst system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses -system.cpu.checker.dtb.read_hits 24588859 # DTB read hits -system.cpu.checker.dtb.read_misses 8478 # DTB read misses -system.cpu.checker.dtb.write_hits 19638229 # DTB write hits -system.cpu.checker.dtb.write_misses 1445 # DTB write misses +system.cpu.checker.dtb.read_hits 24580805 # DTB read hits +system.cpu.checker.dtb.read_misses 8471 # DTB read misses +system.cpu.checker.dtb.write_hits 19633932 # DTB write hits +system.cpu.checker.dtb.write_misses 1454 # DTB write misses system.cpu.checker.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.checker.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.checker.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.checker.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.checker.dtb.flush_entries 4321 # Number of entries that have been flushed from TLB system.cpu.checker.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu.checker.dtb.prefetch_faults 1767 # Number of TLB faults due to prefetch +system.cpu.checker.dtb.prefetch_faults 1778 # Number of TLB faults due to prefetch system.cpu.checker.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.checker.dtb.perms_faults 445 # Number of TLB faults due to permissions restrictions -system.cpu.checker.dtb.read_accesses 24597337 # DTB read accesses -system.cpu.checker.dtb.write_accesses 19639674 # DTB write accesses +system.cpu.checker.dtb.read_accesses 24589276 # DTB read accesses +system.cpu.checker.dtb.write_accesses 19635386 # DTB write accesses system.cpu.checker.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.checker.dtb.hits 44227088 # DTB hits -system.cpu.checker.dtb.misses 9923 # DTB misses -system.cpu.checker.dtb.accesses 44237011 # DTB accesses +system.cpu.checker.dtb.hits 44214737 # DTB hits +system.cpu.checker.dtb.misses 9925 # DTB misses +system.cpu.checker.dtb.accesses 44224662 # DTB accesses system.cpu.checker.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.checker.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -445,9 +440,9 @@ system.cpu.checker.itb.walker.walksShort 4826 # Ta system.cpu.checker.itb.walker.walkWaitTime::samples 4826 # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::0 4826 100.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.checker.itb.walker.walkWaitTime::total 4826 # Table walker wait (enqueue to first request) latency -system.cpu.checker.itb.walker.walksPending::samples 229704000 # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::0 229704000 100.00% 100.00% # Table walker pending requests distribution -system.cpu.checker.itb.walker.walksPending::total 229704000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::samples 226829000 # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::0 226829000 100.00% 100.00% # Table walker pending requests distribution +system.cpu.checker.itb.walker.walksPending::total 226829000 # Table walker pending requests distribution system.cpu.checker.itb.walker.walkPageSizes::4K 2798 88.24% 88.24% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::1M 373 11.76% 100.00% # Table walker page sizes translated system.cpu.checker.itb.walker.walkPageSizes::total 3171 # Table walker page sizes translated @@ -458,7 +453,7 @@ system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Data 0 system.cpu.checker.itb.walker.walkRequestOrigin_Completed::Inst 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin_Completed::total 3171 # Table walker requests started/completed, data/inst system.cpu.checker.itb.walker.walkRequestOrigin::total 7997 # Table walker requests started/completed, data/inst -system.cpu.checker.itb.inst_hits 115853330 # ITB inst hits +system.cpu.checker.itb.inst_hits 115815180 # ITB inst hits system.cpu.checker.itb.inst_misses 4826 # ITB inst misses system.cpu.checker.itb.read_hits 0 # DTB read hits system.cpu.checker.itb.read_misses 0 # DTB read misses @@ -475,11 +470,11 @@ system.cpu.checker.itb.domain_faults 0 # Nu system.cpu.checker.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.checker.itb.read_accesses 0 # DTB read accesses system.cpu.checker.itb.write_accesses 0 # DTB write accesses -system.cpu.checker.itb.inst_accesses 115858156 # ITB inst accesses -system.cpu.checker.itb.hits 115853330 # DTB hits +system.cpu.checker.itb.inst_accesses 115820006 # ITB inst accesses +system.cpu.checker.itb.hits 115815180 # DTB hits system.cpu.checker.itb.misses 4826 # DTB misses -system.cpu.checker.itb.accesses 115858156 # DTB accesses -system.cpu.checker.numCycles 139105254 # number of cpu cycles simulated +system.cpu.checker.itb.accesses 115820006 # DTB accesses +system.cpu.checker.numCycles 139058612 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -511,84 +506,86 @@ system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.dtb.walker.walks 72371 # Table walker walks requested -system.cpu.dtb.walker.walksShort 72371 # Table walker walks initiated with short descriptors -system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29709 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22637 # Level at which table walker walks with short descriptors terminate -system.cpu.dtb.walker.walksSquashedBefore 20025 # Table walks squashed before starting -system.cpu.dtb.walker.walkWaitTime::samples 52346 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::mean 408.397967 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::stdev 2384.163324 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::0-4095 50769 96.99% 96.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::4096-8191 522 1.00% 97.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::8192-12287 392 0.75% 98.73% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::12288-16383 322 0.62% 99.35% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::16384-20479 112 0.21% 99.56% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::20480-24575 191 0.36% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::24576-28671 14 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::28672-32767 8 0.02% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::36864-40959 2 0.00% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walks 72877 # Table walker walks requested +system.cpu.dtb.walker.walksShort 72877 # Table walker walks initiated with short descriptors +system.cpu.dtb.walker.walksShortTerminationLevel::Level1 29786 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksShortTerminationLevel::Level2 22407 # Level at which table walker walks with short descriptors terminate +system.cpu.dtb.walker.walksSquashedBefore 20684 # Table walks squashed before starting +system.cpu.dtb.walker.walkWaitTime::samples 52193 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::mean 427.193302 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::stdev 2519.151181 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::0-4095 50372 96.51% 96.51% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::4096-8191 577 1.11% 97.62% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::8192-12287 541 1.04% 98.65% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::12288-16383 349 0.67% 99.32% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::16384-20479 64 0.12% 99.44% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::20480-24575 245 0.47% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::24576-28671 20 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::28672-32767 5 0.01% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::32768-36863 6 0.01% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::36864-40959 4 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::40960-45055 5 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::45056-49151 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::45056-49151 3 0.01% 100.00% # Table walker wait (enqueue to first request) latency system.cpu.dtb.walker.walkWaitTime::49152-53247 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::61440-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkWaitTime::total 52346 # Table walker wait (enqueue to first request) latency -system.cpu.dtb.walker.walkCompletionTime::samples 17999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::mean 11613.492583 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::gmean 9112.637070 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::stdev 7625.312992 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::0-16383 13355 74.20% 74.20% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::16384-32767 4455 24.75% 98.95% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::32768-49151 181 1.01% 99.96% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.98% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkWaitTime::53248-57343 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkWaitTime::total 52193 # Table walker wait (enqueue to first request) latency +system.cpu.dtb.walker.walkCompletionTime::samples 18420 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::mean 12316.720955 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::gmean 9894.996282 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::stdev 7919.116299 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::0-16383 13659 74.15% 74.15% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::16384-32767 4520 24.54% 98.69% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::32768-49151 229 1.24% 99.93% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::49152-65535 5 0.03% 99.96% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::65536-81919 1 0.01% 99.97% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.99% # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walkCompletionTime::total 17999 # Table walker service (enqueue to completion) latency -system.cpu.dtb.walker.walksPending::samples 117490693224 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::mean 0.629020 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::stdev 0.491115 # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::0-1 117435257724 99.95% 99.95% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::2-3 37744500 0.03% 99.98% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::4-5 7698500 0.01% 99.99% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::6-7 6179000 0.01% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::8-9 1033000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::10-11 848500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::12-13 1404000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::14-15 520500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::16-17 7500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.dtb.walker.walksPending::total 117490693224 # Table walker pending requests distribution -system.cpu.dtb.walker.walkPageSizes::4K 6498 81.61% 81.61% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::1M 1464 18.39% 100.00% # Table walker page sizes translated -system.cpu.dtb.walker.walkPageSizes::total 7962 # Table walker page sizes translated -system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72371 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkCompletionTime::total 18420 # Table walker service (enqueue to completion) latency +system.cpu.dtb.walker.walksPending::samples 117420807224 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::mean 0.629573 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::stdev 0.491742 # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::0-1 117361135224 99.95% 99.95% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::2-3 40228000 0.03% 99.98% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::4-5 8514000 0.01% 99.99% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::6-7 6836000 0.01% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::8-9 1132500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::10-11 742000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::12-13 1403500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::14-15 806000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::16-17 10000 0.00% 100.00% # Table walker pending requests distribution +system.cpu.dtb.walker.walksPending::total 117420807224 # Table walker pending requests distribution +system.cpu.dtb.walker.walkPageSizes::4K 6507 81.76% 81.76% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::1M 1452 18.24% 100.00% # Table walker page sizes translated +system.cpu.dtb.walker.walkPageSizes::total 7959 # Table walker page sizes translated +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 72877 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72371 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7962 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 72877 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 7959 # Table walker requests started/completed, data/inst system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7962 # Table walker requests started/completed, data/inst -system.cpu.dtb.walker.walkRequestOrigin::total 80333 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 7959 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 80836 # Table walker requests started/completed, data/inst system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 25461869 # DTB read hits -system.cpu.dtb.read_misses 62291 # DTB read misses -system.cpu.dtb.write_hits 19915387 # DTB write hits -system.cpu.dtb.write_misses 10080 # DTB write misses +system.cpu.dtb.read_hits 25454298 # DTB read hits +system.cpu.dtb.read_misses 62609 # DTB read misses +system.cpu.dtb.write_hits 19910353 # DTB write hits +system.cpu.dtb.write_misses 10268 # DTB write misses system.cpu.dtb.flush_tlb 128 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID system.cpu.dtb.flush_entries 4354 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 348 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 2290 # Number of TLB faults due to prefetch +system.cpu.dtb.align_faults 354 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 2301 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1335 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 25524160 # DTB read accesses -system.cpu.dtb.write_accesses 19925467 # DTB write accesses +system.cpu.dtb.perms_faults 1336 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 25516907 # DTB read accesses +system.cpu.dtb.write_accesses 19920621 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 45377256 # DTB hits -system.cpu.dtb.misses 72371 # DTB misses -system.cpu.dtb.accesses 45449627 # DTB accesses +system.cpu.dtb.hits 45364651 # DTB hits +system.cpu.dtb.misses 72877 # DTB misses +system.cpu.dtb.accesses 45437528 # DTB accesses system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -618,56 +615,56 @@ system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu.itb.walker.walks 11974 # Table walker walks requested -system.cpu.itb.walker.walksShort 11974 # Table walker walks initiated with short descriptors -system.cpu.itb.walker.walksShortTerminationLevel::Level1 3948 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksShortTerminationLevel::Level2 7776 # Level at which table walker walks with short descriptors terminate -system.cpu.itb.walker.walksSquashedBefore 250 # Table walks squashed before starting -system.cpu.itb.walker.walkWaitTime::samples 11724 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::mean 570.794951 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::stdev 2803.545728 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::0-8191 11373 97.01% 97.01% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::8192-16383 269 2.29% 99.30% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::16384-24575 71 0.61% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::24576-32767 7 0.06% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walks 11947 # Table walker walks requested +system.cpu.itb.walker.walksShort 11947 # Table walker walks initiated with short descriptors +system.cpu.itb.walker.walksShortTerminationLevel::Level1 3916 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksShortTerminationLevel::Level2 7772 # Level at which table walker walks with short descriptors terminate +system.cpu.itb.walker.walksSquashedBefore 259 # Table walks squashed before starting +system.cpu.itb.walker.walkWaitTime::samples 11688 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::mean 646.175565 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::stdev 3062.873414 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::0-8191 11278 96.49% 96.49% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::8192-16383 250 2.14% 98.63% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::16384-24575 145 1.24% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::24576-32767 11 0.09% 99.97% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::40960-49151 1 0.01% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::49152-57343 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::57344-65535 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkWaitTime::65536-73727 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu.itb.walker.walkWaitTime::73728-81919 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkWaitTime::total 11724 # Table walker wait (enqueue to first request) latency -system.cpu.itb.walker.walkCompletionTime::samples 3579 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::mean 12176.865046 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::gmean 9546.126127 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::stdev 7774.383636 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::0-8191 1294 36.16% 36.16% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::8192-16383 1330 37.16% 73.32% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::16384-24575 901 25.17% 98.49% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::24576-32767 22 0.61% 99.11% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::32768-40959 25 0.70% 99.80% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::40960-49151 5 0.14% 99.94% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkWaitTime::total 11688 # Table walker wait (enqueue to first request) latency +system.cpu.itb.walker.walkCompletionTime::samples 3588 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::mean 13165.830546 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::gmean 10749.838149 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::stdev 7878.482425 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::0-8191 1266 35.28% 35.28% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::8192-16383 1353 37.71% 72.99% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::16384-24575 898 25.03% 98.02% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::24576-32767 28 0.78% 98.80% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::32768-40959 19 0.53% 99.33% # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walkCompletionTime::40960-49151 22 0.61% 99.94% # Table walker service (enqueue to completion) latency system.cpu.itb.walker.walkCompletionTime::81920-90111 2 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walkCompletionTime::total 3579 # Table walker service (enqueue to completion) latency -system.cpu.itb.walker.walksPending::samples 23001352712 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::mean 0.973391 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::stdev 0.161136 # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::0 612637000 2.66% 2.66% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::1 22388223712 97.33% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::2 416000 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::3 45500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::4 30500 0.00% 100.00% # Table walker pending requests distribution -system.cpu.itb.walker.walksPending::total 23001352712 # Table walker pending requests distribution +system.cpu.itb.walker.walkCompletionTime::total 3588 # Table walker service (enqueue to completion) latency +system.cpu.itb.walker.walksPending::samples 22931465712 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::mean 0.972560 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::stdev 0.163591 # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::0 629948000 2.75% 2.75% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::1 22300919212 97.25% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::2 517500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::3 46500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::4 34500 0.00% 100.00% # Table walker pending requests distribution +system.cpu.itb.walker.walksPending::total 22931465712 # Table walker pending requests distribution system.cpu.itb.walker.walkPageSizes::4K 3007 90.33% 90.33% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::1M 322 9.67% 100.00% # Table walker page sizes translated system.cpu.itb.walker.walkPageSizes::total 3329 # Table walker page sizes translated system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11974 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin_Requested::total 11974 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 11947 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 11947 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 3329 # Table walker requests started/completed, data/inst system.cpu.itb.walker.walkRequestOrigin_Completed::total 3329 # Table walker requests started/completed, data/inst -system.cpu.itb.walker.walkRequestOrigin::total 15303 # Table walker requests started/completed, data/inst -system.cpu.itb.inst_hits 66270436 # ITB inst hits -system.cpu.itb.inst_misses 11974 # ITB inst misses +system.cpu.itb.walker.walkRequestOrigin::total 15276 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 66251443 # ITB inst hits +system.cpu.itb.inst_misses 11947 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -676,98 +673,98 @@ system.cpu.itb.flush_tlb 128 # Nu system.cpu.itb.flush_tlb_mva 1834 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 3095 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 3094 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2189 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2204 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 66282410 # ITB inst accesses -system.cpu.itb.hits 66270436 # DTB hits -system.cpu.itb.misses 11974 # DTB misses -system.cpu.itb.accesses 66282410 # DTB accesses -system.cpu.numCycles 263104506 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 66263390 # ITB inst accesses +system.cpu.itb.hits 66251443 # DTB hits +system.cpu.itb.misses 11947 # DTB misses +system.cpu.itb.accesses 66263390 # DTB accesses +system.cpu.numCycles 263015768 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 104871759 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 184678718 # Number of instructions fetch has processed -system.cpu.fetch.Branches 46937284 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 33116748 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 147875517 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 6159108 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 184684 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.MiscStallCycles 7836 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 337023 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 520063 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 109 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 66270632 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 1094853 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5249 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 256876545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.877001 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.234757 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 104824855 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 184645834 # Number of instructions fetch has processed +system.cpu.fetch.Branches 46902830 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 33088271 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 147851260 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 6154028 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 194015 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.MiscStallCycles 8214 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 337761 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 519343 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 115 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 66251613 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 1117287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5276 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 256812577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.876982 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.234768 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 157598366 61.35% 61.35% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 29238251 11.38% 72.73% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 14077167 5.48% 78.21% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 55962761 21.79% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 157563978 61.35% 61.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 29227624 11.38% 72.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 14070468 5.48% 78.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 55950507 21.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 256876545 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.178398 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.701922 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 78017085 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 107782223 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 64633482 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 3841952 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2601803 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 3422699 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 486058 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 157446500 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 3690202 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2601803 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 83861883 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 10277178 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 74822964 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 62634848 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 22677869 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 146804130 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 949467 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 441862 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 64017 # Number of times rename has blocked due to IQ full -system.cpu.rename.LQFullEvents 17858 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 19908152 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 150492299 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 678751292 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 164435882 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10966 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 141814735 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 8677561 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 2844686 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 2648369 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 13872312 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 26410080 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 21300681 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1687720 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2166938 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 143540852 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2119167 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 143328298 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 272168 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8409052 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14689564 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 125312 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 256876545 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.557966 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.879925 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 256812577 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.178327 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.702033 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 77991094 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 107772330 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 64608850 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 3840943 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2599360 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 3422500 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 485951 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 157387425 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 3689294 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2599360 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 83831420 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 10325294 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 74929297 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 62613486 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 22513720 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 146758942 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 947731 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 441861 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 64728 # Number of times rename has blocked due to IQ full +system.cpu.rename.LQFullEvents 18116 # Number of times rename has blocked due to LQ full +system.cpu.rename.SQFullEvents 19773665 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 150448126 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 678536041 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 164391886 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10952 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 141768145 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 8679978 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 2842610 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 2646257 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 13861181 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 26401367 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 21296245 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1688204 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2197018 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 143495141 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 2119201 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 143282260 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 272024 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8407927 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14689646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 125355 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 256812577 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.557925 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.879880 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 168573864 65.62% 65.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 45206232 17.60% 83.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 31980064 12.45% 95.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 10303635 4.01% 99.68% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 812717 0.32% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 168546355 65.63% 65.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 45160300 17.58% 83.22% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 32009606 12.46% 95.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 10282549 4.00% 99.68% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 813734 0.32% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 33 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -775,44 +772,44 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 256876545 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 256812577 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 7356620 32.59% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 33 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.59% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 5633879 24.95% 57.54% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 9585743 42.46% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 7349115 32.77% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 31 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 32.77% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 5633990 25.12% 57.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 9444813 42.11% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2337 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 96002656 66.98% 66.98% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 114517 0.08% 67.06% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 95970305 66.98% 66.98% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 114498 0.08% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.06% # Type of FU issued @@ -836,101 +833,101 @@ system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.06% # Ty system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.06% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.06% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 8586 0.01% 67.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 8584 0.01% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.07% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.07% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 26193106 18.27% 85.34% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 21007096 14.66% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 26184358 18.27% 85.34% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 21002178 14.66% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 143328298 # Type of FU issued -system.cpu.iq.rate 0.544758 # Inst issue rate -system.cpu.iq.fu_busy_cnt 22576275 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.157514 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 566346237 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 154074171 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 140211060 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 35347 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 13216 # Number of floating instruction queue writes +system.cpu.iq.FU_type_0::total 143282260 # Type of FU issued +system.cpu.iq.rate 0.544767 # Inst issue rate +system.cpu.iq.fu_busy_cnt 22427949 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.156530 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 566041717 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 154027392 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 140167901 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 35353 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 13184 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 11430 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 165879208 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 23028 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 323617 # Number of loads that had data forwarded from stores +system.cpu.iq.int_alu_accesses 165684822 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 23050 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 323667 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1493976 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1493736 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 505 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18357 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 705133 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 18344 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 705002 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 87833 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 6849 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 87759 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 6780 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2601803 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 997477 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 311742 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 145861072 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 2599360 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 993976 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 306451 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 145815403 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 26410080 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 21300681 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1095001 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 17866 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 276819 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18357 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 317506 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 471434 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 788940 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 142382517 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 25789725 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 873528 # Number of squashed instructions skipped in execute +system.cpu.iew.iewDispLoadInsts 26401367 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 21296245 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1095018 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 17939 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 271517 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 18344 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 317394 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 471153 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 788547 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 142337327 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 25781702 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 872174 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 201053 # number of nop insts executed -system.cpu.iew.exec_refs 46667574 # number of memory reference insts executed -system.cpu.iew.exec_branches 26530134 # Number of branches executed -system.cpu.iew.exec_stores 20877849 # Number of stores executed -system.cpu.iew.exec_rate 0.541163 # Inst execution rate -system.cpu.iew.wb_sent 141996041 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 140222490 # cumulative count of insts written-back -system.cpu.iew.wb_producers 63271750 # num instructions producing a value -system.cpu.iew.wb_consumers 95823649 # num instructions consuming a value +system.cpu.iew.exec_nop 201061 # number of nop insts executed +system.cpu.iew.exec_refs 46654499 # number of memory reference insts executed +system.cpu.iew.exec_branches 26517785 # Number of branches executed +system.cpu.iew.exec_stores 20872797 # Number of stores executed +system.cpu.iew.exec_rate 0.541174 # Inst execution rate +system.cpu.iew.wb_sent 141950761 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 140179331 # cumulative count of insts written-back +system.cpu.iew.wb_producers 63256602 # num instructions producing a value +system.cpu.iew.wb_consumers 95788019 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.532954 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.660294 # average fanout of values written-back +system.cpu.iew.wb_rate 0.532969 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.660381 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 7612502 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1993855 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 755483 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 253938585 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.541099 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.141491 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 7614067 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1993846 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 755141 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 253876624 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.541055 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.141749 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 180469459 71.07% 71.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 43296577 17.05% 88.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 15470824 6.09% 94.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 4378580 1.72% 95.93% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 6397908 2.52% 98.45% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 1648304 0.65% 99.10% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 799189 0.31% 99.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 418335 0.16% 99.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 1059409 0.42% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 180454723 71.08% 71.08% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 43255238 17.04% 88.12% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 15471181 6.09% 94.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 4380130 1.73% 95.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 6364867 2.51% 98.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 1673276 0.66% 99.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 800938 0.32% 99.42% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 418318 0.16% 99.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 1057953 0.42% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 253938585 # Number of insts commited each cycle -system.cpu.commit.committedInsts 113305988 # Number of instructions committed -system.cpu.commit.committedOps 137405868 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 253876624 # Number of insts commited each cycle +system.cpu.commit.committedInsts 113269928 # Number of instructions committed +system.cpu.commit.committedOps 137361316 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 45511652 # Number of memory references committed -system.cpu.commit.loads 24916104 # Number of loads committed -system.cpu.commit.membars 814017 # Number of memory barriers committed -system.cpu.commit.branches 26045610 # Number of branches committed +system.cpu.commit.refs 45498874 # Number of memory references committed +system.cpu.commit.loads 24907631 # Number of loads committed +system.cpu.commit.membars 814016 # Number of memory barriers committed +system.cpu.commit.branches 26032948 # Number of branches committed system.cpu.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu.commit.int_insts 120229462 # Number of committed integer instructions. -system.cpu.commit.function_calls 4892502 # Number of function calls committed. +system.cpu.commit.int_insts 120189151 # Number of committed integer instructions. +system.cpu.commit.function_calls 4888294 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 91772138 66.79% 66.79% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 113493 0.08% 66.87% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 91740391 66.79% 66.79% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 113468 0.08% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::IntDiv 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatAdd 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::FloatCmp 0 0.00% 66.87% # Class of committed instruction @@ -954,489 +951,501 @@ system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 66.87% # system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 66.87% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 66.87% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatMisc 8585 0.01% 66.88% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatMisc 8583 0.01% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.88% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.88% # Class of committed instruction -system.cpu.commit.op_class_0::MemRead 24916104 18.13% 85.01% # Class of committed instruction -system.cpu.commit.op_class_0::MemWrite 20595548 14.99% 100.00% # Class of committed instruction +system.cpu.commit.op_class_0::MemRead 24907631 18.13% 85.01% # Class of committed instruction +system.cpu.commit.op_class_0::MemWrite 20591243 14.99% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 137405868 # Class of committed instruction -system.cpu.commit.bw_lim_events 1059409 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 375672050 # The number of ROB reads -system.cpu.rob.rob_writes 292972268 # The number of ROB writes -system.cpu.timesIdled 891577 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6227961 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 5392127867 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 113151083 # Number of Instructions Simulated -system.cpu.committedOps 137250963 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 2.325250 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.325250 # CPI: Total CPI of All Threads -system.cpu.ipc 0.430061 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.430061 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 155826636 # number of integer regfile reads -system.cpu.int_regfile_writes 88633022 # number of integer regfile writes -system.cpu.fp_regfile_reads 9606 # number of floating regfile reads +system.cpu.commit.op_class_0::total 137361316 # Class of committed instruction +system.cpu.commit.bw_lim_events 1057953 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 375595727 # The number of ROB reads +system.cpu.rob.rob_writes 292884314 # The number of ROB writes +system.cpu.timesIdled 891951 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 6203191 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 5392076833 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 113115023 # Number of Instructions Simulated +system.cpu.committedOps 137206411 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 2.325206 # CPI: Cycles Per Instruction +system.cpu.cpi_total 2.325206 # CPI: Total CPI of All Threads +system.cpu.ipc 0.430069 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.430069 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 155781292 # number of integer regfile reads +system.cpu.int_regfile_writes 88602574 # number of integer regfile writes +system.cpu.fp_regfile_reads 9590 # number of floating regfile reads system.cpu.fp_regfile_writes 2716 # number of floating regfile writes -system.cpu.cc_regfile_reads 502981881 # number of cc regfile reads -system.cpu.cc_regfile_writes 53178096 # number of cc regfile writes -system.cpu.misc_regfile_reads 334359649 # number of misc regfile reads -system.cpu.misc_regfile_writes 1519760 # number of misc regfile writes -system.cpu.dcache.tags.replacements 839617 # number of replacements -system.cpu.dcache.tags.tagsinuse 511.954240 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 40126369 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 840129 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 47.762152 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 270754250 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 511.954240 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.999911 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.999911 # Average percentage of cache occupancy +system.cpu.cc_regfile_reads 502823667 # number of cc regfile reads +system.cpu.cc_regfile_writes 53168068 # number of cc regfile writes +system.cpu.misc_regfile_reads 334407132 # number of misc regfile reads +system.cpu.misc_regfile_writes 1519751 # number of misc regfile writes +system.cpu.dcache.tags.replacements 839265 # number of replacements +system.cpu.dcache.tags.tagsinuse 511.954798 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 40095385 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 839777 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 47.745276 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 267431500 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 511.954798 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.999912 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.999912 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 359 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 360 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::2 28 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 179354797 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 179354797 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 23316087 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 23316087 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 15561026 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 15561026 # number of WriteReq hits -system.cpu.dcache.SoftPFReq_hits::cpu.data 345829 # number of SoftPFReq hits -system.cpu.dcache.SoftPFReq_hits::total 345829 # number of SoftPFReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 441066 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 441066 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 459481 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 459481 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 38877113 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 38877113 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 39222942 # number of overall hits -system.cpu.dcache.overall_hits::total 39222942 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 705718 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 705718 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 3595150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 3595150 # number of WriteReq misses -system.cpu.dcache.SoftPFReq_misses::cpu.data 177438 # number of SoftPFReq misses -system.cpu.dcache.SoftPFReq_misses::total 177438 # number of SoftPFReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 26862 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 26862 # number of LoadLockedReq misses +system.cpu.dcache.tags.tag_accesses 179307579 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 179307579 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 23304230 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 23304230 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 15542006 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 15542006 # number of WriteReq hits +system.cpu.dcache.SoftPFReq_hits::cpu.data 345703 # number of SoftPFReq hits +system.cpu.dcache.SoftPFReq_hits::total 345703 # number of SoftPFReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 441081 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 441081 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 459484 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 459484 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 38846236 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 38846236 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 39191939 # number of overall hits +system.cpu.dcache.overall_hits::total 39191939 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 710133 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 710133 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 3609878 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 3609878 # number of WriteReq misses +system.cpu.dcache.SoftPFReq_misses::cpu.data 177558 # number of SoftPFReq misses +system.cpu.dcache.SoftPFReq_misses::total 177558 # number of SoftPFReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 26867 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 26867 # number of LoadLockedReq misses system.cpu.dcache.StoreCondReq_misses::cpu.data 5 # number of StoreCondReq misses system.cpu.dcache.StoreCondReq_misses::total 5 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 4300868 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 4300868 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 4478306 # number of overall misses -system.cpu.dcache.overall_misses::total 4478306 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10273111663 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 149502808344 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 149502808344 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365521996 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 365521996 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 4320011 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 4320011 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 4497569 # number of overall misses +system.cpu.dcache.overall_misses::total 4497569 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10292232000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10292232000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 148465108677 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 148465108677 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 365302500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 365302500 # number of LoadLockedReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 209000 # number of StoreCondReq miss cycles system.cpu.dcache.StoreCondReq_miss_latency::total 209000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 159775920007 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 159775920007 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 159775920007 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 159775920007 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 24021805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 24021805 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 19156176 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 19156176 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::cpu.data 523267 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.SoftPFReq_accesses::total 523267 # number of SoftPFReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467928 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 467928 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 459486 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 459486 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 43177981 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 43177981 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 43701248 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 43701248 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029378 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.029378 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.187676 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.187676 # miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339096 # miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_miss_rate::total 0.339096 # miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057406 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057406 # miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_miss_latency::cpu.data 158757340677 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 158757340677 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 158757340677 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 158757340677 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 24014363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 24014363 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 19151884 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 19151884 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::cpu.data 523261 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.SoftPFReq_accesses::total 523261 # number of SoftPFReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 467948 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 467948 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 459489 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 459489 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 43166247 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 43166247 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 43689508 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 43689508 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.029571 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.029571 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.188487 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.188487 # miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.339330 # miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_miss_rate::total 0.339330 # miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.057414 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.057414 # miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000011 # miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_miss_rate::total 0.000011 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.099608 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.099608 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102475 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102475 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14556.964202 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 14556.964202 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41584.581546 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41584.581546 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13607.400640 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13607.400640 # average LoadLockedReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.100078 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.100078 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102944 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102944 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14493.386450 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 14493.386450 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41127.458789 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41127.458789 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13596.698552 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13596.698552 # average LoadLockedReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 41800 # average StoreCondReq miss latency system.cpu.dcache.StoreCondReq_avg_miss_latency::total 41800 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37149.691645 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37149.691645 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 35677.758511 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 35677.758511 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 582483 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 36749.290841 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 36749.290841 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 35298.478062 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 35298.478062 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 590707 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 7397 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 7439 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 78.745843 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 79.406775 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 696320 # number of writebacks -system.cpu.dcache.writebacks::total 696320 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 291077 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 291077 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3294875 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 3294875 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18482 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 18482 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3585952 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3585952 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3585952 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3585952 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414641 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 414641 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300275 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 300275 # number of WriteReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119609 # number of SoftPFReq MSHR misses -system.cpu.dcache.SoftPFReq_mshr_misses::total 119609 # number of SoftPFReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8380 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 8380 # number of LoadLockedReq MSHR misses +system.cpu.dcache.writebacks::writebacks 696043 # number of writebacks +system.cpu.dcache.writebacks::total 696043 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 295841 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 295841 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 3309634 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 3309634 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 18475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 18475 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3605475 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3605475 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3605475 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3605475 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 414292 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 414292 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 300244 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 300244 # number of WriteReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 119628 # number of SoftPFReq MSHR misses +system.cpu.dcache.SoftPFReq_mshr_misses::total 119628 # number of SoftPFReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 8392 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 8392 # number of LoadLockedReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 5 # number of StoreCondReq MSHR misses system.cpu.dcache.StoreCondReq_mshr_misses::total 5 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 714916 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 714916 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 834525 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 834525 # number of overall MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 714536 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 714536 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 834164 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 834164 # number of overall MSHR misses system.cpu.dcache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.ReadReq_mshr_uncacheable::total 31127 # number of ReadReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable system.cpu.dcache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses system.cpu.dcache.overall_mshr_uncacheable_misses::total 58711 # number of overall MSHR uncacheable misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5660697158 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13235281165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 13235281165 # number of WriteReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1562991253 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1562991253 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 123125251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 123125251 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 18895978323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 18895978323 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20458969576 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20458969576 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5831942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5831942750 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4511868951 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10343811701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 10343811701 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017261 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015675 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015675 # mshr miss rate for WriteReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228581 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228581 # mshr miss rate for SoftPFReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017909 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017909 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5857375000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5857375000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13373750471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 13373750471 # number of WriteReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1627994000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1627994000 # number of SoftPFReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 128038500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 128038500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 204000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 204000 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 19231125471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 19231125471 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20859119471 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 20859119471 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 5908113500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 5908113500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 4570874950 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 4570874950 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 10478988450 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 10478988450 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.017252 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.017252 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.015677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.015677 # mshr miss rate for WriteReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.228620 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.228620 # mshr miss rate for SoftPFReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.017934 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.017934 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000011 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000011 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016557 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.016557 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019096 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.019096 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 13652.043956 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44077.199784 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44077.199784 # average WriteReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13067.505397 # average SoftPFReq mshr miss latency -system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13067.505397 # average SoftPFReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 14692.750716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14692.750716 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40300 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26431.046896 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26431.046896 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 24515.706032 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 24515.706032 # average overall mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 187359.615446 # average ReadReq mshr uncacheable latency -system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 187359.615446 # average ReadReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 163568.334941 # average WriteReq mshr uncacheable latency -system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 163568.334941 # average WriteReq mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 176181.834767 # average overall mshr uncacheable latency -system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 176181.834767 # average overall mshr uncacheable latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.016553 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.016553 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.019093 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.019093 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 14138.276868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 14138.276868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44542.939979 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44542.939979 # average WriteReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 13608.803959 # average SoftPFReq mshr miss latency +system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 13608.803959 # average SoftPFReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 15257.209247 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15257.209247 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 40800 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 40800 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26914.144943 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26914.144943 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 25006.017367 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 25006.017367 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 189806.711215 # average ReadReq mshr uncacheable latency +system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total 189806.711215 # average ReadReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 165707.473535 # average WriteReq mshr uncacheable latency +system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165707.473535 # average WriteReq mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data 178484.244009 # average overall mshr uncacheable latency +system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total 178484.244009 # average overall mshr uncacheable latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.icache.tags.replacements 1892540 # number of replacements -system.cpu.icache.tags.tagsinuse 511.345997 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 64285030 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 1893052 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 33.958407 # Average number of references to valid blocks. -system.cpu.icache.tags.warmup_cycle 13579028250 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 511.345997 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.998723 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.998723 # Average percentage of cache occupancy +system.cpu.icache.tags.replacements 1891955 # number of replacements +system.cpu.icache.tags.tagsinuse 511.348314 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 64263909 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 1892467 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 33.957744 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 13555622500 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 511.348314 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.998727 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.998727 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 158 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::2 228 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::3 2 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 68160699 # Number of tag accesses -system.cpu.icache.tags.data_accesses 68160699 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 64285030 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 64285030 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 64285030 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 64285030 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 64285030 # number of overall hits -system.cpu.icache.overall_hits::total 64285030 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1982600 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1982600 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1982600 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1982600 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1982600 # number of overall misses -system.cpu.icache.overall_misses::total 1982600 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 26922947970 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 26922947970 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 26922947970 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 26922947970 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 26922947970 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 26922947970 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 66267630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 66267630 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 66267630 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 66267630 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 66267630 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 66267630 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029918 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.029918 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.029918 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.029918 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.029918 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.029918 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13579.616650 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13579.616650 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13579.616650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13579.616650 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13579.616650 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 2392 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 68141093 # Number of tag accesses +system.cpu.icache.tags.data_accesses 68141093 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 64263909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 64263909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 64263909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 64263909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 64263909 # number of overall hits +system.cpu.icache.overall_hits::total 64263909 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1984699 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1984699 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1984699 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1984699 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1984699 # number of overall misses +system.cpu.icache.overall_misses::total 1984699 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26888996997 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26888996997 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26888996997 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26888996997 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26888996997 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26888996997 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 66248608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 66248608 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 66248608 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 66248608 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 66248608 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 66248608 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.029958 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.029958 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.029958 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.029958 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.029958 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.029958 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13548.148609 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13548.148609 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13548.148609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13548.148609 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13548.148609 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2508 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 125 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 127 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 19.136000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 19.748031 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 89529 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 89529 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 89529 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 89529 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 89529 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 89529 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1893071 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 1893071 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 1893071 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 1893071 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 1893071 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 1893071 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable -system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses -system.cpu.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23219754000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23219754000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23219754000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23219754000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23219754000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23219754000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225366000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225366000 # number of ReadReq MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225366000 # number of overall MSHR uncacheable cycles -system.cpu.icache.overall_mshr_uncacheable_latency::total 225366000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028567 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.028567 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028567 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.028567 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12265.654062 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12265.654062 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12265.654062 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 12265.654062 # average overall mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average ReadReq mshr uncacheable latency -system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75071.952032 # average ReadReq mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75071.952032 # average overall mshr uncacheable latency -system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75071.952032 # average overall mshr uncacheable latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 92212 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 92212 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 92212 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 92212 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 92212 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 92212 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1892487 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 1892487 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 1892487 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 1892487 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 1892487 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 1892487 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable +system.cpu.icache.ReadReq_mshr_uncacheable::total 3005 # number of ReadReq MSHR uncacheable +system.cpu.icache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses +system.cpu.icache.overall_mshr_uncacheable_misses::total 3005 # number of overall MSHR uncacheable misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24145787497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 24145787497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24145787497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 24145787497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24145787497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 24145787497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 225776500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 225776500 # number of ReadReq MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 225776500 # number of overall MSHR uncacheable cycles +system.cpu.icache.overall_mshr_uncacheable_latency::total 225776500 # number of overall MSHR uncacheable cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.028566 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.028566 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.028566 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.028566 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12758.760032 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12758.760032 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12758.760032 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 12758.760032 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average ReadReq mshr uncacheable latency +system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total 75133.610649 # average ReadReq mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst 75133.610649 # average overall mshr uncacheable latency +system.cpu.icache.overall_avg_mshr_uncacheable_latency::total 75133.610649 # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.tags.replacements 103160 # number of replacements -system.cpu.l2cache.tags.tagsinuse 65071.102218 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 3020124 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 168359 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 17.938596 # Average number of references to valid blocks. +system.cpu.l2cache.tags.replacements 103023 # number of replacements +system.cpu.l2cache.tags.tagsinuse 65070.034194 # Cycle average of tags in use +system.cpu.l2cache.tags.total_refs 5007824 # Total number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 168222 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 29.769138 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 49253.315053 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 11.936082 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797931 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 10086.820532 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 5716.232619 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::writebacks 0.751546 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000182 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::writebacks 49133.665655 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 12.985449 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 2.797952 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 10208.479538 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 5712.105601 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.749720 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000198 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000043 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.153913 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.087223 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.992906 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_blocks::1024 65183 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.155769 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.087160 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.992890 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1023 17 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_blocks::1024 65182 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1023::4 17 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 28 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 152 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2920 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6837 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55246 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000244 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994614 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 28477722 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 28477722 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56030 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12587 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 1873051 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 528182 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 2469850 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 696320 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 696320 # number of Writeback hits +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 153 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6860 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::4 55225 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_task_id_percent::1023 0.000259 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.occ_task_id_percent::1024 0.994598 # Percentage of cache occupancy per task id +system.cpu.l2cache.tags.tag_accesses 44376961 # Number of tag accesses +system.cpu.l2cache.tags.data_accesses 44376961 # Number of data accesses +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 56023 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 12549 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 68572 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 696043 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 696043 # number of Writeback hits system.cpu.l2cache.UpgradeReq_hits::cpu.data 36 # number of UpgradeReq hits system.cpu.l2cache.UpgradeReq_hits::total 36 # number of UpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 3 # number of SCUpgradeReq hits system.cpu.l2cache.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 157101 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 157101 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 56030 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 12587 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 1873051 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 685283 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 2626951 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 56030 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 12587 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 1873051 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 685283 # number of overall hits -system.cpu.l2cache.overall_hits::total 2626951 # number of overall hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 157187 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 157187 # number of ReadExReq hits +system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1872509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadCleanReq_hits::total 1872509 # number of ReadCleanReq hits +system.cpu.l2cache.ReadSharedReq_hits::cpu.data 527843 # number of ReadSharedReq hits +system.cpu.l2cache.ReadSharedReq_hits::total 527843 # number of ReadSharedReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 56023 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 12549 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 1872509 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 685030 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 2626111 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 56023 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 12549 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 1872509 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 685030 # number of overall hits +system.cpu.l2cache.overall_hits::total 2626111 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 21 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 7 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 19985 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 14326 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 34339 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2720 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2720 # number of UpgradeReq misses +system.cpu.l2cache.ReadReq_misses::total 28 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2721 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2721 # number of UpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 2 # number of SCUpgradeReq misses system.cpu.l2cache.SCUpgradeReq_misses::total 2 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 140540 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 140540 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 140423 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 140423 # number of ReadExReq misses +system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 19944 # number of ReadCleanReq misses +system.cpu.l2cache.ReadCleanReq_misses::total 19944 # number of ReadCleanReq misses +system.cpu.l2cache.ReadSharedReq_misses::cpu.data 14346 # number of ReadSharedReq misses +system.cpu.l2cache.ReadSharedReq_misses::total 14346 # number of ReadSharedReq misses system.cpu.l2cache.demand_misses::cpu.dtb.walker 21 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.itb.walker 7 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 19985 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 154866 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 174879 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 19944 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 154769 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 174741 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.dtb.walker 21 # number of overall misses system.cpu.l2cache.overall_misses::cpu.itb.walker 7 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 19985 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 154866 # number of overall misses -system.cpu.l2cache.overall_misses::total 174879 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1759750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 789750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1637862750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1227493750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 2867906000 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 966469 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 966469 # number of UpgradeReq miss cycles +system.cpu.l2cache.overall_misses::cpu.inst 19944 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 154769 # number of overall misses +system.cpu.l2cache.overall_misses::total 174741 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 1844500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 579500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 2424000 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 955000 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 955000 # number of UpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::cpu.data 165000 # number of SCUpgradeReq miss cycles system.cpu.l2cache.SCUpgradeReq_miss_latency::total 165000 # number of SCUpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11197753141 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 11197753141 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1759750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 789750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 1637862750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12425246891 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14065659141 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1759750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 789750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 1637862750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12425246891 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14065659141 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56051 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12594 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 1893036 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 542508 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 2504189 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 696320 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 696320 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2756 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.UpgradeReq_accesses::total 2756 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 11187095500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 11187095500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 1623118000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadCleanReq_miss_latency::total 1623118000 # number of ReadCleanReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 1226117500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.ReadSharedReq_miss_latency::total 1226117500 # number of ReadSharedReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 1844500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 579500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 1623118000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12413213000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 14038755000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 1844500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 579500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 1623118000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12413213000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 14038755000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 56044 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 12556 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 68600 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 696043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 696043 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2757 # number of UpgradeReq accesses(hits+misses) +system.cpu.l2cache.UpgradeReq_accesses::total 2757 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 5 # number of SCUpgradeReq accesses(hits+misses) system.cpu.l2cache.SCUpgradeReq_accesses::total 5 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 297641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 297641 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56051 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 12594 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 1893036 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 840149 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 2801830 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56051 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 12594 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 1893036 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 840149 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 2801830 # number of overall (read+write) accesses +system.cpu.l2cache.ReadExReq_accesses::cpu.data 297610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 297610 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 1892453 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadCleanReq_accesses::total 1892453 # number of ReadCleanReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 542189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.ReadSharedReq_accesses::total 542189 # number of ReadSharedReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 56044 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 12556 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 1892453 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 839799 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 2800852 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 56044 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 12556 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 1892453 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 839799 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 2800852 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000375 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000556 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.010557 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026407 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.013713 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986938 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986938 # miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000558 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.000408 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986942 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986942 # miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.400000 # miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.400000 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.472180 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.472180 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.471836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.471836 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.010539 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.010539 # miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.026459 # miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.026459 # miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000375 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000556 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010557 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.184332 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.062416 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000558 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.010539 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.184293 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.062389 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000375 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000556 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010557 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.184332 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.062416 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 83797.619048 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 112821.428571 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 81954.603453 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85682.936619 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 83517.458284 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 355.319485 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 355.319485 # average UpgradeReq miss latency +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000558 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.010539 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.184293 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.062389 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 87833.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 82785.714286 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 86571.428571 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 350.973907 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 350.973907 # average UpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::cpu.data 82500 # average SCUpgradeReq miss latency system.cpu.l2cache.SCUpgradeReq_avg_miss_latency::total 82500 # average SCUpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79676.626875 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79676.626875 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 80430.807250 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 83797.619048 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 112821.428571 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81954.603453 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80232.245238 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 80430.807250 # average overall miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79667.116498 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79667.116498 # average ReadExReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 81383.774569 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 81383.774569 # average ReadCleanReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 85467.551931 # average ReadSharedReq miss latency +system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 85467.551931 # average ReadSharedReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 80340.360877 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 87833.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 82785.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 81383.774569 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 80204.776150 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 80340.360877 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1445,176 +1454,187 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 94866 # number of writebacks -system.cpu.l2cache.writebacks::total 94866 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 22 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 112 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 134 # number of ReadReq MSHR hits +system.cpu.l2cache.writebacks::writebacks 94881 # number of writebacks +system.cpu.l2cache.writebacks::total 94881 # number of writebacks +system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 22 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadCleanReq_mshr_hits::total 22 # number of ReadCleanReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 111 # number of ReadSharedReq MSHR hits +system.cpu.l2cache.ReadSharedReq_mshr_hits::total 111 # number of ReadSharedReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.inst 22 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 112 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 134 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 111 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 133 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.inst 22 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 112 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 134 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 111 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 133 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 21 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 7 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 19963 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 14214 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 34205 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2720 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2720 # number of UpgradeReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 28 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2721 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2721 # number of UpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 2 # number of SCUpgradeReq MSHR misses system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 2 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140540 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 140540 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 140423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 140423 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 19922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadCleanReq_mshr_misses::total 19922 # number of ReadCleanReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 14235 # number of ReadSharedReq MSHR misses +system.cpu.l2cache.ReadSharedReq_mshr_misses::total 14235 # number of ReadSharedReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 21 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 7 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 19963 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 154754 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 174745 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 19922 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 154658 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 174608 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 21 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 7 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 19963 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 154754 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 174745 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3002 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.overall_mshr_misses::cpu.inst 19922 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 154658 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 174608 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.inst 3005 # number of ReadReq MSHR uncacheable system.cpu.l2cache.ReadReq_mshr_uncacheable::cpu.data 31127 # number of ReadReq MSHR uncacheable -system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34129 # number of ReadReq MSHR uncacheable +system.cpu.l2cache.ReadReq_mshr_uncacheable::total 34132 # number of ReadReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::cpu.data 27584 # number of WriteReq MSHR uncacheable system.cpu.l2cache.WriteReq_mshr_uncacheable::total 27584 # number of WriteReq MSHR uncacheable -system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3002 # number of overall MSHR uncacheable misses +system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.inst 3005 # number of overall MSHR uncacheable misses system.cpu.l2cache.overall_mshr_uncacheable_misses::cpu.data 58711 # number of overall MSHR uncacheable misses -system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61713 # number of overall MSHR uncacheable misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1495250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 701750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 1386544250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1041614500 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2430355750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 48397220 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 48397220 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 140500 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9440469859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9440469859 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1495250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 701750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1386544250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10482084359 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 11870825609 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1495250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 701750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1386544250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10482084359 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 11870825609 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 181832000 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5395669750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5577501750 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4151610000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4151610000 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 181832000 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9547279750 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9729111750 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_misses::total 61716 # number of overall MSHR uncacheable misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 1634500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 509500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2144000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 56503000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 56503000 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 145000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 145000 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 9782865500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 9782865500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 1422648500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 1422648500 # number of ReadCleanReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 1076334500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 1076334500 # number of ReadSharedReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 1634500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 509500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 1422648500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10859200000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 12283992500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 1634500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 509500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 1422648500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10859200000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 12283992500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 188213500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 5519024000 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 5707237500 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 4252080000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 4252080000 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 188213500 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 9771104000 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 9959317500 # number of overall MSHR uncacheable cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026201 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.013659 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986938 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986938 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000408 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986942 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986942 # mshr miss rate for UpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.400000 # mshr miss rate for SCUpgradeReq accesses system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.400000 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.472180 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.472180 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.471836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.471836 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.010527 # mshr miss rate for ReadCleanReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.026255 # mshr miss rate for ReadSharedReq accesses +system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.026255 # mshr miss rate for ReadSharedReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.062368 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.062341 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000375 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000556 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010545 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184198 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.062368 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 100250 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 69455.705555 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73280.885043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 71052.645812 # average ReadReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 17793.095588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17793.095588 # average UpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 70250 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67172.832354 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67172.832354 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 71202.380952 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 100250 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69455.705555 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67733.850879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67932.276225 # average overall mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 173343.712854 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 163424.118785 # average ReadReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 150507.903132 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 150507.903132 # average WriteReq mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 60570.286476 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 162614.837935 # average overall mshr uncacheable latency -system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 157650.928492 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000558 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.010527 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.184161 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.062341 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 76571.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 20765.527380 # average UpgradeReq mshr miss latency +system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 20765.527380 # average UpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 72500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 72500 # average SCUpgradeReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 69667.116498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 69667.116498 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 71410.927618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 71410.927618 # average ReadCleanReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75611.837021 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 75611.837021 # average ReadSharedReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 77833.333333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 72785.714286 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 71410.927618 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70214.279248 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 70351.830958 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data 177306.646962 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 167210.755303 # average ReadReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data 154150.232019 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 154150.232019 # average WriteReq mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst 62633.444260 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data 166427.143125 # average overall mshr uncacheable latency +system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total 161373.347268 # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 2564424 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2564404 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 128192 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2563081 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 27584 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 27584 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 696320 # Transaction distribution -system.cpu.toL2Bus.trans_dist::WriteInvalidateReq 36268 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2756 # Transaction distribution +system.cpu.toL2Bus.trans_dist::Writeback 827115 # Transaction distribution +system.cpu.toL2Bus.trans_dist::CleanEvict 1997055 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2757 # Transaction distribution system.cpu.toL2Bus.trans_dist::SCUpgradeReq 5 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2761 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 297641 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 297641 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3792109 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2499777 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 131034 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 6455014 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121202208 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98530845 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50376 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224204 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size::total 220007633 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.snoops 62589 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 3624998 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::mean 1.036134 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::stdev 0.186622 # Request fanout histogram +system.cpu.toL2Bus.trans_dist::UpgradeResp 2762 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 297610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 297610 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadCleanReq 1892487 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadSharedReq 542422 # Transaction distribution +system.cpu.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5643819 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2634611 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 32016 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 130644 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 8441090 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 121164944 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 98490717 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 50224 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 224176 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size::total 219930061 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.snoops 201613 # Total snoops (count) +system.cpu.toL2Bus.snoop_fanout::samples 5797948 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::mean 1.046562 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::stdev 0.210699 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::1 3494014 96.39% 96.39% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::2 130984 3.61% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::1 5527984 95.34% 95.34% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::2 269964 4.66% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 3624998 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 2504368734 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 5797948 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 3520857499 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.cpu.toL2Bus.snoopLayer0.occupancy 322500 # Layer occupancy (ticks) system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 2847443747 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 2842352755 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 1338896897 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 1306164667 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer2.occupancy 19507738 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer2.occupancy 19466986 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu.toL2Bus.respLayer3.occupancy 75011458 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer3.occupancy 74632435 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 30182 # Transaction distribution system.iobus.trans_dist::ReadResp 30182 # Transaction distribution system.iobus.trans_dist::WriteReq 59014 # Transaction distribution -system.iobus.trans_dist::WriteResp 22790 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59014 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54170 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -1705,23 +1725,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198816983 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187477456 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 82688000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36845510 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36738000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36423 # number of replacements -system.iocache.tags.tagsinuse 1.000480 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.000222 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36439 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 252520633000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.000480 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062530 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062530 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 252500924000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.000222 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062514 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062514 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -1729,49 +1749,49 @@ system.iocache.tags.tag_accesses 328113 # Nu system.iocache.tags.data_accesses 328113 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 233 # number of ReadReq misses system.iocache.ReadReq_misses::total 233 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 233 # number of demand (read+write) misses system.iocache.demand_misses::total 233 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 233 # number of overall misses system.iocache.overall_misses::total 233 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 28780877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 28780877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6657450596 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6657450596 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 28780877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 28780877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 28780877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 28780877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 28674877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 28674877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4272498579 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4272498579 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 28674877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 28674877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 28674877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 28674877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 233 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 233 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 233 # number of demand (read+write) accesses system.iocache.demand_accesses::total 233 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 233 # number of overall (read+write) accesses system.iocache.overall_accesses::total 233 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 123523.077253 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 123523.077253 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183785.628202 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183785.628202 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 123523.077253 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 123523.077253 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 123523.077253 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22928 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 123068.141631 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 123068.141631 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 117946.625966 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 117946.625966 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 123068.141631 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 123068.141631 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3494 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.562106 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -1779,88 +1799,90 @@ system.iocache.writebacks::writebacks 36190 # nu system.iocache.writebacks::total 36190 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 233 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 233 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 233 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 233 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 233 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 233 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 16449877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 16449877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4773782616 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4773782616 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 16449877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 16449877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 16449877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 16449877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 17024877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 17024877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2461298579 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2461298579 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 17024877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 17024877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 17024877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 17024877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 70600.330472 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 70600.330472 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131785.076634 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131785.076634 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 70600.330472 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 70600.330472 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 73068.141631 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 73068.141631 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67946.625966 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67946.625966 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 73068.141631 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 73068.141631 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 68567 # Transaction distribution -system.membus.trans_dist::ReadResp 68566 # Transaction distribution +system.membus.trans_dist::ReadReq 34132 # Transaction distribution +system.membus.trans_dist::ReadResp 68549 # Transaction distribution system.membus.trans_dist::WriteReq 27584 # Transaction distribution system.membus.trans_dist::WriteResp 27584 # Transaction distribution -system.membus.trans_dist::Writeback 131056 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4579 # Transaction distribution +system.membus.trans_dist::Writeback 131071 # Transaction distribution +system.membus.trans_dist::CleanEvict 8154 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4580 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4581 # Transaction distribution -system.membus.trans_dist::ReadExReq 138681 # Transaction distribution -system.membus.trans_dist::ReadExResp 138681 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4582 # Transaction distribution +system.membus.trans_dist::ReadExReq 138564 # Transaction distribution +system.membus.trans_dist::ReadExResp 138564 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 34418 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 105478 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 16 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 2070 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 465382 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 572946 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108886 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 681832 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 473273 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 580837 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108898 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 689735 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 159125 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 128 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 4140 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17186044 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17349437 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4635456 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21984893 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17178284 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::total 17341677 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2317120 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 19658797 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 497 # Total snoops (count) -system.membus.snoop_fanout::samples 406751 # Request fanout histogram +system.membus.snoop_fanout::samples 414951 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 406751 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 414951 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 406751 # Request fanout histogram -system.membus.reqLayer0.occupancy 83856500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 414951 # Request fanout histogram +system.membus.reqLayer0.occupancy 83605000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 10000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 1725500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 1746000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1057992643 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 911806448 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1020413671 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1019741659 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37506490 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64533936 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA |