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authorJoel Hestness <jthestness@gmail.com>2015-10-10 16:45:41 -0500
committerJoel Hestness <jthestness@gmail.com>2015-10-10 16:45:41 -0500
commit735c4a87665119a33443cf8d191d329c66191c6e (patch)
tree619a6c346beb6f7972acfa41a737b065f6c701c5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
parent1f2e7c1aaa17e55b06504264e40bde1a000f2214 (diff)
downloadgem5-735c4a87665119a33443cf8d191d329c66191c6e.tar.xz
stats: Update for UDelayEvent quiesce change
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr')
-rwxr-xr-xtests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr2
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
index 579777365..0663012e4 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr
@@ -43,4 +43,4 @@ warn: Ignoring write to miscreg pmintenclr
warn: Ignoring write to miscreg pmovsr
warn: Ignoring write to miscreg pmcr
warn: instruction 'mcr dcisw' unimplemented
-warn: CP14 unimplemented crn[9], opc1[1], crm[0], opc2[2]
+warn: CP14 unimplemented crn[3], opc1[2], crm[8], opc2[2]