diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-08-12 14:12:59 +0100 |
| commit | 55ed9609f1056280404a8dc49e53e4ba33ae51dd (patch) | |
| tree | 6e50ced504e91a6d9dadff1b43b89a0911df3d7a /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | |
| parent | ee7d8fdcb2226139fd1d6a6f0cde987721ea3699 (diff) | |
| download | gem5-55ed9609f1056280404a8dc49e53e4ba33ae51dd.tar.xz | |
stats: Update to match classic memory changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 6135 |
1 files changed, 3061 insertions, 3074 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index d38a658b5..ab0dc0047 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,167 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825947 # Number of seconds simulated -sim_ticks 2825947406000 # Number of ticks simulated -final_tick 2825947406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.826111 # Number of seconds simulated +sim_ticks 2826111083000 # Number of ticks simulated +final_tick 2826111083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 132633 # Simulator instruction rate (inst/s) -host_op_rate 160894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3120208803 # Simulator tick rate (ticks/s) -host_mem_usage 618508 # Number of bytes of host memory used -host_seconds 905.69 # Real time elapsed on the host -sim_insts 120124543 # Number of instructions simulated -sim_ops 145720076 # Number of ops (including micro ops) simulated +host_inst_rate 93135 # Simulator instruction rate (inst/s) +host_op_rate 112984 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2190118612 # Simulator tick rate (ticks/s) +host_mem_usage 627176 # Number of bytes of host memory used +host_seconds 1290.39 # Real time elapsed on the host +sim_insts 120180681 # Number of instructions simulated +sim_ops 145794019 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1920 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1303616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1321960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8513856 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 181024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 635732 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 529024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1301824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1315176 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8404800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 512 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 186528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 599252 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 416192 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12488540 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1303616 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 181024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1484640 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8962368 # Number of bytes written to this memory +system.physmem.bytes_read::total 12227420 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1301824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 186528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1488352 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8794944 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8979932 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8812508 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 30 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22616 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21176 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133029 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2896 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9954 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 8266 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22588 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21070 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 131325 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 8 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2982 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 6503 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 197989 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 140037 # Number of write requests responded to by this memory +system.physmem.num_reads::total 193909 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 137421 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144428 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 141812 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 679 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 461302 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 467794 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3012744 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64058 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 224962 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 187202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 460641 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 465366 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 2973981 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 66002 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 212041 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 147267 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4419240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 461302 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64058 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 525360 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3171456 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4326589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 460641 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 66002 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 526643 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3112031 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3177671 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3171456 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3118245 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3112031 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 679 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 461302 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 473995 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3012744 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64058 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 224977 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 187202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 460641 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 471567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 2973981 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 66002 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 212055 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 147267 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7596911 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 197990 # Number of read requests accepted -system.physmem.writeReqs 144428 # Number of write requests accepted -system.physmem.readBursts 197990 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 144428 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12662400 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue -system.physmem.bytesWritten 8992448 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12488604 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8979932 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7444834 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 193910 # Number of read requests accepted +system.physmem.writeReqs 141812 # Number of write requests accepted +system.physmem.readBursts 193910 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 141812 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12399936 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 10304 # Total number of bytes read from write queue +system.physmem.bytesWritten 8824960 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12227484 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8812508 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12407 # Per bank write bursts -system.physmem.perBankRdBursts::1 12295 # Per bank write bursts -system.physmem.perBankRdBursts::2 12935 # Per bank write bursts -system.physmem.perBankRdBursts::3 12653 # Per bank write bursts -system.physmem.perBankRdBursts::4 14543 # Per bank write bursts -system.physmem.perBankRdBursts::5 12106 # Per bank write bursts -system.physmem.perBankRdBursts::6 12653 # Per bank write bursts -system.physmem.perBankRdBursts::7 12509 # Per bank write bursts -system.physmem.perBankRdBursts::8 12223 # Per bank write bursts -system.physmem.perBankRdBursts::9 12064 # Per bank write bursts -system.physmem.perBankRdBursts::10 11718 # Per bank write bursts -system.physmem.perBankRdBursts::11 11008 # Per bank write bursts -system.physmem.perBankRdBursts::12 11914 # Per bank write bursts -system.physmem.perBankRdBursts::13 13060 # Per bank write bursts -system.physmem.perBankRdBursts::14 12107 # Per bank write bursts -system.physmem.perBankRdBursts::15 11655 # Per bank write bursts -system.physmem.perBankWrBursts::0 9105 # Per bank write bursts -system.physmem.perBankWrBursts::1 9127 # Per bank write bursts -system.physmem.perBankWrBursts::2 9615 # Per bank write bursts -system.physmem.perBankWrBursts::3 9150 # Per bank write bursts -system.physmem.perBankWrBursts::4 8481 # Per bank write bursts -system.physmem.perBankWrBursts::5 8750 # Per bank write bursts -system.physmem.perBankWrBursts::6 8993 # Per bank write bursts -system.physmem.perBankWrBursts::7 8806 # Per bank write bursts -system.physmem.perBankWrBursts::8 8720 # Per bank write bursts -system.physmem.perBankWrBursts::9 8569 # Per bank write bursts -system.physmem.perBankWrBursts::10 8518 # Per bank write bursts -system.physmem.perBankWrBursts::11 8119 # Per bank write bursts -system.physmem.perBankWrBursts::12 8743 # Per bank write bursts -system.physmem.perBankWrBursts::13 9182 # Per bank write bursts -system.physmem.perBankWrBursts::14 8573 # Per bank write bursts -system.physmem.perBankWrBursts::15 8056 # Per bank write bursts +system.physmem.perBankRdBursts::0 12140 # Per bank write bursts +system.physmem.perBankRdBursts::1 12135 # Per bank write bursts +system.physmem.perBankRdBursts::2 12398 # Per bank write bursts +system.physmem.perBankRdBursts::3 12886 # Per bank write bursts +system.physmem.perBankRdBursts::4 14558 # Per bank write bursts +system.physmem.perBankRdBursts::5 12353 # Per bank write bursts +system.physmem.perBankRdBursts::6 12494 # Per bank write bursts +system.physmem.perBankRdBursts::7 12590 # Per bank write bursts +system.physmem.perBankRdBursts::8 12207 # Per bank write bursts +system.physmem.perBankRdBursts::9 12490 # Per bank write bursts +system.physmem.perBankRdBursts::10 11644 # Per bank write bursts +system.physmem.perBankRdBursts::11 10772 # Per bank write bursts +system.physmem.perBankRdBursts::12 11273 # Per bank write bursts +system.physmem.perBankRdBursts::13 11534 # Per bank write bursts +system.physmem.perBankRdBursts::14 11359 # Per bank write bursts +system.physmem.perBankRdBursts::15 10916 # Per bank write bursts +system.physmem.perBankWrBursts::0 8885 # Per bank write bursts +system.physmem.perBankWrBursts::1 8987 # Per bank write bursts +system.physmem.perBankWrBursts::2 9257 # Per bank write bursts +system.physmem.perBankWrBursts::3 9509 # Per bank write bursts +system.physmem.perBankWrBursts::4 8433 # Per bank write bursts +system.physmem.perBankWrBursts::5 8902 # Per bank write bursts +system.physmem.perBankWrBursts::6 9078 # Per bank write bursts +system.physmem.perBankWrBursts::7 8908 # Per bank write bursts +system.physmem.perBankWrBursts::8 8674 # Per bank write bursts +system.physmem.perBankWrBursts::9 9007 # Per bank write bursts +system.physmem.perBankWrBursts::10 8474 # Per bank write bursts +system.physmem.perBankWrBursts::11 8031 # Per bank write bursts +system.physmem.perBankWrBursts::12 8318 # Per bank write bursts +system.physmem.perBankWrBursts::13 8000 # Per bank write bursts +system.physmem.perBankWrBursts::14 7983 # Per bank write bursts +system.physmem.perBankWrBursts::15 7444 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 6 # Number of times write queue was full causing retry -system.physmem.totGap 2825947136000 # Total gap between requests +system.physmem.numWrRetry 9 # Number of times write queue was full causing retry +system.physmem.totGap 2826110796000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194325 # Read request sizes (log2) +system.physmem.readPktSize::6 190245 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 140037 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60161 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 72217 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15830 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12957 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7515 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6523 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4740 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1512 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 744 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 304 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 137421 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 59620 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15526 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12745 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8439 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7276 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6358 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5209 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4584 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1421 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 302 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 262 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -189,165 +189,162 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4277 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4910 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5685 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 6030 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7661 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8689 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10204 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9419 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9434 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 10925 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9108 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7984 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 686 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 515 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 149 # 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What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92378 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.414947 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.500025 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.048436 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50794 54.98% 54.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17715 19.18% 74.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5941 6.43% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3366 3.64% 84.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2816 3.05% 87.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1529 1.66% 88.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 925 1.00% 89.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 990 1.07% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8302 8.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92378 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6992 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.296339 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.591514 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6990 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2582 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3484 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4186 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4772 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5590 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5845 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6981 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7513 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8598 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8675 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9940 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10995 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 8918 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7922 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 501 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 329 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 228 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 184 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 131 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 122 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 117 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 104 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 91 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 75 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 79 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 21 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 19 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 84734 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 250.487785 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 142.325533 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 306.970890 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 42837 50.55% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17738 20.93% 71.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6168 7.28% 78.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3519 4.15% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2713 3.20% 86.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1549 1.83% 87.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 945 1.12% 89.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 1056 1.25% 90.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8209 9.69% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 84734 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6846 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.300175 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 562.386287 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6844 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6992 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6992 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.095395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.609227 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 12.295574 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5854 83.72% 83.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 392 5.61% 89.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 80 1.14% 90.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 62 0.89% 91.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 277 3.96% 95.32% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 20 0.29% 95.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 15 0.21% 95.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 24 0.34% 96.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 25 0.36% 96.52% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 12 0.17% 96.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 9 0.13% 96.82% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 14 0.20% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 142 2.03% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 4 0.06% 99.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 10 0.14% 99.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 7 0.10% 99.36% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 6 0.09% 99.44% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.01% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.03% 99.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.01% 99.50% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 3 0.04% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 3 0.04% 99.61% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.01% 99.64% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 14 0.20% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 3 0.04% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6992 # Writes before turning the bus around for reads -system.physmem.totQLat 6748582846 # Total ticks spent queuing -system.physmem.totMemAccLat 10458270346 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989250000 # Total ticks spent in databus transfers -system.physmem.avgQLat 34109.59 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 6846 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6846 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.141689 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.636499 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.164291 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5708 83.38% 83.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 378 5.52% 88.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 91 1.33% 90.23% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 47 0.69% 90.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 276 4.03% 94.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 33 0.48% 95.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 21 0.31% 95.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 23 0.34% 96.07% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 19 0.28% 96.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 10 0.15% 96.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 2 0.03% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 9 0.13% 96.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 166 2.42% 99.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 9 0.13% 99.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 4 0.06% 99.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 11 0.16% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 2 0.03% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 2 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 3 0.04% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 7 0.10% 99.85% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 2 0.03% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 2 0.03% 99.91% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::172-175 3 0.04% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6846 # Writes before turning the bus around for reads +system.physmem.totQLat 6600075879 # Total ticks spent queuing +system.physmem.totMemAccLat 10232869629 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 968745000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34065.08 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52859.59 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 52815.08 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.12 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.33 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.12 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing -system.physmem.readRowHits 165284 # Number of row buffer hits during reads -system.physmem.writeRowHits 80694 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.42 # Row buffer hit rate for writes -system.physmem.avgGap 8252916.42 # Average gap between requests -system.physmem.pageHitRate 72.69 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 361058040 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197005875 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 796387800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466734960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79734690540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625622381750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891755025365 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.424618 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704272847388 # Time in different power states -system.physmem_0.memoryStateTime::REF 94364400000 # Time in different power states +system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.81 # Average write queue length when enqueuing +system.physmem.readRowHits 161373 # Number of row buffer hits during reads +system.physmem.writeRowHits 85531 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.29 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 62.02 # Row buffer hit rate for writes +system.physmem.avgGap 8418008.94 # Average gap between requests +system.physmem.pageHitRate 74.44 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 338612400 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 184758750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 792121200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466294320 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79311033765 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1626092117250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891772383845 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.392029 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2705053539598 # Time in different power states +system.physmem_0.memoryStateTime::REF 94369860000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27304587612 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26681946652 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 337319640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 184053375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 746834400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 443750400 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79554512970 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1625780432250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891623669435 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.378136 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2704538486760 # Time in different power states -system.physmem_1.memoryStateTime::REF 94364400000 # Time in different power states +system.physmem_1.actEnergy 301976640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 164769000 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 719113200 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 427232880 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184587446160 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 78534447525 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626773333250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891508318655 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.298592 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2706191706230 # Time in different power states +system.physmem_1.memoryStateTime::REF 94369860000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27044516240 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25549496770 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -366,30 +363,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53058502 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24374377 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 933450 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32093175 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13944864 # Number of BTB hits +system.cpu0.branchPred.lookups 23913557 # Number of BP lookups +system.cpu0.branchPred.condPredicted 15655751 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 926443 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 14584665 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 9536401 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.451182 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15470259 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33206 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10120086 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9964746 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155340 # Number of indirect misses. -system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. +system.cpu0.branchPred.BTBHitPct 65.386493 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 3854213 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33180 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 1360238 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 1204672 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 155566 # Number of indirect misses. +system.cpu0.branchPredindirectMispredicted 48773 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -419,84 +416,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 67164 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67164 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25323 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19031 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22810 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 458.594490 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2953.911408 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43233 97.47% 97.47% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 862 1.94% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 108 0.24% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 65918 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 65918 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25327 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18922 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 21669 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44249 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 506.926710 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3129.335275 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43005 97.19% 97.19% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 929 2.10% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 148 0.33% 99.62% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 23 0.05% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 20 0.05% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44354 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 17047 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9658.702439 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 6683.029230 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 15750 92.39% 92.39% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1185 6.95% 99.34% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 75 0.44% 99.78% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 14 0.08% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 14 0.08% 99.98% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkWaitTime::total 44249 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16055 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11307.848022 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9898.999015 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6813.334576 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 14595 90.91% 90.91% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1294 8.06% 98.97% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 134 0.83% 99.80% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 9 0.06% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 17 0.11% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 1 0.01% 99.99% # Table walker service (enqueue to completion) latency system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 17047 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 85757506152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.515718 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.512261 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 85699757152 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 40650000 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7189500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4730000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1448500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1006500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1064000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1646000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 85757506152 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5272 77.42% 77.42% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.58% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6810 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67164 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkCompletionTime::total 16055 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 85920956152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.541941 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.508329 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 85862493152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40323000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 8212500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 5190500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 2626000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 844500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 886000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 336500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 44000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 85920956152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5102 78.63% 78.63% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1387 21.37% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6489 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 65918 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67164 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6810 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 65918 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6489 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6810 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 73974 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6489 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 72407 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23645826 # DTB read hits -system.cpu0.dtb.read_misses 56383 # DTB read misses -system.cpu0.dtb.write_hits 17571331 # DTB write hits -system.cpu0.dtb.write_misses 10781 # DTB write misses +system.cpu0.dtb.read_hits 17729387 # DTB read hits +system.cpu0.dtb.read_misses 55806 # DTB read misses +system.cpu0.dtb.write_hits 14606301 # DTB write hits +system.cpu0.dtb.write_misses 10112 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 213 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2243 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3431 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 353 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2188 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 818 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23702209 # DTB read accesses -system.cpu0.dtb.write_accesses 17582112 # DTB write accesses +system.cpu0.dtb.perms_faults 939 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 17785193 # DTB read accesses +system.cpu0.dtb.write_accesses 14616413 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41217157 # DTB hits -system.cpu0.dtb.misses 67164 # DTB misses -system.cpu0.dtb.accesses 41284321 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 32335688 # DTB hits +system.cpu0.dtb.misses 65918 # DTB misses +system.cpu0.dtb.accesses 32401606 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,59 +523,58 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10883 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10883 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3898 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5925 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1060 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9823 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 449.709865 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2327.234590 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9434 96.04% 96.04% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 184 1.87% 97.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.18% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9823 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3631 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4771.165368 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 614 16.91% 16.91% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2801 77.14% 94.05% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.15% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 0.74% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 10845 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10845 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3752 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6021 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1072 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9773 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 438.606364 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2276.348067 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9409 96.28% 96.28% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 161 1.65% 97.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 121 1.24% 99.16% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 47 0.48% 99.64% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 16 0.16% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 6 0.06% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 2 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9773 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3657 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12272.627837 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11484.483595 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4878.254960 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 514 14.06% 14.06% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2884 78.86% 92.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 170 4.65% 97.57% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 55 1.50% 99.07% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 31 0.85% 99.92% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.03% 99.95% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3631 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21332036712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.795904 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.403169 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 4354826000 20.41% 20.41% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 16976239212 79.58% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 901500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21332036712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2243 87.24% 87.24% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 328 12.76% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3657 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21495635712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.820169 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.384194 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 3866725500 17.99% 17.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17627832712 82.01% 99.99% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 1008500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 69000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21495635712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2254 87.20% 87.20% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 331 12.80% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2585 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10883 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10883 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10845 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10845 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13454 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72708520 # ITB inst hits -system.cpu0.itb.inst_misses 10883 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2585 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2585 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13430 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 37503849 # ITB inst hits +system.cpu0.itb.inst_misses 10845 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -587,1047 +583,1055 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2291 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1944 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72719403 # ITB inst accesses -system.cpu0.itb.hits 72708520 # DTB hits -system.cpu0.itb.misses 10883 # DTB misses -system.cpu0.itb.accesses 72719403 # DTB accesses -system.cpu0.numPwrStateTransitions 3678 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1839 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1481668762.034258 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23877600166.586662 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1061 57.69% 57.69% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.03% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 37514694 # ITB inst accesses +system.cpu0.itb.hits 37503849 # DTB hits +system.cpu0.itb.misses 10845 # DTB misses +system.cpu0.itb.accesses 37514694 # DTB accesses +system.cpu0.numPwrStateTransitions 3712 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1856 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1487215700.959052 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23895599673.728432 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1080 58.19% 58.19% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 769 41.43% 99.62% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::5e+10-1e+11 2 0.11% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499971949600 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1839 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 101158552619 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 202318013 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::max_value 499971395296 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1856 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 65838742020 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2760272340980 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 131678547 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20370009 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 195788924 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53058502 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39379869 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 174489676 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5690920 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148682 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 56911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 412776 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 413906 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 90774 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72708226 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 258373 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5359 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 198828194 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.203611 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.307839 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19262499 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 112028029 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 23913557 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 14595286 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 106047706 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2739238 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 149116 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 57008 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 423158 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 407524 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 94244 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 37503537 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 259263 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5228 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 127810874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.056272 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.258048 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 93974548 47.26% 47.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30342793 15.26% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14563641 7.32% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 59947212 30.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 65678610 51.39% 51.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 21331326 16.69% 68.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 8731054 6.83% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 32069884 25.09% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 198828194 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.262253 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.967729 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25600367 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 106949118 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58799478 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4963264 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2515967 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3058039 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 333585 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154217934 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3811468 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2515967 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34209280 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12450122 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83570932 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55016631 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11065262 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137539344 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1033397 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1452682 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 164882 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58749 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6858829 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141646141 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 634543216 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152633070 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9368 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130461493 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11184637 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2697680 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2556046 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22573700 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24576087 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19059052 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1700091 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2321608 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134608055 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1714170 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132746710 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 453040 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10578491 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21717645 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 121089 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 198828194 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.667645 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.963186 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 127810874 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.181606 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.850769 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 19867897 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 60850603 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 41086114 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4967748 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1038512 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3035925 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 335186 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 110135169 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3776324 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1038512 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 25520251 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12577304 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 37369361 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 40264186 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11041260 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 105172145 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1006076 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1476626 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 165177 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 58768 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6832387 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 109365921 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 480109573 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 120259513 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9447 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 98266494 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11099416 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 1228555 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 1085594 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 12372656 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18663457 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 16076197 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1697816 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2228906 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 102290291 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1693186 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 100457201 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 451571 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 9045594 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21384310 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 120136 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 127810874 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.785983 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.028831 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 122140771 61.43% 61.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33611714 16.90% 78.34% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31218891 15.70% 94.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10730115 5.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1126646 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 71664386 56.07% 56.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 23315575 18.24% 74.31% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 22454220 17.57% 91.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 9273638 7.26% 99.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1103003 0.86% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 52 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 198828194 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 127810874 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10786366 43.89% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 65 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.89% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5629308 22.91% 66.79% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8160859 33.21% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 9324082 40.55% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 74 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.55% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5582954 24.28% 64.83% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8086742 35.17% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89668905 67.55% 67.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 111084 0.08% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8099 0.01% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24336393 18.33% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18619956 14.03% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 66279940 65.98% 65.98% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 93468 0.09% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.07% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8018 0.01% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.08% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18419781 18.34% 84.42% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 15653721 15.58% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132746710 # Type of FU issued -system.cpu0.iq.rate 0.656129 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24576598 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185139 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 489318685 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 146908772 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129217545 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32566 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11248 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157299800 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21235 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365614 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 100457201 # Type of FU issued +system.cpu0.iq.rate 0.762897 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 22993852 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.228892 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 352138149 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 113036952 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 98428366 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32549 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11294 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 9716 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 123427553 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21227 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365954 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1914996 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2485 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19372 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 896753 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1901526 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2478 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19250 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 882682 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 121022 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 362352 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 110051 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 360569 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2515967 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1594217 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 188418 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136474692 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 1038512 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1592668 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 210705 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 104136429 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24576087 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19059052 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 876204 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28441 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 136041 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19372 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 261507 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398935 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 660442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131715074 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23894149 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 964599 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 18663457 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 16076197 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876152 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28505 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 158159 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19250 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 253073 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 398879 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 651952 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 99436169 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 17977378 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 955231 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152467 # number of nop insts executed -system.cpu0.iew.exec_refs 42353114 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25555008 # Number of branches executed -system.cpu0.iew.exec_stores 18458965 # Number of stores executed -system.cpu0.iew.exec_rate 0.651030 # Inst execution rate -system.cpu0.iew.wb_sent 131158694 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129227262 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 65946343 # num instructions producing a value -system.cpu0.iew.wb_consumers 106655009 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.638733 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618315 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9548145 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1593081 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 603957 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 195669167 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.643258 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.340979 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152952 # number of nop insts executed +system.cpu0.iew.exec_refs 33471315 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16838084 # Number of branches executed +system.cpu0.iew.exec_stores 15493937 # Number of stores executed +system.cpu0.iew.exec_rate 0.755143 # Inst execution rate +system.cpu0.iew.wb_sent 98890175 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 98438082 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 51269761 # num instructions producing a value +system.cpu0.iew.wb_consumers 84681895 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.747564 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.605439 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 8044326 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1573050 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 595336 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 126126769 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.753686 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.472161 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 135298586 69.15% 69.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33412613 17.08% 86.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12639367 6.46% 92.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3246710 1.66% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4896676 2.50% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2794942 1.43% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1306268 0.67% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 556762 0.28% 99.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1517243 0.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 81783872 64.84% 64.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 24707932 19.59% 84.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 8259395 6.55% 90.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3211630 2.55% 93.53% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 3438301 2.73% 96.25% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 1493917 1.18% 97.44% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1163537 0.92% 98.36% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 551177 0.44% 98.80% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1517008 1.20% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 195669167 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 103932879 # Number of instructions committed -system.cpu0.commit.committedOps 125865777 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 126126769 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 79016795 # Number of instructions committed +system.cpu0.commit.committedOps 95059926 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40823389 # Number of memory references committed -system.cpu0.commit.loads 22661090 # Number of loads committed -system.cpu0.commit.membars 647148 # Number of memory barriers committed -system.cpu0.commit.branches 24954311 # Number of branches committed +system.cpu0.commit.refs 31955445 # Number of memory references committed +system.cpu0.commit.loads 16761930 # Number of loads committed +system.cpu0.commit.membars 647782 # Number of memory barriers committed +system.cpu0.commit.branches 16235143 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 109885490 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4835541 # Number of function calls committed. +system.cpu0.commit.int_insts 81982870 # Number of committed integer instructions. +system.cpu0.commit.function_calls 1931434 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 84925464 67.47% 67.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 108825 0.09% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8099 0.01% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22661090 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18162299 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 63005341 66.28% 66.28% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 91123 0.10% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8017 0.01% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.38% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 16761930 17.63% 84.02% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 15193515 15.98% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 125865777 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1517243 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 306278084 # The number of ROB reads -system.cpu0.rob.rob_writes 273977566 # The number of ROB writes -system.cpu0.timesIdled 123981 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3489819 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5449576943 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 103810827 # Number of Instructions Simulated -system.cpu0.committedOps 125743725 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.948911 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.948911 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.513107 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.513107 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142709258 # number of integer regfile reads -system.cpu0.int_regfile_writes 81672792 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 95059926 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1517008 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 223519030 # The number of ROB reads +system.cpu0.rob.rob_writes 207883288 # The number of ROB writes +system.cpu0.timesIdled 136700 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3867673 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5520543918 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 78894743 # Number of Instructions Simulated +system.cpu0.committedOps 94937874 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.669041 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.669041 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.599147 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.599147 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 110427579 # number of integer regfile reads +system.cpu0.int_regfile_writes 59611828 # number of integer regfile writes system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 464864695 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49723023 # number of cc regfile writes -system.cpu0.misc_regfile_reads 392114938 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224736 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 709879 # number of replacements -system.cpu0.dcache.tags.tagsinuse 499.426037 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37661762 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 710391 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 53.015539 # Average number of references to valid blocks. +system.cpu0.cc_regfile_reads 350340790 # number of cc regfile reads +system.cpu0.cc_regfile_writes 41062621 # number of cc regfile writes +system.cpu0.misc_regfile_reads 252371624 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1225237 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 711089 # number of replacements +system.cpu0.dcache.tags.tagsinuse 494.347987 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 28802334 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 711601 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 40.475398 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.426037 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975441 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.975441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 494.347987 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.965523 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.965523 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 338 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 19 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81162963 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81162963 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21452365 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21452365 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14987011 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14987011 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308699 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 308699 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363086 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363086 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361018 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361018 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36439376 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36439376 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36748075 # number of overall hits -system.cpu0.dcache.overall_hits::total 36748075 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 646473 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 646473 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1887751 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1887751 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147620 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147620 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25081 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25081 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20154 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20154 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2534224 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2534224 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2681844 # number of overall misses -system.cpu0.dcache.overall_misses::total 2681844 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8640238000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8640238000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29904279351 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29904279351 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399794500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 399794500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 485945500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 390500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 390500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38544517351 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38544517351 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38544517351 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38544517351 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22098838 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22098838 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16874762 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16874762 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456319 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456319 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388167 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388167 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381172 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381172 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38973600 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38973600 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39429919 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39429919 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029254 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029254 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111868 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.111868 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323502 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323502 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064614 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052874 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052874 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065024 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065024 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068015 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068015 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13365.195453 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13365.195453 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15841.220241 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15841.220241 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15940.133966 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15940.133966 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24111.615560 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24111.615560 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 63463455 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 63463455 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 15558905 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 15558905 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 12019658 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 12019658 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308619 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 308619 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363044 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363044 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361281 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361281 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 27578563 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 27578563 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 27887182 # number of overall hits +system.cpu0.dcache.overall_hits::total 27887182 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 648058 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 648058 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1895809 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1895809 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147818 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147818 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25317 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25317 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20174 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20174 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2543867 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2543867 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2691685 # number of overall misses +system.cpu0.dcache.overall_misses::total 2691685 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8928091500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8928091500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29690163364 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29690163364 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 404195500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 404195500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 475433000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 475433000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 570500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 570500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38618254864 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38618254864 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38618254864 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38618254864 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 16206963 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 16206963 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 13915467 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 13915467 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456437 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456437 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388361 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388361 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381455 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381455 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 30122430 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 30122430 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 30578867 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 30578867 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039986 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.039986 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136238 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.136238 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323852 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065189 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065189 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052887 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052887 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084451 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.084451 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088024 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.088024 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13776.685883 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13776.685883 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15660.946522 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15660.946522 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15965.378994 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15965.378994 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 23566.620402 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 23566.620402 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4275244 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 201901 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.069767 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21.174952 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 709879 # number of writebacks -system.cpu0.dcache.writebacks::total 709879 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 258972 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 258972 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563802 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1563802 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18565 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822774 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1822774 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822774 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1822774 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387501 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 387501 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323949 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323949 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101413 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101413 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6516 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6516 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20154 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20154 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 711450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 711450 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 812863 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 812863 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31772 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28451 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60223 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4575351000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4575351000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6134433385 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6134433385 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1666291000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1666291000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103051000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103051000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 465800500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 465800500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 381500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 381500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10709784385 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10709784385 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376075385 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12376075385 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621057500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621057500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621057500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017535 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017535 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019197 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222241 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222241 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016787 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016787 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052874 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052874 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020615 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020615 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15180.925286 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15180.925286 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14347.241547 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14347.241547 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1034 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4271446 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 202383 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.541667 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21.105755 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 711089 # number of writebacks +system.cpu0.dcache.writebacks::total 711089 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 260039 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 260039 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1570278 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1570278 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18696 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1830317 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1830317 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1830317 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1830317 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 388019 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 388019 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 325531 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 325531 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101607 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101607 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6621 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6621 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20174 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20174 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 713550 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 713550 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 815157 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 815157 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 20336 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 20336 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 19032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 19032 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 39368 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 39368 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4833813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4833813000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5968230399 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5968230399 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1672759500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1672759500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 104692000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 104692000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 455274000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 455274000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 555500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 555500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10802043399 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10802043399 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12474802899 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12474802899 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 4534406000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 4534406000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 4534406000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4534406000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.023941 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.023941 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023393 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222609 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222609 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.017049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.017049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052887 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052887 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023688 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.023688 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026658 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.026658 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12457.670887 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12457.670887 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18333.831184 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18333.831184 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16463.034043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16463.034043 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15812.112974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15812.112974 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 22567.363934 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 22567.363934 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1252995 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762307 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71397425 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1253507 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.958138 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762307 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999536 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999536 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id -system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146662859 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146662859 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71397425 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71397425 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71397425 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71397425 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71397425 # number of overall hits -system.cpu0.icache.overall_hits::total 71397425 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1307231 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1307231 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1307231 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1307231 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1307231 # number of overall misses -system.cpu0.icache.overall_misses::total 1307231 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13217921463 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13217921463 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13217921463 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13217921463 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13217921463 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13217921463 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72704656 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72704656 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72704656 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72704656 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72704656 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72704656 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017980 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017980 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017980 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017980 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017980 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017980 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10111.389236 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10111.389236 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10111.389236 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10111.389236 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10111.389236 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10111.389236 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1578280 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 443 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 112202 # number of cycles access was blocked +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15138.453366 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15138.453366 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15303.558577 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15303.558577 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 222974.331235 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 222974.331235 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 115179.993904 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 115179.993904 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1254577 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.762789 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 36189840 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1255088 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 28.834504 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6511134000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762789 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999537 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999537 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 130 # Occupied blocks per task id +system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id +system.cpu0.icache.tags.tag_accesses 76255085 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 76255085 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 36189843 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 36189843 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 36189843 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 36189843 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 36189843 # number of overall hits +system.cpu0.icache.overall_hits::total 36189843 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1310126 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1310126 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1310126 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1310126 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1310126 # number of overall misses +system.cpu0.icache.overall_misses::total 1310126 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13674177457 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 13674177457 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 13674177457 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 13674177457 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 13674177457 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 13674177457 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 37499969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 37499969 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 37499969 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 37499969 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 37499969 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 37499969 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034937 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.034937 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034937 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.034937 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034937 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.034937 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10437.299509 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 10437.299509 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 10437.299509 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10437.299509 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10437.299509 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1615389 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 855 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 113956 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.066416 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 44.300000 # average number of cycles each access was blocked -system.cpu0.icache.writebacks::writebacks 1252995 # number of writebacks -system.cpu0.icache.writebacks::total 1252995 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 53683 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 53683 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 53683 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 53683 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 53683 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 53683 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1253548 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1253548 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1253548 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1253548 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1253548 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1253548 # number of overall MSHR misses +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.175550 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 85.500000 # average number of cycles each access was blocked +system.cpu0.icache.writebacks::writebacks 1254577 # number of writebacks +system.cpu0.icache.writebacks::total 1254577 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 54978 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 54978 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 54978 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 54978 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 54978 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 54978 # 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number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 12423139434 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017242 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017242 # 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average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837427 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1839978 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2305 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1846782 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1849282 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2270 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236878 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 277234 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16111.552153 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3276769 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 293338 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.170626 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236718 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 273792 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 15633.615902 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 1886952 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 289401 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 6.520199 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.282247 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.429995 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1405.940159 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.896844 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000689 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000026 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085812 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.983371 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1005 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14449.190897 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.342760 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.746834 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1171.335411 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.881909 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000753 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.071493 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.954200 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 271 # Occupied blocks per task id system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 460 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7019 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2801 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061340 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15328 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 66 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 120 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 81 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 1 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 311 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 1438 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 7629 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 4500 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 1450 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.016541 # Percentage of cache occupancy per task id system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 66263541 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 66263541 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55477 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13130 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 68607 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 482403 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 482403 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1449230 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1449230 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221307 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221307 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1200077 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1200077 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398579 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 398579 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55477 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13130 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1200077 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 619886 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1888570 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55477 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13130 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1200077 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 619886 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1888570 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 420 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 151 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 571 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55011 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55011 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20153 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20153 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 47810 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 47810 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 53438 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 53438 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 96741 # number of ReadSharedReq misses -system.cpu0.l2cache.ReadSharedReq_misses::total 96741 # number of ReadSharedReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 420 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 151 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 53438 # 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number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 23796000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 23796000 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 365500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 365500 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2790491998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2790491998 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2793539000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2793539000 # number of ReadCleanReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2953442497 # number of ReadSharedReq miss cycles -system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2953442497 # 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mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999928 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999928 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155984 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155984 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042593 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193770 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193770 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091953 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.159667 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.159667 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.056741 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.216654 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.216654 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.106420 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008884 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013501 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.056741 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.196574 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.215216 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.233472 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20918.262150 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 57534.711912 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17299.214716 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17299.214716 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15017.203768 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15017.203768 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 110499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 110499.500000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 40813.341067 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 40813.341067 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 40940.561110 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24257.326226 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24257.326226 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 32794.577145 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22180.722892 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17444.751381 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 40940.561110 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28995.783226 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 57534.711912 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 46257.816810 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 214957.194138 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 197865.825442 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4076758 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058809 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31269 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 324106 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 319070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5036 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 113929 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1910818 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28451 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28451 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 712670 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1480466 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 204485 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 327834 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86644 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42628 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112569 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 27 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287578 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284142 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1253548 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576173 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3244 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3766063 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2610032 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29029 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119282 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6524406 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160464624 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98586020 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53124 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259327356 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1029792 # Total snoops (count) -system.cpu0.toL2Bus.snoopTraffic 18816792 # Total snoop traffic (bytes) -system.cpu0.toL2Bus.snoop_fanout::samples 3154811 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.120834 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330795 # Request fanout histogram +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 111038.648141 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 108989.414930 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4083931 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2062737 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31284 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 216422 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 214567 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 1855 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 102316 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1901889 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 19032 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 19032 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 714747 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1482534 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 90142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 335134 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 87548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42677 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113494 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 8 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 288350 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 285091 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1255148 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 586492 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3253 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3770830 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2574893 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29200 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119227 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6494150 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160667312 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98708808 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 224224 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 259653968 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 933771 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18925704 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3041721 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.089004 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.286883 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2778640 88.08% 88.08% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 371135 11.76% 99.84% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 5036 0.16% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2772852 91.16% 91.16% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 267014 8.78% 99.94% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1855 0.06% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3154811 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4076288994 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3041721 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4067278494 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113402059 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 114026414 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1883892360 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1886176090 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1231592300 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1218391120 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15761972 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15802982 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63433401 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63205426 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4691512 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2780704 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 269312 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2468444 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1570862 # Number of BTB hits +system.cpu1.branchPred.lookups 33853439 # Number of BP lookups +system.cpu1.branchPred.condPredicted 11509465 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 280542 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 18730917 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5987349 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.637741 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 878870 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7026 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 249224 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 213650 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 35574 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10610 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 31.965061 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 12496464 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7318 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 9007806 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 8970953 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 36853 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10907 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1657,90 +1661,89 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21486 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21486 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8656 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5913 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6917 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14569 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 593.417530 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3219.344489 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13924 95.57% 95.57% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.90% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 239 1.64% 98.54% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 88 0.60% 99.15% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.31% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.11% 99.42% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.03% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 2 0.01% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21636 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21636 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8665 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5933 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7038 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14598 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 649.780792 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3376.631612 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13908 95.27% 95.27% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 186 1.27% 96.55% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 234 1.60% 98.15% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 108 0.74% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 46 0.32% 99.21% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 30 0.21% 99.41% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 8 0.05% 99.47% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 4 0.03% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.97% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14569 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5700 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9917.122912 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6183.592938 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1944 34.11% 34.11% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3149 55.25% 89.35% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 398 6.98% 96.33% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 155 2.72% 99.05% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 22 0.39% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.42% 99.86% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.95% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14598 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5531 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11435.002712 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10101.039860 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6336.393968 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1833 33.14% 33.14% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3041 54.98% 88.12% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 457 8.26% 96.38% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 138 2.50% 98.88% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 31 0.56% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 23 0.42% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 4 0.07% 99.93% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 2 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5700 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 72594020264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.245062 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.433850 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 72572506264 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 16659500 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 2233500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 1798000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 337000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 155000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 133000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 72594020264 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1956 73.89% 73.89% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 691 26.11% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21486 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkCompletionTime::total 5531 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 68460974968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.179525 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.388721 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 68438733968 99.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 17027000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 2383000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 1817500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 437500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 205000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12-13 153500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14-15 216500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 68460974968 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1927 75.51% 75.51% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 625 24.49% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2552 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21636 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21486 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21636 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2552 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24133 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2552 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24188 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4198525 # DTB read hits -system.cpu1.dtb.read_misses 18524 # DTB read misses -system.cpu1.dtb.write_hits 3495808 # DTB write hits -system.cpu1.dtb.write_misses 2962 # DTB write misses +system.cpu1.dtb.read_hits 10130487 # DTB read hits +system.cpu1.dtb.read_misses 18672 # DTB read misses +system.cpu1.dtb.write_hits 6476473 # DTB write hits +system.cpu1.dtb.write_misses 2964 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1985 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 390 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1961 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 63 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 385 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4217049 # DTB read accesses -system.cpu1.dtb.write_accesses 3498770 # DTB write accesses +system.cpu1.dtb.perms_faults 370 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 10149159 # DTB read accesses +system.cpu1.dtb.write_accesses 6479437 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7694333 # DTB hits -system.cpu1.dtb.misses 21486 # DTB misses -system.cpu1.dtb.accesses 7715819 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 16606960 # DTB hits +system.cpu1.dtb.misses 21636 # DTB misses +system.cpu1.dtb.accesses 16628596 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1770,62 +1773,57 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5992 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5992 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2735 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2646 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 611 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5381 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 357.461438 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2249.604382 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 5186 96.38% 96.38% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.80% 97.18% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 39 0.72% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.39% 98.29% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 21 0.39% 98.68% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 16 0.30% 98.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 17 0.32% 99.29% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 9 0.17% 99.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.11% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.04% 99.61% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 6 0.11% 99.72% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 3 0.06% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.07% 99.85% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::30720-32767 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5381 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1781 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6875.589868 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-16383 1655 92.93% 92.93% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-32767 93 5.22% 98.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-49151 29 1.63% 99.78% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-65535 1 0.06% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.06% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::131072-147455 2 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1781 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16739710416 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.877376 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.328141 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2053443264 12.27% 12.27% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14685521152 87.73% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 746000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16739710416 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 995 85.04% 85.04% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 175 14.96% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1170 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 6064 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6064 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2840 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2623 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 601 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5463 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 343.950211 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2166.504505 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 5312 97.24% 97.24% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 57 1.04% 98.28% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 43 0.79% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 29 0.53% 99.60% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 6 0.11% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 5 0.09% 99.80% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.09% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 5 0.09% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5463 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1764 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 12147.108844 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 11115.999882 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5636.944380 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 277 15.70% 15.70% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 1298 73.58% 89.29% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 111 6.29% 95.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 59 3.34% 98.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 9 0.51% 99.43% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.40% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 2 0.11% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1764 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16901758916 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.861276 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.345783 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2345411264 13.88% 13.88% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14555617152 86.12% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 730500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16901758916 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 989 85.04% 85.04% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 174 14.96% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1163 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5992 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5992 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6064 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6064 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1170 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1170 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7162 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8257878 # ITB inst hits -system.cpu1.itb.inst_misses 5992 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1163 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1163 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7227 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 43493383 # ITB inst hits +system.cpu1.itb.inst_misses 6064 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1834,1032 +1832,1023 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1134 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1129 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 581 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8263870 # ITB inst accesses -system.cpu1.itb.hits 8257878 # DTB hits -system.cpu1.itb.misses 5992 # DTB misses -system.cpu1.itb.accesses 8263870 # DTB accesses -system.cpu1.numPwrStateTransitions 5517 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2759 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1017941071.285973 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25840669198.429722 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1966 71.26% 71.26% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 787 28.52% 99.78% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 43499447 # ITB inst accesses +system.cpu1.itb.hits 43493383 # DTB hits +system.cpu1.itb.misses 6064 # DTB misses +system.cpu1.itb.accesses 43499447 # DTB accesses +system.cpu1.numPwrStateTransitions 5513 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2757 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1005805033.413856 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25768715425.209221 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1955 70.91% 70.91% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 798 28.94% 99.85% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::5e+10-1e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959984595936 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2759 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17447990322 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34896767 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 500 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959983620244 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2757 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 53106605878 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2773004477122 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 106214002 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8573013 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24834691 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4691512 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2663382 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 24575638 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 780918 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78787 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 29336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 166978 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 305850 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23292 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8256698 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 107917 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2264 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 34143353 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.885357 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.219701 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 10283907 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 108683336 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 33853439 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 27454766 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 92513470 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3739662 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81877 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 30058 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 180666 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 303073 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23077 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 43492215 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 108878 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2205 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 105285959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.278787 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.339334 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20247760 59.30% 59.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4892921 14.33% 73.63% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1671892 4.90% 78.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7330780 21.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 48617714 46.18% 46.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 13927599 13.23% 59.41% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 7511266 7.13% 66.54% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 35229380 33.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 34143353 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.134440 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.711662 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7142387 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16886237 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8753269 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1097578 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 263882 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 709919 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129188 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23442151 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1047211 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 263882 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8565513 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2371212 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11834998 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8406528 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2701220 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 22274891 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 187368 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 265665 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 37047 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 14963 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1683318 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 22278743 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 103710935 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25664622 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19882725 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2396018 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407656 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 334437 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2896541 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4450446 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3799896 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 626454 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 628235 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21459278 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 560382 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21266552 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 92050 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2043308 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4721488 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 43321 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 34143353 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.622861 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.949388 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 105285959 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.318729 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.023249 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 13161149 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 62754723 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 26539387 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1087783 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1742917 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 736717 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 129511 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 67619846 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1094387 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1742917 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17542611 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2352209 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 57806856 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 23225004 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2616362 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 54744976 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 213737 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 258070 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37169 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 15433 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1611507 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 54654605 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 258629758 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 58168286 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1683 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 52142746 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2511859 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 1875660 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 1802517 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 13071586 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 10382439 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6812181 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 622946 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 790955 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 53883918 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 580977 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 53654093 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93763 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 3608749 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 5111945 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 44050 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 105285959 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.509603 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.847754 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21621380 63.33% 63.33% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6152293 18.02% 81.34% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4252408 12.45% 93.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1859652 5.45% 99.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 257613 0.75% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 72150462 68.53% 68.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 16497460 15.67% 84.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 13036209 12.38% 96.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3323109 3.16% 99.74% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 278707 0.26% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 12 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 34143353 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 105285959 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1436712 29.87% 29.87% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 667 0.01% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.88% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1615148 33.58% 63.46% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1757949 36.54% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 2901953 45.47% 45.47% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 671 0.01% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 45.48% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1666030 26.11% 71.59% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1813313 28.41% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13152288 61.84% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28200 0.13% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4404606 20.71% 82.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3678091 17.30% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36596131 68.21% 68.21% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 45838 0.09% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.29% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3311 0.01% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.30% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 10338451 19.27% 87.57% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6670296 12.43% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21266552 # Type of FU issued -system.cpu1.iq.rate 0.609413 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4810476 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226199 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 81572724 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24071099 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20803651 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6259 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 26072828 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4134 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87634 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 53654093 # Type of FU issued +system.cpu1.iq.rate 0.505151 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6381967 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.118947 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 219063644 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58081406 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 51689844 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6231 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2072 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 1788 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 60031897 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4097 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 89933 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 411414 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10207 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 255357 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 434041 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 639 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 9872 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 275866 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40430 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 77958 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 52151 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 77961 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 263882 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 544522 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 96828 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22060743 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 1742917 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 520776 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 103336 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 54505946 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4450446 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3799896 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 297241 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7639 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 82763 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10207 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 34804 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 119058 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 153862 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21034955 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4309085 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 210133 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 10382439 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6812181 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 296650 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7746 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 89089 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 9872 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 44543 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 120099 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 164642 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 53411917 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 10242028 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 220561 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41083 # number of nop insts executed -system.cpu1.iew.exec_refs 7936975 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3061868 # Number of branches executed -system.cpu1.iew.exec_stores 3627890 # Number of stores executed -system.cpu1.iew.exec_rate 0.602777 # Inst execution rate -system.cpu1.iew.wb_sent 20903580 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20805440 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10431521 # num instructions producing a value -system.cpu1.iew.wb_consumers 16355895 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.596200 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637784 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1829884 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 517061 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142735 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33733433 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.593157 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.351929 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41051 # number of nop insts executed +system.cpu1.iew.exec_refs 16861277 # number of memory reference insts executed +system.cpu1.iew.exec_branches 11793508 # Number of branches executed +system.cpu1.iew.exec_stores 6619249 # Number of stores executed +system.cpu1.iew.exec_rate 0.502871 # Inst execution rate +system.cpu1.iew.wb_sent 53270244 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 51691632 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 25129407 # num instructions producing a value +system.cpu1.iew.wb_consumers 38339279 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.486674 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.655448 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 3369485 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 536927 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 153628 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 103395222 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.492179 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.152090 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24180502 71.68% 71.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5607484 16.62% 88.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1690092 5.01% 93.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 667448 1.98% 95.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 524113 1.55% 96.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 341983 1.01% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 221163 0.66% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 119335 0.35% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 381313 1.13% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 77830115 75.27% 75.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 14293086 13.82% 89.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 6071280 5.87% 94.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 693599 0.67% 95.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1980010 1.91% 97.56% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 1625143 1.57% 99.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 382099 0.37% 99.50% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 124911 0.12% 99.62% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 394979 0.38% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33733433 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16346571 # Number of instructions committed -system.cpu1.commit.committedOps 20009206 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 103395222 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 41318794 # Number of instructions committed +system.cpu1.commit.committedOps 50889001 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7583571 # Number of memory references committed -system.cpu1.commit.loads 4039032 # Number of loads committed -system.cpu1.commit.membars 208429 # Number of memory barriers committed -system.cpu1.commit.branches 2907402 # Number of branches committed +system.cpu1.commit.refs 16484713 # Number of memory references committed +system.cpu1.commit.loads 9948398 # Number of loads committed +system.cpu1.commit.membars 208127 # Number of memory barriers committed +system.cpu1.commit.branches 11637916 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17776817 # Number of committed integer instructions. -system.cpu1.commit.function_calls 462681 # Number of function calls committed. +system.cpu1.commit.int_insts 45745086 # Number of committed integer instructions. +system.cpu1.commit.function_calls 3368055 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12395212 61.95% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 27122 0.14% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4039032 20.19% 82.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3544539 17.71% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 34356210 67.51% 67.51% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 44767 0.09% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.60% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3311 0.01% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.61% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 9948398 19.55% 87.16% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 6536315 12.84% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 20009206 # Class of committed instruction -system.cpu1.commit.bw_lim_events 381313 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 54211090 # The number of ROB reads -system.cpu1.rob.rob_writes 44079362 # The number of ROB writes -system.cpu1.timesIdled 55353 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 753414 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5616440201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16313716 # Number of Instructions Simulated -system.cpu1.committedOps 19976351 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.139106 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.139106 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.467485 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.467485 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23597502 # number of integer regfile reads -system.cpu1.int_regfile_writes 13487852 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 50889001 # Class of committed instruction +system.cpu1.commit.bw_lim_events 394979 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 137189075 # The number of ROB reads +system.cpu1.rob.rob_writes 110398979 # The number of ROB writes +system.cpu1.timesIdled 58975 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 928043 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5545446856 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 41285938 # Number of Instructions Simulated +system.cpu1.committedOps 50856145 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.572644 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.572644 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.388705 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.388705 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 55995090 # number of integer regfile reads +system.cpu1.int_regfile_writes 35603094 # number of integer regfile writes system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 75515975 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6821727 # number of cc regfile writes -system.cpu1.misc_regfile_reads 68877879 # number of misc regfile reads -system.cpu1.misc_regfile_writes 387520 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 189327 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.259638 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6803525 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 189662 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.871840 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 103705106000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.259638 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922382 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15106665 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15106665 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3632818 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3632818 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2917516 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2917516 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48925 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48925 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78194 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78194 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70603 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70603 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6550334 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6550334 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6599259 # number of overall hits -system.cpu1.dcache.overall_hits::total 6599259 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 216356 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 216356 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 400081 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 400081 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30281 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30281 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18627 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18627 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23453 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23453 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 616437 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 616437 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 646718 # number of overall misses -system.cpu1.dcache.overall_misses::total 646718 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3492190500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3492190500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10142172955 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10142172955 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366644000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 366644000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 571781000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 571781000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1485000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1485000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13634363455 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13634363455 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13634363455 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13634363455 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3849174 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3849174 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3317597 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3317597 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79206 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79206 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96821 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96821 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94056 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 94056 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7166771 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7166771 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7245977 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7245977 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056208 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.056208 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120594 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.120594 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382307 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382307 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192386 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192386 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249351 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249351 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086013 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.086013 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089252 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089252 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16140.945941 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16140.945941 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25350.298952 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25350.298952 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19683.470231 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19683.470231 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24379.866115 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24379.866115 # average StoreCondReq miss latency +system.cpu1.cc_regfile_reads 190376100 # number of cc regfile reads +system.cpu1.cc_regfile_writes 15518701 # number of cc regfile writes +system.cpu1.misc_regfile_reads 209095836 # number of misc regfile reads +system.cpu1.misc_regfile_writes 386203 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 187149 # number of replacements +system.cpu1.dcache.tags.tagsinuse 469.748213 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 15687000 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 187502 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 83.663108 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 93899473000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 469.748213 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.917477 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.917477 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 353 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 348 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 5 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.689453 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 32860265 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 32860265 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 9540081 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 9540081 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 5893568 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 5893568 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48959 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48959 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77987 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77987 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70168 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70168 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 15433649 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 15433649 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 15482608 # number of overall hits +system.cpu1.dcache.overall_hits::total 15482608 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 215586 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 215586 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 396166 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 396166 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30156 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30156 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18335 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18335 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23429 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23429 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 611752 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 611752 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 641908 # number of overall misses +system.cpu1.dcache.overall_misses::total 641908 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3514528500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3514528500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 9742278459 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 9742278459 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 360181500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 360181500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 551095500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 551095500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 166500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 166500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13256806959 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13256806959 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13256806959 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13256806959 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 9755667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 9755667 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 6289734 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 6289734 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79115 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79115 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96322 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93597 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 93597 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 16045401 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 16045401 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 16124516 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 16124516 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.022099 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.022099 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.062986 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.062986 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.381167 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.381167 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.190351 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.190351 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.250318 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.250318 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.038126 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.038126 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.039809 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.039809 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16302.211183 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16302.211183 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 24591.404762 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 24591.404762 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19644.477775 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19644.477775 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23521.938623 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23521.938623 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 336 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1512378 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 40281 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.200000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37.545692 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 189327 # number of writebacks -system.cpu1.dcache.writebacks::total 189327 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79455 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79455 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309049 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 309049 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13259 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13259 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 388504 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 388504 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 388504 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 388504 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136901 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 136901 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91032 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 91032 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28913 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28913 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5368 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23453 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23453 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 227933 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 227933 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 256846 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256846 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2438 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5519 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5519 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1914813500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914813500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2474458965 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2474458965 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 498834500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 498834500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96515500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96515500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548354000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548354000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1459000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1459000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4389272465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4389272465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4888106965 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4888106965 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442121000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442121000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442121000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442121000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035566 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027439 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027439 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365035 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365035 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055443 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055443 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249351 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249351 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031804 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031804 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27182.298148 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27182.298148 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17252.948501 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17252.948501 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17979.787630 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17979.787630 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23380.974715 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23380.974715 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 21670.230680 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 21670.230680 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20652.191527 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 20652.191527 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 350 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1431753 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 38 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 39808 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.210526 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 35.966464 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 187150 # number of writebacks +system.cpu1.dcache.writebacks::total 187150 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79090 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79090 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 306284 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 306284 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13036 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13036 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 385374 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 385374 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 385374 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 385374 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136496 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 136496 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 89882 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 89882 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28741 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28741 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5299 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23429 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 226378 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 226378 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 255119 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 255119 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 14517 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 14517 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 11855 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 11855 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 26372 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 26372 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1963325500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1963325500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2363104967 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2363104967 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 488593500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 488593500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 93065000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 93065000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 527670500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 527670500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 162500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 162500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4326430467 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4326430467 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4815023967 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4815023967 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2528366000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2528366000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 2528366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 2528366000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.013991 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014290 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014290 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.363281 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.363281 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055013 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055013 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.250318 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.250318 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.014109 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.014109 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.015822 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.015822 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14383.758498 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14383.758498 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26291.192530 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26291.192530 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16999.878223 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16999.878223 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17562.747688 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17562.747688 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22522.109352 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22522.109352 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19256.853834 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19031.275414 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19031.275414 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143499.188575 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143499.188575 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80108.896539 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80108.896539 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 586343 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.448153 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7647462 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 586855 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.031263 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79062638500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448153 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19111.532335 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19111.532335 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18873.639231 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18873.639231 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 174165.874492 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 174165.874492 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 95873.123009 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 95873.123009 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 589510 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.449637 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 42880129 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 590022 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 72.675475 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79021423000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.449637 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975488 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.975488 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::2 496 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 17099739 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 17099739 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 7647462 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7647462 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7647462 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7647462 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7647462 # number of overall hits -system.cpu1.icache.overall_hits::total 7647462 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 608974 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 608974 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 608974 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 608974 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 608974 # number of overall misses -system.cpu1.icache.overall_misses::total 608974 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5478938231 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5478938231 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5478938231 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5478938231 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5478938231 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5478938231 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8256436 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8256436 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8256436 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8256436 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8256436 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8256436 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073757 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073757 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073757 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073757 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073757 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073757 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8996.998609 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 8996.998609 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 8996.998609 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 8996.998609 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 488402 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41185 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.858735 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 586343 # number of writebacks -system.cpu1.icache.writebacks::total 586343 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22107 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22107 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22107 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22107 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22107 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22107 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586867 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 586867 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 586867 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 586867 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 586867 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 586867 # number of overall MSHR misses +system.cpu1.icache.tags.tag_accesses 87573930 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 87573930 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 42880129 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 42880129 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 42880129 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 42880129 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 42880129 # number of overall hits +system.cpu1.icache.overall_hits::total 42880129 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 611823 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 611823 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 611823 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 611823 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 611823 # number of overall misses +system.cpu1.icache.overall_misses::total 611823 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5700309356 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5700309356 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5700309356 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5700309356 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5700309356 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5700309356 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 43491952 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 43491952 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 43491952 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 43491952 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 43491952 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 43491952 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014067 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014067 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014067 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014067 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014067 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014067 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9316.925575 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9316.925575 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9316.925575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9316.925575 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9316.925575 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 502398 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 42118 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.928344 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 589510 # number of writebacks +system.cpu1.icache.writebacks::total 589510 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 21797 # 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number of ReadReq MSHR uncacheable system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5026245111 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5026245111 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5026245111 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5026245111 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5026245111 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5026245111 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9125500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9125500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9125500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9125500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071080 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071080 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071080 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8564.538662 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90351.485149 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90351.485149 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 204963 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 205672 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 636 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5243631193 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5243631193 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5243631193 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5243631193 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5243631193 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5243631193 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8747999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8747999 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8747999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8747999 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013566 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013566 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013566 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013566 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8887.118861 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8887.118861 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8887.118861 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86613.851485 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86613.851485 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86613.851485 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 195371 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 196016 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 576 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59720 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 51812 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15242.895875 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1332238 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 66423 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 20.056878 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 57640 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 44567 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 14592.313259 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 696647 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 58721 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 11.863677 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14783.108783 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.856539 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.176183 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 447.754371 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.902289 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000602 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000133 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027329 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.930353 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 977 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13602 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 14 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 835 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 128 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4458 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059631 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.830200 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 26728427 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 26728427 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16758 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6223 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 22981 # number of ReadReq hits -system.cpu1.l2cache.WritebackDirty_hits::writebacks 115160 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackDirty_hits::total 115160 # number of WritebackDirty hits -system.cpu1.l2cache.WritebackClean_hits::writebacks 648098 # number of WritebackClean hits -system.cpu1.l2cache.WritebackClean_hits::total 648098 # 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number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2327426995 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3109010995 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 7760500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4210000 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 769613500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2327426995 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1022179654 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4131190649 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7990000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2412179500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2420169500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7990000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 2412179500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 2420169500 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.032168 # mshr miss rate for ReadReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.999957 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.999957 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.548313 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.548313 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027283 # mshr miss rate for ReadCleanReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404520 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404520 # mshr miss rate for ReadSharedReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142055 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for overall accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.550959 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.550959 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041590 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.417775 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.417775 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.153839 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.027680 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.044034 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.041590 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.452812 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174524 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1264000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1264000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1659506 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 839728 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 183739 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180899 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31691 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 827645 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2438 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 153507 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 660509 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 108712 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33822 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71296 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41636 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86274 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68587 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66399 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586867 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 252106 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 259 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1760267 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 848480 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14499 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37693 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2660939 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75086288 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29768550 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68844 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 104949570 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 408766 # Total snoops (count) -system.cpu1.toL2Bus.snoopTraffic 5198376 # Total snoop traffic (bytes) -system.cpu1.toL2Bus.snoop_fanout::samples 1235773 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.169662 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.381410 # Request fanout histogram +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.183275 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15346.794872 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 41062.935524 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 15478.018461 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 15478.018461 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15006.316958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15006.316958 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 33744.960910 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 33744.960910 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 31362.871348 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16784.184169 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16784.184169 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 23897.821570 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15935.318275 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14368.600683 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 31362.871348 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22213.147876 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 41062.935524 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 26654.734523 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 166162.395812 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 165560.918046 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 79108.910891 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 91467.446534 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 91420.296151 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1661462 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 840058 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12360 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 115637 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 106952 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 8685 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 43235 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 842502 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 11855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 11855 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 146735 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 662812 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 29649 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 30154 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 72596 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41626 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86297 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68185 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 65527 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 590026 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 275295 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 251 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1769762 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 885483 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14740 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 38125 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2708110 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75491792 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29665722 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 26616 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 70376 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 105254506 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 347103 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 4899396 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1195777 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.122893 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.349738 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1028949 83.26% 83.26% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 203984 16.51% 99.77% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2840 0.23% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1057509 88.44% 88.44% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 129583 10.84% 99.27% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 8685 0.73% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1235773 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1618384496 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1195777 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1635737987 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80334899 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 81718473 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 880530739 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 885241795 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381648033 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 395391898 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8035982 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8093984 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20499963 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20543974 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2910,33 +2899,33 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40384000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40381000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 328500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 325000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 16000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 92000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 575500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) +system.iobus.reqLayer15.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) +system.iobus.reqLayer18.occupancy 9500 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer19.occupancy 2500 # Layer occupancy (ticks) system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) @@ -2944,32 +2933,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6095500 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6080500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33840000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33803000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187690100 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187681355 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555462 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.555440 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255127474000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555462 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909716 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909716 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255145986000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.555440 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909715 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909715 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2978,14 +2967,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32581877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32581877 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303830223 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303830223 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4336412100 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4336412100 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4336412100 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4336412100 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32543877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32543877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4303510478 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4303510478 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4336054355 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4336054355 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4336054355 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4336054355 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -3002,19 +2991,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129293.162698 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118883.981248 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118883.981248 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129142.369048 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129142.369048 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118802.740669 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118802.740669 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118874.173566 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118874.173566 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118874.173566 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 36 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 5.333333 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3026,14 +3015,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19981877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19981877 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490259225 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2490259225 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2510241102 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2510241102 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2510241102 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2510241102 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19943877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19943877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2489987873 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2489987873 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2509931750 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2509931750 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2509931750 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2509931750 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3042,620 +3031,618 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 132786 # number of replacements -system.l2c.tags.tagsinuse 63192.932289 # Cycle average of tags in use -system.l2c.tags.total_refs 445408 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196622 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.265301 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13716.070006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.287927 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.059977 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8086.686479 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2783.200527 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.598228 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910717 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1777.688460 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 638.769137 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2513.055836 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.209291 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000249 # Average percentage of cache occupancy +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79142.369048 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79142.369048 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68738.622819 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68738.622819 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68810.498684 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68810.498684 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2826111083000 # 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Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000305 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.528732 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6142016 # Number of tag accesses -system.l2c.tags.data_accesses 6142016 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 267222 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 267222 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32477 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2702 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 35179 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2050 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 948 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2998 # 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number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 79 # number of overall hits -system.l2c.overall_hits::cpu0.inst 33758 # number of overall hits -system.l2c.overall_hits::cpu0.data 51155 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46059 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 69 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 37 # number of overall hits -system.l2c.overall_hits::cpu1.inst 13188 # number of overall hits -system.l2c.overall_hits::cpu1.data 11211 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5574 # number of overall hits -system.l2c.overall_hits::total 161319 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9039 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2774 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11813 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 653 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1278 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1931 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11611 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8840 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 20451 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 26 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.028290 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.045712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.030099 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.994158 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 33193 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 32156 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 172 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 5974 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 27047 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 1 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 173 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4634 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 27347 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.506485 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.490662 # 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average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 24906.494523 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 25207.923356 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 92845.835931 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74468.778507 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 84902.303213 # average ReadExReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average ReadSharedReq mshr miss latency +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.014494 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.102835 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.024550 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.018235 # 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mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.084588 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.466078 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.486252 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.115385 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.033708 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.275149 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.250079 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.735778 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.112676 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.055556 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.117868 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.414487 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.557432 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.486252 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 23267.651888 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 22047.747748 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 22685.996564 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 26990 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 23811.111111 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 24670.270270 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 93715.264274 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 74305.927804 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 85511.583406 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average ReadSharedReq mshr miss latency system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 81305.090241 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 84795.762849 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average ReadSharedReq mshr miss latency -system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96534.502071 # average ReadSharedReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 82145.336563 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80673.431734 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96406.532990 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86700 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73944.858586 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 88467.280064 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99723.724266 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 77375 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 73500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 75611.687414 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75042.809864 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 129570.407043 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95286.265989 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 196956.087726 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 148192.365991 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167436.910471 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 523570 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 298445 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 101739.966470 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 61099.009901 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 81567.901703 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92312.727880 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 505464 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 284514 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.membus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.membus.trans_dist::ReadReq 37954 # Transaction distribution -system.membus.trans_dist::ReadResp 212485 # Transaction distribution -system.membus.trans_dist::WriteReq 30889 # Transaction distribution -system.membus.trans_dist::WriteResp 30889 # Transaction distribution -system.membus.trans_dist::WritebackDirty 140037 # Transaction distribution -system.membus.trans_dist::CleanEvict 17084 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74884 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40573 # Transaction distribution +system.membus.trans_dist::ReadResp 209195 # Transaction distribution +system.membus.trans_dist::WriteReq 30887 # Transaction distribution +system.membus.trans_dist::WriteResp 30887 # Transaction distribution +system.membus.trans_dist::WritebackDirty 137421 # Transaction distribution +system.membus.trans_dist::CleanEvict 16935 # Transaction distribution +system.membus.trans_dist::UpgradeReq 65286 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 38770 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::ReadExReq 40212 # Transaction distribution -system.membus.trans_dist::ReadExResp 20363 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174532 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 39566 # Transaction distribution +system.membus.trans_dist::ReadExResp 19573 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 171242 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13624 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661033 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782607 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 638853 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 760423 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 855556 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 833372 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27248 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19150328 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19340658 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27240 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18721784 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 18912106 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21658802 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122046 # Total snoops (count) +system.membus.pkt_size::total 21230250 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 123250 # Total snoops (count) system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) -system.membus.snoop_fanout::samples 435271 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011878 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108336 # Request fanout histogram +system.membus.snoop_fanout::samples 419934 # Request fanout histogram +system.membus.snoop_fanout::mean 0.012350 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.110440 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430101 98.81% 98.81% # Request fanout histogram -system.membus.snoop_fanout::1 5170 1.19% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 414748 98.77% 98.77% # Request fanout histogram +system.membus.snoop_fanout::1 5186 1.23% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 435271 # Request fanout histogram -system.membus.reqLayer0.occupancy 81633500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 419934 # Request fanout histogram +system.membus.reqLayer0.occupancy 81570000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11523000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11357000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1022470046 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 987545766 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1120816043 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1099710840 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1359381 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1385881 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3687,81 +3674,81 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1014149 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 548985 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 155175 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 21000 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 20112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1051858 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 557134 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 188416 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 28173 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 27109 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 1064 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2826111083000 # Cumulative time (in ticks) in various power states system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 486750 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 371053 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 122899 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109975 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43571 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153546 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50842 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50842 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 448796 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4596 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1244094 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315957 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1560051 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34491784 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674154 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40165938 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382861 # Total snoops (count) -system.toL2Bus.snoopTraffic 15835212 # Total snoop traffic (bytes) -system.toL2Bus.snoop_fanout::samples 859470 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.375184 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486300 # Request fanout histogram +system.toL2Bus.trans_dist::ReadResp 525508 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30887 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30887 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 364306 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 131438 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 111511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43584 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 155095 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 19 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 19 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50612 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50612 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 487554 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4612 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1267106 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 367019 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1634125 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 36291756 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5905726 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 42197482 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 390713 # Total snoops (count) +system.toL2Bus.snoopTraffic 15836620 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 903686 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.404217 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.493133 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 537899 62.58% 62.58% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 320683 37.31% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 888 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 539465 59.70% 59.70% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 363157 40.19% 99.88% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 1064 0.12% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 859470 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 886309294 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 903686 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 901600874 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 648979933 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 679704118 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 232794950 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 260937433 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1839 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1856 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2759 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2757 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |