diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-01 13:20:30 -0500 |
| commit | cb9e208a4c1b564556275d9b6ee0257da4208a88 (patch) | |
| tree | 6d1e5d4393ae0758da69261a11c37374c2a47a88 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | |
| parent | 0facc8e1acb9b5261ac49f87ca489ba823c8e9f3 (diff) | |
| download | gem5-cb9e208a4c1b564556275d9b6ee0257da4208a88.tar.xz | |
stats: Update stats to reflect SimpleDRAM changes
This patch bumps the stats to reflect the slight change in how the
retry is handled, and also the pruning of some redundant stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 3053 |
1 files changed, 1532 insertions, 1521 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 93139ea5d..434326c81 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,180 +1,153 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102937 # Number of seconds simulated -sim_ticks 1102937390000 # Number of ticks simulated -final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102950 # Number of seconds simulated +sim_ticks 1102950399000 # Number of ticks simulated +final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 67484 # Simulator instruction rate (inst/s) -host_op_rate 86868 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1208579190 # Simulator tick rate (ticks/s) -host_mem_usage 412736 # Number of bytes of host memory used -host_seconds 912.59 # Real time elapsed on the host -sim_insts 61585042 # Number of instructions simulated -sim_ops 79274675 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 57810 # Simulator instruction rate (inst/s) +host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1035290197 # Simulator tick rate (ticks/s) +host_mem_usage 414988 # Number of bytes of host memory used +host_seconds 1065.35 # Real time elapsed on the host +sim_insts 61588287 # Number of instructions simulated +sim_ops 79281553 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory -system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory +system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257788 # Total number of read requests seen -system.physmem.writeReqs 823390 # Total number of write requests seen -system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400498432 # Total number of bytes read from memory -system.physmem.bytesWritten 52696960 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis +system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257953 # Total number of read requests seen +system.physmem.writeReqs 823537 # Total number of write requests seen +system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400508992 # Total number of bytes read from memory +system.physmem.bytesWritten 52706368 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102936257500 # Total gap between requests +system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102949217500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162835 # Categorize read packet sizes -system.physmem.readPktSize::7 0 # Categorize read packet sizes -system.physmem.readPktSize::8 0 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # categorize write packet sizes -system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2999773 # categorize write packet sizes -system.physmem.writePktSize::3 0 # categorize write packet sizes -system.physmem.writePktSize::4 0 # categorize write packet sizes -system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66554 # categorize write packet sizes -system.physmem.writePktSize::7 0 # categorize write packet sizes -system.physmem.writePktSize::8 0 # categorize write packet sizes -system.physmem.neitherpktsize::0 0 # categorize neither packet sizes -system.physmem.neitherpktsize::1 0 # categorize neither packet sizes -system.physmem.neitherpktsize::2 0 # categorize neither packet sizes -system.physmem.neitherpktsize::3 0 # categorize neither packet sizes -system.physmem.neitherpktsize::4 0 # categorize neither packet sizes -system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes -system.physmem.neitherpktsize::7 0 # categorize neither packet sizes -system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see +system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # Categorize write packet sizes +system.physmem.writePktSize::1 0 # Categorize write packet sizes +system.physmem.writePktSize::2 756836 # Categorize write packet sizes +system.physmem.writePktSize::3 0 # Categorize write packet sizes +system.physmem.writePktSize::4 0 # Categorize write packet sizes +system.physmem.writePktSize::5 0 # Categorize write packet sizes +system.physmem.writePktSize::6 66701 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -187,292 +160,322 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests -system.physmem.totBusLat 31288540000 # Total cycles spent in databus access -system.physmem.totBankLat 8531820000 # Total cycles spent in bank access -system.physmem.avgQLat 31828.06 # Average queueing delay per request -system.physmem.avgBankLat 1363.41 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see +system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests +system.physmem.totBusLat 31289160000 # Total cycles spent in databus access +system.physmem.totBankLat 8530335000 # Total cycles spent in bank access +system.physmem.avgQLat 31830.81 # Average queueing delay per request +system.physmem.avgBankLat 1363.15 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38191.47 # Average memory access latency -system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38193.95 # Average memory access latency +system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.24 # Average write queue length over time -system.physmem.readRowHits 6213872 # Number of row buffer hits during reads -system.physmem.writeRowHits 799892 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.98 # Average write queue length over time +system.physmem.readRowHits 6213974 # Number of row buffer hits during reads +system.physmem.writeRowHits 800028 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155756.04 # Average gap between requests -system.l2c.replacements 72539 # number of replacements -system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use -system.l2c.total_refs 1841179 # Total number of references to valid blocks. -system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.367838 # Average number of references to valid blocks. +system.physmem.avgGap 155751.01 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72704 # number of replacements +system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use +system.l2c.total_refs 1840692 # Total number of references to valid blocks. +system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061172 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.042983 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056720 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058048 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820194 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 21699 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 385844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166771 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30512 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5160 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 591639 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198020 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403892 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581178 # number of Writeback hits -system.l2c.Writeback_hits::total 581178 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1163 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 739 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1902 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits +system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043063 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056709 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.058067 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21930 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4443 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386616 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166642 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30274 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5231 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590416 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 197851 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403403 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581067 # number of Writeback hits +system.l2c.Writeback_hits::total 581067 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1230 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 737 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1967 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58985 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107027 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 21699 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4247 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 385844 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214813 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30512 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 591639 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257005 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510919 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 21699 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4247 # number of overall hits -system.l2c.overall_hits::cpu0.inst 385844 # number of overall hits -system.l2c.overall_hits::cpu0.data 214813 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30512 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5160 # number of overall hits -system.l2c.overall_hits::cpu1.inst 591639 # number of overall hits -system.l2c.overall_hits::cpu1.data 257005 # number of overall hits -system.l2c.overall_hits::total 1510919 # number of overall hits +system.l2c.SCUpgradeReq_hits::total 342 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48406 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58608 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107014 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21930 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4443 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386616 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 215048 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30274 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5231 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 590416 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256459 # number of demand (read+write) hits +system.l2c.demand_hits::total 1510417 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21930 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4443 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386616 # number of overall hits +system.l2c.overall_hits::cpu0.data 215048 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits +system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits +system.l2c.overall_hits::cpu1.data 256459 # number of overall hits +system.l2c.overall_hits::total 1510417 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6268 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6367 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 20 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6307 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6294 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25269 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5150 # 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mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030747 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017672 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.806816 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836622 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.819176 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.763095 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.743268 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755190 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566577 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567568 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567120 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098720 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000501 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000899 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5998436 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits +system.cpu0.branchPred.lookups 6001263 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8902974 # DTB read hits -system.cpu0.dtb.read_misses 28685 # DTB read misses -system.cpu0.dtb.write_hits 5134917 # DTB write hits -system.cpu0.dtb.write_misses 5599 # DTB write misses +system.cpu0.dtb.read_hits 8907872 # DTB read hits +system.cpu0.dtb.read_misses 28815 # DTB read misses +system.cpu0.dtb.write_hits 5138143 # DTB write hits +system.cpu0.dtb.write_misses 5606 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch +system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8931659 # DTB read accesses -system.cpu0.dtb.write_accesses 5140516 # DTB write accesses +system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936687 # DTB read accesses +system.cpu0.dtb.write_accesses 5143749 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14037891 # DTB hits -system.cpu0.dtb.misses 34284 # DTB misses -system.cpu0.dtb.accesses 14072175 # DTB accesses -system.cpu0.itb.inst_hits 4215172 # ITB inst hits -system.cpu0.itb.inst_misses 5141 # ITB inst misses +system.cpu0.dtb.hits 14046015 # DTB hits +system.cpu0.dtb.misses 34421 # DTB misses +system.cpu0.dtb.accesses 14080436 # DTB accesses +system.cpu0.itb.inst_hits 4220167 # ITB inst hits +system.cpu0.itb.inst_misses 5223 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,148 +718,148 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses -system.cpu0.itb.hits 4215172 # DTB hits -system.cpu0.itb.misses 5141 # DTB misses -system.cpu0.itb.accesses 4220313 # DTB accesses -system.cpu0.numCycles 67779631 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses +system.cpu0.itb.hits 4220167 # DTB hits +system.cpu0.itb.misses 5223 # DTB misses +system.cpu0.itb.accesses 4225390 # DTB accesses +system.cpu0.numCycles 67827032 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued @@ -872,361 +887,361 @@ system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued -system.cpu0.iq.rate 0.549060 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued +system.cpu0.iq.rate 0.549010 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118422 # number of nop insts executed -system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4852888 # Number of branches executed -system.cpu0.iew.exec_stores 5394475 # Number of stores executed -system.cpu0.iew.exec_rate 0.543552 # Inst execution rate -system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18273947 # num instructions producing a value -system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value +system.cpu0.iew.exec_nop 118689 # number of nop insts executed +system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4854206 # Number of branches executed +system.cpu0.iew.exec_stores 5397839 # Number of stores executed +system.cpu0.iew.exec_rate 0.543462 # Inst execution rate +system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18281082 # num instructions producing a value +system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23670531 # Number of instructions committed -system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23679748 # Number of instructions committed +system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11418468 # Number of memory references committed -system.cpu0.commit.loads 6271892 # Number of loads committed -system.cpu0.commit.membars 229609 # Number of memory barriers committed -system.cpu0.commit.branches 4243643 # Number of branches committed +system.cpu0.commit.refs 11426897 # Number of memory references committed +system.cpu0.commit.loads 6276420 # Number of loads committed +system.cpu0.commit.membars 229667 # Number of memory barriers committed +system.cpu0.commit.branches 4245051 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489165 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489354 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75500320 # The number of ROB reads -system.cpu0.rob.rob_writes 75691570 # The number of ROB writes -system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23589789 # Number of Instructions Simulated -system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated -system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads -system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads +system.cpu0.rob.rob_reads 75566033 # The number of ROB reads +system.cpu0.rob.rob_writes 75750322 # The number of ROB writes +system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23599006 # Number of Instructions Simulated +system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated +system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads +system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads system.cpu0.fp_regfile_writes 900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads -system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes -system.cpu0.icache.replacements 392135 # number of replacements -system.cpu0.icache.tagsinuse 511.076170 # Cycle average of tags in use -system.cpu0.icache.total_refs 3790159 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 392647 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.652841 # Average number of references to valid blocks. +system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes +system.cpu0.icache.replacements 392871 # number of replacements +system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use +system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits -system.cpu0.icache.overall_hits::total 3790159 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses -system.cpu0.icache.overall_misses::total 423214 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits +system.cpu0.icache.overall_hits::total 3794104 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses +system.cpu0.icache.overall_misses::total 424196 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30799 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393397 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393397 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393397 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393397 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393397 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393397 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4747932997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4747932997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4747932997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4747932997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4747932997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4747932997 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 276137 # number of replacements -system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5777010 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3157960 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3157960 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139054 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139054 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137010 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137010 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8934970 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8934970 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8934970 # number of overall hits -system.cpu0.dcache.overall_hits::total 8934970 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392909 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392909 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1581686 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1581686 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8773 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8773 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7509 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7509 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1974595 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1974595 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1974595 # number of overall misses -system.cpu0.dcache.overall_misses::total 1974595 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5473319500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5473319500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60618366371 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 276008 # number of replacements +system.cpu0.dcache.tagsinuse 460.701040 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9261257 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276520 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.492178 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 460.701040 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899807 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899807 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781540 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781540 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159285 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159285 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139162 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139162 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137068 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137068 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8940825 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8940825 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8940825 # number of overall hits +system.cpu0.dcache.overall_hits::total 8940825 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392645 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392645 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1583929 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1583929 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8775 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8775 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7462 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7462 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976574 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976574 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976574 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976574 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66155153369 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6174185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6174185 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4743214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4743214 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147937 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147937 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144530 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917399 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917399 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917399 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917399 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063595 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063595 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333936 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333936 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059316 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051629 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051629 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks -system.cpu0.dcache.writebacks::total 256527 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks +system.cpu0.dcache.writebacks::total 256612 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1655511 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655511 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1655511 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188793 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188793 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130291 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130291 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8302 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1249,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9086614 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits +system.cpu1.branchPred.lookups 9071093 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42908069 # DTB read hits -system.cpu1.dtb.read_misses 37093 # DTB read misses -system.cpu1.dtb.write_hits 6828111 # DTB write hits -system.cpu1.dtb.write_misses 10566 # DTB write misses +system.cpu1.dtb.read_hits 42899284 # DTB read hits +system.cpu1.dtb.read_misses 36667 # DTB read misses +system.cpu1.dtb.write_hits 6823776 # DTB write hits +system.cpu1.dtb.write_misses 10740 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42945162 # DTB read accesses -system.cpu1.dtb.write_accesses 6838677 # DTB write accesses +system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42935951 # DTB read accesses +system.cpu1.dtb.write_accesses 6834516 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49736180 # DTB hits -system.cpu1.dtb.misses 47659 # DTB misses -system.cpu1.dtb.accesses 49783839 # DTB accesses -system.cpu1.itb.inst_hits 8400139 # ITB inst hits -system.cpu1.itb.inst_misses 5511 # ITB inst misses +system.cpu1.dtb.hits 49723060 # DTB hits +system.cpu1.dtb.misses 47407 # DTB misses +system.cpu1.dtb.accesses 49770467 # DTB accesses +system.cpu1.itb.inst_hits 8396614 # ITB inst hits +system.cpu1.itb.inst_misses 5496 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1289,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses -system.cpu1.itb.hits 8400139 # DTB hits -system.cpu1.itb.misses 5511 # DTB misses -system.cpu1.itb.accesses 8405650 # DTB accesses -system.cpu1.numCycles 408778710 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses +system.cpu1.itb.hits 8396614 # DTB hits +system.cpu1.itb.misses 5496 # DTB misses +system.cpu1.itb.accesses 8402110 # DTB accesses +system.cpu1.numCycles 408759365 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,399 +1424,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued -system.cpu1.iq.rate 0.218115 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued +system.cpu1.iq.rate 0.218037 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104517 # number of nop insts executed -system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7007502 # Number of branches executed -system.cpu1.iew.exec_stores 7113991 # Number of stores executed -system.cpu1.iew.exec_rate 0.212186 # Inst execution rate -system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29917161 # num instructions producing a value -system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value +system.cpu1.iew.exec_nop 104622 # number of nop insts executed +system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7000416 # Number of branches executed +system.cpu1.iew.exec_stores 7109526 # Number of stores executed +system.cpu1.iew.exec_rate 0.212092 # Inst execution rate +system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29911901 # num instructions producing a value +system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38064892 # Number of instructions committed -system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38058920 # Number of instructions committed +system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595277 # Number of memory references committed -system.cpu1.commit.loads 9755144 # Number of loads committed -system.cpu1.commit.membars 190149 # Number of memory barriers committed -system.cpu1.commit.branches 5967637 # Number of branches committed -system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534638 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16590474 # Number of memory references committed +system.cpu1.commit.loads 9752596 # Number of loads committed +system.cpu1.commit.membars 190088 # Number of memory barriers committed +system.cpu1.commit.branches 5966646 # Number of branches committed +system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534484 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 173015978 # The number of ROB reads -system.cpu1.rob.rob_writes 131360292 # The number of ROB writes -system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995253 # Number of Instructions Simulated -system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated -system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads -system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes -system.cpu1.icache.replacements 597992 # number of replacements -system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use -system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits -system.cpu1.icache.overall_hits::total 7754983 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses -system.cpu1.icache.overall_misses::total 643188 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8398171 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076587 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076587 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076587 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076587 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076587 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076587 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13467.492391 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13467.492391 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13467.492391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked +system.cpu1.rob.rob_reads 172926580 # The number of ROB reads +system.cpu1.rob.rob_writes 131236338 # The number of ROB writes +system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37989281 # Number of Instructions Simulated +system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated +system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads +system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes +system.cpu1.icache.replacements 596801 # number of replacements +system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use +system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits +system.cpu1.icache.overall_hits::total 7752714 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses +system.cpu1.icache.overall_misses::total 641884 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.509091 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44542 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44542 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44542 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44542 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44542 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44542 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597342 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 597342 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 597342 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 597342 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 597342 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 597342 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7075238492 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7075238492 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7075238492 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7075238492 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7075238492 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7075238492 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071158 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071158 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071158 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071158 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11844.535445 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # 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number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4139176 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97757 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97757 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94875 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94875 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12445985 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12445985 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12445985 # number of overall hits -system.cpu1.dcache.overall_hits::total 12445985 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 399972 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 399972 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1557467 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1557467 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14022 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14022 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10623 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10623 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1957439 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1957439 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1957439 # number of overall misses -system.cpu1.dcache.overall_misses::total 1957439 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6115655000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6115655000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61487432499 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61487432499 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129927000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129927000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53882500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53882500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67603087499 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67603087499 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67603087499 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67603087499 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706781 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8706781 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696643 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5696643 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111779 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111779 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105498 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105498 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14403424 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14403424 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14403424 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14403424 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045938 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045938 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273401 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273401 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125444 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100694 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100694 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135901 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135901 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135901 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135901 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9265.939238 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9265.939238 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.248894 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 30853 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 12637 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3329 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.267948 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 80.490446 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360372 # number of replacements +system.cpu1.dcache.tagsinuse 474.682760 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12670584 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360741 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.123770 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.682760 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927115 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927115 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8303637 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8303637 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4137955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4137955 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97570 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97570 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94868 # 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number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1956734 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1956734 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1956734 # number of overall misses +system.cpu1.dcache.overall_misses::total 1956734 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6110776000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6110776000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61798994997 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61798994997 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 128780500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 128780500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53871000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53871000 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67909770997 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67909770997 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67909770997 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67909770997 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703766 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703766 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5694560 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111522 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111522 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105472 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14398326 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14398326 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14398326 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14398326 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045972 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045972 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273349 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273349 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125105 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100539 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100539 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135900 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135900 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34705.673330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34705.673330 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34705.673330 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24403 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13534 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks -system.cpu1.dcache.writebacks::total 324651 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395801 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1444 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1444 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567533 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1567533 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567533 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1567533 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228240 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228240 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161666 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161666 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12578 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89046000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89046000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32648500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32648500 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7987605707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7987605707 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7987605707 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks +system.cpu1.dcache.writebacks::total 324455 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1823,18 +1834,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |