diff options
author | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 16:18:51 -0500 |
---|---|---|
committer | Nilay Vaish <nilay@cs.wisc.edu> | 2014-10-11 16:18:51 -0500 |
commit | 1efe42fa97ed03662666cafee1b9dec9dfe524e9 (patch) | |
tree | dd35dfa8f257445840ea3afe71ebdce4d8e4030e /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
parent | 8e07b36d2b6c1db8c4196336acc66d16e63f8ff3 (diff) | |
download | gem5-1efe42fa97ed03662666cafee1b9dec9dfe524e9.tar.xz |
stats: updates due to changes to x86, stale configs.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini | 792 |
1 files changed, 441 insertions, 351 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 319208ed0..a054d64a7 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -99,12 +99,12 @@ voltage_domain=system.voltage_domain [system.cpu0] type=DerivO3CPU -children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer LFSTSize=1024 -LQEntries=32 +LQEntries=16 LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 +LSQDepCheckShift=0 +SQEntries=16 SSITSize=1024 activity=0 backComSize=5 @@ -119,19 +119,20 @@ commitToRenameDelay=1 commitWidth=8 cpu_id=0 decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -dispatchWidth=8 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dstage2_mmu=system.cpu0.dstage2_mmu dtb=system.cpu0.dtb eventq_index=0 -fetchBufferSize=64 -fetchToDecodeDelay=1 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 fetchTrapLatency=1 -fetchWidth=8 +fetchWidth=3 forwardComSize=5 fuPool=system.cpu0.fuPool function_trace=false @@ -151,20 +152,20 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 numRobs=1 numThreads=1 profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 -renameToIEWDelay=2 +renameToIEWDelay=1 renameToROBDelay=1 -renameWidth=8 +renameWidth=3 simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread @@ -182,7 +183,6 @@ switched_out=false system=system tracer=system.cpu0.tracer trapLatency=13 -wbDepth=1 wbWidth=8 workload= dcache_port=system.cpu0.dcache.cpu_side @@ -190,8 +190,8 @@ icache_port=system.cpu0.icache.cpu_side [system.cpu0.branchPred] type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 +BTBEntries=2048 +BTBTagSize=18 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 @@ -203,20 +203,20 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament +predType=bi-mode [system.cpu0.dcache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -224,15 +224,15 @@ sequential_access=false size=32768 system=system tags=system.cpu0.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu0.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu0.toL2Bus.slave[1] [system.cpu0.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -262,7 +262,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[5] +port=system.cpu0.toL2Bus.slave[5] [system.cpu0.dtb] type=ArmTLB @@ -279,18 +279,18 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu0.toL2Bus.slave[3] [system.cpu0.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList -count=6 +count=2 eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList @@ -303,10 +303,10 @@ opLat=1 [system.cpu0.fuPool.FUList1] type=FUDesc -children=opList0 opList1 -count=2 +children=opList0 opList1 opList2 +count=1 eventq_index=0 -opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 system.cpu0.fuPool.FUList1.opList2 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc @@ -318,308 +318,266 @@ opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 +issueLat=12 opClass=IntDiv -opLat=20 - -[system.cpu0.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 +opLat=12 -[system.cpu0.fuPool.FUList2.opList0] +[system.cpu0.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 issueLat=1 -opClass=FloatAdd -opLat=2 +opClass=IprAccess +opLat=3 -[system.cpu0.fuPool.FUList2.opList1] -type=OpDesc +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList +count=1 eventq_index=0 -issueLat=1 -opClass=FloatCmp -opLat=2 +opList=system.cpu0.fuPool.FUList2.opList -[system.cpu0.fuPool.FUList2.opList2] +[system.cpu0.fuPool.FUList2.opList] type=OpDesc eventq_index=0 issueLat=1 -opClass=FloatCvt +opClass=MemRead opLat=2 [system.cpu0.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 - -[system.cpu0.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu0.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu0.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu0.fuPool.FUList4] -type=FUDesc children=opList -count=0 +count=1 eventq_index=0 -opList=system.cpu0.fuPool.FUList4.opList +opList=system.cpu0.fuPool.FUList3.opList -[system.cpu0.fuPool.FUList4.opList] +[system.cpu0.fuPool.FUList3.opList] type=OpDesc eventq_index=0 issueLat=1 -opClass=MemRead -opLat=1 +opClass=MemWrite +opLat=2 -[system.cpu0.fuPool.FUList5] +[system.cpu0.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 eventq_index=0 -opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 +opList=system.cpu0.fuPool.FUList4.opList00 system.cpu0.fuPool.FUList4.opList01 system.cpu0.fuPool.FUList4.opList02 system.cpu0.fuPool.FUList4.opList03 system.cpu0.fuPool.FUList4.opList04 system.cpu0.fuPool.FUList4.opList05 system.cpu0.fuPool.FUList4.opList06 system.cpu0.fuPool.FUList4.opList07 system.cpu0.fuPool.FUList4.opList08 system.cpu0.fuPool.FUList4.opList09 system.cpu0.fuPool.FUList4.opList10 system.cpu0.fuPool.FUList4.opList11 system.cpu0.fuPool.FUList4.opList12 system.cpu0.fuPool.FUList4.opList13 system.cpu0.fuPool.FUList4.opList14 system.cpu0.fuPool.FUList4.opList15 system.cpu0.fuPool.FUList4.opList16 system.cpu0.fuPool.FUList4.opList17 system.cpu0.fuPool.FUList4.opList18 system.cpu0.fuPool.FUList4.opList19 system.cpu0.fuPool.FUList4.opList20 system.cpu0.fuPool.FUList4.opList21 system.cpu0.fuPool.FUList4.opList22 system.cpu0.fuPool.FUList4.opList23 system.cpu0.fuPool.FUList4.opList24 system.cpu0.fuPool.FUList4.opList25 -[system.cpu0.fuPool.FUList5.opList00] +[system.cpu0.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdAdd -opLat=1 +opLat=4 -[system.cpu0.fuPool.FUList5.opList01] +[system.cpu0.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdAddAcc -opLat=1 +opLat=4 -[system.cpu0.fuPool.FUList5.opList02] +[system.cpu0.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdAlu -opLat=1 +opLat=4 -[system.cpu0.fuPool.FUList5.opList03] +[system.cpu0.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdCmp -opLat=1 +opLat=4 -[system.cpu0.fuPool.FUList5.opList04] +[system.cpu0.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdCvt -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList05] +[system.cpu0.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdMisc -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList06] +[system.cpu0.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdMult -opLat=1 +opLat=5 -[system.cpu0.fuPool.FUList5.opList07] +[system.cpu0.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdMultAcc -opLat=1 +opLat=5 -[system.cpu0.fuPool.FUList5.opList08] +[system.cpu0.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdShift -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList09] +[system.cpu0.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdShiftAcc -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList10] +[system.cpu0.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdSqrt -opLat=1 +opLat=9 -[system.cpu0.fuPool.FUList5.opList11] +[system.cpu0.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatAdd -opLat=1 +opLat=5 -[system.cpu0.fuPool.FUList5.opList12] +[system.cpu0.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatAlu -opLat=1 +opLat=5 -[system.cpu0.fuPool.FUList5.opList13] +[system.cpu0.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatCmp -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList14] +[system.cpu0.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatCvt -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList15] +[system.cpu0.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatDiv -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList16] +[system.cpu0.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatMisc -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList17] +[system.cpu0.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatMult -opLat=1 +opLat=3 -[system.cpu0.fuPool.FUList5.opList18] +[system.cpu0.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 -[system.cpu0.fuPool.FUList5.opList19] +[system.cpu0.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatSqrt -opLat=1 +opLat=9 -[system.cpu0.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu0.fuPool.FUList6.opList - -[system.cpu0.fuPool.FUList6.opList] +[system.cpu0.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 issueLat=1 -opClass=MemWrite -opLat=1 +opClass=FloatAdd +opLat=5 -[system.cpu0.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 +[system.cpu0.fuPool.FUList4.opList21] +type=OpDesc eventq_index=0 -opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 +issueLat=1 +opClass=FloatCmp +opLat=5 -[system.cpu0.fuPool.FUList7.opList0] +[system.cpu0.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 issueLat=1 -opClass=MemRead -opLat=1 +opClass=FloatCvt +opLat=5 -[system.cpu0.fuPool.FUList7.opList1] +[system.cpu0.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=1 -opClass=MemWrite -opLat=1 +issueLat=9 +opClass=FloatDiv +opLat=9 -[system.cpu0.fuPool.FUList8] -type=FUDesc -children=opList -count=1 +[system.cpu0.fuPool.FUList4.opList24] +type=OpDesc eventq_index=0 -opList=system.cpu0.fuPool.FUList8.opList +issueLat=33 +opClass=FloatSqrt +opLat=33 -[system.cpu0.fuPool.FUList8.opList] +[system.cpu0.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=3 -opClass=IprAccess -opLat=3 +issueLat=1 +opClass=FloatMult +opLat=4 [system.cpu0.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu0.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu0.toL2Bus.slave[0] [system.cpu0.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -678,7 +636,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[4] +port=system.cpu0.toL2Bus.slave[4] [system.cpu0.itb] type=ArmTLB @@ -695,7 +653,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu0.toL2Bus.slave[2] + +[system.cpu0.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu0.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu0.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu0.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu0.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu0.l2cache.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port [system.cpu0.tracer] type=ExeTracer @@ -703,12 +725,12 @@ eventq_index=0 [system.cpu1] type=DerivO3CPU -children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb tracer +children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer LFSTSize=1024 -LQEntries=32 +LQEntries=16 LSQCheckLoads=true -LSQDepCheckShift=4 -SQEntries=32 +LSQDepCheckShift=0 +SQEntries=16 SSITSize=1024 activity=0 backComSize=5 @@ -723,19 +745,20 @@ commitToRenameDelay=1 commitWidth=8 cpu_id=1 decodeToFetchDelay=1 -decodeToRenameDelay=1 -decodeWidth=8 -dispatchWidth=8 +decodeToRenameDelay=2 +decodeWidth=3 +dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dstage2_mmu=system.cpu1.dstage2_mmu dtb=system.cpu1.dtb eventq_index=0 -fetchBufferSize=64 -fetchToDecodeDelay=1 +fetchBufferSize=16 +fetchQueueSize=32 +fetchToDecodeDelay=3 fetchTrapLatency=1 -fetchWidth=8 +fetchWidth=3 forwardComSize=5 fuPool=system.cpu1.fuPool function_trace=false @@ -755,20 +778,20 @@ max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 needsTSO=false -numIQEntries=64 -numPhysCCRegs=0 -numPhysFloatRegs=256 -numPhysIntRegs=256 -numROBEntries=192 +numIQEntries=32 +numPhysCCRegs=640 +numPhysFloatRegs=192 +numPhysIntRegs=128 +numROBEntries=40 numRobs=1 numThreads=1 profile=0 progress_interval=0 renameToDecodeDelay=1 renameToFetchDelay=1 -renameToIEWDelay=2 +renameToIEWDelay=1 renameToROBDelay=1 -renameWidth=8 +renameWidth=3 simpoint_start_insts= smtCommitPolicy=RoundRobin smtFetchPolicy=SingleThread @@ -786,7 +809,6 @@ switched_out=false system=system tracer=system.cpu1.tracer trapLatency=13 -wbDepth=1 wbWidth=8 workload= dcache_port=system.cpu1.dcache.cpu_side @@ -794,8 +816,8 @@ icache_port=system.cpu1.icache.cpu_side [system.cpu1.branchPred] type=BranchPredictor -BTBEntries=4096 -BTBTagSize=16 +BTBEntries=2048 +BTBTagSize=18 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 @@ -807,20 +829,20 @@ localCtrBits=2 localHistoryTableSize=2048 localPredictorSize=2048 numThreads=1 -predType=tournament +predType=bi-mode [system.cpu1.dcache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=4 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=6 prefetch_on_access=false prefetcher=Null response_latency=2 @@ -828,15 +850,15 @@ sequential_access=false size=32768 system=system tags=system.cpu1.dcache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false -write_buffers=8 +write_buffers=16 cpu_side=system.cpu1.dcache_port -mem_side=system.toL2Bus.slave[7] +mem_side=system.cpu1.toL2Bus.slave[1] [system.cpu1.dcache.tags] type=LRU -assoc=4 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 @@ -866,7 +888,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[11] +port=system.cpu1.toL2Bus.slave[5] [system.cpu1.dtb] type=ArmTLB @@ -883,18 +905,18 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[9] +port=system.cpu1.toL2Bus.slave[3] [system.cpu1.fuPool] type=FUPool -children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 -FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +children=FUList0 FUList1 FUList2 FUList3 FUList4 +FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList -count=6 +count=2 eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList @@ -907,10 +929,10 @@ opLat=1 [system.cpu1.fuPool.FUList1] type=FUDesc -children=opList0 opList1 -count=2 +children=opList0 opList1 opList2 +count=1 eventq_index=0 -opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 +opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 system.cpu1.fuPool.FUList1.opList2 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc @@ -922,308 +944,266 @@ opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc eventq_index=0 -issueLat=19 +issueLat=12 opClass=IntDiv -opLat=20 - -[system.cpu1.fuPool.FUList2] -type=FUDesc -children=opList0 opList1 opList2 -count=4 -eventq_index=0 -opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 +opLat=12 -[system.cpu1.fuPool.FUList2.opList0] +[system.cpu1.fuPool.FUList1.opList2] type=OpDesc eventq_index=0 issueLat=1 -opClass=FloatAdd -opLat=2 +opClass=IprAccess +opLat=3 -[system.cpu1.fuPool.FUList2.opList1] -type=OpDesc +[system.cpu1.fuPool.FUList2] +type=FUDesc +children=opList +count=1 eventq_index=0 -issueLat=1 -opClass=FloatCmp -opLat=2 +opList=system.cpu1.fuPool.FUList2.opList -[system.cpu1.fuPool.FUList2.opList2] +[system.cpu1.fuPool.FUList2.opList] type=OpDesc eventq_index=0 issueLat=1 -opClass=FloatCvt +opClass=MemRead opLat=2 [system.cpu1.fuPool.FUList3] type=FUDesc -children=opList0 opList1 opList2 -count=2 -eventq_index=0 -opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 - -[system.cpu1.fuPool.FUList3.opList0] -type=OpDesc -eventq_index=0 -issueLat=1 -opClass=FloatMult -opLat=4 - -[system.cpu1.fuPool.FUList3.opList1] -type=OpDesc -eventq_index=0 -issueLat=12 -opClass=FloatDiv -opLat=12 - -[system.cpu1.fuPool.FUList3.opList2] -type=OpDesc -eventq_index=0 -issueLat=24 -opClass=FloatSqrt -opLat=24 - -[system.cpu1.fuPool.FUList4] -type=FUDesc children=opList -count=0 +count=1 eventq_index=0 -opList=system.cpu1.fuPool.FUList4.opList +opList=system.cpu1.fuPool.FUList3.opList -[system.cpu1.fuPool.FUList4.opList] +[system.cpu1.fuPool.FUList3.opList] type=OpDesc eventq_index=0 issueLat=1 -opClass=MemRead -opLat=1 +opClass=MemWrite +opLat=2 -[system.cpu1.fuPool.FUList5] +[system.cpu1.fuPool.FUList4] type=FUDesc -children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 -count=4 +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 +count=2 eventq_index=0 -opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 +opList=system.cpu1.fuPool.FUList4.opList00 system.cpu1.fuPool.FUList4.opList01 system.cpu1.fuPool.FUList4.opList02 system.cpu1.fuPool.FUList4.opList03 system.cpu1.fuPool.FUList4.opList04 system.cpu1.fuPool.FUList4.opList05 system.cpu1.fuPool.FUList4.opList06 system.cpu1.fuPool.FUList4.opList07 system.cpu1.fuPool.FUList4.opList08 system.cpu1.fuPool.FUList4.opList09 system.cpu1.fuPool.FUList4.opList10 system.cpu1.fuPool.FUList4.opList11 system.cpu1.fuPool.FUList4.opList12 system.cpu1.fuPool.FUList4.opList13 system.cpu1.fuPool.FUList4.opList14 system.cpu1.fuPool.FUList4.opList15 system.cpu1.fuPool.FUList4.opList16 system.cpu1.fuPool.FUList4.opList17 system.cpu1.fuPool.FUList4.opList18 system.cpu1.fuPool.FUList4.opList19 system.cpu1.fuPool.FUList4.opList20 system.cpu1.fuPool.FUList4.opList21 system.cpu1.fuPool.FUList4.opList22 system.cpu1.fuPool.FUList4.opList23 system.cpu1.fuPool.FUList4.opList24 system.cpu1.fuPool.FUList4.opList25 -[system.cpu1.fuPool.FUList5.opList00] +[system.cpu1.fuPool.FUList4.opList00] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdAdd -opLat=1 +opLat=4 -[system.cpu1.fuPool.FUList5.opList01] +[system.cpu1.fuPool.FUList4.opList01] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdAddAcc -opLat=1 +opLat=4 -[system.cpu1.fuPool.FUList5.opList02] +[system.cpu1.fuPool.FUList4.opList02] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdAlu -opLat=1 +opLat=4 -[system.cpu1.fuPool.FUList5.opList03] +[system.cpu1.fuPool.FUList4.opList03] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdCmp -opLat=1 +opLat=4 -[system.cpu1.fuPool.FUList5.opList04] +[system.cpu1.fuPool.FUList4.opList04] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdCvt -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList05] +[system.cpu1.fuPool.FUList4.opList05] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdMisc -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList06] +[system.cpu1.fuPool.FUList4.opList06] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdMult -opLat=1 +opLat=5 -[system.cpu1.fuPool.FUList5.opList07] +[system.cpu1.fuPool.FUList4.opList07] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdMultAcc -opLat=1 +opLat=5 -[system.cpu1.fuPool.FUList5.opList08] +[system.cpu1.fuPool.FUList4.opList08] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdShift -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList09] +[system.cpu1.fuPool.FUList4.opList09] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdShiftAcc -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList10] +[system.cpu1.fuPool.FUList4.opList10] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdSqrt -opLat=1 +opLat=9 -[system.cpu1.fuPool.FUList5.opList11] +[system.cpu1.fuPool.FUList4.opList11] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatAdd -opLat=1 +opLat=5 -[system.cpu1.fuPool.FUList5.opList12] +[system.cpu1.fuPool.FUList4.opList12] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatAlu -opLat=1 +opLat=5 -[system.cpu1.fuPool.FUList5.opList13] +[system.cpu1.fuPool.FUList4.opList13] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatCmp -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList14] +[system.cpu1.fuPool.FUList4.opList14] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatCvt -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList15] +[system.cpu1.fuPool.FUList4.opList15] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatDiv -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList16] +[system.cpu1.fuPool.FUList4.opList16] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatMisc -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList17] +[system.cpu1.fuPool.FUList4.opList17] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatMult -opLat=1 +opLat=3 -[system.cpu1.fuPool.FUList5.opList18] +[system.cpu1.fuPool.FUList4.opList18] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 -[system.cpu1.fuPool.FUList5.opList19] +[system.cpu1.fuPool.FUList4.opList19] type=OpDesc eventq_index=0 issueLat=1 opClass=SimdFloatSqrt -opLat=1 - -[system.cpu1.fuPool.FUList6] -type=FUDesc -children=opList -count=0 -eventq_index=0 -opList=system.cpu1.fuPool.FUList6.opList +opLat=9 -[system.cpu1.fuPool.FUList6.opList] +[system.cpu1.fuPool.FUList4.opList20] type=OpDesc eventq_index=0 issueLat=1 -opClass=MemWrite -opLat=1 +opClass=FloatAdd +opLat=5 -[system.cpu1.fuPool.FUList7] -type=FUDesc -children=opList0 opList1 -count=4 +[system.cpu1.fuPool.FUList4.opList21] +type=OpDesc eventq_index=0 -opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 +issueLat=1 +opClass=FloatCmp +opLat=5 -[system.cpu1.fuPool.FUList7.opList0] +[system.cpu1.fuPool.FUList4.opList22] type=OpDesc eventq_index=0 issueLat=1 -opClass=MemRead -opLat=1 +opClass=FloatCvt +opLat=5 -[system.cpu1.fuPool.FUList7.opList1] +[system.cpu1.fuPool.FUList4.opList23] type=OpDesc eventq_index=0 -issueLat=1 -opClass=MemWrite -opLat=1 +issueLat=9 +opClass=FloatDiv +opLat=9 -[system.cpu1.fuPool.FUList8] -type=FUDesc -children=opList -count=1 +[system.cpu1.fuPool.FUList4.opList24] +type=OpDesc eventq_index=0 -opList=system.cpu1.fuPool.FUList8.opList +issueLat=33 +opClass=FloatSqrt +opLat=33 -[system.cpu1.fuPool.FUList8.opList] +[system.cpu1.fuPool.FUList4.opList25] type=OpDesc eventq_index=0 -issueLat=3 -opClass=IprAccess -opLat=3 +issueLat=1 +opClass=FloatMult +opLat=4 [system.cpu1.icache] type=BaseCache children=tags addr_ranges=0:18446744073709551615 -assoc=1 +assoc=2 clk_domain=system.cpu_clk_domain eventq_index=0 forward_snoops=true -hit_latency=2 +hit_latency=1 is_top_level=true max_miss_count=0 -mshrs=4 +mshrs=2 prefetch_on_access=false prefetcher=Null -response_latency=2 +response_latency=1 sequential_access=false size=32768 system=system tags=system.cpu1.icache.tags -tgts_per_mshr=20 +tgts_per_mshr=8 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port -mem_side=system.toL2Bus.slave[6] +mem_side=system.cpu1.toL2Bus.slave[0] [system.cpu1.icache.tags] type=LRU -assoc=1 +assoc=2 block_size=64 clk_domain=system.cpu_clk_domain eventq_index=0 -hit_latency=2 +hit_latency=1 sequential_access=false size=32768 @@ -1282,7 +1262,7 @@ eventq_index=0 is_stage2=true num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[10] +port=system.cpu1.toL2Bus.slave[4] [system.cpu1.itb] type=ArmTLB @@ -1299,7 +1279,71 @@ eventq_index=0 is_stage2=false num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[8] +port=system.cpu1.toL2Bus.slave[2] + +[system.cpu1.l2cache] +type=BaseCache +children=prefetcher tags +addr_ranges=0:18446744073709551615 +assoc=16 +clk_domain=system.cpu_clk_domain +eventq_index=0 +forward_snoops=true +hit_latency=12 +is_top_level=false +max_miss_count=0 +mshrs=16 +prefetch_on_access=true +prefetcher=system.cpu1.l2cache.prefetcher +response_latency=12 +sequential_access=false +size=1048576 +system=system +tags=system.cpu1.l2cache.tags +tgts_per_mshr=8 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.toL2Bus.master[0] +mem_side=system.toL2Bus.slave[1] + +[system.cpu1.l2cache.prefetcher] +type=StridePrefetcher +clk_domain=system.cpu_clk_domain +cross_pages=false +data_accesses_only=false +degree=8 +eventq_index=0 +inst_tagged=true +latency=1 +on_miss_only=false +on_prefetch=true +on_read_only=false +serial_squash=false +size=100 +sys=system +use_master_id=true + +[system.cpu1.l2cache.tags] +type=RandomRepl +assoc=16 +block_size=64 +clk_domain=system.cpu_clk_domain +eventq_index=0 +hit_latency=12 +sequential_access=false +size=1048576 + +[system.cpu1.toL2Bus] +type=CoherentXBar +clk_domain=system.cpu_clk_domain +eventq_index=0 +header_cycles=1 +snoop_filter=Null +system=system +use_default_range=false +width=32 +master=system.cpu1.l2cache.cpu_side +slave=system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port [system.cpu1.tracer] type=ExeTracer @@ -1327,13 +1371,13 @@ eventq_index=0 sys=system [system.iobus] -type=NoncoherentBus +type=NoncoherentXBar clk_domain=system.clk_domain eventq_index=0 header_cycles=1 use_default_range=false width=8 -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.realview.energy_ctrl.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] @@ -1358,7 +1402,7 @@ tags=system.iocache.tags tgts_per_mshr=12 two_queue=false write_buffers=8 -cpu_side=system.iobus.master[25] +cpu_side=system.iobus.master[26] mem_side=system.membus.slave[2] [system.iocache.tags] @@ -1407,11 +1451,12 @@ sequential_access=false size=4194304 [system.membus] -type=CoherentBus +type=CoherentXBar children=badaddr_responder clk_domain=system.clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 @@ -1439,8 +1484,33 @@ pio=system.membus.default [system.physmem] type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 activation_limit=4 addr_mapping=RoRaBaChCo +bank_groups_per_rank=0 banks_per_rank=8 burst_length=8 channels=1 @@ -1449,6 +1519,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +dll=true eventq_index=0 in_addr_map=true max_accesses_per_row=16 @@ -1462,19 +1533,26 @@ read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCCD_L=0 tCK=1250 tCL=13750 +tCS=2500 tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=260000 tRP=13750 tRRD=6000 +tRRD_L=0 tRTP=7500 tRTW=2500 tWR=15000 tWTR=7500 tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 write_buffer_size=64 write_high_thresh_perc=85 write_low_thresh_perc=50 @@ -1482,12 +1560,12 @@ port=system.membus.master[6] [system.realview] type=RealView -children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +children=a9scu aaci_fake cf_ctrl clcd dmac_fake energy_ctrl flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake eventq_index=0 intrctrl=system.intrctrl -max_mem_size=268435456 -mem_start_addr=0 pci_cfg_base=0 +pci_cfg_gen_offsets=false +pci_io_base=0 system=system [system.realview.a9scu] @@ -1542,6 +1620,7 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +LegacyIOBase=0 MSICAPBaseOffset=0 MSICAPCapId=0 MSICAPMaskBits=0 @@ -1626,6 +1705,16 @@ pio_latency=100000 system=system pio=system.iobus.master[9] +[system.realview.energy_ctrl] +type=EnergyCtrl +clk_domain=system.clk_domain +dvfs_handler=system.dvfs_handler +eventq_index=0 +pio_addr=268496896 +pio_latency=100000 +system=system +pio=system.iobus.master[25] + [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain @@ -1944,15 +2033,16 @@ output=true port=3456 [system.toL2Bus] -type=CoherentBus +type=CoherentXBar clk_domain=system.cpu_clk_domain eventq_index=0 header_cycles=1 +snoop_filter=Null system=system use_default_range=false width=8 master=system.l2c.cpu_side -slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.istage2_mmu.stage2_tlb.walker.port system.cpu0.dstage2_mmu.stage2_tlb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.istage2_mmu.stage2_tlb.walker.port system.cpu1.dstage2_mmu.stage2_tlb.walker.port +slave=system.cpu0.l2cache.mem_side system.cpu1.l2cache.mem_side [system.vncserver] type=VncServer |