diff options
| author | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
|---|---|---|
| committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2015-12-05 00:11:25 +0000 |
| commit | bbcbe028fe904ec3f48b39e02c4a8fbc6f438699 (patch) | |
| tree | 2e3c780f3c56f844d4fb36b438c3691af198a02b /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 78275c9d2f918d245902c3c00a9486b4af8e8099 (diff) | |
| download | gem5-bbcbe028fe904ec3f48b39e02c4a8fbc6f438699.tar.xz | |
stats: Update to reflect changes to PCI handling
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
3 files changed, 2903 insertions, 2940 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 3ec6d9660..b9459834e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -43,7 +43,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/work/gem5/outgoing/gem5_2/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -1423,10 +1423,9 @@ eventq_index=0 forward_latency=1 frontend_latency=2 response_latency=2 -use_default_range=true +use_default_range=false width=16 -default=system.realview.pciconfig.pio -master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ide.config system.realview.ethernet.pio system.realview.ethernet.config system.iocache.cpu_side +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.pci_host.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.hdlcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.rtc.pio system.realview.vram.port system.realview.l2x0_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.aaci_fake.pio system.realview.lan_fake.pio system.realview.usb_fake.pio system.realview.mmc_fake.pio system.realview.energy_ctrl.pio system.realview.ide.pio system.realview.ethernet.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] @@ -1453,7 +1452,7 @@ tags=system.iocache.tags tgts_per_mshr=12 write_buffers=8 writeback_clean=false -cpu_side=system.iobus.master[27] +cpu_side=system.iobus.master[25] mem_side=system.membus.slave[3] [system.iocache.tags] @@ -1617,12 +1616,9 @@ port=system.membus.master[5] [system.realview] type=RealView -children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pciconfig realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake +children=aaci_fake cf_ctrl clcd dcc energy_ctrl ethernet generic_timer gic hdlcd ide kmi0 kmi1 l2x0_fake lan_fake local_cpu_timer mcc mmc_fake nvmem pci_host realview_io rtc sp810_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake usb_fake vgic vram watchdog_fake eventq_index=0 intrctrl=system.intrctrl -pci_cfg_base=805306368 -pci_cfg_gen_offsets=false -pci_io_base=0 system=system [system.realview.aaci_fake] @@ -1715,16 +1711,15 @@ config_latency=20000 ctrl_offset=2 disks= eventq_index=0 +host=system.realview.pci_host io_shift=2 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[9] dma=system.iobus.slave[2] -pio=system.iobus.master[8] +pio=system.iobus.master[9] [system.realview.clcd] type=Pl111 @@ -1740,7 +1735,7 @@ pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] -pio=system.iobus.master[4] +pio=system.iobus.master[5] [system.realview.dcc] type=SubSystem @@ -1903,13 +1898,13 @@ eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 +host=system.realview.pci_host pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 -platform=system.realview rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1919,9 +1914,8 @@ tx_fifo_size=393216 tx_read_delay=0 wb_comp_delay=10000 wb_delay=10000 -config=system.iobus.master[26] dma=system.iobus.slave[4] -pio=system.iobus.master[25] +pio=system.iobus.master[24] [system.realview.generic_timer] type=GenericTimer @@ -1963,7 +1957,7 @@ vnc=system.vncserver workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] -pio=system.iobus.master[5] +pio=system.iobus.master[6] [system.realview.ide] type=IdeController @@ -2044,14 +2038,13 @@ config_latency=20000 ctrl_offset=0 disks=system.cf0 eventq_index=0 +host=system.realview.pci_host io_shift=0 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 -platform=system.realview system=system -config=system.iobus.master[24] dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2068,7 +2061,7 @@ pio_addr=470155264 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[6] +pio=system.iobus.master[7] [system.realview.kmi1] type=Pl050 @@ -2083,7 +2076,7 @@ pio_addr=470220800 pio_latency=100000 system=system vnc=system.vncserver -pio=system.iobus.master[7] +pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake @@ -2206,17 +2199,19 @@ null=false range=0:67108863 port=system.membus.master[1] -[system.realview.pciconfig] -type=PciConfigAll -bus=0 +[system.realview.pci_host] +type=GenericPciHost clk_domain=system.clk_domain +conf_base=805306368 +conf_device_bits=16 +conf_size=268435456 eventq_index=0 -pio_addr=0 -pio_latency=30000 +pci_dma_base=0 +pci_mem_base=0 +pci_pio_base=0 platform=system.realview -size=268435456 system=system -pio=system.iobus.default +pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl @@ -2268,7 +2263,7 @@ int_num1=34 pio_addr=470876160 pio_latency=100000 system=system -pio=system.iobus.master[2] +pio=system.iobus.master[3] [system.realview.timer1] type=Sp804 @@ -2283,7 +2278,7 @@ int_num1=35 pio_addr=470941696 pio_latency=100000 system=system -pio=system.iobus.master[3] +pio=system.iobus.master[4] [system.realview.uart] type=Pl011 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index b77f15d87..c56e46cb6 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,10 +1,10 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 3 2015 15:48:05 -gem5 started Dec 3 2015 18:09:43 -gem5 executing on e104799-lin, pid 6272 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Dec 4 2015 11:13:17 +gem5 started Dec 4 2015 11:33:05 +gem5 executing on e104799-lin, pid 30938 +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/gem5/outgoing/gem5_2/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 @@ -27,4 +27,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2837504217500 because m5_exit instruction encountered +Exiting @ tick 2827514981500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index bfde5ebda..9f7a5e2b6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.837504 # Number of seconds simulated -sim_ticks 2837504217500 # Number of ticks simulated -final_tick 2837504217500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.827515 # Number of seconds simulated +sim_ticks 2827514981500 # Number of ticks simulated +final_tick 2827514981500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94020 # Simulator instruction rate (inst/s) -host_op_rate 114023 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2216148296 # Simulator tick rate (ticks/s) -host_mem_usage 620044 # Number of bytes of host memory used -host_seconds 1280.38 # Real time elapsed on the host -sim_insts 120381204 # Number of instructions simulated -sim_ops 145991739 # Number of ops (including micro ops) simulated +host_inst_rate 101964 # Simulator instruction rate (inst/s) +host_op_rate 123693 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2400293976 # Simulator tick rate (ticks/s) +host_mem_usage 620072 # Number of bytes of host memory used +host_seconds 1177.99 # Real time elapsed on the host +sim_insts 120112531 # Number of instructions simulated +sim_ops 145708890 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1298560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1282472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8427712 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1298880 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1333736 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8603840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 172400 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 575316 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 374464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 183536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 661460 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 448448 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12134316 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1298560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 172400 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1470960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8568768 # Number of bytes written to this memory +system.physmem.bytes_read::total 12533612 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1298880 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 183536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1482416 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8896000 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8586332 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 28 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8913564 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22537 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 20559 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 131683 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22542 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21360 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 134435 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2762 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 9010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 5851 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2936 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10356 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 7007 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 192455 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 133887 # Number of write requests responded to by this memory +system.physmem.num_reads::total 198694 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 139000 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 138278 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 632 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 143391 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 724 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 457642 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 451972 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 2970114 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 135 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 459372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 471699 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3042898 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 158 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 60758 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 202754 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 131969 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::realview.ide 338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4276405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 457642 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 60758 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 518399 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3019826 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6176 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 233937 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 158601 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4432731 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 459372 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64911 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 524282 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3146226 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6198 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3026016 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3019826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 632 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3152437 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3146226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 724 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 457642 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 458148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 2970114 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 135 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 459372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 477897 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3042898 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 158 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 60758 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 202768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 131969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.ide 338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7302420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 192456 # Number of read requests accepted -system.physmem.writeReqs 138278 # Number of write requests accepted -system.physmem.readBursts 192456 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 138278 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12307136 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9984 # Total number of bytes read from write queue -system.physmem.bytesWritten 8599232 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12134380 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8586332 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 156 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::cpu1.inst 64911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 233951 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 158601 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 7585168 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 198695 # Number of read requests accepted +system.physmem.writeReqs 143391 # Number of write requests accepted +system.physmem.readBursts 198695 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 143391 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12706944 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9536 # Total number of bytes read from write queue +system.physmem.bytesWritten 8926464 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12533676 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8913564 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 149 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 65662 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 11960 # Per bank write bursts -system.physmem.perBankRdBursts::1 11050 # Per bank write bursts -system.physmem.perBankRdBursts::2 12052 # Per bank write bursts -system.physmem.perBankRdBursts::3 12058 # Per bank write bursts -system.physmem.perBankRdBursts::4 14137 # Per bank write bursts -system.physmem.perBankRdBursts::5 12072 # Per bank write bursts -system.physmem.perBankRdBursts::6 12490 # Per bank write bursts -system.physmem.perBankRdBursts::7 12293 # Per bank write bursts -system.physmem.perBankRdBursts::8 12129 # Per bank write bursts -system.physmem.perBankRdBursts::9 11971 # Per bank write bursts -system.physmem.perBankRdBursts::10 11835 # Per bank write bursts -system.physmem.perBankRdBursts::11 10924 # Per bank write bursts -system.physmem.perBankRdBursts::12 11792 # Per bank write bursts -system.physmem.perBankRdBursts::13 12532 # Per bank write bursts -system.physmem.perBankRdBursts::14 11740 # Per bank write bursts -system.physmem.perBankRdBursts::15 11264 # Per bank write bursts -system.physmem.perBankWrBursts::0 8435 # Per bank write bursts -system.physmem.perBankWrBursts::1 7998 # Per bank write bursts -system.physmem.perBankWrBursts::2 8830 # Per bank write bursts -system.physmem.perBankWrBursts::3 8684 # Per bank write bursts -system.physmem.perBankWrBursts::4 8112 # Per bank write bursts -system.physmem.perBankWrBursts::5 8575 # Per bank write bursts -system.physmem.perBankWrBursts::6 8926 # Per bank write bursts -system.physmem.perBankWrBursts::7 8709 # Per bank write bursts -system.physmem.perBankWrBursts::8 8491 # Per bank write bursts -system.physmem.perBankWrBursts::9 8366 # Per bank write bursts -system.physmem.perBankWrBursts::10 8474 # Per bank write bursts -system.physmem.perBankWrBursts::11 8070 # Per bank write bursts -system.physmem.perBankWrBursts::12 8488 # Per bank write bursts -system.physmem.perBankWrBursts::13 8576 # Per bank write bursts -system.physmem.perBankWrBursts::14 8125 # Per bank write bursts -system.physmem.perBankWrBursts::15 7504 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 66310 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12511 # Per bank write bursts +system.physmem.perBankRdBursts::1 12409 # Per bank write bursts +system.physmem.perBankRdBursts::2 13005 # Per bank write bursts +system.physmem.perBankRdBursts::3 12914 # Per bank write bursts +system.physmem.perBankRdBursts::4 14688 # Per bank write bursts +system.physmem.perBankRdBursts::5 12279 # Per bank write bursts +system.physmem.perBankRdBursts::6 12659 # Per bank write bursts +system.physmem.perBankRdBursts::7 12545 # Per bank write bursts +system.physmem.perBankRdBursts::8 12216 # Per bank write bursts +system.physmem.perBankRdBursts::9 11968 # Per bank write bursts +system.physmem.perBankRdBursts::10 11724 # Per bank write bursts +system.physmem.perBankRdBursts::11 10899 # Per bank write bursts +system.physmem.perBankRdBursts::12 12000 # Per bank write bursts +system.physmem.perBankRdBursts::13 12901 # Per bank write bursts +system.physmem.perBankRdBursts::14 12154 # Per bank write bursts +system.physmem.perBankRdBursts::15 11674 # Per bank write bursts +system.physmem.perBankWrBursts::0 9120 # Per bank write bursts +system.physmem.perBankWrBursts::1 9128 # Per bank write bursts +system.physmem.perBankWrBursts::2 9608 # Per bank write bursts +system.physmem.perBankWrBursts::3 9301 # Per bank write bursts +system.physmem.perBankWrBursts::4 8579 # Per bank write bursts +system.physmem.perBankWrBursts::5 8797 # Per bank write bursts +system.physmem.perBankWrBursts::6 8898 # Per bank write bursts +system.physmem.perBankWrBursts::7 8634 # Per bank write bursts +system.physmem.perBankWrBursts::8 8555 # Per bank write bursts +system.physmem.perBankWrBursts::9 8430 # Per bank write bursts +system.physmem.perBankWrBursts::10 8386 # Per bank write bursts +system.physmem.perBankWrBursts::11 7930 # Per bank write bursts +system.physmem.perBankWrBursts::12 8700 # Per bank write bursts +system.physmem.perBankWrBursts::13 8975 # Per bank write bursts +system.physmem.perBankWrBursts::14 8498 # Per bank write bursts +system.physmem.perBankWrBursts::15 7937 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 5 # Number of times write queue was full causing retry -system.physmem.totGap 2837503950500 # Total gap between requests +system.physmem.numWrRetry 1 # Number of times write queue was full causing retry +system.physmem.totGap 2827514698000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) system.physmem.readPktSize::4 3087 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 188790 # Read request sizes (log2) +system.physmem.readPktSize::6 195029 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 133887 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 61458 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 73949 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 12857 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9980 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8183 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5080 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4433 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 792 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 552 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 233 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 214 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10 # What read 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does an incoming req see +system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,159 +188,160 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2740 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3212 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4058 # What write queue length does an incoming req see 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queue length does an incoming req see -system.physmem.wrQLenPdf::30 8864 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 7907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7439 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 624 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 403 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 219 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 188 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 116 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 135 # What write queue length does an incoming req see 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queue length does an incoming req see +system.physmem.wrQLenPdf::53 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 56 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 49 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 43 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 20 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 16 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 11 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86935 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 240.482751 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 135.610645 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 303.163398 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 46710 53.73% 53.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16982 19.53% 73.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5795 6.67% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3191 3.67% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2666 3.07% 86.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1598 1.84% 88.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 941 1.08% 89.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 911 1.05% 90.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8141 9.36% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86935 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6558 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 29.322812 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 574.114177 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6556 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6558 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6558 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.488411 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.922621 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.969935 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5288 80.63% 80.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 495 7.55% 88.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 103 1.57% 89.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 154 2.35% 92.10% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 30 0.46% 92.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 130 1.98% 94.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 43 0.66% 95.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 19 0.29% 95.49% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 29 0.44% 95.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 20 0.30% 96.23% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 10 0.15% 96.39% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 12 0.18% 96.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 145 2.21% 98.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 7 0.11% 98.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 5 0.08% 98.96% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 33 0.50% 99.47% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 10 0.15% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 3 0.05% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.02% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.71% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 1 0.02% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 2 0.03% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.02% 99.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.02% 99.79% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 10 0.15% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::136-139 1 0.02% 99.95% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.02% 99.97% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.02% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6558 # Writes before turning the bus around for reads -system.physmem.totQLat 6213827144 # Total ticks spent queuing -system.physmem.totMemAccLat 9819433394 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 961495000 # Total ticks spent in databus transfers -system.physmem.avgQLat 32313.19 # Average queueing delay per DRAM burst -system.physmem.avgBusLat 4999.97 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 51063.10 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.34 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.03 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.28 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 3.03 # Average system write bandwidth in MiByte/s +system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 91952 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 235.267792 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 133.235046 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 298.839280 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50134 54.52% 54.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17916 19.48% 74.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5936 6.46% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3412 3.71% 84.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2785 3.03% 87.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1606 1.75% 88.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 997 1.08% 90.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 910 0.99% 91.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8256 8.98% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 91952 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6854 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.967610 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 561.585770 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6852 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 6854 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6854 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.349577 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.863128 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.733584 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5532 80.71% 80.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 528 7.70% 88.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 124 1.81% 90.22% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 151 2.20% 92.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 37 0.54% 92.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 137 2.00% 94.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 51 0.74% 95.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 13 0.19% 95.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 30 0.44% 96.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 17 0.25% 96.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.07% 96.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 10 0.15% 96.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 152 2.22% 99.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 5 0.07% 99.10% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 2 0.03% 99.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 27 0.39% 99.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 3 0.04% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::116-119 1 0.01% 99.74% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 13 0.19% 99.94% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::136-139 1 0.01% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::140-143 1 0.01% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6854 # Writes before turning the bus around for reads +system.physmem.totQLat 6593126991 # Total ticks spent queuing +system.physmem.totMemAccLat 10315864491 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 992730000 # Total ticks spent in databus transfers +system.physmem.avgQLat 33207.05 # Average queueing delay per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 51957.05 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.49 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.16 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.43 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.15 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.06 # Data bus utilization in percentage -system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads +system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.17 # Average write queue length when enqueuing -system.physmem.readRowHits 160530 # Number of row buffer hits during reads -system.physmem.writeRowHits 79197 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.48 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 58.93 # Row buffer hit rate for writes -system.physmem.avgGap 8579414.12 # Average gap between requests -system.physmem.pageHitRate 73.38 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 333396000 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 181912500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 765273600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 442383120 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 80482301685 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1631904131250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1899441376155 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.405614 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2714718220190 # Time in different power states -system.physmem_0.memoryStateTime::REF 94750240000 # Time in different power states +system.physmem.avgWrQLen 28.41 # Average write queue length when enqueuing +system.physmem.readRowHits 165438 # Number of row buffer hits during reads +system.physmem.writeRowHits 80631 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.32 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.80 # Row buffer hit rate for writes +system.physmem.avgGap 8265508.38 # Average gap between requests +system.physmem.pageHitRate 72.79 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 362418840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197748375 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 803470200 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466981200 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 80961093990 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625490282750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1892961490875 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.478934 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704041495487 # Time in different power states +system.physmem_0.memoryStateTime::REF 94416920000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 28035696060 # Time in different power states +system.physmem_0.memoryStateTime::ACT 29056546513 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 323832600 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 176694375 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 734658600 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 428289120 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 185331978000 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 80147926575 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1632197442750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1899340822020 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.370176 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2715209176165 # Time in different power states -system.physmem_1.memoryStateTime::REF 94750240000 # Time in different power states +system.physmem_1.actEnergy 332738280 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 181553625 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 745180800 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 436823280 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184679495520 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 80279403345 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1626088257000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1892743451850 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.401821 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2705042490853 # Time in different power states +system.physmem_1.memoryStateTime::REF 94416920000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 27544740085 # Time in different power states +system.physmem_1.memoryStateTime::ACT 28055246647 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -366,15 +367,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53984881 # Number of BP lookups -system.cpu0.branchPred.condPredicted 25029279 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 1031275 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32703051 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 24288553 # Number of BTB hits +system.cpu0.branchPred.lookups 53824650 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24914718 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 1030270 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32581460 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 24224214 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 74.269991 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15579180 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33867 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.349688 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15556762 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33886 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -405,90 +406,81 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 71885 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 71885 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26706 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21113 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 24066 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 47819 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 500.773751 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3132.734175 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 46517 97.28% 97.28% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 936 1.96% 99.23% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 174 0.36% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 150 0.31% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 13 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.04% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walks 72482 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 72482 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 26840 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 21370 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 24272 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 48210 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 483.737814 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 3068.363590 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 46935 97.36% 97.36% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 960 1.99% 99.35% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 127 0.26% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 144 0.30% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 24 0.05% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 3 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 99.99% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::106496-114687 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::114688-122879 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 47819 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 18759 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11059.171598 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9588.566879 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7711.880133 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-32767 18631 99.32% 99.32% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-65535 106 0.57% 99.88% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-131071 16 0.09% 99.97% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-163839 4 0.02% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::360448-393215 1 0.01% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::393216-425983 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 18759 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 84429292764 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.657402 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.487897 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 29095217424 34.46% 34.46% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 55270258340 65.46% 99.92% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2 29607500 0.04% 99.96% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::3 15656000 0.02% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4 4826500 0.01% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::5 2762000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6 4173000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::7 1494500 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8 1031000 0.00% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::9 697500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10 703000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::11 393500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12 1099500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::13 296000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14 143000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::15 934000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 84429292764 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5818 79.12% 79.12% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1535 20.88% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 7353 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 71885 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 48210 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 19223 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 10866.878219 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9427.660612 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 7974.318697 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-32767 19122 99.47% 99.47% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-65535 77 0.40% 99.88% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-163839 23 0.12% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::425984-458751 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 19223 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 87324939152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.584645 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.504578 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 87261759152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 45052000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7883000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 5458000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1586500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 936000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1172500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1091000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 1000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 87324939152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5998 77.94% 77.94% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1698 22.06% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 7696 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 72482 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 71885 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7353 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 72482 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 7696 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7353 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 79238 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 7696 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 80178 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 24461690 # DTB read hits -system.cpu0.dtb.read_misses 61076 # DTB read misses -system.cpu0.dtb.write_hits 18142518 # DTB write hits -system.cpu0.dtb.write_misses 10809 # DTB write misses +system.cpu0.dtb.read_hits 24348850 # DTB read hits +system.cpu0.dtb.read_misses 61646 # DTB read misses +system.cpu0.dtb.write_hits 18136813 # DTB write hits +system.cpu0.dtb.write_misses 10836 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3811 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 171 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2460 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3858 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 293 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2461 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 1016 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 24522766 # DTB read accesses -system.cpu0.dtb.write_accesses 18153327 # DTB write accesses +system.cpu0.dtb.perms_faults 958 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 24410496 # DTB read accesses +system.cpu0.dtb.write_accesses 18147649 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 42604208 # DTB hits -system.cpu0.dtb.misses 71885 # DTB misses -system.cpu0.dtb.accesses 42676093 # DTB accesses +system.cpu0.dtb.hits 42485663 # DTB hits +system.cpu0.dtb.misses 72482 # DTB misses +system.cpu0.dtb.accesses 42558145 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -518,56 +510,56 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 10900 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10900 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4234 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6533 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 133 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 10767 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 543.187517 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2520.119999 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 10263 95.32% 95.32% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 147 1.37% 96.68% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 248 2.30% 98.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 60 0.56% 99.54% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.12% 99.67% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.17% 99.83% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 11 0.10% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 10767 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3015 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 13136.152570 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 12059.608238 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 6103.776811 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-16383 2740 90.88% 90.88% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-32767 236 7.83% 98.71% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-49151 36 1.19% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::49152-65535 2 0.07% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walks 11063 # Table walker walks requested +system.cpu0.itb.walker.walksShort 11063 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4358 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6586 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 119 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10944 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 511.878655 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2393.914880 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 10440 95.39% 95.39% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 166 1.52% 96.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 245 2.24% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 55 0.50% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 14 0.13% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 14 0.13% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 2 0.02% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 1 0.01% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10944 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3006 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 12466.400532 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11507.410615 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 5482.679017 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-16383 2781 92.51% 92.51% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-32767 206 6.85% 99.37% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-49151 17 0.57% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-65535 1 0.03% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::131072-147455 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3015 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 20004739824 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.958205 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.200359 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 836985000 4.18% 4.18% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 19166939824 95.81% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 745000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 20004739824 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2539 88.10% 88.10% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 343 11.90% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 2882 # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3006 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 18373803416 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.969102 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.173359 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 568612000 3.09% 3.09% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 17804392916 96.90% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 690500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 108000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 18373803416 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2539 87.95% 87.95% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 348 12.05% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 2887 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10900 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10900 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 11063 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 11063 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2882 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2882 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13782 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 74221386 # ITB inst hits -system.cpu0.itb.inst_misses 10900 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2887 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2887 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 13950 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 74042794 # ITB inst hits +system.cpu0.itb.inst_misses 11063 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -576,109 +568,109 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2623 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2625 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 2177 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 2170 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 74232286 # ITB inst accesses -system.cpu0.itb.hits 74221386 # DTB hits -system.cpu0.itb.misses 10900 # DTB misses -system.cpu0.itb.accesses 74232286 # DTB accesses -system.cpu0.numCycles 211089412 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 74053857 # ITB inst accesses +system.cpu0.itb.hits 74042794 # DTB hits +system.cpu0.itb.misses 11063 # DTB misses +system.cpu0.itb.accesses 74053857 # DTB accesses +system.cpu0.numCycles 211047403 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 21154368 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 200477778 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53984881 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39867733 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 180634648 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5887980 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 163875 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 73228 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 386540 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 467083 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 106682 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 74221667 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 284223 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5134 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 205930414 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.189818 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.306225 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 21173136 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 200001666 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53824650 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39780976 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 180559136 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5880452 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 163694 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 71518 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 416219 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 467581 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 105314 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 74043107 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 284080 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5158 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 205896824 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.187509 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.306152 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 98513446 47.84% 47.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 31147875 15.13% 62.96% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14935472 7.25% 70.22% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 61333621 29.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 98736671 47.95% 47.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 31028549 15.07% 63.02% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14918972 7.25% 70.27% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 61212632 29.73% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 205930414 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.255744 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.949729 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 26441792 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 111116512 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 60639193 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 5147176 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2585741 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3185045 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 362773 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 158832709 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 4189276 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2585741 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 35360438 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 13326930 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 85149071 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 56726750 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 12781484 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 141877128 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1133387 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1508513 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 170712 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 63171 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 8443572 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 146064106 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 654194105 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 157626069 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 10971 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 133804111 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 12259992 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2731692 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2584898 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22953113 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 25474104 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19753680 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1758400 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2611655 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 138738893 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1764680 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 136614694 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 514032 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 11572613 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 23827744 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 127449 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 205930414 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.663402 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.962674 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 205896824 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.255036 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.947662 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 26444854 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 111284081 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 60438396 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 5147375 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2582118 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3181251 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 362597 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 158450982 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 4186687 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2582118 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 35356822 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 13355442 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 85192856 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 56532551 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 12877035 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 141523079 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1131567 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1510730 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 170563 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 62525 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 8538727 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 145648252 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 652695637 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 157341344 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 11002 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 133402169 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 12246080 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2729481 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2582524 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22941481 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 25362929 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19747073 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1756360 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2710793 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 138386443 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1765013 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 136262498 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 514521 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 11554986 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 23816746 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 127231 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 205896824 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.661800 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.962021 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 127115623 61.73% 61.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 34474239 16.74% 78.47% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 32051807 15.56% 94.03% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 11118185 5.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1170514 0.57% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 46 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 127277158 61.82% 61.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 34398562 16.71% 78.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31970025 15.53% 94.05% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 11080468 5.38% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1170573 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 38 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 205930414 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 205896824 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 11113465 43.69% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 76 0.00% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 11103787 43.69% 43.69% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 71 0.00% 43.69% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.69% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.69% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.69% # attempts to use FU when none available @@ -706,129 +698,129 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.69% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.69% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.69% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.69% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5930869 23.32% 67.01% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8390890 32.99% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5926512 23.32% 67.02% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8382229 32.98% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2315 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 92049537 67.38% 67.38% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 112728 0.08% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 1 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.46% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8149 0.01% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 91815128 67.38% 67.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 112435 0.08% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.47% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8235 0.01% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.47% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.47% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 25196866 18.44% 85.91% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 19245098 14.09% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 25085333 18.41% 85.88% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 19239052 14.12% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 136614694 # Type of FU issued -system.cpu0.iq.rate 0.647189 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 25435300 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.186183 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 505071342 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 152083684 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 132900099 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 37792 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 13226 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 11443 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 162023237 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 24442 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 380983 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 136262498 # Type of FU issued +system.cpu0.iq.rate 0.645649 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 25412599 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.186497 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 504310819 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 151713950 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 132552939 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 38121 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 13270 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 11439 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 161648054 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 24728 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 380758 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2125903 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2726 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 20804 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 1085884 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2120893 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2730 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 20852 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1081680 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 121982 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 393712 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 121274 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 393141 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2585741 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1952892 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 228879 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 140712950 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2582118 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1967503 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 225282 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 140361265 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 25474104 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19753680 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 902814 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28763 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 175994 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 20804 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 314282 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 420638 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 734920 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 135458636 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 24717807 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1084310 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 25362929 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19747073 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 903285 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28583 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 172530 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 20852 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 314243 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 420118 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 734361 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 135106830 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 24606381 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1083325 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 209377 # number of nop insts executed -system.cpu0.iew.exec_refs 43763584 # number of memory reference insts executed -system.cpu0.iew.exec_branches 26159060 # Number of branches executed -system.cpu0.iew.exec_stores 19045777 # Number of stores executed -system.cpu0.iew.exec_rate 0.641712 # Inst execution rate -system.cpu0.iew.wb_sent 134853240 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 132911542 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 67798610 # num instructions producing a value -system.cpu0.iew.wb_consumers 109653581 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.629646 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618298 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 10465758 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1637231 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 673026 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 202620964 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.637065 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.337510 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 209809 # number of nop insts executed +system.cpu0.iew.exec_refs 43646202 # number of memory reference insts executed +system.cpu0.iew.exec_branches 26044471 # Number of branches executed +system.cpu0.iew.exec_stores 19039821 # Number of stores executed +system.cpu0.iew.exec_rate 0.640173 # Inst execution rate +system.cpu0.iew.wb_sent 134503420 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 132564378 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 67577240 # num instructions producing a value +system.cpu0.iew.wb_consumers 109379746 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.628126 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.617822 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 10448394 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1637782 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 672162 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 202592939 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.635502 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.338703 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 140811364 69.49% 69.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 34122035 16.84% 86.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12973971 6.40% 92.74% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3422170 1.69% 94.43% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4965504 2.45% 96.88% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2761485 1.36% 98.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1431161 0.71% 98.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 576287 0.28% 99.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1556987 0.77% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 141057849 69.63% 69.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33954375 16.76% 86.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12905235 6.37% 92.76% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3389250 1.67% 94.43% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4963565 2.45% 96.88% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2666475 1.32% 98.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1522321 0.75% 98.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 575799 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1558070 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 202620964 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 106609467 # Number of instructions committed -system.cpu0.commit.committedOps 129082799 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 202592939 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 106280740 # Number of instructions committed +system.cpu0.commit.committedOps 128748309 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 42015997 # Number of memory references committed -system.cpu0.commit.loads 23348201 # Number of loads committed -system.cpu0.commit.membars 664671 # Number of memory barriers committed -system.cpu0.commit.branches 25482813 # Number of branches committed +system.cpu0.commit.refs 41907429 # Number of memory references committed +system.cpu0.commit.loads 23242036 # Number of loads committed +system.cpu0.commit.membars 664627 # Number of memory barriers committed +system.cpu0.commit.branches 25370057 # Number of branches committed system.cpu0.commit.fp_insts 11428 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 112616062 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4882659 # Number of function calls committed. +system.cpu0.commit.int_insts 112383608 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4877012 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 86948458 67.36% 67.36% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 110195 0.09% 67.44% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 86722676 67.36% 67.36% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 109969 0.09% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.44% # Class of committed instruction @@ -852,635 +844,635 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.44% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.44% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.44% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8149 0.01% 67.45% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8235 0.01% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.45% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.45% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 23348201 18.09% 85.54% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18667796 14.46% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 23242036 18.05% 85.50% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18665393 14.50% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 129082799 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1556987 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 317266716 # The number of ROB reads -system.cpu0.rob.rob_writes 282405799 # The number of ROB writes -system.cpu0.timesIdled 139400 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 5158998 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5463919353 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 106457624 # Number of Instructions Simulated -system.cpu0.committedOps 128930956 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.982849 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.982849 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.504325 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.504325 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 146869793 # number of integer regfile reads -system.cpu0.int_regfile_writes 83863812 # number of integer regfile writes -system.cpu0.fp_regfile_reads 9544 # number of floating regfile reads -system.cpu0.fp_regfile_writes 2721 # number of floating regfile writes -system.cpu0.cc_regfile_reads 478325864 # number of cc regfile reads -system.cpu0.cc_regfile_writes 51342401 # number of cc regfile writes -system.cpu0.misc_regfile_reads 283146795 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1260752 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 750420 # number of replacements -system.cpu0.dcache.tags.tagsinuse 496.151485 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 38802198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 750932 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 51.672053 # Average number of references to valid blocks. +system.cpu0.commit.op_class_0::total 128748309 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1558070 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 316922543 # The number of ROB reads +system.cpu0.rob.rob_writes 281696540 # The number of ROB writes +system.cpu0.timesIdled 138499 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 5150579 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5443982755 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 106128897 # Number of Instructions Simulated +system.cpu0.committedOps 128596466 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.988595 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.988595 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.502868 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.502868 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 146588252 # number of integer regfile reads +system.cpu0.int_regfile_writes 83723999 # number of integer regfile writes +system.cpu0.fp_regfile_reads 9570 # number of floating regfile reads +system.cpu0.fp_regfile_writes 2716 # number of floating regfile writes +system.cpu0.cc_regfile_reads 476941595 # number of cc regfile reads +system.cpu0.cc_regfile_writes 51071402 # number of cc regfile writes +system.cpu0.misc_regfile_reads 282603834 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1261450 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 749987 # number of replacements +system.cpu0.dcache.tags.tagsinuse 496.992457 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 38690178 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 750499 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 51.552604 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 426635500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.151485 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.969046 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.969046 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 496.992457 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970688 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.970688 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 186 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 15 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 178 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 318 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 83743288 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 83743288 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 22166108 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 22166108 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 15386838 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 15386838 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316240 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 316240 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371193 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 371193 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 369806 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 369806 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 37552946 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 37552946 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 37869186 # number of overall hits -system.cpu0.dcache.overall_hits::total 37869186 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 688329 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 688329 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1970797 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1970797 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153398 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 153398 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 26102 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 26102 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20247 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20247 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2659126 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2659126 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2812524 # number of overall misses -system.cpu0.dcache.overall_misses::total 2812524 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 9979901000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 9979901000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 36499508368 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 36499508368 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 419269000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 419269000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 539016500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 539016500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 316500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 316500 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 46479409368 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 46479409368 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 46479409368 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 46479409368 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22854437 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22854437 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 17357635 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 17357635 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 469638 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 469638 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397295 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 397295 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390053 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 390053 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 40212072 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 40212072 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 40681710 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 40681710 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030118 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.030118 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113541 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.113541 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.326630 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.326630 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.065699 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.065699 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051908 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051908 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.066128 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.066128 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.069135 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.069135 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14498.736796 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14498.736796 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18520.176542 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 18520.176542 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16062.715501 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16062.715501 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26622.042772 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26622.042772 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 83515372 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 83515372 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 22054482 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 22054482 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 15385393 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 15385393 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 316703 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 316703 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 371938 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 371938 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 370232 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 370232 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 37439875 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 37439875 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 37756578 # number of overall hits +system.cpu0.dcache.overall_hits::total 37756578 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 687176 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 687176 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1969830 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1969830 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 153892 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 153892 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25692 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25692 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20263 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20263 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2657006 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2657006 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2810898 # number of overall misses +system.cpu0.dcache.overall_misses::total 2810898 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 10005125000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 10005125000 # number of ReadReq miss cycles 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demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 46958486360 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 46958486360 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22741658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22741658 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 17355223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 17355223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 470595 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 470595 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 397630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 397630 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 390495 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 390495 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 40096881 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 40096881 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 40567476 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 40567476 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.030217 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.030217 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.113501 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.113501 # miss rate for WriteReq accesses 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14559.770714 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14559.770714 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 18759.670307 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 18759.670307 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 16131.305465 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 16131.305465 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 26334.328579 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 26334.328579 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17479.205336 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 17479.205336 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16525.871199 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 16525.871199 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1220 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5610117 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 53 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 211671 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 23.018868 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 26.503947 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 17673.458908 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 17673.458908 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 16705.866367 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 16705.866367 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 1927 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5691402 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 46 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 211704 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 41.891304 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 26.883772 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 750420 # number of writebacks -system.cpu0.dcache.writebacks::total 750420 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 277928 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 277928 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1634691 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1634691 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 19352 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 19352 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1912619 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1912619 # number of demand (read+write) MSHR hits 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misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20247 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 746507 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 746507 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 853826 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 853826 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31838 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31838 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28498 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28498 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60336 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60336 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5125711500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5125711500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 7684887402 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 7684887402 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1795459000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1795459000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 109420000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 109420000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 518776500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 518776500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 309500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 309500 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 12810598902 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12810598902 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 14606057902 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 14606057902 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6629004500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6629004500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5396257500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5396257500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12025262000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12025262000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017957 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017957 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019364 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019364 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.228514 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.228514 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016990 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016990 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051908 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051908 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018564 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018564 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020988 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020988 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12489.520006 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12489.520006 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 22864.475499 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 22864.475499 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16730.113028 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16730.113028 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16210.370370 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16210.370370 # average LoadLockedReq mshr miss latency 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MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1911401 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1911401 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1911401 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 409916 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 409916 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 335689 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 335689 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 107270 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 107270 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6647 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6647 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20263 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20263 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 745605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 745605 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 852875 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 852875 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31809 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31809 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28493 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28493 # number of WriteReq MSHR uncacheable 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cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6623643500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6623643500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 5395209000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 5395209000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 12018852500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 12018852500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.018025 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.018025 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019342 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.227945 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.227945 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016717 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016717 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051891 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051891 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018595 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018595 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.021024 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.021024 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.345495 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.345495 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 23172.914185 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 23172.914185 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16720.555607 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16720.555607 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 16272.829848 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 16272.829848 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 25334.920792 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 25334.920792 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17160.721737 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17160.721737 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17106.597717 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17106.597717 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208210.456059 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208210.456059 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 189355.656537 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189355.656537 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 199304.925749 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 199304.925749 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17338.924618 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17338.924618 # average overall mshr miss latency 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Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1310169 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.377289 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 72850689 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1310681 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 55.582319 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 1312325 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.728748 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 72670068 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1312837 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 55.353458 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 8207375500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.377289 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998784 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998784 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.728748 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999470 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999470 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 236 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 138 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 239 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 135 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 149746644 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 149746644 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 72850689 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 72850689 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 72850689 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 72850689 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 72850689 # number of overall hits -system.cpu0.icache.overall_hits::total 72850689 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1367277 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1367277 # number of ReadReq misses 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accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 74217966 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 74217966 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 74217966 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 74217966 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 74217966 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.018422 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.018422 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.018422 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.018422 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.018422 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.018422 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10928.944362 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10928.944362 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10928.944362 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10928.944362 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10928.944362 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2021185 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 149391678 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 149391678 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 72670068 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 72670068 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 72670068 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 72670068 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 72670068 # number of overall hits +system.cpu0.icache.overall_hits::total 72670068 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1369337 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1369337 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1369337 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1369337 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1369337 # number of overall misses +system.cpu0.icache.overall_misses::total 1369337 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14942606327 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14942606327 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14942606327 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14942606327 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14942606327 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14942606327 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 74039405 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 74039405 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 74039405 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 74039405 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 74039405 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 74039405 # number of overall (read+write) accesses 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overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 10912.292830 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2029991 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 1804 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 126207 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 126413 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 15 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.014841 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.058404 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 120.266667 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 1310169 # number of writebacks -system.cpu0.icache.writebacks::total 1310169 # number of writebacks -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56563 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 56563 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 56563 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 56563 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 56563 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 56563 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1310714 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1310714 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1310714 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1310714 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1310714 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1310714 # number of overall MSHR misses +system.cpu0.icache.writebacks::writebacks 1312325 # number of writebacks +system.cpu0.icache.writebacks::total 1312325 # number of writebacks +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 56467 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 56467 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 56467 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 56467 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 56467 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 56467 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1312870 # number of ReadReq MSHR misses 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-system.cpu0.icache.ReadReq_mshr_miss_latency::total 13414113616 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13414113616 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 13414113616 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13414113616 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 13414113616 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13422835685 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13422835685 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13422835685 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13422835685 # number of demand (read+write) MSHR miss cycles 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-system.cpu0.icache.demand_mshr_miss_rate::total 0.017660 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017660 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017660 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10234.203355 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 10234.203355 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10234.203355 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 10234.203355 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017732 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017732 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017732 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017732 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 10224.040221 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 10224.040221 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 10224.040221 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 140030.625166 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 140030.625166 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 140030.625166 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1920430 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1923198 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2526 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1922264 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1925121 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2600 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 245058 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 284507 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16100.171768 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3421600 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 300660 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.380297 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 245295 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 283525 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16106.133558 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3424599 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 299662 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.428206 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14677.549696 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.049066 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.660096 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1408.912909 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.895847 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000735 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000101 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085993 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982676 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1016 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15129 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 23 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 340 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 424 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 229 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 5 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_blocks::writebacks 14666.612197 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.987362 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.024801 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1424.509198 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.895179 # Average percentage of cache occupancy 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blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 2 # Occupied blocks per task id system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 129 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 499 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4650 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7772 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2079 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062012 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.923401 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 69513277 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 69513277 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 60951 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14637 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 75588 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 505486 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 505486 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1521984 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1521984 # number of WritebackClean hits +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 119 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 496 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4568 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7930 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2049 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.059143 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000366 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925415 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 69529329 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 69529329 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 59791 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 14320 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 74111 # number of ReadReq hits +system.cpu0.l2cache.WritebackDirty_hits::writebacks 505100 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackDirty_hits::total 505100 # number of WritebackDirty hits +system.cpu0.l2cache.WritebackClean_hits::writebacks 1523954 # number of WritebackClean hits +system.cpu0.l2cache.WritebackClean_hits::total 1523954 # number of WritebackClean hits system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 1 # number of UpgradeReq hits system.cpu0.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 205294 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 205294 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1255409 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1255409 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 426614 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 426614 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 60951 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 14637 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1255409 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 631908 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1962905 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 60951 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 14637 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1255409 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 631908 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1962905 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 405 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 157 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 562 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 55507 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 55507 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20246 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20246 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 75528 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 75528 # number of ReadExReq misses -system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 55277 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadCleanReq_misses::total 55277 # number of ReadCleanReq misses -system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 97728 # number of ReadSharedReq misses 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# mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.207675 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 24826.203209 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 82913.548852 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26305.339867 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26305.339867 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 18059.641361 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 18059.641361 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 254999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 254999 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 57253.797365 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 57253.797365 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 62622.175514 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28583.126123 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28583.126123 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 44458.479333 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 26845.297030 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19630.573248 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 62622.175514 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 37354.260919 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 82913.548852 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 66402.273009 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.206922 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28255.656109 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 84762.290433 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 26370.495617 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 26370.495617 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17777.528207 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 17777.528207 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 234249 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 234249 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 60278.082852 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 60278.082852 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 63253.262785 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 28938.767033 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 28938.767033 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 45374.487804 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 30676.991150 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 20286.407767 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 63253.262785 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 38364.193447 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 84762.290433 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 67994.717128 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200200.625039 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194366.224671 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181741.366482 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181741.366482 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200221.509636 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 194380.446959 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 181738.232619 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 181738.232619 # average WriteReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 132530.126498 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191481.917296 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188686.035081 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 191488.067759 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 188690.392096 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.snoop_filter.tot_requests 4274202 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2158357 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33137 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 328935 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 324390 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4545 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.trans_dist::ReadReq 121088 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 2005227 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28498 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28498 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 739211 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1521984 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 210746 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 317495 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 85916 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42642 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 113550 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 9 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 299038 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 295760 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1310714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595848 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3361 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3912120 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2727113 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 32094 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 130288 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6801615 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166153536 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103357964 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 59176 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 245424 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 269816100 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1019832 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3249125 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.119614 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.328792 # Request fanout histogram +system.cpu0.toL2Bus.snoop_filter.tot_requests 4279317 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2162325 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 33276 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 327449 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 323077 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4372 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.trans_dist::ReadReq 121937 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 2006842 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28493 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28493 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 739077 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1523954 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 209281 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 317808 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 85654 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42585 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 113145 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 298662 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 295385 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1312870 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 595361 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3427 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3918545 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2723305 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 31953 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 129711 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6803514 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 166426752 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 103211806 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 57692 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 240524 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 269936774 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1020233 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 3250109 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.119815 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.328862 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2865028 88.18% 88.18% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 379552 11.68% 99.86% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4545 0.14% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2865068 88.15% 88.15% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 380669 11.71% 99.87% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 4372 0.13% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3249125 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4275785445 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3250109 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4279335949 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 115025120 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113715191 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1969663813 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1972888832 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1293120190 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1291542228 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 17309980 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 17537485 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 68982399 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 69622914 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4001540 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2313487 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 245860 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2018567 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1484210 # Number of BTB hits +system.cpu1.branchPred.lookups 4034173 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2335207 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 244345 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2038897 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1508183 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 73.527904 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 788035 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 5731 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.970534 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 793679 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 5620 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1639,87 +1631,88 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 15963 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 15963 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8440 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3082 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 4441 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 11522 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 609.182434 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3297.605064 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 10996 95.43% 95.43% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 174 1.51% 96.94% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 184 1.60% 98.54% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 58 0.50% 99.05% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 21 0.18% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.04% 99.38% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 47 0.41% 99.79% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 21 0.18% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 15746 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 15746 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8388 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 3065 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 4293 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 11453 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 595.826421 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3233.762475 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 10927 95.41% 95.41% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 176 1.54% 96.94% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 209 1.82% 98.77% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 35 0.31% 99.07% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 13 0.11% 99.19% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 23 0.20% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 3 0.03% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 42 0.37% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 20 0.17% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 11522 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 3235 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11713.446677 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 10455.998129 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6677.373091 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-16383 2744 84.82% 84.82% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-32767 453 14.00% 98.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-49151 32 0.99% 99.81% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-65535 5 0.15% 99.97% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::147456-163839 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 3235 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 75555560672 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.169680 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.377976 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 62765308336 83.07% 83.07% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 12774698836 16.91% 99.98% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 10450000 0.01% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 2017500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 1080000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 463500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 984500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 133500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 33500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 93000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 18000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 18000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 88500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 24500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 138000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 75555560672 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1230 72.78% 72.78% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 460 27.22% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1690 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15963 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::total 11453 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 3271 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11706.970345 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 10400.215389 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 7344.366479 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-16383 2791 85.33% 85.33% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-32767 443 13.54% 98.87% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-49151 31 0.95% 99.82% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-65535 3 0.09% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::131072-147455 1 0.03% 99.94% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::147456-163839 2 0.06% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 3271 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 78450006060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.184600 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.390418 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 63997466940 81.58% 81.58% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 14437247120 18.40% 99.98% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 10341500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 2133500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 875500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 457000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 962000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 87500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 30500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 79000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 14000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 48000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 54000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 17000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 17500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 175000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 78450006060 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1233 71.11% 71.11% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 501 28.89% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1734 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 15746 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15963 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1690 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 15746 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1734 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1690 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 17653 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1734 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 17480 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3544820 # DTB read hits -system.cpu1.dtb.read_misses 14056 # DTB read misses -system.cpu1.dtb.write_hits 3033862 # DTB write hits -system.cpu1.dtb.write_misses 1907 # DTB write misses +system.cpu1.dtb.read_hits 3564995 # DTB read hits +system.cpu1.dtb.read_misses 13832 # DTB read misses +system.cpu1.dtb.write_hits 3032176 # DTB write hits +system.cpu1.dtb.write_misses 1914 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1651 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 51 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 364 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1668 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 34 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 253 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 252 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3558876 # DTB read accesses -system.cpu1.dtb.write_accesses 3035769 # DTB write accesses +system.cpu1.dtb.perms_faults 227 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3578827 # DTB read accesses +system.cpu1.dtb.write_accesses 3034090 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6578682 # DTB hits -system.cpu1.dtb.misses 15963 # DTB misses -system.cpu1.dtb.accesses 6594645 # DTB accesses +system.cpu1.dtb.hits 6597171 # DTB hits +system.cpu1.dtb.misses 15746 # DTB misses +system.cpu1.dtb.accesses 6612917 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1749,60 +1742,55 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6382 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6382 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2250 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 56 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 181.394246 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1406.259305 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 6214 98.23% 98.23% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 59 0.93% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 37 0.58% 99.75% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 6 0.09% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 4 0.06% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 2 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 3 0.05% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6326 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 893 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11600.783875 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10727.998992 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5550.111041 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 41 4.59% 4.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 147 16.46% 21.05% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 548 61.37% 82.42% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 107 11.98% 94.40% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 11 1.23% 95.63% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 5 0.56% 96.19% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 19 2.13% 98.32% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 3 0.34% 98.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 1 0.11% 98.77% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.56% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 3 0.34% 99.66% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::53248-57343 2 0.22% 99.89% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.11% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 893 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 11098487732 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.931053 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.253398 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 765303264 6.90% 6.90% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 10333090968 93.10% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 93500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 11098487732 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 693 82.80% 82.80% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 144 17.20% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 837 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6257 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6257 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 3920 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2276 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 61 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6196 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 206.181407 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1542.947362 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6076 98.06% 98.06% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 60 0.97% 99.03% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 39 0.63% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 7 0.11% 99.77% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.08% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.06% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 4 0.06% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::32768-36863 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6196 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 896 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11471.540179 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10591.082273 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 5713.555798 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 197 21.99% 21.99% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 650 72.54% 94.53% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 13 1.45% 95.98% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 24 2.68% 98.66% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.56% 99.22% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 2 0.22% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.45% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 896 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 13992892620 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.945402 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.227238 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 764122764 5.46% 5.46% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 13228629356 94.54% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 140500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 13992892620 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 692 82.87% 82.87% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 143 17.13% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 835 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6382 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6382 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6257 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6257 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 837 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 837 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7219 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 7191521 # ITB inst hits -system.cpu1.itb.inst_misses 6382 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 835 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 835 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7092 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 7247489 # ITB inst hits +system.cpu1.itb.inst_misses 6257 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1811,1027 +1799,1015 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 901 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 899 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 347 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 342 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7197903 # ITB inst accesses -system.cpu1.itb.hits 7191521 # DTB hits -system.cpu1.itb.misses 6382 # DTB misses -system.cpu1.itb.accesses 7197903 # DTB accesses -system.cpu1.numCycles 32425900 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7253746 # ITB inst accesses +system.cpu1.itb.hits 7247489 # DTB hits +system.cpu1.itb.misses 6257 # DTB misses +system.cpu1.itb.accesses 7253746 # DTB accesses +system.cpu1.numCycles 32825676 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8095443 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 21322301 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4001540 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2272245 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 22576717 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 701366 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 87665 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 29928 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 190452 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 273109 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 16492 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7191191 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 105174 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2314 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 31620489 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.824543 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.195918 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8001289 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 21471337 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4034173 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2301862 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 23036367 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 699414 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 85773 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 29291 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 185520 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 275269 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 17468 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7247139 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 103562 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 31980684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.819942 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.194084 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 19556210 61.85% 61.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4372737 13.83% 75.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1374906 4.35% 80.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 6316636 19.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 19847655 62.06% 62.06% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4393311 13.74% 75.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1390148 4.35% 80.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 6349570 19.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 31620489 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.123406 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.657570 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 6635373 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16232056 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 7605382 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 916534 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 231144 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 619166 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 122135 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 20047523 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 930312 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 231144 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 7872130 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2262020 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11428772 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 7266376 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2560047 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 19035604 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 152359 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 204838 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 28045 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 12601 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1704098 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 18785965 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 89036414 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 21967957 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 31980684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.122897 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.654102 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 6559156 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16660335 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 7594258 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 935690 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 231245 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 620374 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 121000 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 20120105 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 926045 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 231245 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 7803762 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2337008 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11658570 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 7267589 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2682510 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 19097640 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 153089 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 210195 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 28229 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 13307 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1810658 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 18872486 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 89304984 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 22006430 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 6 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 16823959 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 1962006 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 364639 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 299553 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2452699 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 3781052 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3343720 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 554765 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 448879 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 18340674 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 508914 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 18185979 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 84059 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 1788804 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4127246 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 41236 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 31620489 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.575133 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.924807 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 16903103 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 1969383 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 373801 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 306197 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2490350 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 3798024 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3334408 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 558239 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 459403 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 18396455 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 514218 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 18243143 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80370 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1798248 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4138161 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 41963 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 31980684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.570443 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.921832 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 20837444 65.90% 65.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 5408008 17.10% 83.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3574976 11.31% 94.31% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1572233 4.97% 99.28% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 227820 0.72% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 8 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21156406 66.15% 66.15% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 5430198 16.98% 83.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3595564 11.24% 94.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1572256 4.92% 99.29% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 226251 0.71% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 9 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 31620489 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 31980684 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1135208 27.60% 27.60% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 664 0.02% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.61% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1335102 32.46% 60.07% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1642689 39.93% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1148262 27.95% 27.95% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 668 0.02% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 27.97% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1340987 32.64% 60.61% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1618003 39.39% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 24 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 11205359 61.62% 61.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 26215 0.14% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.76% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3128 0.02% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.78% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 3726030 20.49% 82.27% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3225223 17.73% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 11255159 61.70% 61.70% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 26433 0.14% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.84% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3176 0.02% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.86% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 3744432 20.53% 82.38% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3213919 17.62% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 18185979 # Type of FU issued -system.cpu1.iq.rate 0.560847 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4113663 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226200 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 72190169 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 20646412 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 17793804 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.FU_type_0::total 18243143 # Type of FU issued +system.cpu1.iq.rate 0.555758 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4107920 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.225176 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 72655260 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 20717149 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 17851675 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 22299618 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 22351039 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 72560 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 72767 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 346468 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 605 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 8056 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 274891 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 344909 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 550 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 8264 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 279088 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 35566 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 53462 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 35940 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 54533 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 231144 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 519259 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 154115 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 18866238 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 231245 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 541574 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 157299 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 18927437 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 3781052 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3343720 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 266301 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 6646 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 141712 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 8056 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 30125 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 104168 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 134293 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 17982694 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 3650056 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 187326 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 3798024 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3334408 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 272337 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 6587 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 145035 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 8264 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 30633 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 103644 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 134277 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 18042171 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 3670535 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 185229 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 16650 # number of nop insts executed -system.cpu1.iew.exec_refs 6820794 # number of memory reference insts executed -system.cpu1.iew.exec_branches 2588349 # Number of branches executed -system.cpu1.iew.exec_stores 3170738 # Number of stores executed -system.cpu1.iew.exec_rate 0.554578 # Inst execution rate -system.cpu1.iew.wb_sent 17880625 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 17793804 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 8844802 # num instructions producing a value -system.cpu1.iew.wb_consumers 13735859 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.548753 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.643921 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1618894 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 467678 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 126321 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 31256140 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.545936 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.299262 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 16764 # number of nop insts executed +system.cpu1.iew.exec_refs 6830795 # number of memory reference insts executed +system.cpu1.iew.exec_branches 2603132 # Number of branches executed +system.cpu1.iew.exec_stores 3160260 # Number of stores executed +system.cpu1.iew.exec_rate 0.549636 # Inst execution rate +system.cpu1.iew.wb_sent 17938795 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 17851675 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 8886835 # num instructions producing a value +system.cpu1.iew.wb_consumers 13789507 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.543833 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.644464 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1628624 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 472255 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 125883 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 31615084 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.541371 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.295044 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 23000082 73.59% 73.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 4925249 15.76% 89.34% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1442060 4.61% 93.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 538119 1.72% 95.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 452265 1.45% 97.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 297433 0.95% 98.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 181915 0.58% 98.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 99730 0.32% 98.98% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 319287 1.02% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 23337715 73.82% 73.82% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 4942860 15.63% 89.45% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1433345 4.53% 93.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 542164 1.71% 95.70% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 455708 1.44% 97.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 302171 0.96% 98.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 181914 0.58% 98.67% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 99381 0.31% 98.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 319826 1.01% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 31256140 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 13926644 # Number of instructions committed -system.cpu1.commit.committedOps 17063847 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 31615084 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 13986698 # Number of instructions committed +system.cpu1.commit.committedOps 17115488 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 6503413 # Number of memory references committed -system.cpu1.commit.loads 3434584 # Number of loads committed -system.cpu1.commit.membars 191656 # Number of memory barriers committed -system.cpu1.commit.branches 2466066 # Number of branches committed +system.cpu1.commit.refs 6508435 # Number of memory references committed +system.cpu1.commit.loads 3453115 # Number of loads committed +system.cpu1.commit.membars 191139 # Number of memory barriers committed +system.cpu1.commit.branches 2479082 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 15229015 # Number of committed integer instructions. -system.cpu1.commit.function_calls 413334 # Number of function calls committed. +system.cpu1.commit.int_insts 15267561 # Number of committed integer instructions. +system.cpu1.commit.function_calls 414980 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 10531890 61.72% 61.72% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 25416 0.15% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.87% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3128 0.02% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.89% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 3434584 20.13% 82.02% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3068829 17.98% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 10578262 61.81% 61.81% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 25615 0.15% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3176 0.02% 61.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 61.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 61.97% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 61.97% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 3453115 20.18% 82.15% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3055320 17.85% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 17063847 # Class of committed instruction -system.cpu1.commit.bw_lim_events 319287 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 48731479 # The number of ROB reads -system.cpu1.rob.rob_writes 37726129 # The number of ROB writes -system.cpu1.timesIdled 54512 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 805411 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5642014046 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 13923580 # Number of Instructions Simulated -system.cpu1.committedOps 17060783 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.328848 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.328848 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.429397 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.429397 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 20183446 # number of integer regfile reads -system.cpu1.int_regfile_writes 11616875 # number of integer regfile writes -system.cpu1.cc_regfile_reads 64541382 # number of cc regfile reads -system.cpu1.cc_regfile_writes 5516447 # number of cc regfile writes -system.cpu1.misc_regfile_reads 46291245 # number of misc regfile reads -system.cpu1.misc_regfile_writes 345789 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 150536 # number of replacements -system.cpu1.dcache.tags.tagsinuse 478.106753 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 5837857 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 150895 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 38.688207 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89621465500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.106753 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.933802 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.933802 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 359 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 351 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 8 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.701172 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 12869097 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 12869097 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 3072993 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3072993 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2528751 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2528751 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42878 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 42878 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70516 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 70516 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61926 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 61926 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5601744 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5601744 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5644622 # number of overall hits -system.cpu1.dcache.overall_hits::total 5644622 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 178967 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 178967 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 316584 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 316584 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23990 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 23990 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17392 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 17392 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23411 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23411 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 495551 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 495551 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 519541 # number of overall misses -system.cpu1.dcache.overall_misses::total 519541 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3311567500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3311567500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11108580447 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 11108580447 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 357363500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 357363500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 641574000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 641574000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 819500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 819500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 14420147947 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 14420147947 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 14420147947 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 14420147947 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3251960 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3251960 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 2845335 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 2845335 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66868 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 66868 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87908 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 87908 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 85337 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 85337 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 6097295 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 6097295 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 6164163 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 6164163 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.055034 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.055034 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111264 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.111264 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.358767 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.358767 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.197843 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.197843 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274336 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274336 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081274 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.081274 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084284 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.084284 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 18503.788408 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 18503.788408 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 35088.887774 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 35088.887774 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20547.579347 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20547.579347 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27404.809705 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27404.809705 # average StoreCondReq miss latency +system.cpu1.commit.op_class_0::total 17115488 # Class of committed instruction +system.cpu1.commit.bw_lim_events 319826 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 49145756 # The number of ROB reads +system.cpu1.rob.rob_writes 37850174 # The number of ROB writes +system.cpu1.timesIdled 55034 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 844992 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5621633430 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 13983634 # Number of Instructions Simulated +system.cpu1.committedOps 17112424 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.347435 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.347435 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.425997 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.425997 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 20215691 # number of integer regfile reads +system.cpu1.int_regfile_writes 11658166 # number of integer regfile writes +system.cpu1.cc_regfile_reads 64782198 # number of cc regfile reads +system.cpu1.cc_regfile_writes 5550427 # number of cc regfile writes +system.cpu1.misc_regfile_reads 46731168 # number of misc regfile reads +system.cpu1.misc_regfile_writes 350339 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 150744 # number of replacements +system.cpu1.dcache.tags.tagsinuse 471.669505 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 5845075 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 151083 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 38.687840 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 104824569000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 471.669505 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.921230 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.921230 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 339 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 328 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 11 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.662109 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 12896760 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 12896760 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 3092594 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3092594 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2524465 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2524465 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 42426 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 42426 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 70168 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 70168 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 61430 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 61430 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 5617059 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5617059 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5659485 # number of overall hits +system.cpu1.dcache.overall_hits::total 5659485 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 178952 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 178952 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 316827 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 316827 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 23604 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 23604 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 17348 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 17348 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23299 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23299 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 495779 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 495779 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 519383 # number of overall misses +system.cpu1.dcache.overall_misses::total 519383 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3441746500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3441746500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11862734947 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11862734947 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 362002500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 362002500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 631001500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 631001500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1169000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1169000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15304481447 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15304481447 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15304481447 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15304481447 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3271546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3271546 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 2841292 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 2841292 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 66030 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 66030 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 87516 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 87516 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 84729 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 84729 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 6112838 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 6112838 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 6178868 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 6178868 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.054700 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.054700 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.111508 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.111508 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.357474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.357474 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.198227 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.198227 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.274983 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.274983 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.081105 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.081105 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.084058 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.084058 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19232.791475 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 19232.791475 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 37442.310621 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 37442.310621 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 20867.102836 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 20867.102836 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 27082.771793 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 27082.771793 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 29099.220760 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 29099.220760 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 27755.553358 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 27755.553358 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 351 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1652938 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 24 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 30246 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 14.625000 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 54.649805 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30869.563751 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 30869.563751 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 29466.658414 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 29466.658414 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 358 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1808008 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 31 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 30216 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.548387 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 59.836113 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 150537 # number of writebacks -system.cpu1.dcache.writebacks::total 150537 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62639 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 62639 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 238187 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 238187 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12480 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12480 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 300826 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 300826 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 300826 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 300826 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116328 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 116328 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78397 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 78397 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 23066 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 23066 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4912 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4912 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23411 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23411 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 194725 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 194725 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 217791 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 217791 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3053 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3053 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2412 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2412 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5465 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1734233000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1734233000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2786620456 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2786620456 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 403892500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 403892500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 94891500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 94891500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 618171000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 618171000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 811500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 811500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4520853456 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4520853456 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4924745956 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4924745956 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 433886500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 433886500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 300722000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 300722000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 734608500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 734608500 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035772 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035772 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027553 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027553 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.344948 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.344948 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055877 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055877 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274336 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274336 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031936 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031936 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035332 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.035332 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14908.130459 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14908.130459 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35544.988405 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 35544.988405 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17510.296540 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17510.296540 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 19318.302117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 19318.302117 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 26405.151425 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 26405.151425 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 150744 # number of writebacks +system.cpu1.dcache.writebacks::total 150744 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 62223 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 62223 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 237836 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 237836 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 12586 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 12586 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 300059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 300059 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 300059 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 300059 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 116729 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 116729 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 78991 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 78991 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 22881 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 22881 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 4762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 4762 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23299 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23299 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 195720 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 195720 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 218601 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 218601 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3069 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3069 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2411 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2411 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5480 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5480 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1778715000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1778715000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2939877456 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2939877456 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 425185000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 425185000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 98534500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 98534500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 607713500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 607713500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1158000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1158000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4718592456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4718592456 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5143777456 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5143777456 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 437774500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 437774500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 301405500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 301405500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 739180000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 739180000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035680 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035680 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027801 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.346524 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.346524 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.054413 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.054413 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.274983 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.274983 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.032018 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.032018 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035379 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.035379 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15237.987133 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15237.987133 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 37217.878695 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 37217.878695 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 18582.448320 # average SoftPFReq mshr miss latency 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average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 22612.256503 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 22612.256503 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142118.080576 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 142118.080576 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 124677.446103 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 124677.446103 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 134420.585544 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134420.585544 # average overall mshr uncacheable latency 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134886.861314 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 134886.861314 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 559207 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.428858 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6611589 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 559719 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.812336 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79408312500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.428858 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975447 # Average percentage of cache occupancy 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system.cpu1.icache.tags.age_task_id_blocks_1024::2 494 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id -system.cpu1.icache.tags.age_task_id_blocks_1024::4 1 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu1.icache.tags.age_task_id_blocks_1024::4 2 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 14941719 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 14941719 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 6611589 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6611589 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6611589 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6611589 # number of demand (read+write) hits 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of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5260271690 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5260271690 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7190998 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7190998 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7190998 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7190998 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7190998 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7190998 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.080574 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.080574 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.080574 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.080574 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.080574 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.080574 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9078.684815 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9078.684815 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9078.684815 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9078.684815 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9078.684815 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 508858 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41527 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.253666 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu1.icache.tags.tag_accesses 15046317 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 15046317 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 6675021 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6675021 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6675021 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6675021 # number of demand (read+write) hits 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of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5247903529 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5247903529 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7246945 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7246945 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7246945 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7246945 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7246945 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7246945 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.078919 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.078919 # miss rate for ReadReq accesses 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cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 438 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 40965 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.654461 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 146 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 559207 # number of writebacks -system.cpu1.icache.writebacks::total 559207 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19686 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 19686 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 19686 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 19686 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 19686 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 19686 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 559723 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 559723 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 559723 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 559723 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 559723 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 559723 # number of overall MSHR misses +system.cpu1.icache.writebacks::writebacks 551908 # number of writebacks +system.cpu1.icache.writebacks::total 551908 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 19497 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 19497 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 19497 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 19497 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 19497 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 19497 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 552427 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 552427 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 552427 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 552427 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 552427 # number of overall MSHR misses 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of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 4814325924 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 4796273338 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 4796273338 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 4796273338 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 4796273338 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 4796273338 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 4796273338 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 14117999 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 14117999 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 14117999 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 14117999 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.077837 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.077837 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.077837 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.077837 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8601.265133 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8601.265133 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8601.265133 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8601.265133 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.076229 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.076229 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.076229 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.076229 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8682.184864 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8682.184864 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8682.184864 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 137067.951456 # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 137067.951456 # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 137067.951456 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 109440 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 110020 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 525 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 114901 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 115599 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 633 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped 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# average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total inf # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 50389.116561 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 50389.116561 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 53873.419933 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17578.962863 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17578.962863 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 30752.074217 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16052.863436 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14480 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 53873.419933 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 28273.133258 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 63486.677450 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 36050.879577 # average overall mshr miss latency system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134022.436947 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133876.901141 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117077.941957 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117077.941957 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 134577.712610 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 134414.880202 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 117410.408959 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 117410.408959 # average WriteReq mshr uncacheable latency system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 129563.106796 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 126543.915096 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 126599.765805 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 127024.725547 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 127071.555794 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.snoop_filter.tot_requests 1523677 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 769701 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12410 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 171538 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 169858 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1680 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.trans_dist::ReadReq 26336 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 768409 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2412 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2412 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 120538 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 604293 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 90253 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 23776 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71073 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41600 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 85044 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 11 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 57287 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 54410 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 559723 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 223005 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 24 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1668415 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 728070 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15878 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27246 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2439609 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70944752 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24680600 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29208 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50568 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 95705128 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 366083 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1123000 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.171945 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.381277 # Request fanout histogram +system.cpu1.toL2Bus.snoop_filter.tot_requests 1510050 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 763127 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12108 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 172945 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 171137 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 1808 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.trans_dist::ReadReq 26162 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 760461 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2411 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2411 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 125070 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 598066 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 92914 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 26023 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 70036 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41455 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 85358 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 57012 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 54811 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 552427 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 220569 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 25 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1646728 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 729194 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 15588 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 27029 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2418539 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 70023728 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 24695290 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 28464 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 50044 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 94797526 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 371473 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 1121639 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.173444 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.382865 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 931586 82.96% 82.96% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 189734 16.90% 99.85% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 1680 0.15% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 928905 82.82% 82.82% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 190926 17.02% 99.84% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1808 0.16% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1123000 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1483438992 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1121639 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1469339490 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80062850 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 79587436 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 839820234 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 828867751 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 323064197 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 323642126 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8585980 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8481980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 14617972 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 14527980 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31018 # Transaction distribution system.iobus.trans_dist::ReadResp 31018 # Transaction distribution @@ -2839,6 +2815,7 @@ system.iobus.trans_dist::WriteReq 59424 # Tr system.iobus.trans_dist::WriteResp 59424 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56618 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.pci_host.pio 434 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) @@ -2854,16 +2831,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::total 107932 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes) system.iobus.pkt_count::total 180884 # Packet count per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 71562 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 244 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_size_system.bridge.master::system.realview.pci_host.pio 638 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) @@ -2879,26 +2854,25 @@ system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes) -system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.bridge.master::total 162812 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484060 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40405000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40431500 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 111500 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 31500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 324000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 31500 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer6.occupancy 90500 # Layer occupancy (ticks) -system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 581000 # Layer occupancy (ticks) +system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) +system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) +system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) +system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 11500 # Layer occupancy (ticks) @@ -2919,31 +2893,25 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6141000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6146000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 169500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 34110000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 34081000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 186335542 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer26.occupancy 124500 # Layer occupancy (ticks) -system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 186321543 # Layer occupancy (ticks) -system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer28.occupancy 31500 # Layer occupancy (ticks) -system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84732000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.554671 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.549511 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 256310853000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.554671 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909667 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909667 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 256320229000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.549511 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909344 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909344 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2957,14 +2925,14 @@ system.iocache.demand_misses::realview.ide 252 # system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32664376 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32664376 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4736716167 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4736716167 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32664376 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32664376 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32664376 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32664376 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32965876 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32965876 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4737835666 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4737835666 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32965876 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32965876 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32965876 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32965876 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2981,19 +2949,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129620.539683 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129620.539683 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130761.819981 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 130761.819981 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 129620.539683 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 129620.539683 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 129620.539683 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 734 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 130816.968254 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 130816.968254 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 130792.724879 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 130792.724879 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 130816.968254 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 130816.968254 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 130816.968254 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 713 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 91 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 8.065934 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 7.835165 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -3007,14 +2975,14 @@ system.iocache.demand_mshr_misses::realview.ide 252 system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 20064376 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 20064376 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2925516167 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2925516167 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 20064376 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 20064376 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 20064376 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 20064376 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 20365876 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 20365876 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2926635666 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2926635666 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 20365876 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 20365876 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 20365876 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 20365876 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3023,602 +2991,602 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79620.539683 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79620.539683 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80761.819981 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80761.819981 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 79620.539683 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 79620.539683 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 80816.968254 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 80816.968254 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 80792.724879 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 80792.724879 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 80816.968254 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 80816.968254 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 124125 # number of replacements -system.l2c.tags.tagsinuse 63228.123175 # Cycle average of tags in use -system.l2c.tags.total_refs 440353 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 188206 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.339739 # Average number of references to valid blocks. +system.l2c.tags.replacements 131293 # number of replacements +system.l2c.tags.tagsinuse 63152.978828 # Cycle average of tags in use +system.l2c.tags.total_refs 442353 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 195350 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.264413 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13402.508661 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.314049 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.063314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8220.125540 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2863.958869 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34966.595872 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.597372 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909987 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1640.209162 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 501.782314 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 1607.058034 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.204506 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000279 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13838.997413 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 18.349981 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.060621 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8045.868087 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2735.320064 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33659.346102 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 6.413836 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.909660 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1799.024775 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 856.706825 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2190.981465 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.211166 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000280 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.125429 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043701 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.533548 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000085 # Average percentage of cache occupancy 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-system.l2c.tags.occ_task_id_blocks::1024 33176 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 142 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5961 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 24779 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 23 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 36 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 587 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4232 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 28320 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.471222 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000351 # Percentage of cache occupancy per task id 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# number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 245 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 135 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 35685 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 48934 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 48260 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 39 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 11 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 7748 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 5393 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 2770 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::total 149220 # number of ReadSharedReq hits -system.l2c.demand_hits::cpu0.dtb.walker 245 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 135 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 35685 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 53133 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 48260 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 39 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 11 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 7748 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 6930 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 2770 # number of demand (read+write) hits -system.l2c.demand_hits::total 154956 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 245 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 135 # number of overall hits -system.l2c.overall_hits::cpu0.inst 35685 # number of overall hits -system.l2c.overall_hits::cpu0.data 53133 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 48260 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 39 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 11 # number of overall hits -system.l2c.overall_hits::cpu1.inst 7748 # number of overall hits -system.l2c.overall_hits::cpu1.data 6930 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 2770 # number of overall hits -system.l2c.overall_hits::total 154956 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 9737 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2474 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12211 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 860 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1323 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2183 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 11128 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8036 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 19164 # number of ReadExReq misses -system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 28 # number of ReadSharedReq misses +system.l2c.tags.occ_percent::cpu1.inst 0.027451 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.013072 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.033432 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.963638 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30319 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 26 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33712 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 117 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6038 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24164 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 622 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 4436 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28625 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.462631 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000397 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.514404 # Percentage of cache occupancy per task id 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# mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.151510 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for ReadSharedReq accesses -system.l2c.ReadSharedReq_mshr_miss_rate::total 0.532585 # mshr miss rate for ReadSharedReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.021739 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.353853 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.275999 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.732038 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.133333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.083333 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.256236 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.564944 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.678692 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.549735 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.102564 # mshr miss rate for overall accesses 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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 75545.445209 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 75297.493937 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 75495.209238 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 77613.373256 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 76659.486017 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 77035.273019 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 141701.923077 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 123108.138377 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 133905.030265 # average ReadExReq mshr miss latency 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# average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 128884.959047 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 144495.643980 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 141281.250000 # average overall mshr miss latency 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-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 124118.869337 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 123922.380264 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 170077.143394 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 142423.155007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 122782.827817 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 136006.129431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 147831.968542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 122785.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 123000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 125656.590510 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 124320.492992 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 171515.539318 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 143331.915216 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182200.248131 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182221.195259 # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116137.868852 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171355.441505 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164737.386413 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100066.751244 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159690.942802 # average WriteReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 116692.922374 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 171386.248749 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 164734.444881 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 100401.287433 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 159715.442726 # average WriteReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 114529.960053 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173952.160203 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 173958.617260 # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 111553.398058 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109040.919810 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 166122.879936 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 109521.271499 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 166150.430305 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 37995 # Transaction distribution -system.membus.trans_dist::ReadResp 208280 # Transaction distribution -system.membus.trans_dist::WriteReq 30910 # Transaction distribution -system.membus.trans_dist::WriteResp 30910 # Transaction distribution -system.membus.trans_dist::WritebackDirty 133887 # Transaction distribution -system.membus.trans_dist::CleanEvict 14956 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74359 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40536 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14484 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution -system.membus.trans_dist::ReadExReq 38707 # Transaction distribution -system.membus.trans_dist::ReadExResp 19074 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 170286 # Transaction distribution +system.membus.trans_dist::ReadReq 37982 # Transaction distribution +system.membus.trans_dist::ReadResp 212889 # Transaction distribution +system.membus.trans_dist::WriteReq 30904 # Transaction distribution +system.membus.trans_dist::WriteResp 30904 # Transaction distribution +system.membus.trans_dist::WritebackDirty 139000 # Transaction distribution +system.membus.trans_dist::CleanEvict 16061 # Transaction distribution +system.membus.trans_dist::UpgradeReq 72768 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40424 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14027 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 2 # Transaction distribution +system.membus.trans_dist::ReadExReq 40474 # Transaction distribution +system.membus.trans_dist::ReadExResp 20691 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174908 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107932 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13724 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 655631 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 777327 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13686 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 672318 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 793976 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 886261 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 902910 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162812 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27448 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18402504 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18593084 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27372 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19129032 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19319536 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 20911228 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 120617 # Total snoops (count) -system.membus.snoop_fanout::samples 578108 # Request fanout histogram +system.membus.pkt_size::total 21637680 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 119522 # Total snoops (count) +system.membus.snoop_fanout::samples 588990 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 578108 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 588990 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 578108 # Request fanout histogram -system.membus.reqLayer0.occupancy 81934000 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 588990 # Request fanout histogram +system.membus.reqLayer0.occupancy 81993500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11360491 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11365991 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 977870256 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1011151356 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1121733386 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1153249220 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 64044757 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64060493 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks @@ -3661,56 +3629,56 @@ system.realview.mcc.osc_clcd.clock 42105 # Cl system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.snoop_filter.tot_requests 989446 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 534228 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 146104 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20085 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19207 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 878 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.trans_dist::ReadReq 37998 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 475278 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30910 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30910 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 393382 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 89983 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 108688 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43642 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 152330 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 15 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 15 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50244 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50244 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 437296 # Transaction distribution +system.toL2Bus.snoop_filter.tot_requests 995943 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 537996 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 143832 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21510 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20627 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 883 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.trans_dist::ReadReq 37985 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 476927 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30904 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30904 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 403719 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 92623 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 107653 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43539 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 151192 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50791 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50791 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 438958 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1240411 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 256111 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1496522 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34963008 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 3945788 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 38908796 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 440874 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 905624 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.341764 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.476341 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1238290 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 270024 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1508314 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 35030546 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 4521886 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 39552432 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 444179 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 913848 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.335282 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.474132 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 596992 65.92% 65.92% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 307754 33.98% 99.90% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 878 0.10% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 608334 66.57% 66.57% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 304631 33.33% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 883 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 905624 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 871666747 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 913848 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 880459353 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.snoopLayer0.occupancy 356120 # Layer occupancy (ticks) +system.toL2Bus.snoopLayer0.occupancy 356618 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 657174901 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 654259891 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 205942747 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 211427270 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1875 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1860 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2747 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2725 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |