diff options
| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-07-21 17:19:18 +0100 |
| commit | 84f138ba96201431513eb2ae5f847389ac731aa2 (patch) | |
| tree | 3aee721699295c85e4e0c2d3d4a6bb27595bfabd /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | a288c94387b110112461ff5686fa727a43ddbe9c (diff) | |
| download | gem5-84f138ba96201431513eb2ae5f847389ac731aa2.tar.xz | |
stats: update references
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
4 files changed, 3269 insertions, 2926 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 6af9f752e..ecd5fd333 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -12,11 +12,12 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/home/stever/m5/aarch-system-2014-10/binaries/boot_emm.arm +boot_loader=/arm/projectscratch/randd/systems/dist/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb +default_p_state=UNDEFINED +dtb_filename=/arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -29,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -41,10 +42,14 @@ mmap_using_noreserve=false multi_proc=true multi_thread=false num_work_ids=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh +power_model=Null +readfile=/work/curdun01/gem5-external.hg/tests/testing/../halt.sh reset_addr_64=0 symbolfile= thermal_components= @@ -61,8 +66,13 @@ system_port=system.membus.slave[1] [system.bridge] type=Bridge clk_domain=system.clk_domain +default_p_state=UNDEFINED delay=50000 eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null ranges=788529152:805306367 721420288:725614591 805306368:1073741823 1073741824:1610612735 402653184:469762047 469762048:536870911 req_size=16 resp_size=16 @@ -89,7 +99,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/home/stever/m5/aarch-system-2014-10/disks/linux-aarch32-ael.img +image_file=/arm/projectscratch/randd/systems/dist/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -124,6 +134,7 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -162,6 +173,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -218,12 +233,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -242,8 +262,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -266,9 +291,14 @@ walker=system.cpu0.dstage2_mmu.stage2_tlb.walker [system.cpu0.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.dtb] @@ -282,9 +312,14 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[3] @@ -560,12 +595,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -584,8 +624,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -643,9 +688,14 @@ walker=system.cpu0.istage2_mmu.stage2_tlb.walker [system.cpu0.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu0.itb] @@ -659,9 +709,14 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu0.toL2Bus.slave[2] @@ -672,12 +727,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu0.l2cache.prefetcher response_latency=12 @@ -695,6 +755,7 @@ mem_side=system.toL2Bus.slave[0] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -705,6 +766,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -721,8 +786,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -730,10 +800,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu0.toL2Bus.snoop_filter snoop_response_latency=1 @@ -778,6 +853,7 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=2 decodeWidth=3 +default_p_state=UNDEFINED dispatchWidth=6 do_checkpoint_insts=true do_quiesce=true @@ -816,6 +892,10 @@ numPhysIntRegs=128 numROBEntries=40 numRobs=1 numThreads=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null profile=0 progress_interval=0 renameToDecodeDelay=1 @@ -872,12 +952,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=2 is_read_only=false max_miss_count=0 mshrs=6 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=2 @@ -896,8 +981,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -920,9 +1010,14 @@ walker=system.cpu1.dstage2_mmu.stage2_tlb.walker [system.cpu1.dstage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.dtb] @@ -936,9 +1031,14 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[3] @@ -1214,12 +1314,17 @@ addr_ranges=0:18446744073709551615 assoc=2 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=1 is_read_only=true max_miss_count=0 mshrs=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=1 @@ -1238,8 +1343,13 @@ type=LRU assoc=2 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=32768 @@ -1297,9 +1407,14 @@ walker=system.cpu1.istage2_mmu.stage2_tlb.walker [system.cpu1.istage2_mmu.stage2_tlb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=true num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system [system.cpu1.itb] @@ -1313,9 +1428,14 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 is_stage2=false num_squash_per_cycle=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sys=system port=system.cpu1.toL2Bus.slave[2] @@ -1326,12 +1446,17 @@ addr_ranges=0:18446744073709551615 assoc=16 clk_domain=system.cpu_clk_domain clusivity=mostly_excl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=12 is_read_only=false max_miss_count=0 mshrs=16 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=true prefetcher=system.cpu1.l2cache.prefetcher response_latency=12 @@ -1349,6 +1474,7 @@ mem_side=system.toL2Bus.slave[1] type=StridePrefetcher cache_snoop=false clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED degree=8 eventq_index=0 latency=1 @@ -1359,6 +1485,10 @@ on_inst=true on_miss=false on_read=true on_write=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null queue_filter=true queue_size=32 queue_squash=true @@ -1375,8 +1505,13 @@ type=RandomRepl assoc=16 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=12 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1048576 @@ -1384,10 +1519,15 @@ size=1048576 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.cpu1.toL2Bus.snoop_filter snoop_response_latency=1 @@ -1432,9 +1572,14 @@ sys=system [system.iobus] type=NoncoherentXBar clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=1 frontend_latency=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null response_latency=2 use_default_range=false width=16 @@ -1448,12 +1593,17 @@ addr_ranges=2147483648:2415919103 assoc=8 clk_domain=system.clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=50 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=50 @@ -1472,8 +1622,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=50 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=1024 @@ -1484,12 +1639,17 @@ addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain clusivity=mostly_incl +default_p_state=UNDEFINED demand_mshr_reserve=1 eventq_index=0 hit_latency=20 is_read_only=false max_miss_count=0 mshrs=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null prefetch_on_access=false prefetcher=Null response_latency=20 @@ -1508,8 +1668,13 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 hit_latency=20 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null sequential_access=false size=4194304 @@ -1517,10 +1682,15 @@ size=4194304 type=CoherentXBar children=badaddr_responder snoop_filter clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=4 frontend_latency=3 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=true +power_model=Null response_latency=2 snoop_filter=system.membus.snoop_filter snoop_response_latency=4 @@ -1534,11 +1704,16 @@ slave=system.realview.hdlcd.dma system.system_port system.l2c.mem_side system.io [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=0 pio_latency=100000 pio_size=8 +power_model=Null ret_bad_addr=true ret_data16=65535 ret_data32=4294967295 @@ -1590,6 +1765,7 @@ burst_length=8 channels=1 clk_domain=system.clk_domain conf_table_reported=true +default_p_state=UNDEFINED device_bus_width=8 device_rowbuffer_size=1024 device_size=536870912 @@ -1601,7 +1777,11 @@ max_accesses_per_row=16 mem_sched_policy=frfcfs min_writes_per_switch=16 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 page_policy=open_adaptive +power_model=Null range=2147483648:2415919103 ranks_per_channel=2 read_buffer_size=32 @@ -1644,10 +1824,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470024192 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[18] @@ -1728,14 +1913,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 +default_p_state=UNDEFINED disks= eventq_index=0 host=system.realview.pci_host io_shift=2 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=2 pci_dev=0 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[2] pio=system.iobus.master[9] @@ -1744,13 +1934,18 @@ pio=system.iobus.master[9] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=46 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471793664 pio_latency=10000 pixel_clock=41667 +power_model=Null system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -1831,10 +2026,15 @@ voltage_domain=system.voltage_domain [system.realview.energy_ctrl] type=EnergyCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED dvfs_handler=system.dvfs_handler eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470286336 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[22] @@ -1914,17 +2114,22 @@ SubsystemVendorID=32902 VendorID=32902 clk_domain=system.clk_domain config_latency=20000 +default_p_state=UNDEFINED eventq_index=0 fetch_comp_delay=10000 fetch_delay=10000 hardware_address=00:90:00:00:00:01 host=system.realview.pci_host +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=0 pci_func=0 phy_epid=896 phy_pid=680 pio_latency=30000 +power_model=Null rx_desc_cache_size=64 rx_fifo_size=393216 rx_write_delay=0 @@ -1950,13 +2155,18 @@ type=Pl390 clk_domain=system.clk_domain cpu_addr=738205696 cpu_pio_delay=10000 +default_p_state=UNDEFINED dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 gem5_extensions=true int_latency=10000 it_lines=128 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 platform=system.realview +power_model=Null system=system pio=system.membus.master[2] @@ -1964,14 +2174,19 @@ pio=system.membus.master[2] type=HDLcd amba_id=1314816 clk_domain=system.clk_domain +default_p_state=UNDEFINED enable_capture=true eventq_index=0 gic=system.realview.gic int_num=117 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=721420288 pio_latency=10000 pixel_buffer_size=2048 pixel_chunk=32 +power_model=Null pxl_clk=system.realview.dcc.osc_pxl system=system vnc=system.vncserver @@ -2057,14 +2272,19 @@ VendorID=32902 clk_domain=system.clk_domain config_latency=20000 ctrl_offset=0 +default_p_state=UNDEFINED disks=system.cf0 eventq_index=0 host=system.realview.pci_host io_shift=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_bus=0 pci_dev=1 pci_func=0 pio_latency=30000 +power_model=Null system=system dma=system.iobus.slave[3] pio=system.iobus.master[23] @@ -2073,13 +2293,18 @@ pio=system.iobus.master[23] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=44 is_mouse=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470155264 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[7] @@ -2088,13 +2313,18 @@ pio=system.iobus.master[7] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=45 is_mouse=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470220800 pio_latency=100000 +power_model=Null system=system vnc=system.vncserver pio=system.iobus.master[8] @@ -2102,11 +2332,16 @@ pio=system.iobus.master[8] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=739246080 pio_latency=100000 pio_size=4095 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2120,11 +2355,16 @@ pio=system.iobus.master[12] [system.realview.lan_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=436207616 pio_latency=100000 pio_size=65535 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2138,12 +2378,17 @@ pio=system.iobus.master[19] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=738721792 pio_latency=100000 +power_model=Null system=system pio=system.membus.master[4] @@ -2211,10 +2456,15 @@ system=system type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470089728 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[21] @@ -2223,11 +2473,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=0:67108863 port=system.membus.master[1] @@ -2237,21 +2492,31 @@ clk_domain=system.clk_domain conf_base=805306368 conf_device_bits=16 conf_size=268435456 +default_p_state=UNDEFINED eventq_index=0 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pci_dma_base=0 pci_mem_base=0 pci_pio_base=0 platform=system.realview +power_model=Null system=system pio=system.iobus.master[2] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 idreg=35979264 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469827584 pio_latency=100000 +power_model=Null proc_id0=335544320 proc_id1=335544320 system=system @@ -2261,12 +2526,17 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=36 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=471269376 pio_latency=100000 +power_model=Null system=system time=Thu Jan 1 00:00:00 2009 pio=system.iobus.master[10] @@ -2275,10 +2545,15 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=true +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=469893120 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[16] @@ -2288,12 +2563,17 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=34 int_num1=34 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470876160 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[3] @@ -2303,26 +2583,36 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic int_num0=35 int_num1=35 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470941696 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[4] [system.realview.uart] type=Pl011 clk_domain=system.clk_domain +default_p_state=UNDEFINED end_on_eot=false eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=37 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470351872 pio_latency=100000 platform=system.realview +power_model=Null system=system terminal=system.terminal pio=system.iobus.master[0] @@ -2331,10 +2621,15 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470417408 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[13] @@ -2342,10 +2637,15 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470482944 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[14] @@ -2353,21 +2653,31 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470548480 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[15] [system.realview.usb_fake] type=IsaFake clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 fake_mem=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=452984832 pio_latency=100000 pio_size=131071 +power_model=Null ret_bad_addr=false ret_data16=65535 ret_data32=4294967295 @@ -2381,11 +2691,16 @@ pio=system.iobus.master[20] [system.realview.vgic] type=VGic clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 gic=system.realview.gic hv_addr=738213888 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_delay=10000 platform=system.realview +power_model=Null ppint=25 system=system vcpu_addr=738222080 @@ -2396,11 +2711,16 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +default_p_state=UNDEFINED eventq_index=0 in_addr_map=true latency=30000 latency_var=0 null=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 +power_model=Null range=402653184:436207615 port=system.iobus.master[11] @@ -2408,10 +2728,15 @@ port=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +default_p_state=UNDEFINED eventq_index=0 ignore_access=false +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 pio_addr=470745088 pio_latency=100000 +power_model=Null system=system pio=system.iobus.master[17] @@ -2427,10 +2752,15 @@ port=3456 type=CoherentXBar children=snoop_filter clk_domain=system.cpu_clk_domain +default_p_state=UNDEFINED eventq_index=0 forward_latency=0 frontend_latency=1 +p_state_clk_gate_bins=20 +p_state_clk_gate_max=1000000000000 +p_state_clk_gate_min=1000 point_of_coherency=false +power_model=Null response_latency=1 snoop_filter=system.toL2Bus.snoop_filter snoop_response_latency=1 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 3e7bd42ce..8041988f0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -2,6 +2,8 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: ClockedObject: More than one power state change request encountered within the same simulation tick +warn: ClockedObject: More than one power state change request encountered within the same simulation tick warn: Existing EnergyCtrl, but no enabled DVFSHandler found. warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index 5b77a63d3..1edb75ef2 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -3,16 +3,16 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Mar 15 2016 21:26:42 -gem5 started Mar 15 2016 21:34:31 -gem5 executing on phenom, pid 15964 -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual +gem5 compiled Jul 21 2016 14:37:41 +gem5 started Jul 21 2016 14:39:51 +gem5 executing on e108600-lin, pid 23108 +command line: /work/curdun01/gem5-external.hg/build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re /work/curdun01/gem5-external.hg/tests/testing/../run.py long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /home/stever/m5/aarch-system-2014-10/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +info: kernel located at: /arm/projectscratch/randd/systems/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 info: Using bootloader at address 0x10 info: Using kernel entry physical address at 0x80008000 -info: Loading DTB file: /home/stever/m5/aarch-system-2014-10/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 +info: Loading DTB file: /arm/projectscratch/randd/systems/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.2cpu.dtb at address 0x88000000 info: Entering event queue @ 0. Starting simulation... info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2825959731500 because m5_exit instruction encountered +Exiting @ tick 2825947406000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index a155d5f42..d0d350a97 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,162 +1,162 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.825960 # Number of seconds simulated -sim_ticks 2825959731500 # Number of ticks simulated -final_tick 2825959731500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.825947 # Number of seconds simulated +sim_ticks 2825947406000 # Number of ticks simulated +final_tick 2825947406000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 99061 # Simulator instruction rate (inst/s) -host_op_rate 120168 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2330545961 # Simulator tick rate (ticks/s) -host_mem_usage 626024 # Number of bytes of host memory used -host_seconds 1212.57 # Real time elapsed on the host -sim_insts 120118276 # Number of instructions simulated -sim_ops 145712235 # Number of ops (including micro ops) simulated +host_inst_rate 72283 # Simulator instruction rate (inst/s) +host_op_rate 87685 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1700475056 # Simulator tick rate (ticks/s) +host_mem_usage 618496 # Number of bytes of host memory used +host_seconds 1661.86 # Real time elapsed on the host +sim_insts 120124543 # Number of instructions simulated +sim_ops 145720076 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory +system.physmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.physmem.bytes_read::cpu0.dtb.walker 1664 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1306176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1321704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8517568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 181104 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 644308 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 521472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1303616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1321960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8513856 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 384 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 181024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 635732 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 529024 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12495724 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1306176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 181104 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1487280 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8956736 # Number of bytes written to this memory +system.physmem.bytes_read::total 12488540 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1303616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 181024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1484640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8962368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8974300 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 8979932 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 26 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 22656 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 21172 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 133087 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 2898 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10088 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 8148 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 22616 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 21176 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 133029 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 6 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 2896 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 9954 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 8266 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 198102 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 139949 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197989 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140037 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 144340 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 611 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 144428 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 68 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 462206 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 467701 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3014044 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 159 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 64086 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 227996 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 184529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 461302 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 467794 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3012744 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 45 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 64058 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 224962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 187202 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4421763 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 462206 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 64086 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 526292 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3169449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4419240 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 461302 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 64058 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 525360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3171456 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6201 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 14 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3175665 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3169449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 611 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3177671 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3171456 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 68 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 462206 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 473902 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3014044 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 159 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 64086 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 228010 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 184529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 461302 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 473995 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3012744 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 45 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 64058 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 224977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 187202 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7597427 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 198102 # Number of read requests accepted -system.physmem.writeReqs 144340 # Number of write requests accepted -system.physmem.readBursts 198102 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 144340 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12669056 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 9472 # Total number of bytes read from write queue -system.physmem.bytesWritten 8986944 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12495724 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 8974300 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 148 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 7596911 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197990 # Number of read requests accepted +system.physmem.writeReqs 144428 # Number of write requests accepted +system.physmem.readBursts 197990 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 144428 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12662400 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 8960 # Total number of bytes read from write queue +system.physmem.bytesWritten 8992448 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12488604 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 8979932 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 140 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 3897 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12421 # Per bank write bursts -system.physmem.perBankRdBursts::1 12320 # Per bank write bursts -system.physmem.perBankRdBursts::2 12949 # Per bank write bursts -system.physmem.perBankRdBursts::3 12687 # Per bank write bursts -system.physmem.perBankRdBursts::4 14539 # Per bank write bursts -system.physmem.perBankRdBursts::5 12136 # Per bank write bursts -system.physmem.perBankRdBursts::6 12666 # Per bank write bursts -system.physmem.perBankRdBursts::7 12482 # Per bank write bursts -system.physmem.perBankRdBursts::8 12195 # Per bank write bursts -system.physmem.perBankRdBursts::9 12078 # Per bank write bursts -system.physmem.perBankRdBursts::10 11738 # Per bank write bursts -system.physmem.perBankRdBursts::11 11022 # Per bank write bursts -system.physmem.perBankRdBursts::12 11908 # Per bank write bursts -system.physmem.perBankRdBursts::13 13049 # Per bank write bursts -system.physmem.perBankRdBursts::14 12095 # Per bank write bursts -system.physmem.perBankRdBursts::15 11669 # Per bank write bursts -system.physmem.perBankWrBursts::0 9112 # Per bank write bursts +system.physmem.perBankRdBursts::0 12407 # Per bank write bursts +system.physmem.perBankRdBursts::1 12295 # Per bank write bursts +system.physmem.perBankRdBursts::2 12935 # Per bank write bursts +system.physmem.perBankRdBursts::3 12653 # Per bank write bursts +system.physmem.perBankRdBursts::4 14543 # Per bank write bursts +system.physmem.perBankRdBursts::5 12106 # Per bank write bursts +system.physmem.perBankRdBursts::6 12653 # Per bank write bursts +system.physmem.perBankRdBursts::7 12509 # Per bank write bursts +system.physmem.perBankRdBursts::8 12223 # Per bank write bursts +system.physmem.perBankRdBursts::9 12064 # Per bank write bursts +system.physmem.perBankRdBursts::10 11718 # Per bank write bursts +system.physmem.perBankRdBursts::11 11008 # Per bank write bursts +system.physmem.perBankRdBursts::12 11914 # Per bank write bursts +system.physmem.perBankRdBursts::13 13060 # Per bank write bursts +system.physmem.perBankRdBursts::14 12107 # Per bank write bursts +system.physmem.perBankRdBursts::15 11655 # Per bank write bursts +system.physmem.perBankWrBursts::0 9105 # Per bank write bursts system.physmem.perBankWrBursts::1 9127 # Per bank write bursts -system.physmem.perBankWrBursts::2 9607 # Per bank write bursts -system.physmem.perBankWrBursts::3 9172 # Per bank write bursts -system.physmem.perBankWrBursts::4 8420 # Per bank write bursts -system.physmem.perBankWrBursts::5 8729 # Per bank write bursts -system.physmem.perBankWrBursts::6 8984 # Per bank write bursts -system.physmem.perBankWrBursts::7 8803 # Per bank write bursts -system.physmem.perBankWrBursts::8 8716 # Per bank write bursts -system.physmem.perBankWrBursts::9 8606 # Per bank write bursts -system.physmem.perBankWrBursts::10 8527 # Per bank write bursts -system.physmem.perBankWrBursts::11 8118 # Per bank write bursts -system.physmem.perBankWrBursts::12 8733 # Per bank write bursts -system.physmem.perBankWrBursts::13 9183 # Per bank write bursts -system.physmem.perBankWrBursts::14 8560 # Per bank write bursts -system.physmem.perBankWrBursts::15 8024 # Per bank write bursts +system.physmem.perBankWrBursts::2 9615 # Per bank write bursts +system.physmem.perBankWrBursts::3 9150 # Per bank write bursts +system.physmem.perBankWrBursts::4 8481 # Per bank write bursts +system.physmem.perBankWrBursts::5 8750 # Per bank write bursts +system.physmem.perBankWrBursts::6 8993 # Per bank write bursts +system.physmem.perBankWrBursts::7 8806 # Per bank write bursts +system.physmem.perBankWrBursts::8 8720 # Per bank write bursts +system.physmem.perBankWrBursts::9 8569 # Per bank write bursts +system.physmem.perBankWrBursts::10 8518 # Per bank write bursts +system.physmem.perBankWrBursts::11 8119 # Per bank write bursts +system.physmem.perBankWrBursts::12 8743 # Per bank write bursts +system.physmem.perBankWrBursts::13 9182 # Per bank write bursts +system.physmem.perBankWrBursts::14 8573 # Per bank write bursts +system.physmem.perBankWrBursts::15 8056 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 19 # Number of times write queue was full causing retry -system.physmem.totGap 2825959428000 # Total gap between requests +system.physmem.numWrRetry 6 # Number of times write queue was full causing retry +system.physmem.totGap 2825947136000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3087 # Read request sizes (log2) +system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 194436 # Read request sizes (log2) +system.physmem.readPktSize::6 194325 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 139949 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 60343 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 72005 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 15875 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12985 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5357 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4768 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1542 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 975 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 736 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140037 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 72217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 15830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12957 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8715 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7515 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6523 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5382 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4740 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 989 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 256 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see @@ -189,118 +189,120 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2761 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 3720 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4251 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4868 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5700 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5982 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 6922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 7546 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8592 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 8610 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 10123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 10779 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 9327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 9570 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11050 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9220 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8388 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 7975 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 571 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 246 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 197 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 177 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 131 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 155 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 123 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 118 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 141 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 120 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 122 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 117 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 121 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 89 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 93 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 53 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 41 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 37 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 54 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 92433 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 234.287927 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 132.256290 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 299.423161 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 50967 55.14% 55.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 17630 19.07% 74.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5955 6.44% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3343 3.62% 84.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2739 2.96% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1518 1.64% 88.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 933 1.01% 89.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1042 1.13% 91.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 8306 8.99% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 92433 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6998 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 28.287082 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 556.369682 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6996 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 2737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3737 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4277 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4910 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5685 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6030 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 7661 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8663 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 8689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 10204 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 10681 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9419 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9434 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 10925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9108 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8385 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 232 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 165 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 132 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 144 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 164 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 103 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 129 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 125 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 98 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 88 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 72 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 44 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 26 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 92378 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 234.414947 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 132.500025 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 299.048436 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 50794 54.98% 54.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17715 19.18% 74.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 5941 6.43% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3366 3.64% 84.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2816 3.05% 87.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1529 1.66% 88.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 925 1.00% 89.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 990 1.07% 91.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8302 8.99% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 92378 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 6992 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 28.296339 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 556.591514 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 6990 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6998 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6998 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 20.065876 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.638507 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 11.720707 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 5824 83.22% 83.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 388 5.54% 88.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 101 1.44% 90.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 68 0.97% 91.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 286 4.09% 95.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 30 0.43% 95.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 22 0.31% 96.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 18 0.26% 96.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 13 0.19% 96.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 6 0.09% 96.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 8 0.11% 96.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 11 0.16% 96.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 167 2.39% 99.20% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 8 0.11% 99.31% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 2 0.03% 99.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::76-79 5 0.07% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-83 8 0.11% 99.53% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 4 0.06% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 1 0.01% 99.60% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 2 0.03% 99.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-99 4 0.06% 99.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 3 0.04% 99.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::108-111 1 0.01% 99.74% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-115 1 0.01% 99.76% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 9 0.13% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.01% 99.90% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 2 0.03% 99.93% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::156-159 1 0.01% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-163 2 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.rdPerTurnAround::total 6992 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 6992 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 20.095395 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.609227 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.295574 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5854 83.72% 83.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 392 5.61% 89.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 80 1.14% 90.47% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 62 0.89% 91.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 277 3.96% 95.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 20 0.29% 95.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 15 0.21% 95.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 24 0.34% 96.17% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 25 0.36% 96.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 12 0.17% 96.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 9 0.13% 96.82% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 14 0.20% 97.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 142 2.03% 99.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 4 0.06% 99.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 10 0.14% 99.26% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 7 0.10% 99.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 6 0.09% 99.44% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::84-87 1 0.01% 99.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 2 0.03% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.01% 99.50% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 3 0.04% 99.54% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 2 0.03% 99.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::108-111 3 0.04% 99.61% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.01% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 14 0.20% 99.84% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::132-135 2 0.03% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::156-159 3 0.04% 99.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::160-163 2 0.03% 99.96% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::168-171 1 0.01% 99.97% # Writes before turning the bus around for reads system.physmem.wrPerTurnAround::180-183 1 0.01% 99.99% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::204-207 1 0.01% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6998 # Writes before turning the bus around for reads -system.physmem.totQLat 6678126737 # Total ticks spent queuing -system.physmem.totMemAccLat 10389764237 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 989770000 # Total ticks spent in databus transfers -system.physmem.avgQLat 33735.75 # Average queueing delay per DRAM burst +system.physmem.wrPerTurnAround::188-191 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 6992 # Writes before turning the bus around for reads +system.physmem.totQLat 6748582846 # Total ticks spent queuing +system.physmem.totMemAccLat 10458270346 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 989250000 # Total ticks spent in databus transfers +system.physmem.avgQLat 34109.59 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 52485.75 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 52859.59 # Average memory access latency per DRAM burst system.physmem.avgRdBW 4.48 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 3.18 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 4.42 # Average system read bandwidth in MiByte/s @@ -309,43 +311,43 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.08 # Average read queue length when enqueuing -system.physmem.avgWrQLen 24.31 # Average write queue length when enqueuing -system.physmem.readRowHits 165316 # Number of row buffer hits during reads -system.physmem.writeRowHits 80625 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.51 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 57.41 # Row buffer hit rate for writes -system.physmem.avgGap 8252373.91 # Average gap between requests -system.physmem.pageHitRate 72.68 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 362040840 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 197542125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 797160000 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 466261920 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 79687786095 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1625672869500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1891761444000 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.423201 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2704357113137 # Time in different power states -system.physmem_0.memoryStateTime::REF 94364920000 # Time in different power states +system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing +system.physmem.avgWrQLen 24.52 # Average write queue length when enqueuing +system.physmem.readRowHits 165284 # Number of row buffer hits during reads +system.physmem.writeRowHits 80694 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 57.42 # Row buffer hit rate for writes +system.physmem.avgGap 8252916.42 # Average gap between requests +system.physmem.pageHitRate 72.69 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 361058040 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 197005875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 796387800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 466734960 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 79734690540 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1625622381750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1891755025365 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.424618 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2704272847388 # Time in different power states +system.physmem_0.memoryStateTime::REF 94364400000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 27235374363 # Time in different power states +system.physmem_0.memoryStateTime::ACT 27304587612 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 336752640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 183744000 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 746873400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 443666160 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 184577783520 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 79354368585 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1625965341000 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1891608529305 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.369090 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2704844457298 # Time in different power states -system.physmem_1.memoryStateTime::REF 94364920000 # Time in different power states +system.physmem_1.actEnergy 337319640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 184053375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 746834400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 443750400 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 184576766400 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 79554512970 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1625780432250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1891623669435 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.378136 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2704538486760 # Time in different power states +system.physmem_1.memoryStateTime::REF 94364400000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 26750317702 # Time in different power states +system.physmem_1.memoryStateTime::ACT 27044516240 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.nvmem.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.nvmem.bytes_read::cpu0.inst 112 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 176 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 288 # Number of bytes read from this memory @@ -364,30 +366,30 @@ system.realview.nvmem.bw_inst_read::total 102 # I system.realview.nvmem.bw_total::cpu0.inst 40 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 62 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 102 # Total bandwidth to/from this memory (bytes/s) -system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.bridge.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.vram.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.bridge.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD). system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 53057105 # Number of BP lookups -system.cpu0.branchPred.condPredicted 24374304 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 933540 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 32092107 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 13945777 # Number of BTB hits +system.cpu0.branchPred.lookups 53058502 # Number of BP lookups +system.cpu0.branchPred.condPredicted 24374377 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 933450 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 32093175 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 13944864 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 43.455473 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 15468620 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 33215 # Number of incorrect RAS predictions. -system.cpu0.branchPred.indirectLookups 10119517 # Number of indirect predictor lookups. -system.cpu0.branchPred.indirectHits 9964028 # Number of indirect target hits. -system.cpu0.branchPred.indirectMisses 155489 # Number of indirect misses. +system.cpu0.branchPred.BTBHitPct 43.451182 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15470259 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 33206 # Number of incorrect RAS predictions. +system.cpu0.branchPred.indirectLookups 10120086 # Number of indirect predictor lookups. +system.cpu0.branchPred.indirectHits 9964746 # Number of indirect target hits. +system.cpu0.branchPred.indirectMisses 155340 # Number of indirect misses. system.cpu0.branchPredindirectMispredicted 48572 # Number of mispredicted indirect branches. system.cpu_clk_domain.clock 500 # Clock period in ticks -system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu0.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -417,86 +419,84 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.dtb.walker.walks 67255 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 67255 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25406 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18986 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 22863 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 44392 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 465.320328 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 3000.549463 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 43255 97.44% 97.44% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 874 1.97% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 114 0.26% 99.66% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 99 0.22% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 12 0.03% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 21 0.05% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 1 0.00% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 13 0.03% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.walker.walks 67164 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 67164 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 25323 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 19031 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 22810 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 44354 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 458.594490 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2953.911408 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 43233 97.47% 97.47% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 862 1.94% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 108 0.24% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 108 0.24% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 9 0.02% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 18 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 14 0.03% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::65536-73727 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency system.cpu0.dtb.walker.walkWaitTime::73728-81919 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::81920-90111 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 44392 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 17098 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 11190.109954 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 9724.852754 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7829.867535 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 15731 92.00% 92.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1253 7.33% 99.33% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 72 0.42% 99.75% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::49152-65535 7 0.04% 99.80% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.02% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 1 0.01% 99.82% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::114688-131071 13 0.08% 99.90% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::147456-163839 16 0.09% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 17098 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 81474776356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.525392 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.513017 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 81416314856 99.93% 99.93% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 41234500 0.05% 99.98% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 7083500 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 4738000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 1423000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 1004000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 1185500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 1778000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 81474776356 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5261 77.38% 77.38% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.62% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6799 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67255 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkWaitTime::total 44354 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 17047 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 11038.716490 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 9658.702439 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6683.029230 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 15750 92.39% 92.39% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 1185 6.95% 99.34% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 75 0.44% 99.78% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 14 0.08% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 5 0.03% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 14 0.08% 99.98% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::114688-131071 2 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::131072-147455 1 0.01% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 17047 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 85757506152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.515718 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.512261 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 85699757152 99.93% 99.93% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 40650000 0.05% 99.98% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 7189500 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 4730000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1448500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 1006500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 1064000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 1646000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 14500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 85757506152 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5272 77.42% 77.42% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1538 22.58% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6810 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 67164 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67255 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6799 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 67164 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6810 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6799 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 74054 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6810 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 73974 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 23647306 # DTB read hits -system.cpu0.dtb.read_misses 56401 # DTB read misses -system.cpu0.dtb.write_hits 17573284 # DTB write hits -system.cpu0.dtb.write_misses 10854 # DTB write misses +system.cpu0.dtb.read_hits 23645826 # DTB read hits +system.cpu0.dtb.read_misses 56383 # DTB read misses +system.cpu0.dtb.write_hits 17571331 # DTB write hits +system.cpu0.dtb.write_misses 10781 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3477 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 219 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2242 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3487 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 213 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 2243 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 851 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 23703707 # DTB read accesses -system.cpu0.dtb.write_accesses 17584138 # DTB write accesses +system.cpu0.dtb.perms_faults 818 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 23702209 # DTB read accesses +system.cpu0.dtb.write_accesses 17582112 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 41220590 # DTB hits -system.cpu0.dtb.misses 67255 # DTB misses -system.cpu0.dtb.accesses 41287845 # DTB accesses -system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu0.dtb.hits 41217157 # DTB hits +system.cpu0.dtb.misses 67164 # DTB misses +system.cpu0.dtb.accesses 41284321 # DTB accesses +system.cpu0.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -526,56 +526,59 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.itb.walker.walks 10944 # Table walker walks requested -system.cpu0.itb.walker.walksShort 10944 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3906 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5976 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 1062 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9882 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 441.003845 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 2235.176297 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9496 96.09% 96.09% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 178 1.80% 97.90% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 126 1.28% 99.17% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.62% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 8 0.08% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 23 0.23% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 2 0.02% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9882 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 3633 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 11938.893476 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 11121.754202 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 4829.169649 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 620 17.07% 17.07% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 2792 76.85% 93.92% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.83% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 45 1.24% 99.06% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 33 0.91% 99.97% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.itb.walker.walks 10883 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10883 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3898 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 5925 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 1060 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 9823 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 449.709865 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2327.234590 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9434 96.04% 96.04% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 184 1.87% 97.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 123 1.25% 99.17% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 44 0.45% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 7 0.07% 99.68% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 18 0.18% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 4 0.04% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 3 0.03% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 9823 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 3631 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11923.299367 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 11119.549027 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 4771.165368 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 614 16.91% 16.91% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 2801 77.14% 94.05% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 142 3.91% 97.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 43 1.18% 99.15% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 27 0.74% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 3 0.08% 99.97% # Table walker service (enqueue to completion) latency system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.03% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 3633 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 21344293712 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.816978 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.386812 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 3907509500 18.31% 18.31% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17435777712 81.69% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 987000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 19500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 21344293712 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2239 87.09% 87.09% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 332 12.91% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkCompletionTime::total 3631 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 21332036712 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.795904 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.403169 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 4354826000 20.41% 20.41% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 16976239212 79.58% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 901500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 70000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 21332036712 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2243 87.24% 87.24% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 328 12.76% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2571 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10944 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10944 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10883 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10883 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2571 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2571 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 13515 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 72708872 # ITB inst hits -system.cpu0.itb.inst_misses 10944 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin::total 13454 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 72708520 # ITB inst hits +system.cpu0.itb.inst_misses 10883 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -584,111 +587,111 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2281 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2280 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1928 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1927 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 72719816 # ITB inst accesses -system.cpu0.itb.hits 72708872 # DTB hits -system.cpu0.itb.misses 10944 # DTB misses -system.cpu0.itb.accesses 72719816 # DTB accesses -system.cpu0.numPwrStateTransitions 3656 # Number of power state transitions -system.cpu0.pwrStateClkGateDist::samples 1828 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::mean 1490596475.785011 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::stdev 23949118810.105305 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::underflows 1055 57.71% 57.71% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::1000-5e+10 768 42.01% 99.73% # Distribution of time spent in the clock gated state +system.cpu0.itb.inst_accesses 72719403 # ITB inst accesses +system.cpu0.itb.hits 72708520 # DTB hits +system.cpu0.itb.misses 10883 # DTB misses +system.cpu0.itb.accesses 72719403 # DTB accesses +system.cpu0.numPwrStateTransitions 3678 # Number of power state transitions +system.cpu0.pwrStateClkGateDist::samples 1839 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::mean 1481668762.034258 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::stdev 23877600166.586662 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::underflows 1061 57.69% 57.69% # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::1000-5e+10 773 42.03% 99.73% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::1.5e+11-2e+11 1 0.05% 99.78% # Distribution of time spent in the clock gated state system.cpu0.pwrStateClkGateDist::4.5e+11-5e+11 4 0.22% 100.00% # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::max_value 499973380096 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateClkGateDist::total 1828 # Distribution of time spent in the clock gated state -system.cpu0.pwrStateResidencyTicks::ON 101149373765 # Cumulative time (in ticks) in various power states -system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724810357735 # Cumulative time (in ticks) in various power states -system.cpu0.numCycles 202299816 # number of cpu cycles simulated +system.cpu0.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::max_value 499971949600 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateClkGateDist::total 1839 # Distribution of time spent in the clock gated state +system.cpu0.pwrStateResidencyTicks::ON 101158552619 # Cumulative time (in ticks) in various power states +system.cpu0.pwrStateResidencyTicks::CLK_GATED 2724788853381 # Cumulative time (in ticks) in various power states +system.cpu0.numCycles 202318013 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 20373611 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 195792180 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 53057105 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 39378425 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 174483712 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 5690816 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 148557 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 57787 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 411894 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 415808 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 91444 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 72708572 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 259286 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 5400 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 198828221 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.203592 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.307832 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 20370009 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 195788924 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 53058502 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 39379869 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 174489676 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5690920 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 148682 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 56911 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 412776 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 413906 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 90774 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 72708226 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 258373 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 5359 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 198828194 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.203611 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.307839 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 93975229 47.26% 47.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 30343697 15.26% 62.53% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 14563448 7.32% 69.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 59945847 30.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 93974548 47.26% 47.26% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 30342793 15.26% 62.53% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14563641 7.32% 69.85% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 59947212 30.15% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 198828221 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.262270 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.967832 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 25603497 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 106945433 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 58799621 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4964058 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 2515612 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 3059417 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 333874 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 154225745 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3810952 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 2515612 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 34211381 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 12457896 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 83569478 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 55018547 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 11055307 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 137550697 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 1033071 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1452205 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 164556 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 58179 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6849429 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 141656181 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 634589847 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 152645231 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9369 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 130468277 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 11187893 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 2697265 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 2555549 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 22573870 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 24578234 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 19061004 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1697434 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2322680 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 134618116 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1713414 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 132756465 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 452944 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10581179 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 21719888 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 120083 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 198828221 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.667694 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 0.963230 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 198828194 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.262253 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.967729 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 25600367 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 106949118 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 58799478 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4963264 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2515967 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 3058039 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 333585 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 154217934 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3811468 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2515967 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 34209280 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 12450122 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 83570932 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 55016631 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 11065262 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 137539344 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1033397 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1452682 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 164882 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 58749 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6858829 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 141646141 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 634543216 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 152633070 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9368 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 130461493 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 11184637 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2697680 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2556046 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22573700 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 24576087 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 19059052 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1700091 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2321608 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 134608055 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1714170 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 132746710 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 453040 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10578491 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21717645 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 121089 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 198828194 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.667645 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.963186 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 122137220 61.43% 61.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 33612355 16.91% 78.33% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 31219254 15.70% 94.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 10732023 5.40% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1127312 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 122140771 61.43% 61.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 33611714 16.90% 78.34% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 31218891 15.70% 94.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10730115 5.40% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1126646 0.57% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::5 57 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -696,44 +699,44 @@ system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 198828221 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 198828194 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 10787922 43.88% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 67 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.88% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5632694 22.91% 66.78% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 8166758 33.22% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10786366 43.89% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 65 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.89% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5629308 22.91% 66.79% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 8160859 33.21% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2273 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 89674441 67.55% 67.55% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 111153 0.08% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 89668905 67.55% 67.55% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 111084 0.08% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.63% # Type of FU issued @@ -756,100 +759,100 @@ system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.63% # Ty system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.63% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 67.63% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 8107 0.01% 67.64% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.63% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 8099 0.01% 67.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.64% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.64% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 24338377 18.33% 85.97% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 18622113 14.03% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 24336393 18.33% 85.97% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 18619956 14.03% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 132756465 # Type of FU issued -system.cpu0.iq.rate 0.656236 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 24587441 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.185207 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 489349072 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 146920725 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 129226985 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32463 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11252 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 132746710 # Type of FU issued +system.cpu0.iq.rate 0.656129 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 24576598 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.185139 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 489318685 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 146908772 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 129217545 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32566 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11248 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9717 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 157320500 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21133 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 365431 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 157299800 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21235 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 365614 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1915604 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2466 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 19339 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 897405 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1914996 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2485 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 19372 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 896753 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 120966 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 361642 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 121022 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 362352 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 2515612 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1602789 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 184527 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 136483987 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2515967 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1594217 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 188418 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 136474692 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 24578234 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 19061004 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 875924 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 28511 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 132116 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 19339 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 261906 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 398193 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 660099 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 131724041 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 23895876 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 965291 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 24576087 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 19059052 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 876204 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 28441 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 136041 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 19372 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 261507 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 398935 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 660442 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 131715074 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 23894149 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 964599 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 152457 # number of nop insts executed -system.cpu0.iew.exec_refs 42356949 # number of memory reference insts executed -system.cpu0.iew.exec_branches 25556056 # Number of branches executed -system.cpu0.iew.exec_stores 18461073 # Number of stores executed -system.cpu0.iew.exec_rate 0.651133 # Inst execution rate -system.cpu0.iew.wb_sent 131168007 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 129236702 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 65950850 # num instructions producing a value -system.cpu0.iew.wb_consumers 106665798 # num instructions consuming a value -system.cpu0.iew.wb_rate 0.638837 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.618294 # average fanout of values written-back -system.cpu0.commit.commitSquashedInsts 9550008 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1593331 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 603744 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 195669003 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.643292 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.341136 # Number of insts commited each cycle +system.cpu0.iew.exec_nop 152467 # number of nop insts executed +system.cpu0.iew.exec_refs 42353114 # number of memory reference insts executed +system.cpu0.iew.exec_branches 25555008 # Number of branches executed +system.cpu0.iew.exec_stores 18458965 # Number of stores executed +system.cpu0.iew.exec_rate 0.651030 # Inst execution rate +system.cpu0.iew.wb_sent 131158694 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 129227262 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 65946343 # num instructions producing a value +system.cpu0.iew.wb_consumers 106655009 # num instructions consuming a value +system.cpu0.iew.wb_rate 0.638733 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618315 # average fanout of values written-back +system.cpu0.commit.commitSquashedInsts 9548145 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1593081 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 603957 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 195669167 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.643258 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.340979 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 135299612 69.15% 69.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 33411311 17.08% 86.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 12639941 6.46% 92.68% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3246105 1.66% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 4896411 2.50% 96.84% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 2789558 1.43% 98.27% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1311154 0.67% 98.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 556760 0.28% 99.22% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1518151 0.78% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 135298586 69.15% 69.15% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 33412613 17.08% 86.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12639367 6.46% 92.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3246710 1.66% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4896676 2.50% 96.84% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2794942 1.43% 98.27% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1306268 0.67% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 556762 0.28% 99.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1517243 0.78% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 195669003 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 103938440 # Number of instructions committed -system.cpu0.commit.committedOps 125872394 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 195669167 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 103932879 # Number of instructions committed +system.cpu0.commit.committedOps 125865777 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 40826228 # Number of memory references committed -system.cpu0.commit.loads 22662629 # Number of loads committed -system.cpu0.commit.membars 647252 # Number of memory barriers committed -system.cpu0.commit.branches 24954847 # Number of branches committed +system.cpu0.commit.refs 40823389 # Number of memory references committed +system.cpu0.commit.loads 22661090 # Number of loads committed +system.cpu0.commit.membars 647148 # Number of memory barriers committed +system.cpu0.commit.branches 24954311 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 109891295 # Number of committed integer instructions. -system.cpu0.commit.function_calls 4835454 # Number of function calls committed. +system.cpu0.commit.int_insts 109885490 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4835541 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 84929206 67.47% 67.47% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 108853 0.09% 67.56% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 84925464 67.47% 67.47% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 108825 0.09% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.56% # Class of committed instruction @@ -873,762 +876,758 @@ system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.56% # system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.56% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.56% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 8107 0.01% 67.57% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 8099 0.01% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.57% # Class of committed instruction system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 22662629 18.00% 85.57% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 18163599 14.43% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 22661090 18.00% 85.57% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 18162299 14.43% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 125872394 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1518151 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 306287204 # The number of ROB reads -system.cpu0.rob.rob_writes 273994781 # The number of ROB writes -system.cpu0.timesIdled 123974 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3471595 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5449619957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 103816388 # Number of Instructions Simulated -system.cpu0.committedOps 125750342 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.948631 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.948631 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.513181 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.513181 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 142719808 # number of integer regfile reads -system.cpu0.int_regfile_writes 81679098 # number of integer regfile writes +system.cpu0.commit.op_class_0::total 125865777 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1517243 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 306278084 # The number of ROB reads +system.cpu0.rob.rob_writes 273977566 # The number of ROB writes +system.cpu0.timesIdled 123981 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3489819 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5449576943 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 103810827 # Number of Instructions Simulated +system.cpu0.committedOps 125743725 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.948911 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.948911 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.513107 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.513107 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 142709258 # number of integer regfile reads +system.cpu0.int_regfile_writes 81672792 # number of integer regfile writes system.cpu0.fp_regfile_reads 8185 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 464897652 # number of cc regfile reads -system.cpu0.cc_regfile_writes 49725456 # number of cc regfile writes -system.cpu0.misc_regfile_reads 388373326 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1224889 # number of misc regfile writes -system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.tags.replacements 709828 # number of replacements -system.cpu0.dcache.tags.tagsinuse 497.174198 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 37665141 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 710340 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 53.024103 # Average number of references to valid blocks. +system.cpu0.cc_regfile_reads 464864695 # number of cc regfile reads +system.cpu0.cc_regfile_writes 49723023 # number of cc regfile writes +system.cpu0.misc_regfile_reads 388122601 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1224736 # number of misc regfile writes +system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.tags.replacements 709879 # number of replacements +system.cpu0.dcache.tags.tagsinuse 499.426037 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 37661762 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 710391 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.015539 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 278078500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.174198 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.971043 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.971043 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 499.426037 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.975441 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.975441 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 175 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 320 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 17 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 174 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 322 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 81170296 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 81170296 # Number of data accesses -system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.dcache.ReadReq_hits::cpu0.data 21454849 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 21454849 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 14988122 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 14988122 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308527 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 308527 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 363066 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361109 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 361109 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 36442971 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 36442971 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 36751498 # number of overall hits -system.cpu0.dcache.overall_hits::total 36751498 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 646522 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 646522 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1887777 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1887777 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147802 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 147802 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25065 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 25065 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20108 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 20108 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2534299 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2534299 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2682101 # number of overall misses -system.cpu0.dcache.overall_misses::total 2682101 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8646662000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8646662000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29876871349 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 29876871349 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399690500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 399690500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484891000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 484891000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 240000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 240000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 38523533349 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 38523533349 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 38523533349 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 38523533349 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 22101371 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 22101371 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 16875899 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 16875899 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456329 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 456329 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388131 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 388131 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381217 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 381217 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 38977270 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 38977270 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 39433599 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 39433599 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029253 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029253 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111862 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.111862 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323894 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323894 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064579 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064579 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052747 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052747 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065020 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.065020 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068016 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.068016 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13374.118746 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13374.118746 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15826.483398 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 15826.483398 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15946.159984 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15946.159984 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24114.332604 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24114.332604 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 81162963 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 81162963 # Number of data accesses +system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.dcache.ReadReq_hits::cpu0.data 21452365 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 21452365 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14987011 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14987011 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 308699 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 308699 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 363086 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 363086 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 361018 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 361018 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 36439376 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 36439376 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 36748075 # number of overall hits +system.cpu0.dcache.overall_hits::total 36748075 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 646473 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 646473 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1887751 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1887751 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 147620 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 147620 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 25081 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 25081 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 20154 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 20154 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2534224 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2534224 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2681844 # number of overall misses +system.cpu0.dcache.overall_misses::total 2681844 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8640238000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8640238000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 29904279351 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 29904279351 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 399794500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 399794500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 485945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 485945500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 390500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 390500 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 38544517351 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 38544517351 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 38544517351 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 38544517351 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 22098838 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 22098838 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16874762 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16874762 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 456319 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 456319 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 388167 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 388167 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 381172 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 381172 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 38973600 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 38973600 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 39429919 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 39429919 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029254 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029254 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111868 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.111868 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323502 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323502 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064614 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.052874 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.052874 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.065024 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.065024 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.068015 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.068015 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13365.195453 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13365.195453 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 15841.220241 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 15841.220241 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15940.133966 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15940.133966 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 24111.615560 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 24111.615560 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15200.863572 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 15200.863572 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14363.192642 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 14363.192642 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 1028 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 4276317 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 48 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 201917 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 21.416667 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 21.178588 # average number of cycles each access was blocked -system.cpu0.dcache.writebacks::writebacks 709828 # number of writebacks -system.cpu0.dcache.writebacks::total 709828 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 259036 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 259036 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563852 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1563852 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18553 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18553 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1822888 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822888 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1822888 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387486 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 387486 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323925 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 323925 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101400 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 101400 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6512 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6512 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20108 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 20108 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 711411 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 711411 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 812811 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 812811 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31771 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31771 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28450 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28450 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60221 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60221 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4570691500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4570691500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6113916381 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6113916381 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1664414000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1664414000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 102380000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 102380000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 464790000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 464790000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 233000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 233000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10684607881 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10684607881 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12349021881 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 12349021881 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621026500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621026500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621026500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621026500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017532 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017532 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019195 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222208 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222208 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016778 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052747 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052747 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018252 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.018252 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020612 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.020612 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11795.759073 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11795.759073 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18874.481380 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18874.481380 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16414.339250 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16414.339250 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15721.744472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15721.744472 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23114.680724 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23114.680724 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 15209.593687 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 15209.593687 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 14372.393529 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 14372.393529 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 691 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4275244 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 201901 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 16.069767 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 21.174952 # average number of cycles each access was blocked +system.cpu0.dcache.writebacks::writebacks 709879 # number of writebacks +system.cpu0.dcache.writebacks::total 709879 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 258972 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 258972 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1563802 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1563802 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18565 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18565 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1822774 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1822774 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1822774 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1822774 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 387501 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 387501 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 323949 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 323949 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 101413 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 101413 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6516 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6516 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 20154 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 20154 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 711450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 711450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 812863 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 812863 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 31772 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 31772 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 28451 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 28451 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 60223 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 60223 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4575351000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4575351000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6134433385 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6134433385 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1666291000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1666291000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 103051000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 103051000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 465800500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 465800500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 381500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 381500 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10709784385 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10709784385 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 12376075385 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 12376075385 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 6621057500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 6621057500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6621057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6621057500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017535 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017535 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019197 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.222241 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.222241 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016787 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016787 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052874 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052874 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018255 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018255 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020615 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020615 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11807.326949 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11807.326949 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 18936.417106 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 18936.417106 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16430.743593 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16430.743593 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15815.070595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15815.070595 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 23112.062122 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 23112.062122 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15018.896083 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15018.896083 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15192.980756 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15192.980756 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208398.429385 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208398.429385 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109945.475831 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109945.475831 # average overall mshr uncacheable latency -system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.tags.replacements 1253795 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.762128 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 71396857 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1254307 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 56.921357 # Average number of references to valid blocks. +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 15053.460377 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 15053.460377 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 15225.290590 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 15225.290590 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 208392.845902 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 208392.845902 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 109942.339306 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 109942.339306 # average overall mshr uncacheable latency +system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.tags.replacements 1252995 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.762307 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 71397425 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1253507 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 56.958138 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 7880422000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762128 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999535 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999535 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.762307 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999536 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999536 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 150 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 122 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 152 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 232 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 128 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 146664376 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 146664376 # Number of data accesses -system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.icache.ReadReq_hits::cpu0.inst 71396857 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 71396857 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 71396857 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 71396857 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 71396857 # number of overall hits -system.cpu0.icache.overall_hits::total 71396857 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1308156 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1308156 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1308156 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1308156 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1308156 # number of overall misses -system.cpu0.icache.overall_misses::total 1308156 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 13216802476 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 13216802476 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 13216802476 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 13216802476 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 13216802476 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 13216802476 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 72705013 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 72705013 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 72705013 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 72705013 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 72705013 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 72705013 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017993 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.017993 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017993 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.017993 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017993 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.017993 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 10103.384058 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 10103.384058 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 10103.384058 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 10103.384058 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 10103.384058 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1586454 # number of cycles access was blocked +system.cpu0.icache.tags.tag_accesses 146662859 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 146662859 # Number of data accesses +system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.icache.ReadReq_hits::cpu0.inst 71397425 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 71397425 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 71397425 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 71397425 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 71397425 # number of overall hits +system.cpu0.icache.overall_hits::total 71397425 # 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number of ReadReq MSHR uncacheable system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3003 # number of overall MSHR uncacheable misses system.cpu0.icache.overall_mshr_uncacheable_misses::total 3003 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11994065954 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 11994065954 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11994065954 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 11994065954 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11994065954 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 11994065954 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11993376465 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11993376465 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11993376465 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11993376465 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11993376465 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11993376465 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 269145498 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 269145498 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 269145498 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017253 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.017253 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017253 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.017253 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9561.969460 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9561.969460 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 9561.969460 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017242 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017242 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017242 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017242 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9567.544653 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9567.544653 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9567.544653 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9567.544653 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 89625.540460 # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 89625.540460 # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 89625.540460 # average overall mshr uncacheable latency -system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837870 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1840472 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 2353 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1837427 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1839978 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 2305 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 236752 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.tags.replacements 276743 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16098.325627 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 3280707 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 292864 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 11.202152 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 236878 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.l2cache.tags.replacements 277234 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16111.552153 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3276769 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 293338 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 11.170626 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 14667.103561 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 16.169259 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 1.382075 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1413.670732 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.895209 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000987 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000084 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.086284 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.982564 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1008 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15101 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 35 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 303 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 375 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 295 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::0 1 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 7 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 109 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 469 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4669 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 6979 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2875 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061523 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.921692 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 66287217 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 66287217 # Number of data accesses -system.cpu0.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 55484 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 13243 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 68727 # number of ReadReq hits -system.cpu0.l2cache.WritebackDirty_hits::writebacks 481730 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackDirty_hits::total 481730 # number of WritebackDirty hits -system.cpu0.l2cache.WritebackClean_hits::writebacks 1450652 # number of WritebackClean hits -system.cpu0.l2cache.WritebackClean_hits::total 1450652 # number of WritebackClean hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 221301 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 221301 # number of ReadExReq hits -system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1201423 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadCleanReq_hits::total 1201423 # number of ReadCleanReq hits -system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 398814 # number of ReadSharedReq hits -system.cpu0.l2cache.ReadSharedReq_hits::total 398814 # number of ReadSharedReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 55484 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 13243 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1201423 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 620115 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1890265 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 55484 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 13243 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1201423 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 620115 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1890265 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 413 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 141 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 554 # number of ReadReq misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 54992 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 54992 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 20107 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 20107 # number of SCUpgradeReq misses +system.cpu0.l2cache.tags.occ_blocks::writebacks 14693.899751 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 11.282247 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.429995 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1405.940159 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.896844 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000689 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000026 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.085812 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.983371 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1005 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 10 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15089 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 38 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 280 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 408 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 279 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 4 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::4 3 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 104 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 460 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4705 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7019 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2801 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.061340 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000610 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.920959 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 66263541 # 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number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2471910000 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2337830497 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2337830497 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 9410500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2658500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2471910000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 4137245497 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 6621224497 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 9410500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2658500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2471910000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 4137245497 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15460252226 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 22081476723 # number of overall MSHR miss cycles system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 246621000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366568000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613189000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 6366599000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 6613220000 # number of ReadReq MSHR uncacheable cycles system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 246621000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366568000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613189000 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.007982 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6366599000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6613220000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.008254 # mshr miss rate for ReadReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999964 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999964 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.999982 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.999982 # mshr miss rate for UpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155926 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155926 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042142 # mshr miss rate for ReadCleanReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193237 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193237 # mshr miss rate for ReadSharedReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091515 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007371 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.010535 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042142 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180102 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155984 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155984 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.042593 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.193770 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.193770 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.091953 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007514 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.011370 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.042593 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.180467 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.214872 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21102.169982 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 59806.977641 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19406.413660 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19406.413660 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15556.497737 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15556.497737 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 178499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 178499 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42895.951002 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42895.951002 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46654.909194 # average ReadCleanReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24316.828228 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24316.828228 # average ReadSharedReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34566.939827 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22103.155340 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 18177.304965 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46654.909194 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29979.675860 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 59806.977641 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49057.182910 # average overall mshr miss latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.215216 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 21136.602452 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 60094.658138 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19414.471651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19414.471651 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15555.078648 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15555.078648 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 311500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 311500 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 42865.667731 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 42865.667731 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 46298.252514 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 24357.983048 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 24357.983048 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 34500.278749 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 22405.952381 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17605.960265 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 46298.252514 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 29989.601735 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 60094.658138 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49159.199531 # average overall mshr miss latency system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200389.285827 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190176.252372 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 200383.954425 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 190171.675054 # average ReadReq mshr uncacheable latency system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 82124.875125 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105720.064429 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104599.345185 # average overall mshr uncacheable latency -system.cpu0.toL2Bus.snoop_filter.tot_requests 4078191 # Total number of requests made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2059480 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31273 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.snoop_filter.tot_snoops 323545 # Total number of snoops made to the snoop filter. -system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 318913 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 4632 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu0.toL2Bus.trans_dist::ReadReq 114042 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1911688 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 28450 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 28450 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackDirty 711578 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WritebackClean 1481889 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::CleanEvict 203573 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 327784 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 86629 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42593 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 112544 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 26 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 287566 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 284127 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1254351 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576083 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::InvalidateReq 3239 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3768469 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2609794 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29242 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119275 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 6526780 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160567216 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98579420 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53536 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 105717.068230 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 104596.526745 # average overall mshr uncacheable latency +system.cpu0.toL2Bus.snoop_filter.tot_requests 4076758 # Total number of requests made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_requests 2058809 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_requests 31269 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.snoop_filter.tot_snoops 324106 # Total number of snoops made to the snoop filter. +system.cpu0.toL2Bus.snoop_filter.hit_single_snoops 319070 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu0.toL2Bus.snoop_filter.hit_multi_snoops 5036 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu0.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu0.toL2Bus.trans_dist::ReadReq 113929 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1910818 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 28451 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 28451 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackDirty 712670 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WritebackClean 1480466 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 204485 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 327834 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 86644 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 42628 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 112569 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 27 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 287578 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 284142 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1253548 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 576173 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 3244 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3766063 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2610032 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 29029 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 119282 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6524406 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 160464624 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 98586020 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 53124 # Cumulative packet size per connected master and slave (bytes) system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 223588 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 259423760 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 1028398 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3154188 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 0.120549 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.330082 # Request fanout histogram +system.cpu0.toL2Bus.pkt_size::total 259327356 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1029792 # Total snoops (count) +system.cpu0.toL2Bus.snoopTraffic 18816792 # Total snoop traffic (bytes) +system.cpu0.toL2Bus.snoop_fanout::samples 3154811 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 0.120834 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.330795 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::0 2778586 88.09% 88.09% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 370970 11.76% 99.85% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 4632 0.15% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::0 2778640 88.08% 88.08% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 371135 11.76% 99.84% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 5036 0.16% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3154188 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 4077816986 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 3154811 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 4076288994 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 113410626 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 113402059 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1885067918 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1883892360 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1231542700 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1231592300 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15872970 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 15761972 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 63417420 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 63433401 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 4689327 # Number of BP lookups -system.cpu1.branchPred.condPredicted 2779312 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 269179 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 2466051 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 1570212 # Number of BTB hits +system.cpu1.branchPred.lookups 4691512 # Number of BP lookups +system.cpu1.branchPred.condPredicted 2780704 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 269312 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 2468444 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 1570862 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 63.673136 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 878603 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 7046 # Number of incorrect RAS predictions. -system.cpu1.branchPred.indirectLookups 249142 # Number of indirect predictor lookups. -system.cpu1.branchPred.indirectHits 213575 # Number of indirect target hits. -system.cpu1.branchPred.indirectMisses 35567 # Number of indirect misses. -system.cpu1.branchPredindirectMispredicted 10613 # Number of mispredicted indirect branches. -system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu1.branchPred.BTBHitPct 63.637741 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 878870 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 7026 # Number of incorrect RAS predictions. +system.cpu1.branchPred.indirectLookups 249224 # Number of indirect predictor lookups. +system.cpu1.branchPred.indirectHits 213650 # Number of indirect target hits. +system.cpu1.branchPred.indirectMisses 35574 # Number of indirect misses. +system.cpu1.branchPredindirectMispredicted 10610 # Number of mispredicted indirect branches. +system.cpu1.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1658,89 +1657,90 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.dtb.walker.walks 21410 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 21410 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8641 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5914 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6855 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 14555 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 598.110615 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 3237.595624 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 13903 95.52% 95.52% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 193 1.33% 96.85% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 240 1.65% 98.50% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 97 0.67% 99.16% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 26 0.18% 99.34% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 15 0.10% 99.44% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 4 0.03% 99.47% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 64 0.44% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 5 0.03% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::45056-49151 4 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 14555 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5693 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 11275.601616 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 9954.937359 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6246.075100 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-8191 1927 33.85% 33.85% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3145 55.24% 89.09% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::16384-24575 429 7.54% 96.63% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::24576-32767 137 2.41% 99.03% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-40959 17 0.30% 99.33% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::40960-49151 31 0.54% 99.88% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::49152-57343 2 0.04% 99.91% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::98304-106495 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.walker.walks 21486 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 21486 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 8656 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5913 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 6917 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 14569 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 593.417530 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 3219.344489 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 13924 95.57% 95.57% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 194 1.33% 96.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 239 1.64% 98.54% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 88 0.60% 99.15% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 24 0.16% 99.31% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 16 0.11% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 5 0.03% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 66 0.45% 99.91% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 2 0.01% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::36864-40959 7 0.05% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::40960-45055 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 14569 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 11230.789474 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9917.122912 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6183.592938 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 1944 34.11% 34.11% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 3149 55.25% 89.35% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 398 6.98% 96.33% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 155 2.72% 99.05% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 22 0.39% 99.44% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 24 0.42% 99.86% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::49152-57343 5 0.09% 99.95% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::57344-65535 1 0.02% 99.96% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 99.98% # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5693 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 72606451764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.284045 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.454557 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0-1 72584974764 99.97% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2-3 16673000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4-5 2243500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6-7 1638500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8-9 418000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10-11 173000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walkCompletionTime::total 5700 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 72594020264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.245062 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.433850 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0-1 72572506264 99.97% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2-3 16659500 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4-5 2233500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6-7 1798000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8-9 337000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10-11 155000 0.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::12-13 183000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14-15 118000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::16-17 30000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 72606451764 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1957 73.85% 73.85% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 693 26.15% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2650 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21410 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walksPending::14-15 133000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::16-17 15000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 72594020264 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1956 73.89% 73.89% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 691 26.11% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2647 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 21486 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21410 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2650 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 21486 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2647 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2650 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 24060 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2647 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 24133 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 4195760 # DTB read hits -system.cpu1.dtb.read_misses 18440 # DTB read misses -system.cpu1.dtb.write_hits 3493575 # DTB write hits -system.cpu1.dtb.write_misses 2970 # DTB write misses +system.cpu1.dtb.read_hits 4198525 # DTB read hits +system.cpu1.dtb.read_misses 18524 # DTB read misses +system.cpu1.dtb.write_hits 3495808 # DTB write hits +system.cpu1.dtb.write_misses 2962 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1987 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 47 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 392 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 1985 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 48 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 390 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 375 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 4214200 # DTB read accesses -system.cpu1.dtb.write_accesses 3496545 # DTB write accesses +system.cpu1.dtb.read_accesses 4217049 # DTB read accesses +system.cpu1.dtb.write_accesses 3498770 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 7689335 # DTB hits -system.cpu1.dtb.misses 21410 # DTB misses -system.cpu1.dtb.accesses 7710745 # DTB accesses -system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.cpu1.dtb.hits 7694333 # DTB hits +system.cpu1.dtb.misses 21486 # DTB misses +system.cpu1.dtb.accesses 7715819 # DTB accesses +system.cpu1.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1770,58 +1770,62 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.itb.walker.walks 5994 # Table walker walks requested -system.cpu1.itb.walker.walksShort 5994 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2734 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2643 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 617 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 5377 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 333.364330 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 2161.417395 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-4095 5231 97.28% 97.28% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-8191 63 1.17% 98.46% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-12287 36 0.67% 99.13% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-16383 24 0.45% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::16384-20479 7 0.13% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-24575 4 0.07% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-28671 7 0.13% 99.91% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::28672-32767 3 0.06% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::32768-36863 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 5377 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 11592.031425 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 10629.889069 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5561.428024 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-8191 316 17.73% 17.73% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-16383 1349 75.70% 93.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-24575 63 3.54% 96.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-32767 25 1.40% 98.37% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-40959 19 1.07% 99.44% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-49151 3 0.17% 99.61% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::49152-57343 4 0.22% 99.83% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::57344-65535 2 0.11% 99.94% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.06% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1782 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 16752128416 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.862615 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.344368 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 2302152764 13.74% 13.74% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 14449314652 86.25% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 661000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 16752128416 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 990 84.98% 84.98% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 175 15.02% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated +system.cpu1.itb.walker.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.itb.walker.walks 5992 # Table walker walks requested +system.cpu1.itb.walker.walksShort 5992 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 2735 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2646 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 611 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 5381 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 357.461438 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 2249.604382 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-2047 5186 96.38% 96.38% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::2048-4095 43 0.80% 97.18% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-6143 39 0.72% 97.90% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::6144-8191 21 0.39% 98.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-10239 21 0.39% 98.68% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::10240-12287 16 0.30% 98.98% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-14335 17 0.32% 99.29% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::14336-16383 9 0.17% 99.46% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-18431 6 0.11% 99.57% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::18432-20479 2 0.04% 99.61% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-22527 6 0.11% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::22528-24575 3 0.06% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-26623 4 0.07% 99.85% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::26624-28671 4 0.07% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-30719 2 0.04% 99.96% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::30720-32767 2 0.04% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 5381 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1781 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11779.618192 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 10714.112038 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6875.589868 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-16383 1655 92.93% 92.93% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-32767 93 5.22% 98.15% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-49151 29 1.63% 99.78% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::49152-65535 1 0.06% 99.83% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-81919 1 0.06% 99.89% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::131072-147455 2 0.11% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1781 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 16739710416 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.877376 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.328141 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 2053443264 12.27% 12.27% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 14685521152 87.73% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 746000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 16739710416 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.04% 85.04% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 175 14.96% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1170 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5994 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5994 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 5992 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 5992 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7159 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 8253439 # ITB inst hits -system.cpu1.itb.inst_misses 5994 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1170 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1170 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 7162 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 8257878 # ITB inst hits +system.cpu1.itb.inst_misses 5992 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1830,114 +1834,114 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1130 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1134 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 578 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 574 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8259433 # ITB inst accesses -system.cpu1.itb.hits 8253439 # DTB hits -system.cpu1.itb.misses 5994 # DTB misses -system.cpu1.itb.accesses 8259433 # DTB accesses -system.cpu1.numPwrStateTransitions 5525 # Number of power state transitions -system.cpu1.pwrStateClkGateDist::samples 2763 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::mean 1016473602.620702 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::stdev 25821981878.711128 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::underflows 1969 71.26% 71.26% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::1000-5e+10 788 28.52% 99.78% # Distribution of time spent in the clock gated state +system.cpu1.itb.inst_accesses 8263870 # ITB inst accesses +system.cpu1.itb.hits 8257878 # DTB hits +system.cpu1.itb.misses 5992 # DTB misses +system.cpu1.itb.accesses 8263870 # DTB accesses +system.cpu1.numPwrStateTransitions 5517 # Number of power state transitions +system.cpu1.pwrStateClkGateDist::samples 2759 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::mean 1017941071.285973 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::stdev 25840669198.429722 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::underflows 1966 71.26% 71.26% # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::1000-5e+10 787 28.52% 99.78% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+10-1e+11 2 0.07% 99.86% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::1e+11-1.5e+11 1 0.04% 99.89% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::5e+11-5.5e+11 1 0.04% 99.93% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::7.5e+11-8e+11 1 0.04% 99.96% # Distribution of time spent in the clock gated state system.cpu1.pwrStateClkGateDist::9.5e+11-1e+12 1 0.04% 100.00% # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::min_value 1 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::max_value 959984667908 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateClkGateDist::total 2763 # Distribution of time spent in the clock gated state -system.cpu1.pwrStateResidencyTicks::ON 17443167459 # Cumulative time (in ticks) in various power states -system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808516564041 # Cumulative time (in ticks) in various power states -system.cpu1.numCycles 34887121 # number of cpu cycles simulated +system.cpu1.pwrStateClkGateDist::min_value 501 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::max_value 959984595936 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateClkGateDist::total 2759 # Distribution of time spent in the clock gated state +system.cpu1.pwrStateResidencyTicks::ON 17447990322 # Cumulative time (in ticks) in various power states +system.cpu1.pwrStateResidencyTicks::CLK_GATED 2808499415678 # Cumulative time (in ticks) in various power states +system.cpu1.numCycles 34896767 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 8560607 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 24821804 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 4689327 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 2662390 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 24583766 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 780426 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 78816 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 28892 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 168872 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 301988 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 23027 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8252257 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 107887 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2262 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 34136181 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.885084 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.219625 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 8573013 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 24834691 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 4691512 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 2663382 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 24575638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 780918 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 78787 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 29336 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 166978 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 305850 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 23292 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8256698 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 107917 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2264 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 34143353 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.885357 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.219701 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 20248194 59.32% 59.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 4889749 14.32% 73.64% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1671087 4.90% 78.54% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 7327151 21.46% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 20247760 59.30% 59.30% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 4892921 14.33% 73.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1671892 4.90% 78.53% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 7330780 21.47% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 34136181 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.134414 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.711489 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 7136711 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 16890873 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 8747772 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1097057 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 263768 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 709532 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 129045 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 23428697 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1046505 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 263768 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 8558773 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2377328 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11841982 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8401624 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 2692706 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 22261726 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 187544 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 264330 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 36982 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 15461 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1675349 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 22265644 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 103648875 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 25648399 # Number of integer rename lookups +system.cpu1.fetch.rateDist::total 34143353 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.134440 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.711662 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7142387 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 16886237 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 8753269 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1097578 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 263882 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 709919 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 129188 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 23442151 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1047211 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 263882 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8565513 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2371212 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 11834998 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8406528 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 2701220 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 22274891 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 187368 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 265665 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 37047 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 14963 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1683318 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 22278743 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 103710935 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 25664622 # Number of integer rename lookups system.cpu1.rename.fp_rename_lookups 1667 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 19867778 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 2397866 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 407377 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 334219 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 2894111 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 4447920 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 3797613 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 625649 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 631175 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 21446441 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 559995 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 21251983 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 91992 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 2044542 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 4726903 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 43295 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 34136181 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.622565 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.949324 # Number of insts issued each cycle +system.cpu1.rename.CommittedMaps 19882725 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2396018 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 407656 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 334437 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 2896541 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 4450446 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 3799896 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 626454 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 628235 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 21459278 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 560382 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 21266552 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 92050 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2043308 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 4721488 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 43321 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 34143353 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.622861 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.949388 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 21624116 63.35% 63.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6146372 18.01% 81.35% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4248735 12.45% 93.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 1859698 5.45% 99.25% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 257253 0.75% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 21621380 63.33% 63.33% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6152293 18.02% 81.34% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4252408 12.45% 93.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 1859652 5.45% 99.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 257613 0.75% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 7 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -1945,44 +1949,44 @@ system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 34136181 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 34143353 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 1435935 29.89% 29.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 668 0.01% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.90% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1614233 33.60% 63.50% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 1753849 36.50% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1436712 29.87% 29.87% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 667 0.01% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 29.88% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1615148 33.58% 63.46% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 1757949 36.54% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 66 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 13143313 61.85% 61.85% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 28154 0.13% 61.98% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 13152288 61.84% 61.85% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 28200 0.13% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 61.98% # Type of FU issued @@ -2006,99 +2010,99 @@ system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.98% # Ty system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.98% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 3291 0.02% 61.99% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 3301 0.02% 61.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 61.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.99% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 4401591 20.71% 82.70% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 3675568 17.30% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 4404606 20.71% 82.70% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 3678091 17.30% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 21251983 # Type of FU issued -system.cpu1.iq.rate 0.609164 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4804685 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.226082 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 81530573 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 24059081 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 20789563 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 6251 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 2056 # Number of floating instruction queue writes +system.cpu1.iq.FU_type_0::total 21266552 # Type of FU issued +system.cpu1.iq.rate 0.609413 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4810476 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.226199 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 81572724 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 24071099 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 20803651 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 6259 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 2054 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1789 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 26052476 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 4126 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 87608 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 26072828 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 4134 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 87634 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 411817 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 594 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10183 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 255647 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 411414 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 595 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10207 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 255357 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 40342 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 77877 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 40430 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 77958 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 263768 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 542908 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 100291 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 22047493 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 263882 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 544522 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 96828 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 22060743 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 4447920 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 3797613 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 296998 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 7633 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 86238 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10183 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 34861 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 119032 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 153893 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 21020629 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 4306114 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 209967 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 4450446 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 3799896 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 297241 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 7639 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 82763 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10207 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 34804 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 119058 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 153862 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 21034955 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 4309085 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 210133 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 41057 # number of nop insts executed -system.cpu1.iew.exec_refs 7931495 # number of memory reference insts executed -system.cpu1.iew.exec_branches 3060021 # Number of branches executed -system.cpu1.iew.exec_stores 3625381 # Number of stores executed -system.cpu1.iew.exec_rate 0.602533 # Inst execution rate -system.cpu1.iew.wb_sent 20889464 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 20791352 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 10424214 # num instructions producing a value -system.cpu1.iew.wb_consumers 16342751 # num instructions consuming a value -system.cpu1.iew.wb_rate 0.595961 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.637849 # average fanout of values written-back -system.cpu1.commit.commitSquashedInsts 1830942 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 516700 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 142734 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 33726190 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.592855 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.351829 # Number of insts commited each cycle +system.cpu1.iew.exec_nop 41083 # number of nop insts executed +system.cpu1.iew.exec_refs 7936975 # number of memory reference insts executed +system.cpu1.iew.exec_branches 3061868 # Number of branches executed +system.cpu1.iew.exec_stores 3627890 # Number of stores executed +system.cpu1.iew.exec_rate 0.602777 # Inst execution rate +system.cpu1.iew.wb_sent 20903580 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 20805440 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 10431521 # num instructions producing a value +system.cpu1.iew.wb_consumers 16355895 # num instructions consuming a value +system.cpu1.iew.wb_rate 0.596200 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.637784 # average fanout of values written-back +system.cpu1.commit.commitSquashedInsts 1829884 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 517061 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 142735 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 33733433 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.593157 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.351929 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 24181138 71.70% 71.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 5602280 16.61% 88.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1689893 5.01% 93.32% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 666101 1.98% 95.30% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 523339 1.55% 96.85% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 342031 1.01% 97.86% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 220744 0.65% 98.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 118908 0.35% 98.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 381756 1.13% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 24180502 71.68% 71.68% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 5607484 16.62% 88.30% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1690092 5.01% 93.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 667448 1.98% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 524113 1.55% 96.85% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 341983 1.01% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 221163 0.66% 98.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 119335 0.35% 98.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 381313 1.13% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 33726190 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 16334743 # Number of instructions committed -system.cpu1.commit.committedOps 19994748 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 33733433 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 16346571 # Number of instructions committed +system.cpu1.commit.committedOps 20009206 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 7578069 # Number of memory references committed -system.cpu1.commit.loads 4036103 # Number of loads committed -system.cpu1.commit.membars 208295 # Number of memory barriers committed -system.cpu1.commit.branches 2905369 # Number of branches committed +system.cpu1.commit.refs 7583571 # Number of memory references committed +system.cpu1.commit.loads 4039032 # Number of loads committed +system.cpu1.commit.membars 208429 # Number of memory barriers committed +system.cpu1.commit.branches 2907402 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 17763800 # Number of committed integer instructions. -system.cpu1.commit.function_calls 462325 # Number of function calls committed. +system.cpu1.commit.int_insts 17776817 # Number of committed integer instructions. +system.cpu1.commit.function_calls 462681 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 12386323 61.95% 61.95% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 27065 0.14% 62.08% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 12395212 61.95% 61.95% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 27122 0.14% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::IntDiv 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 62.08% # Class of committed instruction @@ -2122,737 +2126,740 @@ system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 62.08% # system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 62.08% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 62.08% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 3291 0.02% 62.10% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 3301 0.02% 62.10% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 62.10% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 62.10% # Class of committed instruction system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 62.10% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 4036103 20.19% 82.29% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 3541966 17.71% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4039032 20.19% 82.29% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 3544539 17.71% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 19994748 # Class of committed instruction -system.cpu1.commit.bw_lim_events 381756 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 54190677 # The number of ROB reads -system.cpu1.rob.rob_writes 44052640 # The number of ROB writes -system.cpu1.timesIdled 55343 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 750940 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5616474700 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 16301888 # Number of Instructions Simulated -system.cpu1.committedOps 19961893 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.140066 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.140066 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.467275 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.467275 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 23580432 # number of integer regfile reads -system.cpu1.int_regfile_writes 13478394 # number of integer regfile writes +system.cpu1.commit.op_class_0::total 20009206 # Class of committed instruction +system.cpu1.commit.bw_lim_events 381313 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 54211090 # The number of ROB reads +system.cpu1.rob.rob_writes 44079362 # The number of ROB writes +system.cpu1.timesIdled 55353 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 753414 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5616440201 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 16313716 # Number of Instructions Simulated +system.cpu1.committedOps 19976351 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.139106 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.139106 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.467485 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.467485 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 23597502 # number of integer regfile reads +system.cpu1.int_regfile_writes 13487852 # number of integer regfile writes system.cpu1.fp_regfile_reads 1401 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 75464831 # number of cc regfile reads -system.cpu1.cc_regfile_writes 6816973 # number of cc regfile writes -system.cpu1.misc_regfile_reads 66091366 # number of misc regfile reads -system.cpu1.misc_regfile_writes 387254 # number of misc regfile writes -system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.tags.replacements 189214 # number of replacements -system.cpu1.dcache.tags.tagsinuse 472.223119 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 6799121 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 189549 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 35.869991 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 103707030000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.223119 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922311 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.922311 # Average percentage of cache occupancy +system.cpu1.cc_regfile_reads 75515975 # number of cc regfile reads +system.cpu1.cc_regfile_writes 6821727 # number of cc regfile writes +system.cpu1.misc_regfile_reads 66067792 # number of misc regfile reads +system.cpu1.misc_regfile_writes 387520 # number of misc regfile writes +system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.tags.replacements 189327 # number of replacements +system.cpu1.dcache.tags.tagsinuse 472.259638 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 6803525 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 189662 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 35.871840 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103705106000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 472.259638 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.922382 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.922382 # Average percentage of cache occupancy system.cpu1.dcache.tags.occ_task_id_blocks::1024 335 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::2 319 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 16 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::2 318 # Occupied blocks per task id +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.dcache.tags.occ_task_id_percent::1024 0.654297 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 15096738 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 15096738 # Number of data accesses -system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.dcache.ReadReq_hits::cpu1.data 3630827 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3630827 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2915447 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2915447 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48893 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 48893 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78128 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 78128 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70537 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 70537 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 6546274 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 6546274 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 6595167 # number of overall hits -system.cpu1.dcache.overall_hits::total 6595167 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 215923 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 215923 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 399880 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 399880 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30250 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 30250 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18610 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 18610 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23458 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23458 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 615803 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 615803 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 646053 # number of overall misses -system.cpu1.dcache.overall_misses::total 646053 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3499498000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3499498000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10163021954 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10163021954 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366635500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 366635500 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 572131000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 572131000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1270000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1270000 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 13662519954 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 13662519954 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 13662519954 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 13662519954 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 3846750 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 3846750 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3315327 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3315327 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79143 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 79143 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96738 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 96738 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 93995 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 93995 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 7162077 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 7162077 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 7241220 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 7241220 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056131 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.056131 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120616 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.120616 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382220 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192375 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249566 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249566 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.085981 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.085981 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089219 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.089219 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16207.157181 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 16207.157181 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25415.179439 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 25415.179439 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19700.994089 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19700.994089 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24389.589905 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24389.589905 # average StoreCondReq miss latency +system.cpu1.dcache.tags.tag_accesses 15106665 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 15106665 # Number of data accesses +system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.dcache.ReadReq_hits::cpu1.data 3632818 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3632818 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2917516 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2917516 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 48925 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 48925 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 78194 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 78194 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 70603 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 70603 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 6550334 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 6550334 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 6599259 # number of overall hits +system.cpu1.dcache.overall_hits::total 6599259 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 216356 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 216356 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 400081 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 400081 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 30281 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 30281 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 18627 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 18627 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23453 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23453 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 616437 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 616437 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 646718 # number of overall misses +system.cpu1.dcache.overall_misses::total 646718 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3492190500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 3492190500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10142172955 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 10142172955 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 366644000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 366644000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 571781000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 571781000 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 1485000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 1485000 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 13634363455 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 13634363455 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 13634363455 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 13634363455 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 3849174 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 3849174 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 3317597 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 3317597 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 79206 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 79206 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 96821 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 96821 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 94056 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 94056 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 7166771 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 7166771 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 7245977 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 7245977 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.056208 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.056208 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.120594 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.120594 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.382307 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.382307 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.192386 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.192386 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.249351 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.249351 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.086013 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.086013 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.089252 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.089252 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 16140.945941 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 16140.945941 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 25350.298952 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 25350.298952 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19683.470231 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19683.470231 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 24379.866115 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 24379.866115 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22186.510871 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 22186.510871 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21147.676667 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 21147.676667 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 397 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1522509 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 39 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 40277 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 10.179487 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 37.800953 # average number of cycles each access was blocked -system.cpu1.dcache.writebacks::writebacks 189214 # number of writebacks -system.cpu1.dcache.writebacks::total 189214 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79118 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 79118 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 308913 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 308913 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13245 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13245 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 388031 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 388031 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 388031 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 388031 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136805 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 136805 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 90967 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 90967 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28906 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 28906 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5365 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5365 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23458 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23458 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 227772 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 227772 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 256678 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 256678 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3078 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3078 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2435 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2435 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5513 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5513 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1918091000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1918091000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2479606465 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2479606465 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 495967500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 495967500 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96498000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96498000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548698000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548698000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1245000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1245000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4397697465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4397697465 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4893664965 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 4893664965 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 441985000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 441985000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 441985000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 441985000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035564 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035564 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027438 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027438 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365238 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365238 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055459 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249566 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249566 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031803 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.031803 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 22118.016042 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 22118.016042 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 21082.393648 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 21082.393648 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 336 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1512378 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 30 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 40281 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 11.200000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 37.545692 # average number of cycles each access was blocked +system.cpu1.dcache.writebacks::writebacks 189327 # number of writebacks +system.cpu1.dcache.writebacks::total 189327 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 79455 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 79455 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 309049 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 309049 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13259 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13259 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 388504 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 388504 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 388504 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 388504 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 136901 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 136901 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 91032 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 91032 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 28913 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 28913 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5368 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5368 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23453 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23453 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 227933 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 227933 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 256846 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 256846 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 3081 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 2438 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 2438 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 5519 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 5519 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1914813500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1914813500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2474458965 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2474458965 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 498834500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 498834500 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 96515500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 96515500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 548354000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 548354000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1459000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1459000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4389272465 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4389272465 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 4888106965 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 4888106965 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 442121000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 442121000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 442121000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 442121000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.035566 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.035566 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027439 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027439 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.365035 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.365035 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.055443 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.055443 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.249351 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.249351 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.031804 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.031804 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.035447 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.035447 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 14020.620591 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 14020.620591 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27258.307573 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27258.307573 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17157.942988 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17157.942988 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17986.579683 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17986.579683 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23390.655640 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23390.655640 # average StoreCondReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13986.848160 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13986.848160 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 27182.298148 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 27182.298148 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 17252.948501 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 17252.948501 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17979.787630 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17979.787630 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 23380.974715 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 23380.974715 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19307.454231 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19307.454231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19065.385288 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19065.385288 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143594.866797 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143594.866797 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80171.413024 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80171.413024 # average overall mshr uncacheable latency -system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.tags.replacements 585593 # number of replacements -system.cpu1.icache.tags.tagsinuse 499.448296 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7643805 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 586105 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 13.041699 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 79061349000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448296 # Average occupied blocks per requestor +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 19256.853834 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 19256.853834 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 19031.275414 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 19031.275414 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 143499.188575 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 143499.188575 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 80108.896539 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 80108.896539 # average overall mshr uncacheable latency +system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.tags.replacements 586343 # number of replacements +system.cpu1.icache.tags.tagsinuse 499.448153 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 7647462 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 586855 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 13.031263 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 79062638500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 499.448153 # Average occupied blocks per requestor system.cpu1.icache.tags.occ_percent::cpu1.inst 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_percent::total 0.975485 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 17090093 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 17090093 # Number of data accesses -system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.icache.ReadReq_hits::cpu1.inst 7643805 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7643805 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7643805 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7643805 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7643805 # number of overall hits -system.cpu1.icache.overall_hits::total 7643805 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 608184 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 608184 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 608184 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 608184 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 608184 # number of overall misses -system.cpu1.icache.overall_misses::total 608184 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5475305711 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 5475305711 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 5475305711 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 5475305711 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 5475305711 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 5475305711 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8251989 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8251989 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8251989 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8251989 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8251989 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8251989 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073702 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073702 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073702 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073702 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073702 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073702 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9002.712520 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9002.712520 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9002.712520 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9002.712520 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9002.712520 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 487413 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 41153 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.843924 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.writebacks::writebacks 585593 # number of writebacks -system.cpu1.icache.writebacks::total 585593 # number of writebacks -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22069 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 22069 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 22069 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 22069 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 22069 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 22069 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586115 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 586115 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 586115 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 586115 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 586115 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 586115 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5018314097 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5018314097 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5018314097 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5018314097 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5018314097 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5018314097 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9229000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9229000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9229000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 9229000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071027 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071027 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071027 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071027 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8561.995678 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8561.995678 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8561.995678 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90480.392157 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90480.392157 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90480.392157 # average overall mshr uncacheable latency -system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.prefetcher.num_hwpf_issued 204984 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 205710 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 651 # number of redundant prefetches already in prefetch queue +system.cpu1.icache.tags.tag_accesses 17099739 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 17099739 # Number of data accesses +system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.icache.ReadReq_hits::cpu1.inst 7647462 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7647462 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7647462 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7647462 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7647462 # number of overall hits +system.cpu1.icache.overall_hits::total 7647462 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 608974 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 608974 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 608974 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 608974 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 608974 # number of overall misses +system.cpu1.icache.overall_misses::total 608974 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 5478938231 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 5478938231 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 5478938231 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 5478938231 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 5478938231 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 5478938231 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8256436 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8256436 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8256436 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8256436 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8256436 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8256436 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073757 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.073757 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073757 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.073757 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073757 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.073757 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 8996.998609 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 8996.998609 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 8996.998609 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 8996.998609 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 8996.998609 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 488402 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 32 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 41185 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.858735 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 32 # average number of cycles each access was blocked +system.cpu1.icache.writebacks::writebacks 586343 # number of writebacks +system.cpu1.icache.writebacks::total 586343 # number of writebacks +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 22107 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 22107 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 22107 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 22107 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 22107 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 22107 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 586867 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 586867 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 586867 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 586867 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 586867 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 586867 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 101 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 101 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 101 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 101 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5026245111 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5026245111 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5026245111 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5026245111 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5026245111 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5026245111 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 9125500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 9125500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 9125500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 9125500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071080 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071080 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071080 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071080 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8564.538662 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8564.538662 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8564.538662 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 90351.485149 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 90351.485149 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 90351.485149 # average overall mshr uncacheable latency +system.cpu1.l2cache.prefetcher.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.prefetcher.num_hwpf_issued 204963 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 205672 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 636 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 59802 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.tags.replacements 51951 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15270.218898 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 1330892 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 66549 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 19.998678 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 59720 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.tags.replacements 51812 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15242.895875 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1332238 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 66423 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.056878 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 14780.960176 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.872611 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.970486 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 470.415625 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.902158 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000969 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000181 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.028712 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.932020 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1023 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 34 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13541 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 870 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 142 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_blocks::writebacks 14783.108783 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 9.856539 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.176183 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 447.754371 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.902289 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000602 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000133 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.027329 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.930353 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 977 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 32 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13602 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 14 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 835 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 128 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 11 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 13 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 10 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 448 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 439 # Occupied blocks per task id system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8705 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4388 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.062439 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002075 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.826477 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 26699823 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 26699823 # Number of data accesses -system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16755 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6229 # 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number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 6229 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 570057 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 128890 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 721931 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 16755 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 6229 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 570057 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 128890 # number of overall hits -system.cpu1.l2cache.overall_hits::total 721931 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 448 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 243 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 691 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29892 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29892 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 23453 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 23453 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.SCUpgradeFailReq_misses::total 5 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 34596 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 34596 # number of ReadExReq misses -system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 16047 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadCleanReq_misses::total 16047 # number of ReadCleanReq misses -system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 69320 # number of ReadSharedReq misses -system.cpu1.l2cache.ReadSharedReq_misses::total 69320 # number of ReadSharedReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 448 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 243 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 16047 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 103916 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 120654 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 448 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 243 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 16047 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 103916 # number of overall misses -system.cpu1.l2cache.overall_misses::total 120654 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9860500 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5063000 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 14923500 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 63584500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 63584500 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 34923000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 34923000 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 1206498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 1206498 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1459821998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1459821998 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 658205000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadCleanReq_miss_latency::total 658205000 # number of ReadCleanReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1571289999 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1571289999 # number of ReadSharedReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9860500 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5063000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 658205000 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3031111997 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 3704240497 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9860500 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5063000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 658205000 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3031111997 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 3704240497 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 17203 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4458 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.059631 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001953 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.830200 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 26728427 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 26728427 # Number of data accesses +system.cpu1.l2cache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 16758 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 6223 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 22981 # number of ReadReq hits +system.cpu1.l2cache.WritebackDirty_hits::writebacks 115160 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackDirty_hits::total 115160 # number of WritebackDirty hits +system.cpu1.l2cache.WritebackClean_hits::writebacks 648098 # number of WritebackClean hits +system.cpu1.l2cache.WritebackClean_hits::total 648098 # number of WritebackClean hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 27344 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 27344 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 570840 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 570840 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 101859 # 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mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.027283 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.404520 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.404520 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.142055 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.026320 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.038473 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.027283 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.442648 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174709 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15596.960926 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 44891.286612 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16708.902047 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16708.902047 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15884.215239 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15884.215239 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 211299.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 211299.600000 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34828.542457 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34828.542457 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35023.437013 # average ReadCleanReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16661.301721 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16661.301721 # average ReadSharedReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24260.714307 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16010.044643 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14835.390947 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35023.437013 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22646.680020 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 44891.286612 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28073.264587 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135579.272255 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133892.138365 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82980.392157 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75696.172683 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75828.495102 # average overall mshr uncacheable latency -system.cpu1.toL2Bus.snoop_filter.tot_requests 1657712 # Total number of requests made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_requests 838800 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12415 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.snoop_filter.tot_snoops 183176 # Total number of snoops made to the snoop filter. -system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180762 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2414 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.cpu1.toL2Bus.trans_dist::ReadReq 31669 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 826741 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 2435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 2435 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackDirty 153550 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WritebackClean 659699 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::CleanEvict 108887 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 33537 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 71200 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41639 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 86222 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 68548 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 66385 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586115 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadSharedReq 251518 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::InvalidateReq 256 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1758016 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 847991 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14492 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37672 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2658171 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 74990240 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29751886 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174524 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15688.746439 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 45067.816403 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16719.386733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16719.386733 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15872.713317 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15872.713317 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 1264000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 1264000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34904.520758 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34904.520758 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 35242.114796 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 16647.638634 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 16647.638634 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24286.916090 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15886.313466 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 15329.317269 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 35242.114796 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 22644.259296 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 45067.816403 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 28152.992215 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 135484.582928 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 133813.953488 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 82851.485149 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 75634.716434 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 75764.412811 # average overall mshr uncacheable latency +system.cpu1.toL2Bus.snoop_filter.tot_requests 1659506 # Total number of requests made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_requests 839728 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_requests 12423 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.snoop_filter.tot_snoops 183739 # Total number of snoops made to the snoop filter. +system.cpu1.toL2Bus.snoop_filter.hit_single_snoops 180899 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.cpu1.toL2Bus.snoop_filter.hit_multi_snoops 2840 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.cpu1.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.cpu1.toL2Bus.trans_dist::ReadReq 31691 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 827645 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 2438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 2438 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackDirty 153507 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WritebackClean 660509 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 108712 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 33822 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 71296 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 41636 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 86274 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 10 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 68587 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 66399 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 586867 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 252106 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 259 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1760267 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 848480 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 14499 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 37693 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 2660939 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 75086288 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29768550 # Cumulative packet size per connected master and slave (bytes) system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 25888 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68812 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 104836826 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 408149 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1234265 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 0.169046 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.379975 # Request fanout histogram +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 68844 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 104949570 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 408766 # Total snoops (count) +system.cpu1.toL2Bus.snoopTraffic 5198376 # Total snoop traffic (bytes) +system.cpu1.toL2Bus.snoop_fanout::samples 1235773 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 0.169662 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.381410 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::0 1028032 83.29% 83.29% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 203819 16.51% 99.80% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 2414 0.20% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::0 1028949 83.26% 83.26% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 203984 16.51% 99.77% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 2840 0.23% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1234265 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 1616622989 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 1235773 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1618384496 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 80296887 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 80334899 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 879411723 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 880530739 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 381445015 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 381648033 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 8027984 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 8035982 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 20485966 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 20499963 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.iobus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.iobus.trans_dist::ReadReq 31012 # Transaction distribution system.iobus.trans_dist::ReadResp 31012 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution @@ -2903,31 +2910,31 @@ system.iobus.pkt_size_system.bridge.master::total 162794 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2484042 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 40382501 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 40384000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 112500 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 112000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 327500 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 328500 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer3.occupancy 31000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 15500 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 91500 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 89500 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer8.occupancy 582000 # Layer occupancy (ticks) +system.iobus.reqLayer8.occupancy 582500 # Layer occupancy (ticks) system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer10.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer10.occupancy 22500 # Layer occupancy (ticks) system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer13.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer14.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer14.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer15.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer16.occupancy 51500 # Layer occupancy (ticks) system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer17.occupancy 11500 # Layer occupancy (ticks) +system.iobus.reqLayer17.occupancy 12000 # Layer occupancy (ticks) system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer18.occupancy 10000 # Layer occupancy (ticks) system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%) @@ -2937,32 +2944,32 @@ system.iobus.reqLayer20.occupancy 9000 # La system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer21.occupancy 11500 # Layer occupancy (ticks) system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 6099000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 6095500 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 33797500 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 33840000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 187673606 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 187690100 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84717000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.iocache.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.555465 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.555462 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 255128019000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.555465 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.909717 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.909717 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 255127474000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.555462 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.909716 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.909716 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id system.iocache.tags.tag_accesses 328284 # Number of tag accesses system.iocache.tags.data_accesses 328284 # Number of data accesses -system.iocache.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.iocache.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses @@ -2971,14 +2978,14 @@ system.iocache.demand_misses::realview.ide 36476 # system.iocache.demand_misses::total 36476 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 36476 # number of overall misses system.iocache.overall_misses::total 36476 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32586377 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32586377 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 4303595229 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 4303595229 # number of WriteLineReq miss cycles -system.iocache.demand_miss_latency::realview.ide 4336181606 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 4336181606 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 4336181606 # number of overall miss cycles -system.iocache.overall_miss_latency::total 4336181606 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32581877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32581877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4303830223 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4303830223 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 4336412100 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 4336412100 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 4336412100 # number of overall miss cycles +system.iocache.overall_miss_latency::total 4336412100 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) @@ -2995,19 +3002,19 @@ system.iocache.demand_miss_rate::realview.ide 1 system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 129311.019841 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 129311.019841 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118805.080306 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 118805.080306 # average WriteLineReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 118877.662189 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 118877.662189 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 118877.662189 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 15 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 129293.162698 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 129293.162698 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118811.567552 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118811.567552 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 118883.981248 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 118883.981248 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 118883.981248 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 32 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 5 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 6 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 3 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 5.333333 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.writebacks::writebacks 36206 # number of writebacks system.iocache.writebacks::total 36206 # number of writebacks @@ -3019,14 +3026,14 @@ system.iocache.demand_mshr_misses::realview.ide 36476 system.iocache.demand_mshr_misses::total 36476 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 36476 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 36476 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19986377 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19986377 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490041664 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 2490041664 # number of WriteLineReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 2510028041 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 2510028041 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 2510028041 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 2510028041 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19981877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19981877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2490259225 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2490259225 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 2510241102 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 2510241102 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 2510241102 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 2510241102 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses @@ -3035,617 +3042,620 @@ system.iocache.demand_mshr_miss_rate::realview.ide 1 system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79311.019841 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 79311.019841 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68740.107774 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68740.107774 # average WriteLineReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 68813.138529 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 68813.138529 # average overall mshr miss latency -system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.l2c.tags.replacements 132778 # number of replacements -system.l2c.tags.tagsinuse 63203.828730 # Cycle average of tags in use -system.l2c.tags.total_refs 444088 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 196669 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 2.258048 # Average number of references to valid blocks. +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 79293.162698 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 79293.162698 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68746.113764 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68746.113764 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 68818.979658 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 68818.979658 # average overall mshr miss latency +system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.l2c.tags.replacements 132786 # number of replacements +system.l2c.tags.tagsinuse 63192.932289 # Cycle average of tags in use +system.l2c.tags.total_refs 445408 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 196622 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.265301 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 13685.490361 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.358726 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 1.065836 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 8064.380543 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2772.729395 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33768.581689 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 5.679196 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910017 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 1783.108864 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 674.072360 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2431.451744 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.208824 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000250 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::writebacks 13716.070006 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 16.287927 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 1.059977 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 8086.686479 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2783.200527 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 33654.604995 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 4.598228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.910717 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 1777.688460 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 638.769137 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 2513.055836 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.209291 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000249 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000016 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.123053 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.042308 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.515268 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000087 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.123393 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.042468 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.513529 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000070 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.027208 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010286 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.037101 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.964414 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 29279 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 30 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 34582 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 180 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 5628 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 23471 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::3 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 579 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6711 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27249 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.446762 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000458 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.527679 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 6131058 # Number of tag accesses -system.l2c.tags.data_accesses 6131058 # Number of data accesses -system.l2c.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.l2c.WritebackDirty_hits::writebacks 266860 # number of WritebackDirty hits -system.l2c.WritebackDirty_hits::total 266860 # number of WritebackDirty hits -system.l2c.UpgradeReq_hits::cpu0.data 32430 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 2686 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 35116 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 2009 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 933 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2942 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 4036 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 1379 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 5415 # number of ReadExReq hits -system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 163 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.itb.walker 75 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.inst 33190 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.data 46982 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 46066 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 73 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.itb.walker 29 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.inst 13227 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.data 9835 # number of ReadSharedReq hits -system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 5456 # 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number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 75 # number of overall hits -system.l2c.overall_hits::cpu0.inst 33190 # number of overall hits -system.l2c.overall_hits::cpu0.data 51018 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 46066 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 73 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 29 # number of overall hits -system.l2c.overall_hits::cpu1.inst 13227 # number of overall hits -system.l2c.overall_hits::cpu1.data 11214 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 5456 # number of overall hits -system.l2c.overall_hits::total 160511 # number of overall hits -system.l2c.UpgradeReq_misses::cpu0.data 8984 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 2771 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 11755 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 655 # 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average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 96534.502071 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 86259.259259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 89788.461538 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 70333.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73130.683806 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87544.578804 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99385.423509 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 83142.857143 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 87500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76142.145707 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 74736.952074 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 125196.569465 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 94934.807877 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72881.160118 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 87727.616996 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 99848.908954 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 80833.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 83500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 76729.510335 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75619.911850 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124673.871401 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95312.867617 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182388.624878 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117695.609756 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167473.228663 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 182383.088883 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 117600.389864 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 167459.688043 # average ReadReq mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 64124.708625 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96223.393849 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64970.588235 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65683.121597 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 92332.159059 # average overall mshr uncacheable latency -system.membus.snoop_filter.tot_requests 523609 # Total number of requests made to the snoop filter. -system.membus.snoop_filter.hit_single_requests 298426 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 96220.306195 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 64841.584158 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 65622.552574 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 92322.603605 # average overall mshr uncacheable latency +system.membus.snoop_filter.tot_requests 523570 # Total number of requests made to the snoop filter. +system.membus.snoop_filter.hit_single_requests 298445 # Number of requests hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_requests 572 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.membus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.membus.trans_dist::ReadReq 37951 # Transaction distribution -system.membus.trans_dist::ReadResp 212466 # Transaction distribution -system.membus.trans_dist::WriteReq 30885 # Transaction distribution -system.membus.trans_dist::WriteResp 30885 # Transaction distribution -system.membus.trans_dist::WritebackDirty 139949 # Transaction distribution -system.membus.trans_dist::CleanEvict 17155 # Transaction distribution -system.membus.trans_dist::UpgradeReq 74789 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 40592 # Transaction distribution +system.membus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.membus.trans_dist::ReadReq 37954 # Transaction distribution +system.membus.trans_dist::ReadResp 212485 # Transaction distribution +system.membus.trans_dist::WriteReq 30889 # Transaction distribution +system.membus.trans_dist::WriteResp 30889 # Transaction distribution +system.membus.trans_dist::WritebackDirty 140037 # Transaction distribution +system.membus.trans_dist::CleanEvict 17084 # Transaction distribution +system.membus.trans_dist::UpgradeReq 74884 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 40573 # Transaction distribution system.membus.trans_dist::UpgradeResp 2 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 3 # Transaction distribution -system.membus.trans_dist::ReadExReq 40333 # Transaction distribution -system.membus.trans_dist::ReadExResp 20490 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 174516 # Transaction distribution +system.membus.trans_dist::ReadExReq 40212 # Transaction distribution +system.membus.trans_dist::ReadExResp 20363 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174532 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107914 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 36 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13608 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661161 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 782719 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 13624 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 661033 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 782607 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72949 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 72949 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 855668 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 855556 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162794 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 288 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27216 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19151816 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 19342114 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 27248 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19150328 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19340658 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 21660258 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 122014 # Total snoops (count) -system.membus.snoop_fanout::samples 435296 # Request fanout histogram -system.membus.snoop_fanout::mean 0.011884 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.108364 # Request fanout histogram +system.membus.pkt_size::total 21658802 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 122046 # Total snoops (count) +system.membus.snoopTraffic 36480 # Total snoop traffic (bytes) +system.membus.snoop_fanout::samples 435271 # Request fanout histogram +system.membus.snoop_fanout::mean 0.011878 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.108336 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 430123 98.81% 98.81% # Request fanout histogram -system.membus.snoop_fanout::1 5173 1.19% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 430101 98.81% 98.81% # Request fanout histogram +system.membus.snoop_fanout::1 5170 1.19% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 435296 # Request fanout histogram -system.membus.reqLayer0.occupancy 81593499 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 435271 # Request fanout histogram +system.membus.reqLayer0.occupancy 81633500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) system.membus.reqLayer1.occupancy 24500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 11516500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11523000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1022226685 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1022470046 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1121401156 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1120816043 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 1360881 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 1359381 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) -system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.membus.badaddr_responder.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.aaci_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.pci_host.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.cf_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.gic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.clcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.realview_io.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.dcc.osc_cpu.clock 16667 # Clock period in ticks system.realview.dcc.osc_ddr.clock 25000 # Clock period in ticks system.realview.dcc.osc_hsbm.clock 25000 # Clock period in ticks system.realview.dcc.osc_pxl.clock 42105 # Clock period in ticks system.realview.dcc.osc_smb.clock 20000 # Clock period in ticks system.realview.dcc.osc_sys.clock 16667 # Clock period in ticks -system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.energy_ctrl.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.ethernet.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA @@ -3677,80 +3687,81 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states +system.realview.hdlcd.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.ide.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.kmi0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.kmi1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.l2x0_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.lan_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.local_cpu_timer.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states system.realview.mcc.osc_clcd.clock 42105 # Clock period in ticks system.realview.mcc.osc_mcc.clock 20000 # Clock period in ticks system.realview.mcc.osc_peripheral.clock 41667 # Clock period in ticks system.realview.mcc.osc_system_bus.clock 41667 # Clock period in ticks -system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.toL2Bus.snoop_filter.tot_requests 1012829 # Total number of requests made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_requests 548493 # Number of requests hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_requests 154614 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.snoop_filter.tot_snoops 20965 # Total number of snoops made to the snoop filter. -system.toL2Bus.snoop_filter.hit_single_snoops 19995 # Number of snoops hitting in the snoop filter with a single holder of the requested data. -system.toL2Bus.snoop_filter.hit_multi_snoops 970 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. -system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825959731500 # Cumulative time (in ticks) in various power states -system.toL2Bus.trans_dist::ReadReq 37954 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 485832 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 30885 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 30885 # Transaction distribution -system.toL2Bus.trans_dist::WritebackDirty 370603 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 122893 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 109820 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 43534 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 153354 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 32 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 32 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 51065 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 51065 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 447881 # Transaction distribution -system.toL2Bus.trans_dist::InvalidateReq 4599 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1241884 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315944 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1557828 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34423168 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674082 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 40097250 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 382843 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 858573 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 0.374933 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.486434 # Request fanout histogram +system.realview.mmc_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.rtc.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.sp810_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.timer0.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.timer1.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart1_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart2_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.uart3_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.usb_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.vgic.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.realview.watchdog_fake.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.toL2Bus.snoop_filter.tot_requests 1014149 # Total number of requests made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_requests 548985 # Number of requests hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_requests 155175 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.snoop_filter.tot_snoops 21000 # Total number of snoops made to the snoop filter. +system.toL2Bus.snoop_filter.hit_single_snoops 20112 # Number of snoops hitting in the snoop filter with a single holder of the requested data. +system.toL2Bus.snoop_filter.hit_multi_snoops 888 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. +system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 2825947406000 # Cumulative time (in ticks) in various power states +system.toL2Bus.trans_dist::ReadReq 37957 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 486750 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 30889 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 30889 # Transaction distribution +system.toL2Bus.trans_dist::WritebackDirty 371053 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 122899 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 109975 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 43571 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 153546 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 35 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 35 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50842 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50842 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 448796 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 4596 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1244094 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 315957 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1560051 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 34491784 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 5674154 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 40165938 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 382861 # Total snoops (count) +system.toL2Bus.snoopTraffic 15835212 # Total snoop traffic (bytes) +system.toL2Bus.snoop_fanout::samples 859470 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 0.375184 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.486300 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::0 537636 62.62% 62.62% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 319967 37.27% 99.89% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 970 0.11% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::0 537899 62.58% 62.58% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 320683 37.31% 99.90% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 888 0.10% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 858573 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 885446562 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 859470 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 886309294 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 356119 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 647873032 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 648979933 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 232753441 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 232794950 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 1828 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 1839 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2763 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2759 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |