diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
| commit | 08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch) | |
| tree | d3588f01b572538601360998b89e23607549934c /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff) | |
| download | gem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz | |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 2976 |
1 files changed, 1490 insertions, 1486 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 5e12f3369..ee857cd58 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,152 +1,152 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102940 # Number of seconds simulated -sim_ticks 1102940172000 # Number of ticks simulated -final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102937 # Number of seconds simulated +sim_ticks 1102936899000 # Number of ticks simulated +final_tick 1102936899000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 65652 # Simulator instruction rate (inst/s) -host_op_rate 84510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1175755462 # Simulator tick rate (ticks/s) -host_mem_usage 411412 # Number of bytes of host memory used -host_seconds 938.07 # Real time elapsed on the host -sim_insts 61586245 # Number of instructions simulated -sim_ops 79276446 # Number of ops (including micro ops) simulated +host_inst_rate 56405 # Simulator instruction rate (inst/s) +host_op_rate 72609 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010130266 # Simulator tick rate (ticks/s) +host_mem_usage 440004 # Number of bytes of host memory used +host_seconds 1091.88 # Real time elapsed on the host +sim_insts 61587196 # Number of instructions simulated +sim_ops 79280303 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 408960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4359540 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory -system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 406528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5228208 # Number of bytes read from this memory +system.physmem.bytes_read::total 59164324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 406528 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4242368 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory +system.physmem.bytes_written::total 7269712 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6390 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68190 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6352 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81717 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257533 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66287 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823123 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370792 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952665 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368587 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4740260 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53642528 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370792 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368587 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739379 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846429 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729389 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6591231 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846429 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370792 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968078 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257967 # Total number of read requests seen -system.physmem.writeReqs 823548 # Total number of write requests seen -system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400509888 # Total number of bytes read from memory -system.physmem.bytesWritten 52707072 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis +system.physmem.bw_total::cpu1.inst 368587 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7469649 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60233760 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257533 # Total number of read requests seen +system.physmem.writeReqs 823123 # Total number of write requests seen +system.physmem.cpureqs 241438 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400482112 # Total number of bytes read from memory +system.physmem.bytesWritten 52679872 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59164324 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7269712 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12571 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391437 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391240 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390831 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391498 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390850 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390980 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391704 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390658 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390771 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391161 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391176 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390450 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 390424 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391246 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51442 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51251 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51666 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50946 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51023 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51720 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52026 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51302 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51417 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51807 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51192 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51138 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51881 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102939019000 # Total gap between requests +system.physmem.numWrRetry 32625 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102935703000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163014 # Categorize read packet sizes +system.physmem.readPktSize::6 162580 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66712 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66287 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 494185 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430784 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 392337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441558 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1085468 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1097761 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1063978 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26861 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44400 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63675 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12096 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11871 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 15313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 7884 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -160,59 +160,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32734 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32711 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see -system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests -system.physmem.totBusLat 31289230000 # Total cycles spent in databus access -system.physmem.totBankLat 8532328750 # Total cycles spent in bank access -system.physmem.avgQLat 31830.77 # Average queueing delay per request -system.physmem.avgBankLat 1363.46 # Average bank access latency per request +system.physmem.wrQLenPdf::0 2876 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2946 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2993 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3052 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3101 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3124 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35788 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32912 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32842 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32754 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32715 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32687 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32664 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32641 # What write queue length does an incoming req see +system.physmem.totQLat 199281441500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239111429000 # Sum of mem lat for all requests +system.physmem.totBusLat 31287030000 # Total cycles spent in databus access +system.physmem.totBankLat 8542957500 # Total cycles spent in bank access +system.physmem.avgQLat 31847.29 # Average queueing delay per request +system.physmem.avgBankLat 1365.26 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38194.23 # Average memory access latency -system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.62 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 38212.55 # Average memory access latency +system.physmem.avgRdBW 363.11 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.76 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.64 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.59 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 12.05 # Average write queue length over time -system.physmem.readRowHits 6213954 # Number of row buffer hits during reads -system.physmem.writeRowHits 800040 # Number of row buffer hits during writes +system.physmem.avgWrQLen 11.59 # Average write queue length over time +system.physmem.readRowHits 6213376 # Number of row buffer hits during reads +system.physmem.writeRowHits 799550 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155749.02 # Average gap between requests +system.physmem.writeRowHitRate 97.14 # Row buffer hit rate for writes +system.physmem.avgGap 155767.45 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -231,251 +231,251 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72718 # number of replacements -system.l2c.tagsinuse 53743.140165 # Cycle average of tags in use -system.l2c.total_refs 1840331 # Total number of references to valid blocks. -system.l2c.sampled_refs 137862 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.349081 # Average number of references to valid blocks. +system.l2c.replacements 72282 # number of replacements +system.l2c.tagsinuse 53744.299693 # Cycle average of tags in use +system.l2c.total_refs 1841477 # Total number of references to valid blocks. +system.l2c.sampled_refs 137500 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.392560 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.587396 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.826422 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.187080 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.736100 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2822.118244 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.062372 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.921462 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3716.187342 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3805.513745 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600793 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061168 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043062 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000169 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39371.893894 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 5.466670 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.665850 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4003.284493 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2820.568488 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.108443 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.919823 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3725.007986 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3804.384047 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600767 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000083 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000025 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061085 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.043038 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000170 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056705 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058068 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820055 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22141 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4502 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386239 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166660 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30329 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5168 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197820 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403245 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580806 # number of Writeback hits -system.l2c.Writeback_hits::total 580806 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1235 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1978 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 145 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 346 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48231 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58599 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106830 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22141 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4502 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386239 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214891 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30329 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5168 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590386 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256419 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510075 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22141 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4502 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386239 # number of overall hits -system.l2c.overall_hits::cpu0.data 214891 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30329 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5168 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590386 # number of overall hits -system.l2c.overall_hits::cpu1.data 256419 # number of overall hits -system.l2c.overall_hits::total 1510075 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6277 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6416 # number of ReadReq misses +system.l2c.occ_percent::cpu1.inst 0.056839 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.058050 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820073 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22824 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4741 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386299 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 167150 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30426 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5232 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589817 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 197825 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1404314 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581284 # number of Writeback hits +system.l2c.Writeback_hits::total 581284 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1196 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 780 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1976 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 199 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 146 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 345 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48442 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58735 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107177 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 22824 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4741 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386299 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 215592 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30426 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5232 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 589817 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256560 # number of demand (read+write) hits +system.l2c.demand_hits::total 1511491 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22824 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4741 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386299 # number of overall hits +system.l2c.overall_hits::cpu0.data 215592 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30426 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5232 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589817 # number of overall hits +system.l2c.overall_hits::cpu1.data 256560 # number of overall hits +system.l2c.overall_hits::total 1511491 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 14 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6269 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6424 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 17 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6302 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6301 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25330 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5125 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3774 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8899 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 638 # number of SCUpgradeReq misses +system.l2c.ReadReq_misses::cpu1.inst 6316 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6288 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25333 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5101 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8883 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 646 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 411 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1049 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63279 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76923 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140202 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6277 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69695 # number of demand (read+write) misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63146 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76636 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 139782 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 14 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 4 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6269 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69570 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 17 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6302 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83224 # number of demand (read+write) misses -system.l2c.demand_misses::total 165532 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6277 # number of overall misses -system.l2c.overall_misses::cpu0.data 69695 # number of overall misses +system.l2c.demand_misses::cpu1.inst 6316 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 82924 # number of demand (read+write) misses +system.l2c.demand_misses::total 165115 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 14 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 4 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6269 # number of overall misses +system.l2c.overall_misses::cpu0.data 69570 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 17 # number of overall misses system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6302 # number of overall misses -system.l2c.overall_misses::cpu1.data 83224 # number of overall misses -system.l2c.overall_misses::total 165532 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 728500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 324500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 347861000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 370402499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1384000 # number of ReadReq miss cycles +system.l2c.overall_misses::cpu1.inst 6316 # number of overall misses +system.l2c.overall_misses::cpu1.data 82924 # number of overall misses +system.l2c.overall_misses::total 165115 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 933000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 255500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 347054000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 368774499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1319000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.itb.walker 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 379078500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 392453000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1492300499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 8816984 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 11833500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 20650484 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 568000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2844000 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 3412000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3138283486 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4133582496 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7271865982 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 728500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 324500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 347861000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3508685985 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1384000 # number of demand (read+write) miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 385195500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 391956499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1495556498 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 8608988 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 11814499 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 20423487 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 591500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 2846500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 3438000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3130357988 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4120844492 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7251202480 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 933000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 255500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 347054000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3499132487 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 1319000 # number of demand (read+write) miss cycles system.l2c.demand_miss_latency::cpu1.itb.walker 68500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 379078500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4526035496 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8764166481 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 728500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 324500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 347861000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3508685985 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1384000 # number of overall miss cycles +system.l2c.demand_miss_latency::cpu1.inst 385195500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4512800991 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8746758978 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 933000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 255500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 347054000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3499132487 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 1319000 # number of overall miss cycles system.l2c.overall_miss_latency::cpu1.itb.walker 68500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 379078500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4526035496 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8764166481 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 22152 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 4507 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 392516 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 173076 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 30346 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 5169 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 596688 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 204121 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1428575 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 580806 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 580806 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6360 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4517 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 10877 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 839 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 556 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1395 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111510 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135522 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247032 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 22152 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 4507 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 392516 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 284586 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 30346 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 5169 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 596688 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 339643 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1675607 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 22152 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 4507 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 392516 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 284586 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 30346 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 5169 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 596688 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 339643 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1675607 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001109 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015992 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.037070 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000193 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010562 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030869 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.017731 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.805818 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.835510 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.818148 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.760429 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.739209 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.751971 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567474 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.567605 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.567546 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.001109 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015992 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244900 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000193 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010562 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.245034 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.098789 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000497 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.001109 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015992 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244900 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000560 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000193 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010562 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.245034 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.098789 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 64900 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55418.352716 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 57731.062812 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average ReadReq miss latency +system.l2c.overall_miss_latency::cpu1.inst 385195500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4512800991 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8746758978 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 22838 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 4745 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 392568 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 173574 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 30443 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5233 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 596133 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204113 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1429647 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581284 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581284 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6297 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4562 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10859 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 845 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 557 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1402 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111588 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135371 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246959 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 22838 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 4745 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 392568 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 285162 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 30443 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5233 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 596133 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339484 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1676606 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 22838 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 4745 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 392568 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 285162 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 30443 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5233 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 596133 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339484 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1676606 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000843 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015969 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.037010 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000191 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010595 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030806 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017720 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.810068 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.829022 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.818031 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.764497 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.737882 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.753923 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.565885 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.566118 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.566013 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000843 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015969 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.243967 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.000191 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010595 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244265 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098482 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000613 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000843 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015969 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.243967 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000558 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.000191 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010595 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244265 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098482 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 63875 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 55360.344553 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 57405.743929 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60152.094573 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 62284.240597 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 58914.350533 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1720.387122 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3135.532591 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 2320.539836 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 890.282132 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6919.708029 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.621544 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49594.391283 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53736.626185 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 51867.063109 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 60987.254592 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 62334.048823 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59035.901709 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 1687.705940 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 3123.875992 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 2299.165485 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 915.634675 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 6925.790754 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 3252.601703 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 49573.337789 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53771.654210 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 51875.080339 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency system.l2c.demand_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52945.451520 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66227.272727 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 64900 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 55418.352716 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 50343.439056 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 81411.764706 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52973.739382 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 66642.857143 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 63875 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 55360.344553 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 50296.571611 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 77588.235294 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.itb.walker 68500 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 60152.094573 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 54383.777468 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52945.451520 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 60987.254592 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 54420.927488 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52973.739382 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -484,8 +484,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66712 # number of writebacks -system.l2c.writebacks::total 66712 # number of writebacks +system.l2c.writebacks::writebacks 66287 # number of writebacks +system.l2c.writebacks::total 66287 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu0.inst 4 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits @@ -501,163 +501,163 @@ system.l2c.overall_mshr_hits::cpu0.data 37 # nu system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 72 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6273 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6379 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 14 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 4 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6265 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6387 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 17 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6295 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6277 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25258 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5125 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3774 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8899 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 638 # number of SCUpgradeReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6309 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6264 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25261 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5101 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3782 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8883 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 646 # number of SCUpgradeReq MSHR misses system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 411 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1049 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63279 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76923 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140202 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6273 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69658 # number of demand (read+write) MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63146 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76636 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 139782 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 14 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 4 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6265 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69533 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 17 # number of demand (read+write) MSHR misses system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6295 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83200 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165460 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6273 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69658 # number of overall MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6309 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 82900 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165043 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 14 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 4 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6265 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69533 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 17 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6295 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83200 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165460 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 591261 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 262004 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 269548612 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 289309796 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of ReadReq MSHR miss cycles +system.l2c.overall_mshr_misses::cpu1.inst 6309 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 82900 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165043 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 760014 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 205753 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 268851852 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 287876545 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 300356052 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312753448 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1174048691 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51546985 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38368705 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 89915690 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6444113 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4119409 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 10563522 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2354035161 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3171377741 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5525412902 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 591261 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 262004 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 269548612 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2643344957 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of demand (read+write) MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 306166045 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 312367924 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1177390401 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 51308459 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 38489213 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 89797672 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 6525620 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 4130906 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10656526 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2347754082 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3162202952 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5509957034 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 760014 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 205753 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 268851852 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2635630627 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of demand (read+write) MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 300356052 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3484131189 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6699461593 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 591261 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 262004 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 269548612 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2643344957 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1171267 # number of overall MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 306166045 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3474570876 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6687347435 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 760014 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 205753 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 268851852 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2635630627 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1106017 # number of overall MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 300356052 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3484131189 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6699461593 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5299085 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408099047 # number of ReadReq MSHR uncacheable cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 306166045 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3474570876 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6687347435 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5300585 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12408061544 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100282 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667429748 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167082928162 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050132738 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25922779804 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 26972912542 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299085 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458231785 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154666775744 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167082238155 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050331237 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25987896299 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 27038227536 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5300585 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458392781 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2100282 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590209552 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 194055840704 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036857 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030751 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017681 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805818 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835510 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.818148 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.760429 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.739209 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.751971 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567474 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567605 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567546 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098746 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098746 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180654672043 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194120465691 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036797 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017669 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.810068 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.829022 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818031 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.764497 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.737882 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753923 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.565885 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.566118 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.566013 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098439 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000613 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000843 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015959 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.243837 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000558 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010583 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244194 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098439 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45072.263191 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49867.165390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46609.017893 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10058.509900 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10176.946854 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10108.935270 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10101.578947 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.866180 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10081.859981 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37179.775156 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41262.630513 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39418.215750 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 54286.714286 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42913.304389 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37904.744898 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 65059.823529 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 48528.458551 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41912.797057 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40518.818944 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 5998401 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits +system.cpu0.branchPred.lookups 6001640 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4577059 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 296005 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3758008 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2912273 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.495125 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673236 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28713 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907261 # DTB read hits -system.cpu0.dtb.read_misses 28773 # DTB read misses -system.cpu0.dtb.write_hits 5136781 # DTB write hits -system.cpu0.dtb.write_misses 5705 # DTB write misses +system.cpu0.dtb.read_hits 8910999 # DTB read hits +system.cpu0.dtb.read_misses 29151 # DTB read misses +system.cpu0.dtb.write_hits 5140269 # DTB write hits +system.cpu0.dtb.write_misses 5702 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1812 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1035 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 300 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936034 # DTB read accesses -system.cpu0.dtb.write_accesses 5142486 # DTB write accesses +system.cpu0.dtb.perms_faults 584 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8940150 # DTB read accesses +system.cpu0.dtb.write_accesses 5145971 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14044042 # DTB hits -system.cpu0.dtb.misses 34478 # DTB misses -system.cpu0.dtb.accesses 14078520 # DTB accesses -system.cpu0.itb.inst_hits 4215431 # ITB inst hits -system.cpu0.itb.inst_misses 5154 # ITB inst misses +system.cpu0.dtb.hits 14051268 # DTB hits +system.cpu0.dtb.misses 34853 # DTB misses +system.cpu0.dtb.accesses 14086121 # DTB accesses +system.cpu0.itb.inst_hits 4221147 # ITB inst hits +system.cpu0.itb.inst_misses 5166 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -722,144 +722,144 @@ system.cpu0.itb.flush_entries 1347 # Nu system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1454 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses -system.cpu0.itb.hits 4215431 # DTB hits -system.cpu0.itb.misses 5154 # DTB misses -system.cpu0.itb.accesses 4220585 # DTB accesses -system.cpu0.numCycles 67803924 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4226313 # ITB inst accesses +system.cpu0.itb.hits 4221147 # DTB hits +system.cpu0.itb.misses 5166 # DTB misses +system.cpu0.itb.accesses 4226313 # DTB accesses +system.cpu0.numCycles 67826289 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11756286 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32014298 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6001640 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3585509 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7517140 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1455004 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 67247 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20650253 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4770 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46433 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85685 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 203 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4219566 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157765 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2202 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41172573 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004783 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385116 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33662869 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565639 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 818038 1.99% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675166 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 774675 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559568 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667522 1.62% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 352154 0.86% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3096942 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41172573 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088485 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12265416 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20593296 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6819123 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 513990 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 980748 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935580 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64947 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40010595 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213478 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 980748 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12833750 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5743138 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12737000 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6715008 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2162929 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38912871 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1796 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435724 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1235455 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 48 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39264355 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175753145 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175718969 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34176 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30934227 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8330127 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411039 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370083 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5348370 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7652222 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5686978 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1127413 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1231482 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36837080 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895317 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37247377 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80474 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6286180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13172304 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256448 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41172573 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904665 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512453 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26032414 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5734790 13.93% 77.16% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3160933 7.68% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2474953 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2097868 5.10% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 946815 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 486964 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184157 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53679 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41172573 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26092 2.44% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843251 78.76% 81.24% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200824 18.76% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22332748 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46981 0.13% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued @@ -869,14 +869,14 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued @@ -885,363 +885,367 @@ system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Ty system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9367267 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5447389 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued -system.cpu0.iq.rate 0.549040 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37247377 # Type of FU issued +system.cpu0.iq.rate 0.549158 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070619 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028743 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116844627 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44026356 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34344813 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8420 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4690 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3883 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38261309 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4408 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307850 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1374402 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2480 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12973 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 535370 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192711 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5613 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 980748 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4124012 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98712 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37850539 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85674 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7652222 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5686978 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571475 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40167 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2962 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12973 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149952 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 118190 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 268142 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36871873 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9226575 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 375504 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118468 # number of nop insts executed -system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853073 # Number of branches executed -system.cpu0.iew.exec_stores 5396490 # Number of stores executed -system.cpu0.iew.exec_rate 0.543517 # Inst execution rate -system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18277167 # num instructions producing a value -system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value +system.cpu0.iew.exec_nop 118142 # number of nop insts executed +system.cpu0.iew.exec_refs 14626690 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4856874 # Number of branches executed +system.cpu0.iew.exec_stores 5400115 # Number of stores executed +system.cpu0.iew.exec_rate 0.543622 # Inst execution rate +system.cpu0.iew.wb_sent 36677250 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34348696 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18291021 # num instructions producing a value +system.cpu0.iew.wb_consumers 35196356 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506422 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519685 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6101158 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638869 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232197 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40191825 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778547 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740754 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28520633 70.96% 70.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5717076 14.22% 85.19% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1914444 4.76% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974820 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784169 1.95% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523265 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386798 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 217938 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1152682 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23678008 # Number of instructions committed -system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40191825 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23681661 # Number of instructions committed +system.cpu0.commit.committedOps 31291235 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11424361 # Number of memory references committed -system.cpu0.commit.loads 6275038 # Number of loads committed -system.cpu0.commit.membars 229662 # Number of memory barriers committed -system.cpu0.commit.branches 4244821 # Number of branches committed +system.cpu0.commit.refs 11429428 # Number of memory references committed +system.cpu0.commit.loads 6277820 # Number of loads committed +system.cpu0.commit.membars 229679 # Number of memory barriers committed +system.cpu0.commit.branches 4245347 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489334 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27647557 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489379 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1152682 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75534199 # The number of ROB reads -system.cpu0.rob.rob_writes 75722713 # The number of ROB writes -system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23597266 # Number of Instructions Simulated -system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated -system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads -system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads -system.cpu0.fp_regfile_writes 902 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes -system.cpu0.icache.replacements 392511 # number of replacements -system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use -system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75580359 # The number of ROB reads +system.cpu0.rob.rob_writes 75767781 # The number of ROB writes +system.cpu0.timesIdled 360539 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26653716 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138005786 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23600919 # Number of Instructions Simulated +system.cpu0.committedOps 31210493 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23600919 # Number of Instructions Simulated +system.cpu0.cpi 2.873883 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873883 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.347961 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.347961 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171874490 # number of integer regfile reads +system.cpu0.int_regfile_writes 34096600 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads +system.cpu0.fp_regfile_writes 872 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012666 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451076 # number of misc regfile writes +system.cpu0.icache.replacements 392591 # number of replacements +system.cpu0.icache.tagsinuse 511.076357 # Cycle average of tags in use +system.cpu0.icache.total_refs 3795579 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393103 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.655431 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076357 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits -system.cpu0.icache.overall_hits::total 3789958 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses -system.cpu0.icache.overall_misses::total 423709 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3795579 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3795579 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3795579 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3795579 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3795579 # number of overall hits +system.cpu0.icache.overall_hits::total 3795579 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423854 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423854 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423854 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423854 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423854 # number of overall misses +system.cpu0.icache.overall_misses::total 423854 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5804082997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5804082997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5804082997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5804082997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5804082997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5804082997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4219433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4219433 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4219433 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4219433 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4219433 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4219433 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100453 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100453 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100453 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100453 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100453 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100453 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13693.590239 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13693.590239 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13693.590239 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13693.590239 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13693.590239 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2620 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.124183 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30672 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30672 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30672 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30672 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30672 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30672 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393037 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393037 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393037 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393037 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393037 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30736 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30736 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30736 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30736 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30736 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30736 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393118 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 393118 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 393118 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 393118 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 393118 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393118 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745929997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745929997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745929997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4745929997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745929997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4745929997 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7902000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7902000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 7902000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093168 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093168 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093168 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093168 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12072.532921 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12072.532921 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12072.532921 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275921 # number of replacements -system.cpu0.dcache.tagsinuse 460.698692 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9260016 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276433 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.498229 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 276649 # number of replacements +system.cpu0.dcache.tagsinuse 460.596566 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9262154 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 277161 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.417956 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 43509000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits -system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses -system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.596566 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899603 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899603 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5782081 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5782081 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3160908 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3160908 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139098 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139098 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137052 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137052 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8942989 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8942989 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8942989 # number of overall hits +system.cpu0.dcache.overall_hits::total 8942989 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 394048 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 394048 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1583429 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1583429 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8774 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8774 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7489 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7489 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977477 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977477 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977477 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977477 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5492603000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5492603000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60464990363 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60464990363 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87990000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87990000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46572500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46572500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65957593363 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65957593363 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65957593363 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65957593363 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6176129 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6176129 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744337 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744337 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147872 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144541 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144541 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10920466 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10920466 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10920466 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10920466 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063802 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063802 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333751 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333751 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059335 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051812 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051812 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181080 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181080 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181080 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181080 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13938.918609 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13938.918609 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38186.107721 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38186.107721 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10028.493276 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10028.493276 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6218.787555 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6218.787555 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33354.417454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33354.417454 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33354.417454 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8825 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 4351 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 671 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.152012 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 54.387500 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks -system.cpu0.dcache.writebacks::total 256512 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 257146 # number of writebacks +system.cpu0.dcache.writebacks::total 257146 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204997 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204997 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453030 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1453030 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 464 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 464 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1658027 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1658027 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1658027 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1658027 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189051 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 189051 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130399 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130399 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8310 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7487 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319450 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319450 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319450 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2382504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2382504500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4025705992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4025705992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66268000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66268000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31600500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6408210492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6408210492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6408210492 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6408210492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514784000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180269878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180269878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695053878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695053878 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030610 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030610 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027485 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056197 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051798 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051798 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029252 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029252 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029252 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12602.443256 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12602.443256 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30872.215216 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30872.215216 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7974.488568 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7974.488568 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4220.715908 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20060.136147 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20060.136147 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1249,38 +1253,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9068423 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits +system.cpu1.branchPred.lookups 9057370 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7441884 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 409640 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6090561 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5229548 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.863158 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772754 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42888 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42898238 # DTB read hits -system.cpu1.dtb.read_misses 36741 # DTB read misses -system.cpu1.dtb.write_hits 6823025 # DTB write hits -system.cpu1.dtb.write_misses 10725 # DTB write misses +system.cpu1.dtb.read_hits 42905047 # DTB read hits +system.cpu1.dtb.read_misses 36603 # DTB read misses +system.cpu1.dtb.write_hits 6822006 # DTB write hits +system.cpu1.dtb.write_misses 10721 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2003 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2568 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 298 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42934979 # DTB read accesses -system.cpu1.dtb.write_accesses 6833750 # DTB write accesses +system.cpu1.dtb.perms_faults 647 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42941650 # DTB read accesses +system.cpu1.dtb.write_accesses 6832727 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49721263 # DTB hits -system.cpu1.dtb.misses 47466 # DTB misses -system.cpu1.dtb.accesses 49768729 # DTB accesses -system.cpu1.itb.inst_hits 8394494 # ITB inst hits -system.cpu1.itb.inst_misses 5446 # ITB inst misses +system.cpu1.dtb.hits 49727053 # DTB hits +system.cpu1.dtb.misses 47324 # DTB misses +system.cpu1.dtb.accesses 49774377 # DTB accesses +system.cpu1.itb.inst_hits 8402267 # ITB inst hits +system.cpu1.itb.inst_misses 5496 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1289,114 +1293,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1556 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses -system.cpu1.itb.hits 8394494 # DTB hits -system.cpu1.itb.misses 5446 # DTB misses -system.cpu1.itb.accesses 8399940 # DTB accesses -system.cpu1.numCycles 408755802 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8407763 # ITB inst accesses +system.cpu1.itb.hits 8402267 # DTB hits +system.cpu1.itb.misses 5496 # DTB misses +system.cpu1.itb.accesses 8407763 # DTB accesses +system.cpu1.numCycles 408754758 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19786435 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66033865 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9057370 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6002302 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14145991 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3963679 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 66957 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77248735 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4641 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42710 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129584 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 102 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8400411 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 741502 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2853 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114126440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700482 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.044104 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99987714 87.61% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 797074 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939049 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1891067 1.66% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1525429 1.34% 92.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 571908 0.50% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2134670 1.87% 94.50% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410312 0.36% 94.86% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5869217 5.14% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114126440 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022158 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161549 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21303172 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76905866 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12788673 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523903 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2604826 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105931 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97877 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75200071 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 325666 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2604826 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22687981 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31933680 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40739903 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11832589 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4327461 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69726432 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18789 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 667798 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3085321 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1194 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73678442 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321083951 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321025301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58650 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49043171 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24635271 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445050 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388065 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7869897 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13205633 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8143981 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1031020 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1549372 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63452075 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1154123 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89105675 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94570 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16177961 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45638243 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 273609 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114126440 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780763 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519063 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83740358 73.38% 73.38% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8394887 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4311710 3.78% 84.51% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3761165 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10575130 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1975219 1.73% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1022890 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 270730 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 74351 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114126440 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29540 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 995 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1424,399 +1428,399 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7547716 95.90% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292001 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37588774 42.18% 42.54% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59166 0.07% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.60% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43972144 49.35% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170135 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued -system.cpu1.iq.rate 0.218023 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89105675 # Type of FU issued +system.cpu1.iq.rate 0.217993 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7870252 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088325 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300334896 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80792722 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53591705 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14852 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6792 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96654176 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7819 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342901 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3454829 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3906 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17123 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1307403 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31911868 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888624 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2604826 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24177502 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360064 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64710295 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 111591 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13205633 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8143981 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 865041 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65040 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3489 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17123 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203707 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155314 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 359021 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86656699 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43274731 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2448976 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104827 # number of nop insts executed -system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6999376 # Number of branches executed -system.cpu1.iew.exec_stores 7108814 # Number of stores executed -system.cpu1.iew.exec_rate 0.212079 # Inst execution rate -system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29908204 # num instructions producing a value -system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value +system.cpu1.iew.exec_nop 104097 # number of nop insts executed +system.cpu1.iew.exec_refs 50382465 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6984824 # Number of branches executed +system.cpu1.iew.exec_stores 7107734 # Number of stores executed +system.cpu1.iew.exec_rate 0.212002 # Inst execution rate +system.cpu1.iew.wb_sent 85679792 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53598497 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29912489 # num instructions producing a value +system.cpu1.iew.wb_consumers 53377026 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131126 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560400 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16097351 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880514 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 313181 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111521614 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431660 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.399918 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94783688 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8232715 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2113496 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1251152 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1245297 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 569963 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001738 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 503665 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1819900 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38058618 # Number of instructions committed -system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111521614 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38055916 # Number of instructions committed +system.cpu1.commit.committedOps 48139449 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16590369 # Number of memory references committed -system.cpu1.commit.loads 9752527 # Number of loads committed -system.cpu1.commit.membars 190082 # Number of memory barriers committed -system.cpu1.commit.branches 5966603 # Number of branches committed +system.cpu1.commit.refs 16587382 # Number of memory references committed +system.cpu1.commit.loads 9750804 # Number of loads committed +system.cpu1.commit.membars 190065 # Number of memory barriers committed +system.cpu1.commit.branches 5966253 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534481 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42675584 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534450 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1819900 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172920681 # The number of ROB reads -system.cpu1.rob.rob_writes 131224345 # The number of ROB writes -system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37988979 # Number of Instructions Simulated -system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated -system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads -system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes -system.cpu1.icache.replacements 596769 # number of replacements -system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use -system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks. +system.cpu1.rob.rob_reads 172894643 # The number of ROB reads +system.cpu1.rob.rob_writes 131171187 # The number of ROB writes +system.cpu1.timesIdled 1407429 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294628318 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796480472 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37986277 # Number of Instructions Simulated +system.cpu1.committedOps 48069810 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37986277 # Number of Instructions Simulated +system.cpu1.cpi 10.760590 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.760590 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092932 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092932 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 387762774 # number of integer regfile reads +system.cpu1.int_regfile_writes 56160786 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4853 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18458538 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405362 # number of misc regfile writes +system.cpu1.icache.replacements 596198 # number of replacements +system.cpu1.icache.tagsinuse 480.885955 # Cycle average of tags in use +system.cpu1.icache.total_refs 7759207 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 596710 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.003313 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits -system.cpu1.icache.overall_hits::total 7750669 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses -system.cpu1.icache.overall_misses::total 641966 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076492 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13479.566661 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13479.566661 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13479.566661 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13479.566661 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13479.566661 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2249 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 480.885955 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.939230 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.939230 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7759207 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7759207 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7759207 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7759207 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7759207 # number of overall hits +system.cpu1.icache.overall_hits::total 7759207 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641153 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641153 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641153 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641153 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641153 # number of overall misses +system.cpu1.icache.overall_misses::total 641153 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8644043496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8644043496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8644043496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8644043496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8644043496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8644043496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8400360 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8400360 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8400360 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8400360 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8400360 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8400360 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076324 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076324 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076324 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076324 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076324 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.076324 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13482.029244 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13482.029244 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13482.029244 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13482.029244 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13482.029244 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2220 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 165 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 167 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.630303 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 13.293413 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44655 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44655 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44655 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44655 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44655 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44655 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597311 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597311 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597311 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 597311 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 597311 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 597311 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076959992 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076959992 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076959992 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7076959992 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076959992 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7076959992 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44405 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44405 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44405 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44405 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44405 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44405 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596748 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 596748 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 596748 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 596748 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 596748 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 596748 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7076621996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7076621996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7076621996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7076621996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7076621996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7076621996 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071038 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071038 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071038 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071038 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.643843 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.643843 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.643843 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360267 # number of replacements -system.cpu1.dcache.tagsinuse 474.654017 # Cycle average of tags in use -system.cpu1.dcache.total_refs 12671092 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 360637 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.135308 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 359991 # number of replacements +system.cpu1.dcache.tagsinuse 474.520156 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12670892 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 360323 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.165371 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 70354132000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 474.654017 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.927059 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.927059 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8304151 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8304151 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4137952 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4137952 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97565 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97565 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94853 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94853 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12442103 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12442103 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12442103 # number of overall hits -system.cpu1.dcache.overall_hits::total 12442103 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 399179 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 399179 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1556589 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1556589 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13972 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13972 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10605 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10605 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1955768 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1955768 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1955768 # number of overall misses -system.cpu1.dcache.overall_misses::total 1955768 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6101251500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6101251500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61874023496 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61874023496 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129109000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129109000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53792000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53792000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67975274996 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67975274996 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67975274996 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67975274996 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8703330 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked +system.cpu1.dcache.occ_blocks::cpu1.data 474.520156 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.926797 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.926797 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8303862 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8303862 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4138320 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4138320 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97526 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97526 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94815 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94815 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12442182 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12442182 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12442182 # number of overall hits +system.cpu1.dcache.overall_hits::total 12442182 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 400057 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 400057 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1554920 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1554920 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13970 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 13970 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10628 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10628 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1954977 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1954977 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1954977 # number of overall misses +system.cpu1.dcache.overall_misses::total 1954977 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6105054500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6105054500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61696466986 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61696466986 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129466000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129466000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53986500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53986500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67801521486 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67801521486 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67801521486 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67801521486 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8703919 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8703919 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693240 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5693240 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111496 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111496 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105443 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105443 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14397159 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14397159 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14397159 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14397159 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045963 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045963 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273117 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273117 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125296 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125296 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100794 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100794 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135789 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135789 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135789 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135789 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15260.461634 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15260.461634 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39678.225880 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39678.225880 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9267.430208 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9267.430208 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.648099 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.648099 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34681.493177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34681.493177 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34681.493177 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 24449 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13557 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3317 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.370817 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 83.685185 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks -system.cpu1.dcache.writebacks::total 324294 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 324138 # number of writebacks +system.cpu1.dcache.writebacks::total 324138 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172104 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 172104 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393517 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1393517 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565621 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1565621 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565621 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1565621 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227953 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227953 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161403 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161403 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12514 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10624 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10624 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389356 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389356 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389356 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389356 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2849477500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2849477500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5127514196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5127514196 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88527000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88527000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32740500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32740500 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7976991696 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7976991696 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7976991696 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7976991696 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989374500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989374500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35732843580 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35732843580 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204722218080 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204722218080 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026190 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026190 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112237 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100756 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100756 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027044 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027044 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027044 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12500.285146 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12500.285146 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31768.394615 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31768.394615 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7074.236855 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7074.236855 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3081.748870 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3081.748870 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20487.655760 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20487.655760 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1838,17 +1842,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540238105555 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540238105555 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540238105555 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540238105555 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41724 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed |