diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-03-04 23:33:47 -0500 |
| commit | 09b2430e95df4f744a000bac34100eeb9ebcb878 (patch) | |
| tree | 1db0ab99b4186f15335a866fd7239ba51755b7d9 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | f205d83359dfb3c4f75159f83081b5e356c3c4b4 (diff) | |
| download | gem5-09b2430e95df4f744a000bac34100eeb9ebcb878.tar.xz | |
stats: update patches for branch predictor and fetch updates.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
4 files changed, 1390 insertions, 1384 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 2403b9510..053c6a286 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,21 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/dist/m5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 -dtb_filename= +dtb_filename=False early_kernel_symbols=false enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/dist/m5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1077,6 +1077,7 @@ type=SimpleDRAM activation_limit=4 addr_mapping=openmap banks_per_rank=8 +channels=1 clock=1000 conf_table_reported=true in_addr_map=true diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index e8e271d58..4ccac5e7b 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index d8e2a14f0..8d856e1ed 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Feb 13 2013 11:38:19 -gem5 started Feb 13 2013 21:11:40 -gem5 executing on u200540-lin +gem5 compiled Feb 25 2013 18:24:48 +gem5 started Feb 25 2013 23:05:46 +gem5 executing on zizzer command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1102937390000 because m5_exit instruction encountered +Exiting @ tick 1102934903000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 434326c81..5e12f3369 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,149 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.102950 # Number of seconds simulated -sim_ticks 1102950399000 # Number of ticks simulated -final_tick 1102950399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102940 # Number of seconds simulated +sim_ticks 1102940172000 # Number of ticks simulated +final_tick 1102940172000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57810 # Simulator instruction rate (inst/s) -host_op_rate 74418 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1035290197 # Simulator tick rate (ticks/s) -host_mem_usage 414988 # Number of bytes of host memory used -host_seconds 1065.35 # Real time elapsed on the host -sim_insts 61588287 # Number of instructions simulated -sim_ops 79281553 # Number of ops (including micro ops) simulated +host_inst_rate 65652 # Simulator instruction rate (inst/s) +host_op_rate 84510 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1175755462 # Simulator tick rate (ticks/s) +host_mem_usage 411412 # Number of bytes of host memory used +host_seconds 938.07 # Real time elapsed on the host +sim_insts 61586245 # Number of instructions simulated +sim_ops 79276446 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368244 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409472 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4368500 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 405632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247408 # Number of bytes read from this memory -system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409024 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory +system.physmem.bytes_read::total 59192100 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 409472 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 405632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 814656 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268864 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4269568 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7296208 # Number of bytes written to this memory +system.physmem.bytes_written::total 7296912 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6391 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68326 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6398 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68330 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 6338 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82017 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66701 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257967 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66712 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823537 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44207595 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823548 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208004 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 232 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 370845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960508 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371255 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3960777 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 986 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 367770 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4757610 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53666243 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 370845 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 367770 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 738615 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3870404 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367773 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4757770 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53667553 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371255 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367773 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739028 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3871079 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729356 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6615173 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3870404 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44207595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729381 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6615873 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3871079 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208004 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 232 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 370845 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3975921 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371255 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3976190 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 986 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 367770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7486966 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60281416 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257953 # Total number of read requests seen -system.physmem.writeReqs 823537 # Total number of write requests seen -system.physmem.cpureqs 242283 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508992 # Total number of bytes read from memory -system.physmem.bytesWritten 52706368 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7296208 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 367773 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7487151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60283426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257967 # Total number of read requests seen +system.physmem.writeReqs 823548 # Total number of write requests seen +system.physmem.cpureqs 242288 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400509888 # Total number of bytes read from memory +system.physmem.bytesWritten 52707072 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59192100 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7296912 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 121 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12582 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391384 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391213 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 12562 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391387 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391216 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 390896 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391625 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391537 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390907 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391623 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391542 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390911 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390957 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 391661 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391406 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390709 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 390852 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391232 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390507 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391233 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391227 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390512 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 390457 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391260 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51392 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51231 # Track writes on a per bank basis +system.physmem.perBankRdReqs::15 391259 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51233 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50996 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51009 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51679 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52043 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51353 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51501 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51565 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51001 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51007 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51680 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52040 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51500 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51879 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51844 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51252 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51893 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 2243059 # Number of times wr buffer was full causing retry -system.physmem.totGap 1102949217500 # Total gap between requests +system.physmem.totGap 1102939019000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.readPktSize::6 163014 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66701 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 493596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441381 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1086282 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1098776 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1064567 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26922 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24897 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44531 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63867 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44258 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12048 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17164 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5936 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66712 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 493693 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430180 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441411 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098726 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44513 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44248 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12053 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11796 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5937 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 152 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see @@ -160,16 +160,16 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2900 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3009 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3072 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3095 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3127 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3151 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2968 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3073 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3128 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3152 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3172 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35806 # What write queue length does an incoming req see @@ -182,8 +182,8 @@ system.physmem.wrQLenPdf::18 35806 # Wh system.physmem.wrQLenPdf::19 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35806 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35806 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32906 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35806 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 32839 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 32797 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32760 # What write queue length does an incoming req see @@ -192,14 +192,14 @@ system.physmem.wrQLenPdf::28 32711 # Wh system.physmem.wrQLenPdf::29 32679 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32655 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 32635 # What write queue length does an incoming req see -system.physmem.totQLat 199191841750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 239011336750 # Sum of mem lat for all requests -system.physmem.totBusLat 31289160000 # Total cycles spent in databus access -system.physmem.totBankLat 8530335000 # Total cycles spent in bank access -system.physmem.avgQLat 31830.81 # Average queueing delay per request -system.physmem.avgBankLat 1363.15 # Average bank access latency per request +system.physmem.totQLat 199192058500 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 239013617250 # Sum of mem lat for all requests +system.physmem.totBusLat 31289230000 # Total cycles spent in databus access +system.physmem.totBankLat 8532328750 # Total cycles spent in bank access +system.physmem.avgQLat 31830.77 # Average queueing delay per request +system.physmem.avgBankLat 1363.46 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38193.95 # Average memory access latency +system.physmem.avgMemAccLat 38194.23 # Average memory access latency system.physmem.avgRdBW 363.13 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 47.79 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.67 # Average consumed read bandwidth in MB/s @@ -207,12 +207,12 @@ system.physmem.avgConsumedWrBW 6.62 # Av system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 11.98 # Average write queue length over time -system.physmem.readRowHits 6213974 # Number of row buffer hits during reads -system.physmem.writeRowHits 800028 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.05 # Average write queue length over time +system.physmem.readRowHits 6213954 # Number of row buffer hits during reads +system.physmem.writeRowHits 800040 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155751.01 # Average gap between requests +system.physmem.avgGap 155749.02 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -231,251 +231,251 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72704 # number of replacements -system.l2c.tagsinuse 53743.106475 # Cycle average of tags in use -system.l2c.total_refs 1840692 # Total number of references to valid blocks. -system.l2c.sampled_refs 137860 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.351893 # Average number of references to valid blocks. +system.l2c.replacements 72718 # number of replacements +system.l2c.tagsinuse 53743.140165 # Cycle average of tags in use +system.l2c.total_refs 1840331 # Total number of references to valid blocks. +system.l2c.sampled_refs 137862 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.349081 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39373.484726 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.828040 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 1.177687 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4008.510797 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2822.170311 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.062329 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.921455 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3716.471787 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3805.479341 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600792 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39373.587396 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.826422 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 1.187080 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4008.736100 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2822.118244 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.062372 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.itb.walker 0.921462 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3716.187342 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3805.513745 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.600793 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000018 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061165 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043063 # 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number of overall hits -system.l2c.overall_hits::cpu0.data 215048 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30274 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5231 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590416 # number of overall hits -system.l2c.overall_hits::cpu1.data 256459 # number of overall hits -system.l2c.overall_hits::total 1510417 # number of overall hits +system.l2c.ReadReq_hits::cpu0.dtb.walker 22141 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4502 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386239 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166660 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30329 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5168 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 590386 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 197820 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403245 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015949 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244624 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000561 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000191 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010549 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244934 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098720 # mshr miss rate for overall accesses +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180590209552 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 194055840704 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036857 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030751 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017681 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805818 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835510 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.818148 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.760429 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.739209 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.751971 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567474 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567605 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567546 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098746 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000497 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001109 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015982 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244770 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000560 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.000193 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010550 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244963 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098746 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45524.469657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45353.471704 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49953.990123 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 46439.556638 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10054.798131 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10171.225755 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.107732 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.024961 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10027.560386 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10071.588626 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37275.370609 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41145.112190 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39398.566983 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 49825.306357 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 46482.250812 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10057.948293 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10166.588500 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10104.021800 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10100.490596 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10022.892944 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10070.087703 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 37200.890675 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41227.951861 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39410.371478 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 53751 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 51438.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42663.078998 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 38030.596506 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52400.800000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42969.649609 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37947.471317 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 68898.058824 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47543.098014 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41809.695445 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40473.049037 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47713.431612 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41876.576791 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40489.916554 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -678,38 +678,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6001263 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4576664 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 295188 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3775279 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913941 # Number of BTB hits +system.cpu0.branchPred.lookups 5998401 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575821 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294349 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3757481 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2911128 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.184786 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673658 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28611 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.475521 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672992 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28616 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8907872 # DTB read hits -system.cpu0.dtb.read_misses 28815 # DTB read misses -system.cpu0.dtb.write_hits 5138143 # DTB write hits -system.cpu0.dtb.write_misses 5606 # DTB write misses +system.cpu0.dtb.read_hits 8907261 # DTB read hits +system.cpu0.dtb.read_misses 28773 # DTB read misses +system.cpu0.dtb.write_hits 5136781 # DTB write hits +system.cpu0.dtb.write_misses 5705 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1053 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.flush_entries 1814 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1038 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 532 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8936687 # DTB read accesses -system.cpu0.dtb.write_accesses 5143749 # DTB write accesses +system.cpu0.dtb.perms_faults 560 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936034 # DTB read accesses +system.cpu0.dtb.write_accesses 5142486 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046015 # DTB hits -system.cpu0.dtb.misses 34421 # DTB misses -system.cpu0.dtb.accesses 14080436 # DTB accesses -system.cpu0.itb.inst_hits 4220167 # ITB inst hits -system.cpu0.itb.inst_misses 5223 # ITB inst misses +system.cpu0.dtb.hits 14044042 # DTB hits +system.cpu0.dtb.misses 34478 # DTB misses +system.cpu0.dtb.accesses 14078520 # DTB accesses +system.cpu0.itb.inst_hits 4215431 # ITB inst hits +system.cpu0.itb.inst_misses 5154 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -718,530 +718,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1350 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1347 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1535 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4225390 # ITB inst accesses -system.cpu0.itb.hits 4220167 # DTB hits -system.cpu0.itb.misses 5223 # DTB misses -system.cpu0.itb.accesses 4225390 # DTB accesses -system.cpu0.numCycles 67827032 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4220585 # ITB inst accesses +system.cpu0.itb.hits 4215431 # DTB hits +system.cpu0.itb.misses 5154 # DTB misses +system.cpu0.itb.accesses 4220585 # DTB accesses +system.cpu0.numCycles 67803924 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11757994 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32012326 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6001263 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3587599 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516289 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1452567 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61154 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20647681 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4894 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47403 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85456 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.icacheStallCycles 11747073 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32000754 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998401 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3584120 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7510773 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450164 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 64498 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20642358 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4878 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46878 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85526 # Number of stall cycles due to pending quiesce instructions system.cpu0.fetch.IcacheWaitRetryStallCycles 225 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4218433 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 158199 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2369 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41163993 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.004932 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.385225 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.CacheLines 4213800 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157670 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2178 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41143503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.004869 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385262 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33655210 81.76% 81.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565659 1.37% 83.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816805 1.98% 85.12% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 675504 1.64% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 773580 1.88% 88.64% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559421 1.36% 90.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 670235 1.63% 91.62% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352235 0.86% 92.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3095344 7.52% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33640113 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 564874 1.37% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 815232 1.98% 85.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 675522 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773200 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 558709 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669860 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351529 0.85% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3094464 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41163993 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088479 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471970 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12263422 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20589298 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6819290 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 512710 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 979273 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935723 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64727 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40009195 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 212284 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 979273 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12830808 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5739819 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12737837 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6714966 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2161290 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38908996 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1807 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435519 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1234283 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39260907 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175730932 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175696732 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34200 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30930361 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8330545 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411120 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370260 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5349265 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7648868 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5685535 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1126587 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1232322 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36830553 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895643 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37237747 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80326 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6284476 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13189556 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256860 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41163993 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.904619 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.512118 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41143503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088467 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471960 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12253117 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20585756 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6814381 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512539 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977710 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934268 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64694 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39987776 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212486 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977710 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12820427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5742393 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12731772 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6709970 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2161231 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38889294 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1829 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434890 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1234500 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 47 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39244828 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175643455 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175609334 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34121 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30926653 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8318174 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411256 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370334 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5351915 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7647673 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5682766 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124413 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1217910 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36816448 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895564 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37227077 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80165 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6275180 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13166441 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256842 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41143503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.904811 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512506 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26023978 63.22% 63.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5734172 13.93% 77.15% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3165060 7.69% 84.84% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2475453 6.01% 90.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2094791 5.09% 95.94% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 945417 2.30% 98.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 488035 1.19% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184059 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53028 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26013518 63.23% 63.23% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5726772 13.92% 77.15% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3163675 7.69% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471330 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2096927 5.10% 95.94% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 946781 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 487184 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 184280 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53036 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41163993 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41143503 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25953 2.43% 2.43% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 456 0.04% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.47% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841491 78.81% 81.29% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199811 18.71% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25911 2.42% 2.42% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.46% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841841 78.68% 81.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 201703 18.85% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22327853 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46961 0.13% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22320567 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46962 0.13% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 11 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9364731 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5445265 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9363552 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5443123 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37237747 # Type of FU issued -system.cpu0.iq.rate 0.549010 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1067711 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028673 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116813355 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44018555 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34334136 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8379 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3876 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38248858 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4386 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 306561 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37227077 # Type of FU issued +system.cpu0.iq.rate 0.549040 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1069907 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028740 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116773591 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43995152 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34325365 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8374 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4656 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3873 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38240450 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4385 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307272 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1372448 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2379 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13100 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 535058 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372635 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2428 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13158 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 533443 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192712 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5628 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192715 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5605 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 979273 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4122692 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 98715 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37844885 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85302 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7648868 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5685535 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571530 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40279 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 2826 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13100 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150418 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117037 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 267455 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36861439 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9223512 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376308 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977710 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4125178 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98819 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37830480 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84891 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7647673 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5682766 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571414 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 40435 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2836 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13158 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149420 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117102 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266522 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36852561 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222790 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 374516 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118689 # number of nop insts executed -system.cpu0.iew.exec_refs 14621351 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4854206 # Number of branches executed -system.cpu0.iew.exec_stores 5397839 # Number of stores executed -system.cpu0.iew.exec_rate 0.543462 # Inst execution rate -system.cpu0.iew.wb_sent 36666981 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34338012 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18281082 # num instructions producing a value -system.cpu0.iew.wb_consumers 35173096 # num instructions consuming a value +system.cpu0.iew.exec_nop 118468 # number of nop insts executed +system.cpu0.iew.exec_refs 14619280 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4853073 # Number of branches executed +system.cpu0.iew.exec_stores 5396490 # Number of stores executed +system.cpu0.iew.exec_rate 0.543517 # Inst execution rate +system.cpu0.iew.wb_sent 36658484 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34329238 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18277167 # num instructions producing a value +system.cpu0.iew.wb_consumers 35166979 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.506259 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519746 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506302 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519725 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6098128 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638783 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231564 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40184720 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.778562 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.740417 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6089898 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638722 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 230765 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40165793 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778810 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740848 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28508400 70.94% 70.94% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5724488 14.25% 85.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913763 4.76% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 974414 2.42% 92.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 785086 1.95% 94.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 523080 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 385100 0.96% 96.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 218421 0.54% 97.13% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1151968 2.87% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28496220 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5717219 14.23% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1914261 4.77% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974261 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784320 1.95% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 523319 1.30% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386116 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218199 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1151878 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40184720 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23679748 # Number of instructions committed -system.cpu0.commit.committedOps 31286291 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40165793 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23678008 # Number of instructions committed +system.cpu0.commit.committedOps 31281512 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11426897 # Number of memory references committed -system.cpu0.commit.loads 6276420 # Number of loads committed -system.cpu0.commit.membars 229667 # Number of memory barriers committed -system.cpu0.commit.branches 4245051 # Number of branches committed +system.cpu0.commit.refs 11424361 # Number of memory references committed +system.cpu0.commit.loads 6275038 # Number of loads committed +system.cpu0.commit.membars 229662 # Number of memory barriers committed +system.cpu0.commit.branches 4244821 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27642937 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489354 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1151968 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27638419 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489334 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1151878 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75566033 # The number of ROB reads -system.cpu0.rob.rob_writes 75750322 # The number of ROB writes -system.cpu0.timesIdled 360462 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26663039 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138032042 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23599006 # Number of Instructions Simulated -system.cpu0.committedOps 31205549 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23599006 # Number of Instructions Simulated -system.cpu0.cpi 2.874148 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.874148 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347929 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347929 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171822030 # number of integer regfile reads -system.cpu0.int_regfile_writes 34087122 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3256 # number of floating regfile reads -system.cpu0.fp_regfile_writes 900 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13007989 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451063 # number of misc regfile writes -system.cpu0.icache.replacements 392871 # number of replacements -system.cpu0.icache.tagsinuse 511.076375 # Cycle average of tags in use -system.cpu0.icache.total_refs 3794104 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393383 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.644809 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75534199 # The number of ROB reads +system.cpu0.rob.rob_writes 75722713 # The number of ROB writes +system.cpu0.timesIdled 360446 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26660421 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138034694 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23597266 # Number of Instructions Simulated +system.cpu0.committedOps 31200770 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23597266 # Number of Instructions Simulated +system.cpu0.cpi 2.873381 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873381 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.348022 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.348022 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171786019 # number of integer regfile reads +system.cpu0.int_regfile_writes 34080976 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3260 # number of floating regfile reads +system.cpu0.fp_regfile_writes 902 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13006141 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451094 # number of misc regfile writes +system.cpu0.icache.replacements 392511 # number of replacements +system.cpu0.icache.tagsinuse 511.076367 # Cycle average of tags in use +system.cpu0.icache.total_refs 3789958 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 393023 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.643095 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.076375 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 511.076367 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3794104 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3794104 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3794104 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3794104 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3794104 # number of overall hits -system.cpu0.icache.overall_hits::total 3794104 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424196 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424196 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424196 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424196 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424196 # number of overall misses -system.cpu0.icache.overall_misses::total 424196 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5806369997 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5806369997 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5806369997 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5806369997 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5806369997 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5806369997 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4218300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4218300 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4218300 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4218300 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4218300 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4218300 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100561 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100561 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100561 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100561 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100561 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100561 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13687.941416 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13687.941416 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13687.941416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13687.941416 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13687.941416 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2612 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 3789958 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3789958 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3789958 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3789958 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3789958 # number of overall hits +system.cpu0.icache.overall_hits::total 3789958 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423709 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423709 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423709 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423709 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423709 # number of overall misses +system.cpu0.icache.overall_misses::total 423709 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803688497 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5803688497 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5803688497 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5803688497 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5803688497 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5803688497 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213667 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4213667 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4213667 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4213667 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4213667 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4213667 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13697.345341 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13697.345341 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13697.345341 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13697.345341 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13697.345341 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2656 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 153 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 149 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.071895 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.825503 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30799 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30799 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30799 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30799 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30799 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30799 # 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number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 393037 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4746801497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4746801497 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4746801497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4746801497 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4746801497 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4746801497 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093260 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093260 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093260 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093260 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.062542 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.062542 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.062542 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093277 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093277 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093277 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093277 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12077.238268 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12077.238268 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12077.238268 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # 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number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5479209500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5479209500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60675943869 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 60675943869 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88042500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 88042500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46456500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 46456500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 66155153369 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 66155153369 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 66155153369 # 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miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.614219 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.614219 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38307.237174 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38307.237174 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10033.333333 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10033.333333 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6225.743768 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6225.743768 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33469.606182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33469.606182 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33469.606182 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8661 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 5567 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 621 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.946860 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 67.890244 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 460.698692 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899802 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899802 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5779987 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5779987 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159663 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159663 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139233 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139233 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137076 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137076 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8939650 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8939650 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8939650 # number of overall hits +system.cpu0.dcache.overall_hits::total 8939650 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392818 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392818 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1582384 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1582384 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8769 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8769 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1975202 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1975202 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1975202 # number of overall misses +system.cpu0.dcache.overall_misses::total 1975202 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5481439500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5481439500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60566359369 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60566359369 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87760500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46440000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46440000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66047798869 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66047798869 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66047798869 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66047798869 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6172805 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4742047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4742047 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 148002 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144540 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10914852 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10914852 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10914852 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10914852 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063637 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063637 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333692 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333692 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059249 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059249 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051640 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180965 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180965 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180965 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180965 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13954.145431 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13954.145431 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38275.386612 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38275.386612 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10008.039685 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10008.039685 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6221.864952 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6221.864952 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33438.503439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33438.503439 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33438.503439 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8565 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 5561 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 643 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 81 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.320373 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 68.654321 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256612 # number of writebacks -system.cpu0.dcache.writebacks::total 256612 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204222 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 204222 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1453551 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1453551 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657773 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657773 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657773 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657773 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188423 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188423 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130378 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130378 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8304 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8304 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7462 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7462 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318801 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318801 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318801 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378188000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378188000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4038291991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4038291991 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66252500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66252500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31532500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6416479991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6416479991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6416479991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6416479991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514893000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180267878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180267878 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695160878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695160878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030518 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030518 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027487 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056132 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051629 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029201 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029201 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12621.537710 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12621.537710 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30973.722492 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30973.722492 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7978.383911 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7978.383911 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4225.743768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4225.743768 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20126.912999 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20126.912999 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks +system.cpu0.dcache.writebacks::total 256512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204354 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204354 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1452130 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1452130 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 476 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1656484 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1656484 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1656484 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1656484 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188464 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188464 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130254 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130254 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8293 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8293 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7464 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7464 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318718 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318718 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2378480500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2378480500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4031341491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4031341491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65938500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65938500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31512000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31512000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6409821991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6409821991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6409821991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6409821991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514864500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514864500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180302878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180302878 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695167378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695167378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030531 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027468 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027468 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056033 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051640 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051640 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029200 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029200 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029200 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12620.343938 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12620.343938 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30949.847920 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30949.847920 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7951.103340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7951.103340 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4221.864952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4221.864952 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20111.264475 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20111.264475 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1249,38 +1249,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9071093 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7457126 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 408382 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6063336 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5242542 # Number of BTB hits +system.cpu1.branchPred.lookups 9068423 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7455270 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 408018 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6064102 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5241151 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.462997 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772870 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42976 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.429137 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 772299 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42697 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42899284 # DTB read hits -system.cpu1.dtb.read_misses 36667 # DTB read misses -system.cpu1.dtb.write_hits 6823776 # DTB write hits -system.cpu1.dtb.write_misses 10740 # DTB write misses +system.cpu1.dtb.read_hits 42898238 # DTB read hits +system.cpu1.dtb.read_misses 36741 # DTB read misses +system.cpu1.dtb.write_hits 6823025 # DTB write hits +system.cpu1.dtb.write_misses 10725 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2487 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 293 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2008 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2490 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 302 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 676 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42935951 # DTB read accesses -system.cpu1.dtb.write_accesses 6834516 # DTB write accesses +system.cpu1.dtb.perms_faults 655 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42934979 # DTB read accesses +system.cpu1.dtb.write_accesses 6833750 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49723060 # DTB hits -system.cpu1.dtb.misses 47407 # DTB misses -system.cpu1.dtb.accesses 49770467 # DTB accesses -system.cpu1.itb.inst_hits 8396614 # ITB inst hits -system.cpu1.itb.inst_misses 5496 # ITB inst misses +system.cpu1.dtb.hits 49721263 # DTB hits +system.cpu1.dtb.misses 47466 # DTB misses +system.cpu1.dtb.accesses 49768729 # DTB accesses +system.cpu1.itb.inst_hits 8394494 # ITB inst hits +system.cpu1.itb.inst_misses 5446 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1289,114 +1289,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1535 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1530 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1557 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1510 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8402110 # ITB inst accesses -system.cpu1.itb.hits 8396614 # DTB hits -system.cpu1.itb.misses 5496 # DTB misses -system.cpu1.itb.accesses 8402110 # DTB accesses -system.cpu1.numCycles 408759365 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8399940 # ITB inst accesses +system.cpu1.itb.hits 8394494 # DTB hits +system.cpu1.itb.misses 5446 # DTB misses +system.cpu1.itb.accesses 8399940 # DTB accesses +system.cpu1.numCycles 408755802 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19792479 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66053661 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9071093 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6015412 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14141488 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3960570 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63871 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77254295 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4578 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 41467 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129632 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.icacheStallCycles 19793701 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66043012 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9068423 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6013450 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14139093 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3958938 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 65451 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77253219 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4575 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41710 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 129512 # Number of stall cycles due to pending quiesce instructions system.cpu1.fetch.IcacheWaitRetryStallCycles 148 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8394649 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 740550 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3020 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114126730 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.700802 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.045190 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.CacheLines 8392686 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 740378 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2825 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114124947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.700718 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.045131 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 99992423 87.62% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796833 0.70% 88.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937270 0.82% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1888150 1.65% 90.79% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1516879 1.33% 92.12% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570874 0.50% 92.62% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2130694 1.87% 94.49% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410492 0.36% 94.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5883115 5.15% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99993030 87.62% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796567 0.70% 88.32% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937489 0.82% 89.14% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1887963 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1516591 1.33% 92.12% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 569617 0.50% 92.62% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2129815 1.87% 94.49% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410324 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5883551 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114126730 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022192 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.161595 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21309229 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 76907002 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12785223 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523232 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2602044 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105609 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98242 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75190345 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327184 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2602044 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22692364 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 31945147 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40728563 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11830258 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4328354 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69732759 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18777 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 668377 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3086520 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 411 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73724172 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321062566 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321003544 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59022 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49048322 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24675850 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444626 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387642 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7869295 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13203135 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8142815 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1033166 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1534389 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63494746 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157882 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89124827 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94932 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16221194 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45699544 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277241 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114126730 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.780929 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.519205 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114124947 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022185 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161571 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21308374 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76909285 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12783383 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 523008 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2600897 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1105255 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98147 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75181804 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327202 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2600897 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22691617 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31944842 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40730815 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11827860 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4328916 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69723383 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18766 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668457 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3086605 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 426 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73713482 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321023926 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 320964994 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58932 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49048009 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24665473 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444684 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387735 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7872422 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13201823 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8142648 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1033883 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1534096 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63487985 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158001 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89118015 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94635 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16215431 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45695453 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277388 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114124947 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.780881 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519165 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83735089 73.37% 73.37% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8399712 7.36% 80.73% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4300489 3.77% 84.50% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3770900 3.30% 87.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10582685 9.27% 97.08% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1966579 1.72% 98.80% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1024954 0.90% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 272498 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73824 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83732864 73.37% 73.37% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8404718 7.36% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4298594 3.77% 84.50% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3768314 3.30% 87.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10582090 9.27% 97.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1967507 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024622 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272364 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73874 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114126730 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114124947 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29743 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 996 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29701 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1424,13 +1424,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7545200 95.88% 96.27% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 293621 3.73% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7545557 95.86% 96.25% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 295033 3.75% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37614506 42.20% 42.56% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59141 0.07% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37610156 42.20% 42.55% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59163 0.07% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.62% # Type of FU issued @@ -1443,11 +1443,11 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.62% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.62% # Type of FU issued @@ -1456,363 +1456,367 @@ system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.62% # Ty system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.62% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.62% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.62% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43964242 49.33% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171411 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43962640 49.33% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7170532 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89124827 # Type of FU issued -system.cpu1.iq.rate 0.218037 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7869560 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088298 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300373215 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80882348 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53634324 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14862 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8064 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6807 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96672574 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7816 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 343282 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89118015 # Type of FU issued +system.cpu1.iq.rate 0.218023 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7871289 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088324 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300359292 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80869896 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53629107 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14882 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8062 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6802 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96667481 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7826 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342650 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3450539 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3807 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17140 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1304937 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3449296 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3766 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17093 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1304806 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31906056 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 888018 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31906048 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888017 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2602044 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24184461 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 360387 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64757250 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 110652 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13203135 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8142815 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869312 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 65433 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3547 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17140 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 201642 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155418 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 357060 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86694604 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43269055 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2430223 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2600897 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24182074 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360611 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64750813 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 110749 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13201823 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8142648 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869251 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65576 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3534 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17093 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201242 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 155476 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356718 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86688682 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43267985 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2429333 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104622 # number of nop insts executed -system.cpu1.iew.exec_refs 50378581 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7000416 # Number of branches executed -system.cpu1.iew.exec_stores 7109526 # Number of stores executed -system.cpu1.iew.exec_rate 0.212092 # Inst execution rate -system.cpu1.iew.wb_sent 85717179 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53641131 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29911901 # num instructions producing a value -system.cpu1.iew.wb_consumers 53368558 # num instructions consuming a value +system.cpu1.iew.exec_nop 104827 # number of nop insts executed +system.cpu1.iew.exec_refs 50376799 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6999376 # Number of branches executed +system.cpu1.iew.exec_stores 7108814 # Number of stores executed +system.cpu1.iew.exec_rate 0.212079 # Inst execution rate +system.cpu1.iew.wb_sent 85711710 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53635909 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29908204 # num instructions producing a value +system.cpu1.iew.wb_consumers 53361522 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131229 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560478 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131217 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560483 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16124623 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880641 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 311654 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111524686 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.431704 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.400261 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16119527 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880613 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311377 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111524050 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431703 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400207 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94788278 84.99% 84.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8230770 7.38% 92.37% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2113389 1.89% 94.27% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254382 1.12% 95.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1243785 1.12% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 567669 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997860 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 504120 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1824433 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94787660 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8229182 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114661 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1254724 1.13% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1244333 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 567856 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 997712 0.89% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 503621 0.45% 98.36% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1824301 1.64% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111524686 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38058920 # Number of instructions committed -system.cpu1.commit.committedOps 48145643 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111524050 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38058618 # Number of instructions committed +system.cpu1.commit.committedOps 48145315 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16590474 # Number of memory references committed -system.cpu1.commit.loads 9752596 # Number of loads committed -system.cpu1.commit.membars 190088 # Number of memory barriers committed -system.cpu1.commit.branches 5966646 # Number of branches committed +system.cpu1.commit.refs 16590369 # Number of memory references committed +system.cpu1.commit.loads 9752527 # Number of loads committed +system.cpu1.commit.membars 190082 # Number of memory barriers committed +system.cpu1.commit.branches 5966603 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42681359 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534484 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1824433 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42681078 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534481 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1824301 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172926580 # The number of ROB reads -system.cpu1.rob.rob_writes 131236338 # The number of ROB writes -system.cpu1.timesIdled 1408486 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294632635 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796502635 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37989281 # Number of Instructions Simulated -system.cpu1.committedOps 48076004 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37989281 # Number of Instructions Simulated -system.cpu1.cpi 10.759861 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.759861 # CPI: Total CPI of All Threads +system.cpu1.rob.rob_reads 172920681 # The number of ROB reads +system.cpu1.rob.rob_writes 131224345 # The number of ROB writes +system.cpu1.timesIdled 1408365 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294630855 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796488086 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37988979 # Number of Instructions Simulated +system.cpu1.committedOps 48075676 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37988979 # Number of Instructions Simulated +system.cpu1.cpi 10.759852 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.759852 # CPI: Total CPI of All Threads system.cpu1.ipc 0.092938 # IPC: Instructions Per Cycle system.cpu1.ipc_total 0.092938 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387915275 # number of integer regfile reads -system.cpu1.int_regfile_writes 56205449 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4899 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18464839 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405417 # number of misc regfile writes -system.cpu1.icache.replacements 596801 # number of replacements -system.cpu1.icache.tagsinuse 480.742161 # Cycle average of tags in use -system.cpu1.icache.total_refs 7752714 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597313 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.979316 # Average number of references to valid blocks. +system.cpu1.int_regfile_reads 387889245 # number of integer regfile reads +system.cpu1.int_regfile_writes 56198451 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4879 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18462900 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405383 # number of misc regfile writes +system.cpu1.icache.replacements 596769 # number of replacements +system.cpu1.icache.tagsinuse 480.741673 # Cycle average of tags in use +system.cpu1.icache.total_refs 7750669 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 597281 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.976587 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 74225092500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.742161 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.938950 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.938950 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7752714 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7752714 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7752714 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7752714 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7752714 # number of overall hits -system.cpu1.icache.overall_hits::total 7752714 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641884 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641884 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641884 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641884 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641884 # number of overall misses -system.cpu1.icache.overall_misses::total 641884 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8651274491 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8651274491 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8651274491 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8651274491 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8651274491 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8651274491 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8394598 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8394598 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8394598 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8394598 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8394598 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8394598 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076464 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076464 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076464 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.076464 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076464 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.076464 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13477.940704 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13477.940704 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13477.940704 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13477.940704 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13477.940704 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 2229 # number of cycles access was blocked +system.cpu1.icache.occ_blocks::cpu1.inst 480.741673 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938949 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938949 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7750669 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7750669 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7750669 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7750669 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7750669 # number of overall hits +system.cpu1.icache.overall_hits::total 7750669 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641966 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641966 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641966 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641966 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641966 # number of overall misses +system.cpu1.icache.overall_misses::total 641966 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8653423491 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8653423491 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8653423491 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8653423491 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8653423491 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8653423491 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8392635 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8392635 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8392635 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8392635 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8392635 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8392635 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076492 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.076492 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.076492 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.076492 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.076492 # 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average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11844.535445 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11844.535445 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071171 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071171 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071171 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071171 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11848.032251 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11848.032251 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11848.032251 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 360372 # 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miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135900 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135900 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15272.014775 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15272.014775 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39701.141264 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39701.141264 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9230.253727 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9230.253727 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5080.252735 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5080.252735 # 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number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5694541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5694541 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111537 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111537 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105458 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105458 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14397871 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14397871 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14397871 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14397871 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045865 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045865 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273348 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273348 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125268 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100561 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100561 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135837 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135837 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135837 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135837 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15284.500187 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15284.500187 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39749.749931 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39749.749931 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9240.552534 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9240.552534 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.324375 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.324375 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34756.308006 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34756.308006 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34756.308006 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 25344 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 13325 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 3330 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 160 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.328228 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 84.587500 # average number of cycles each access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.610811 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 84.872611 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324455 # number of writebacks -system.cpu1.dcache.writebacks::total 324455 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 172117 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 172117 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395143 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1395143 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1446 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1446 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567260 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1567260 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567260 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1567260 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228012 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228012 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161462 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161462 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12506 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12506 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 324294 # number of writebacks +system.cpu1.dcache.writebacks::total 324294 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171223 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171223 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395128 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395128 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1566351 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566351 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1566351 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227956 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 227956 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161461 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161461 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12522 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12522 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10600 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 10600 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389474 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389474 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389474 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389474 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2852988500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2852988500 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131820706 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131820706 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87942500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87942500 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32671000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7984809206 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7984809206 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7984809206 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7984809206 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989984000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989984000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691030962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691030962 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681014962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681014962 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026197 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026197 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389417 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389417 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389417 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389417 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2851782000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2851782000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5138031205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5138031205 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88180500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32594000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989813205 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7989813205 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989813205 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7989813205 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990081000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990081000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35691035962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35691035962 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204681116962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204681116962 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026192 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026192 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028354 # mshr miss rate for WriteReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028354 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112139 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100501 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100501 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12512.448906 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12512.448906 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31783.458064 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31783.458064 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7032.024628 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7032.024628 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3082.169811 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3082.169811 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20501.520528 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20501.520528 # average overall mshr miss latency +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112268 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112268 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100514 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100514 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027047 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027047 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027047 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12510.230044 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12510.230044 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31822.119304 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31822.119304 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7042.045999 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7042.045999 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.905660 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20517.371365 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20517.371365 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1834,18 +1838,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540140520228 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 540140520228 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540140520228 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 540140520228 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540139410201 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540139410201 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540139410201 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540139410201 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41727 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48854 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |