diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-07-03 10:15:03 -0400 |
| commit | 25e1b1c1f5f4e0ad3976c88998161700135f4aae (patch) | |
| tree | 36e668b99a36c3dfcfefc157d7bd6b102b8f8af6 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 7e711c98f8fcd949b9430bbf243d60348d0ef28b (diff) | |
| download | gem5-25e1b1c1f5f4e0ad3976c88998161700135f4aae.tar.xz | |
stats: Update stats for cache, crossbar and DRAM changes
This update includes the changes to whole-line writes, the refinement
of Read to ReadClean and ReadShared, the introduction of CleanEvict
for snoop-filter tracking, and updates to the DRAM command scheduler
for bank-group-aware scheduling.
Needless to say, almost every regression is affected.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 6035 |
1 files changed, 3050 insertions, 2985 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 22d20f171..51ea3fd8c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,166 +1,166 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.625378 # Number of seconds simulated -sim_ticks 2625378187500 # Number of ticks simulated -final_tick 2625378187500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.625395 # Number of seconds simulated +sim_ticks 2625394935000 # Number of ticks simulated +final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 105357 # Simulator instruction rate (inst/s) -host_op_rate 127837 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2300779000 # Simulator tick rate (ticks/s) -host_mem_usage 602544 # Number of bytes of host memory used -host_seconds 1141.08 # Real time elapsed on the host -sim_insts 120220550 # Number of instructions simulated -sim_ops 145872273 # Number of ops (including micro ops) simulated +host_inst_rate 95356 # Simulator instruction rate (inst/s) +host_op_rate 115687 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2080724894 # Simulator tick rate (ticks/s) +host_mem_usage 655064 # Number of bytes of host memory used +host_seconds 1261.77 # Real time elapsed on the host +sim_insts 120317196 # Number of instructions simulated +sim_ops 145970023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu0.dtb.walker 1728 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 320 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 1156128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 1193576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.l2cache.prefetcher 8234944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 336832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 657616 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.l2cache.prefetcher 605504 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 1600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 1152320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 1224232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.l2cache.prefetcher 8325184 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 318816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 736276 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.l2cache.prefetcher 690624 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 12188376 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 1156128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 336832 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1492960 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8634432 # Number of bytes written to this memory +system.physmem.bytes_read::total 12451228 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 1152320 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 318816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1471136 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 9003520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 40 # Number of bytes written to this memory -system.physmem.bytes_written::total 8651996 # Number of bytes written to this memory -system.physmem.num_reads::cpu0.dtb.walker 27 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 5 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 20310 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 19170 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.l2cache.prefetcher 128671 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5329 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10295 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.l2cache.prefetcher 9461 # Number of read requests responded to by this memory +system.physmem.bytes_written::total 9021084 # Number of bytes written to this memory +system.physmem.num_reads::cpu0.dtb.walker 25 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 20252 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 19649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.l2cache.prefetcher 130081 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5049 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11525 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.l2cache.prefetcher 10791 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 193295 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 134913 # Number of write requests responded to by this memory +system.physmem.num_reads::total 197406 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 140680 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 10 # Number of write requests responded to by this memory -system.physmem.num_writes::total 139304 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0.dtb.walker 658 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 122 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 440366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 454630 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.l2cache.prefetcher 3136670 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 268 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 24 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 128298 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 250484 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.l2cache.prefetcher 230635 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 145071 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0.dtb.walker 609 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 171 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 438913 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 466304 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.l2cache.prefetcher 3171022 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 244 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 49 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 121435 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280444 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.l2cache.prefetcher 263055 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 366 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 4642522 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 440366 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 128298 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 568665 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3288834 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 4742611 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 438913 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 121435 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 560348 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3429396 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6675 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 15 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3295524 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3288834 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 658 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 122 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 440366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 461305 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.l2cache.prefetcher 3136670 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 268 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 24 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 128298 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 250500 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.l2cache.prefetcher 230635 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 3436086 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3429396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 171 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 438913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 472979 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.l2cache.prefetcher 3171022 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 244 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 121435 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 280459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.l2cache.prefetcher 263055 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 366 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 7938046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 193296 # Number of read requests accepted -system.physmem.writeReqs 175528 # Number of write requests accepted -system.physmem.readBursts 193296 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 175528 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 12362624 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 8320 # Total number of bytes read from write queue -system.physmem.bytesWritten 9724800 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 12188440 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 10970332 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 130 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 23562 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 14506 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 12287 # Per bank write bursts -system.physmem.perBankRdBursts::1 11514 # Per bank write bursts -system.physmem.perBankRdBursts::2 12472 # Per bank write bursts -system.physmem.perBankRdBursts::3 12180 # Per bank write bursts -system.physmem.perBankRdBursts::4 14590 # Per bank write bursts -system.physmem.perBankRdBursts::5 12444 # Per bank write bursts -system.physmem.perBankRdBursts::6 12518 # Per bank write bursts -system.physmem.perBankRdBursts::7 12466 # Per bank write bursts -system.physmem.perBankRdBursts::8 11679 # Per bank write bursts -system.physmem.perBankRdBursts::9 12089 # Per bank write bursts -system.physmem.perBankRdBursts::10 11915 # Per bank write bursts -system.physmem.perBankRdBursts::11 11053 # Per bank write bursts -system.physmem.perBankRdBursts::12 11299 # Per bank write bursts -system.physmem.perBankRdBursts::13 11450 # Per bank write bursts -system.physmem.perBankRdBursts::14 11880 # Per bank write bursts -system.physmem.perBankRdBursts::15 11330 # Per bank write bursts -system.physmem.perBankWrBursts::0 9713 # Per bank write bursts -system.physmem.perBankWrBursts::1 9189 # Per bank write bursts -system.physmem.perBankWrBursts::2 10054 # Per bank write bursts -system.physmem.perBankWrBursts::3 9647 # Per bank write bursts -system.physmem.perBankWrBursts::4 9435 # Per bank write bursts -system.physmem.perBankWrBursts::5 9608 # Per bank write bursts -system.physmem.perBankWrBursts::6 10036 # Per bank write bursts -system.physmem.perBankWrBursts::7 9866 # Per bank write bursts -system.physmem.perBankWrBursts::8 9192 # Per bank write bursts -system.physmem.perBankWrBursts::9 9471 # Per bank write bursts -system.physmem.perBankWrBursts::10 9539 # Per bank write bursts -system.physmem.perBankWrBursts::11 9209 # Per bank write bursts -system.physmem.perBankWrBursts::12 9294 # Per bank write bursts -system.physmem.perBankWrBursts::13 9108 # Per bank write bursts -system.physmem.perBankWrBursts::14 9699 # Per bank write bursts -system.physmem.perBankWrBursts::15 8890 # Per bank write bursts +system.physmem.bw_total::total 8178698 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 197407 # Number of read requests accepted +system.physmem.writeReqs 145071 # Number of write requests accepted +system.physmem.readBursts 197407 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 145071 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 12624448 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 9600 # Total number of bytes read from write queue +system.physmem.bytesWritten 9033728 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 12451292 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 9021084 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 150 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 3896 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 50333 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 12702 # Per bank write bursts +system.physmem.perBankRdBursts::1 12398 # Per bank write bursts +system.physmem.perBankRdBursts::2 12869 # Per bank write bursts +system.physmem.perBankRdBursts::3 12803 # Per bank write bursts +system.physmem.perBankRdBursts::4 14881 # Per bank write bursts +system.physmem.perBankRdBursts::5 12147 # Per bank write bursts +system.physmem.perBankRdBursts::6 12755 # Per bank write bursts +system.physmem.perBankRdBursts::7 12276 # Per bank write bursts +system.physmem.perBankRdBursts::8 11968 # Per bank write bursts +system.physmem.perBankRdBursts::9 12044 # Per bank write bursts +system.physmem.perBankRdBursts::10 11861 # Per bank write bursts +system.physmem.perBankRdBursts::11 11195 # Per bank write bursts +system.physmem.perBankRdBursts::12 11579 # Per bank write bursts +system.physmem.perBankRdBursts::13 12354 # Per bank write bursts +system.physmem.perBankRdBursts::14 11791 # Per bank write bursts +system.physmem.perBankRdBursts::15 11634 # Per bank write bursts +system.physmem.perBankWrBursts::0 9169 # Per bank write bursts +system.physmem.perBankWrBursts::1 9145 # Per bank write bursts +system.physmem.perBankWrBursts::2 9512 # Per bank write bursts +system.physmem.perBankWrBursts::3 9193 # Per bank write bursts +system.physmem.perBankWrBursts::4 8772 # Per bank write bursts +system.physmem.perBankWrBursts::5 8759 # Per bank write bursts +system.physmem.perBankWrBursts::6 9221 # Per bank write bursts +system.physmem.perBankWrBursts::7 8821 # Per bank write bursts +system.physmem.perBankWrBursts::8 8638 # Per bank write bursts +system.physmem.perBankWrBursts::9 8679 # Per bank write bursts +system.physmem.perBankWrBursts::10 8601 # Per bank write bursts +system.physmem.perBankWrBursts::11 8338 # Per bank write bursts +system.physmem.perBankWrBursts::12 8547 # Per bank write bursts +system.physmem.perBankWrBursts::13 8875 # Per bank write bursts +system.physmem.perBankWrBursts::14 8631 # Per bank write bursts +system.physmem.perBankWrBursts::15 8251 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 46 # Number of times write queue was full causing retry -system.physmem.totGap 2625377925000 # Total gap between requests +system.physmem.numWrRetry 15 # Number of times write queue was full causing retry +system.physmem.totGap 2625394672500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) -system.physmem.readPktSize::2 550 # Read request sizes (log2) +system.physmem.readPktSize::2 551 # Read request sizes (log2) system.physmem.readPktSize::3 28 # Read request sizes (log2) -system.physmem.readPktSize::4 3082 # Read request sizes (log2) +system.physmem.readPktSize::4 3086 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 189636 # Read request sizes (log2) +system.physmem.readPktSize::6 193742 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 4391 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 171137 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 58646 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 70721 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 16311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 12182 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 8246 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 7467 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 6266 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 5177 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 4683 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1253 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 715 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 259 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.writePktSize::6 140680 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 60453 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 70781 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 16881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 12152 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 8838 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 7520 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 6581 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 5428 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 4952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 1308 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 775 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 324 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -188,158 +188,159 @@ system.physmem.wrQLenPdf::11 1 # Wh system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 2100 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 2340 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3256 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4036 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4706 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5294 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5941 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 6575 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8147 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 7082 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 7445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 9281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 7962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 8621 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 11356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 9282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 8943 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 8063 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 1588 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 1232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 1372 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 2519 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 2445 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 1674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 1915 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 2563 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 1837 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 1717 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 1608 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 1995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 1694 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 1307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 1362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 1075 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 796 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 483 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 429 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 337 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 271 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 211 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 144 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 223 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 134 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 79 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 85 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 82 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 87477 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 252.493341 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 140.519371 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 314.341475 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 45925 52.50% 52.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16983 19.41% 71.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 5819 6.65% 78.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3357 3.84% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2775 3.17% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 1460 1.67% 87.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 948 1.08% 88.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 995 1.14% 89.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9215 10.53% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 87477 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 6395 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 30.205629 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 580.308341 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 6393 99.97% 99.97% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::2048-4095 1 0.02% 99.98% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::45056-47103 1 0.02% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 6395 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 6395 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 23.760751 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.753987 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 37.694415 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-31 6028 94.26% 94.26% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-47 95 1.49% 95.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-63 28 0.44% 96.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-79 10 0.16% 96.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::80-95 24 0.38% 96.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::96-111 40 0.63% 97.34% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::112-127 30 0.47% 97.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-143 13 0.20% 98.01% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::144-159 18 0.28% 98.30% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::160-175 5 0.08% 98.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::176-191 23 0.36% 98.73% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::192-207 21 0.33% 99.06% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::208-223 7 0.11% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::224-239 3 0.05% 99.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::240-255 2 0.03% 99.25% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::256-271 5 0.08% 99.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::272-287 3 0.05% 99.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::288-303 2 0.03% 99.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::304-319 3 0.05% 99.45% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::320-335 7 0.11% 99.56% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::336-351 6 0.09% 99.66% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::352-367 11 0.17% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::368-383 1 0.02% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::384-399 2 0.03% 99.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::480-495 2 0.03% 99.91% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::512-527 2 0.03% 99.94% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::528-543 3 0.05% 99.98% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::688-703 1 0.02% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 6395 # Writes before turning the bus around for reads -system.physmem.totQLat 6824061250 # Total ticks spent queuing -system.physmem.totMemAccLat 10445923750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 965830000 # Total ticks spent in databus transfers -system.physmem.avgQLat 35327.45 # Average queueing delay per DRAM burst +system.physmem.wrQLenPdf::15 2665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 3161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4593 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5057 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 6102 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 6711 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 8346 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 8856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 10182 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 9756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 9787 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 9219 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 9902 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 11207 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 9191 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 8461 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 7930 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 662 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 456 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 371 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 274 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 202 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 167 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 189 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 143 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 119 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 155 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 169 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 118 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 127 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 105 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 77 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 71 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 68 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 67 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 89 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 86 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 15 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 40 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 90794 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 238.541225 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 134.856216 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 301.373578 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 48956 53.92% 53.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 17750 19.55% 73.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6013 6.62% 80.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3452 3.80% 83.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2808 3.09% 86.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 1564 1.72% 88.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 893 0.98% 89.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 995 1.10% 90.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 8363 9.21% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 90794 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 7077 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 27.872686 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 551.008017 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 7075 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::2048-4095 1 0.01% 99.99% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::45056-47103 1 0.01% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 7077 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 7077 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 19.945175 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.553311 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 11.579174 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 5904 83.43% 83.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 368 5.20% 88.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 217 3.07% 91.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 59 0.83% 92.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 82 1.16% 93.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 159 2.25% 95.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 25 0.35% 96.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 12 0.17% 96.45% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 13 0.18% 96.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 11 0.16% 96.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 10 0.14% 96.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 6 0.08% 97.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 165 2.33% 99.35% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 6 0.08% 99.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.04% 99.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 6 0.08% 99.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.01% 99.58% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::88-91 3 0.04% 99.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 3 0.04% 99.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::96-99 2 0.03% 99.69% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.01% 99.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::104-107 1 0.01% 99.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.01% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 10 0.14% 99.87% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.01% 99.89% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::148-151 1 0.01% 99.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.01% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::164-167 5 0.07% 99.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::176-179 1 0.01% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 7077 # Writes before turning the bus around for reads +system.physmem.totQLat 6986626052 # Total ticks spent queuing +system.physmem.totMemAccLat 10685194802 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 986285000 # Total ticks spent in databus transfers +system.physmem.avgQLat 35418.90 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 54077.45 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 4.71 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 3.70 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 4.64 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 4.18 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 54168.90 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 4.81 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 3.44 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 4.74 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 3.44 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 0.07 # Data bus utilization in percentage +system.physmem.busUtil 0.06 # Data bus utilization in percentage system.physmem.busUtilRead 0.04 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.03 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.02 # Average read queue length when enqueuing -system.physmem.avgWrQLen 27.24 # Average write queue length when enqueuing -system.physmem.readRowHits 161531 # Number of row buffer hits during reads -system.physmem.writeRowHits 96107 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.62 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 63.24 # Row buffer hit rate for writes -system.physmem.avgGap 7118240.48 # Average gap between requests -system.physmem.pageHitRate 74.65 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 340124400 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 185583750 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 783673800 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 502511040 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 74898468540 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1509525073500 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1757712204390 # Total energy per rank (pJ) -system.physmem_0.averagePower 669.508799 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2511124862587 # Time in different power states -system.physmem_0.memoryStateTime::REF 87667060000 # Time in different power states +system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing +system.physmem.avgWrQLen 26.34 # Average write queue length when enqueuing +system.physmem.readRowHits 164764 # Number of row buffer hits during reads +system.physmem.writeRowHits 82850 # Number of row buffer hits during writes +system.physmem.readRowHitRate 83.53 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 58.69 # Row buffer hit rate for writes +system.physmem.avgGap 7665878.31 # Average gap between requests +system.physmem.pageHitRate 73.17 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 357081480 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 194836125 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 802081800 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 470396160 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 75099546585 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1509358032750 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1757759761380 # Total energy per rank (pJ) +system.physmem_0.averagePower 669.522942 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2510844795677 # Time in different power states +system.physmem_0.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 26583898663 # Time in different power states +system.physmem_0.memoryStateTime::ACT 26879018073 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 321201720 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 175258875 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 723013200 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 482124960 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 171476769360 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 74441693340 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1509925753500 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1757545814955 # Total energy per rank (pJ) -system.physmem_1.averagePower 669.445422 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2511799542258 # Time in different power states -system.physmem_1.memoryStateTime::REF 87667060000 # Time in different power states +system.physmem_1.actEnergy 329321160 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 179689125 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 736515000 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 444268800 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 171477786480 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 74435410800 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1509940608000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1757543599365 # Total energy per rank (pJ) +system.physmem_1.averagePower 669.440607 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2511823665901 # Time in different power states +system.physmem_1.memoryStateTime::REF 87667580000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 25911565742 # Time in different power states +system.physmem_1.memoryStateTime::ACT 25903669599 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 128 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 192 # Number of bytes read from this memory @@ -365,15 +366,15 @@ system.cf0.dma_read_txs 1 # Nu system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes. system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 631 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 22612465 # Number of BP lookups -system.cpu0.branchPred.condPredicted 14651481 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 907853 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 13732961 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 10133003 # Number of BTB hits +system.cpu0.branchPred.lookups 51763361 # Number of BP lookups +system.cpu0.branchPred.condPredicted 23412597 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 921572 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 31250401 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 23297364 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 73.786003 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 3723828 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 29274 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 74.550608 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 15315613 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29376 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu0.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -404,80 +405,80 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 61748 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 61748 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 23984 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18764 # Level at which table walker walks with short descriptors terminate -system.cpu0.dtb.walker.walksSquashedBefore 19000 # Table walks squashed before starting -system.cpu0.dtb.walker.walkWaitTime::samples 42748 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::mean 436.289417 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::stdev 2694.039371 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0-8191 41732 97.62% 97.62% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::8192-16383 726 1.70% 99.32% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::16384-24575 177 0.41% 99.74% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::24576-32767 77 0.18% 99.92% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::32768-40959 11 0.03% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::40960-49151 19 0.04% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::49152-57343 4 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::57344-65535 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::98304-106495 1 0.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 42748 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkCompletionTime::samples 15024 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::mean 8664.869276 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::gmean 7136.607726 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::stdev 7119.581025 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::0-16383 14229 94.71% 94.71% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::16384-32767 745 4.96% 99.67% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::32768-49151 26 0.17% 99.84% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::81920-98303 4 0.03% 99.87% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::98304-114687 3 0.02% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::131072-147455 16 0.11% 99.99% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::180224-196607 1 0.01% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walkCompletionTime::total 15024 # Table walker service (enqueue to completion) latency -system.cpu0.dtb.walker.walksPending::samples 87051634064 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 0.443285 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::stdev 0.503059 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0-1 87007241564 99.95% 99.95% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::2-3 33256500 0.04% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::4-5 5843000 0.01% 99.99% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::6-7 2996500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::8-9 874000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::10-11 581000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::12-13 581000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::14-15 249500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::16-17 11000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 87051634064 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 5088 77.48% 77.48% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1479 22.52% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 6567 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 61748 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 63347 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 63347 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walksShortTerminationLevel::Level1 24259 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksShortTerminationLevel::Level2 18763 # Level at which table walker walks with short descriptors terminate +system.cpu0.dtb.walker.walksSquashedBefore 20325 # Table walks squashed before starting +system.cpu0.dtb.walker.walkWaitTime::samples 43022 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::mean 472.792990 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::stdev 2838.942862 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0-8191 41882 97.35% 97.35% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::8192-16383 877 2.04% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::16384-24575 115 0.27% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::24576-32767 113 0.26% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::32768-40959 6 0.01% 99.93% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::40960-49151 23 0.05% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::49152-57343 2 0.00% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::57344-65535 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::65536-73727 2 0.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 43022 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkCompletionTime::samples 16160 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::mean 9833.168317 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::gmean 8304.443400 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::stdev 6846.428458 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::0-16383 15169 93.87% 93.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::16384-32767 911 5.64% 99.50% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::32768-49151 54 0.33% 99.84% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::49152-65535 3 0.02% 99.86% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::81920-98303 2 0.01% 99.87% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::98304-114687 20 0.12% 99.99% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::196608-212991 1 0.01% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walkCompletionTime::total 16160 # Table walker service (enqueue to completion) latency +system.cpu0.dtb.walker.walksPending::samples 95658285656 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 0.461466 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::stdev 0.505385 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0-1 95607533656 99.95% 99.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::2-3 37952000 0.04% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::4-5 6012000 0.01% 99.99% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::6-7 3722000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::8-9 1321500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::10-11 760000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::12-13 604000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::14-15 360500 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::16-17 20000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 95658285656 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 5176 77.00% 77.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1546 23.00% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 6722 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 63347 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 61748 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6567 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 63347 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 6722 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6567 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 68315 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 6722 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 70069 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 16748968 # DTB read hits -system.cpu0.dtb.read_misses 52995 # DTB read misses -system.cpu0.dtb.write_hits 13907664 # DTB write hits -system.cpu0.dtb.write_misses 8753 # DTB write misses +system.cpu0.dtb.read_hits 22737235 # DTB read hits +system.cpu0.dtb.read_misses 54172 # DTB read misses +system.cpu0.dtb.write_hits 16921500 # DTB write hits +system.cpu0.dtb.write_misses 9175 # DTB write misses system.cpu0.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 3489 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 88 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 2047 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 3524 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 141 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 1882 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 843 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 16801963 # DTB read accesses -system.cpu0.dtb.write_accesses 13916417 # DTB write accesses +system.cpu0.dtb.perms_faults 854 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 22791407 # DTB read accesses +system.cpu0.dtb.write_accesses 16930675 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 30656632 # DTB hits -system.cpu0.dtb.misses 61748 # DTB misses -system.cpu0.dtb.accesses 30718380 # DTB accesses +system.cpu0.dtb.hits 39658735 # DTB hits +system.cpu0.dtb.misses 63347 # DTB misses +system.cpu0.dtb.accesses 39722082 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -507,56 +508,62 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 9874 # Table walker walks requested -system.cpu0.itb.walker.walksShort 9874 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walksShortTerminationLevel::Level1 3715 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6056 # Level at which table walker walks with short descriptors terminate -system.cpu0.itb.walker.walksSquashedBefore 103 # Table walks squashed before starting -system.cpu0.itb.walker.walkWaitTime::samples 9771 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::mean 366.390339 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::stdev 1951.164851 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0-4095 9421 96.42% 96.42% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::4096-8191 224 2.29% 98.71% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::8192-12287 80 0.82% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::12288-16383 17 0.17% 99.70% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::16384-20479 13 0.13% 99.84% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::20480-24575 5 0.05% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::24576-28671 4 0.04% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::28672-32767 6 0.06% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::32768-36863 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 9771 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkCompletionTime::samples 2691 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::mean 9965.812709 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::gmean 8554.132900 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::stdev 5681.325139 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::0-8191 1024 38.05% 38.05% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::8192-16383 1554 57.75% 95.80% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::16384-24575 43 1.60% 97.40% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::24576-32767 63 2.34% 99.74% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::32768-40959 4 0.15% 99.89% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::40960-49151 2 0.07% 99.96% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 100.00% # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walkCompletionTime::total 2691 # Table walker service (enqueue to completion) latency -system.cpu0.itb.walker.walksPending::samples 18106130328 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 0.976227 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::stdev 0.152552 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 430953000 2.38% 2.38% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 17674714828 97.62% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::2 401500 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::3 61000 0.00% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 18106130328 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 2271 87.75% 87.75% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 317 12.25% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walks 10275 # Table walker walks requested +system.cpu0.itb.walker.walksShort 10275 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walksShortTerminationLevel::Level1 4076 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksShortTerminationLevel::Level2 6085 # Level at which table walker walks with short descriptors terminate +system.cpu0.itb.walker.walksSquashedBefore 114 # Table walks squashed before starting +system.cpu0.itb.walker.walkWaitTime::samples 10161 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::mean 480.267690 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::stdev 2390.213266 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0-4095 9738 95.84% 95.84% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::4096-8191 133 1.31% 97.15% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::8192-12287 215 2.12% 99.26% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::12288-16383 37 0.36% 99.63% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::16384-20479 9 0.09% 99.71% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::20480-24575 15 0.15% 99.86% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::24576-28671 3 0.03% 99.89% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::28672-32767 3 0.03% 99.92% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::32768-36863 2 0.02% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::36864-40959 4 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::40960-45055 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::45056-49151 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 10161 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkCompletionTime::samples 2702 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::mean 11438.934123 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::gmean 10140.740913 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::stdev 6204.580963 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::0-8191 871 32.24% 32.24% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::8192-16383 1681 62.21% 94.45% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::16384-24575 53 1.96% 96.41% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::24576-32767 85 3.15% 99.56% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::32768-40959 7 0.26% 99.81% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::40960-49151 1 0.04% 99.85% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::49152-57343 1 0.04% 99.89% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::81920-90111 1 0.04% 99.93% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::90112-98303 1 0.04% 99.96% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::98304-106495 1 0.04% 100.00% # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walkCompletionTime::total 2702 # Table walker service (enqueue to completion) latency +system.cpu0.itb.walker.walksPending::samples 22643799124 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 0.979659 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::stdev 0.141451 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 461404000 2.04% 2.04% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 22181693124 97.96% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::2 593000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::3 109000 0.00% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 22643799124 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 2268 87.64% 87.64% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 320 12.36% 100.00% # Table walker page sizes translated system.cpu0.itb.walker.walkPageSizes::total 2588 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 9874 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 9874 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 10275 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 10275 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 2588 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::total 2588 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 12462 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 35678798 # ITB inst hits -system.cpu0.itb.inst_misses 9874 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin::total 12863 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 70928349 # ITB inst hits +system.cpu0.itb.inst_misses 10275 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -565,1020 +572,1041 @@ system.cpu0.itb.flush_tlb 66 # Nu system.cpu0.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2368 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2365 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1932 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1936 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 35688672 # ITB inst accesses -system.cpu0.itb.hits 35678798 # DTB hits -system.cpu0.itb.misses 9874 # DTB misses -system.cpu0.itb.accesses 35688672 # DTB accesses -system.cpu0.numCycles 121733824 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 70938624 # ITB inst accesses +system.cpu0.itb.hits 70928349 # DTB hits +system.cpu0.itb.misses 10275 # DTB misses +system.cpu0.itb.accesses 70938624 # DTB accesses +system.cpu0.numCycles 192976868 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 17621783 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 106366119 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 22612465 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 13856831 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 98711813 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2650530 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 130938 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.MiscStallCycles 54154 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 345087 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 416739 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 73296 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 35679429 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 256075 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 4180 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 118679075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.081251 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 1.263308 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 19363908 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 190332929 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 51763361 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 38612977 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 166709106 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 5608958 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 145099 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.MiscStallCycles 54692 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 348676 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 420281 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 85262 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 70928958 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 257958 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 4691 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 189931503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.225932 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 1.310916 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 59721044 50.32% 50.32% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 20146281 16.98% 67.30% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 8259650 6.96% 74.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 30552100 25.74% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 88125904 46.40% 46.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 29232702 15.39% 61.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 14108338 7.43% 69.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 58464559 30.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 118679075 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.185753 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.873760 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 18470879 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 55646585 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 38814384 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 4744194 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1003033 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 2910392 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 326287 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 104430369 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 3709386 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1003033 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 23916141 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 11897059 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 33727750 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 37986661 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 10148431 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 99624170 # Number of instructions processed by rename -system.cpu0.rename.SquashedInsts 979348 # Number of squashed instructions processed by rename -system.cpu0.rename.ROBFullEvents 1380369 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 148421 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LQFullEvents 51935 # Number of times rename has blocked due to LQ full -system.cpu0.rename.SQFullEvents 6127142 # Number of times rename has blocked due to SQ full -system.cpu0.rename.RenamedOperands 103189966 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 455330287 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 114159594 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 9381 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 92428419 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 10761544 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 1188796 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 1051388 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 11830283 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 17680232 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 15386939 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1636462 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 2175060 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 96814528 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1636038 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 95024919 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 451413 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 8911325 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 20849804 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 116309 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 118679075 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.800688 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.033122 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 189931503 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.268236 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.986299 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 24608865 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 101406874 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 56677604 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 4757932 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2480228 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 2944179 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 328448 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 148845488 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 3759445 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 2480228 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 33020653 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 11928133 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 79389996 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 52895431 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 10217062 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 132354164 # Number of instructions processed by rename +system.cpu0.rename.SquashedInsts 1007004 # Number of squashed instructions processed by rename +system.cpu0.rename.ROBFullEvents 1382043 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 149840 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LQFullEvents 52195 # Number of times rename has blocked due to LQ full +system.cpu0.rename.SQFullEvents 6188026 # Number of times rename has blocked due to SQ full +system.cpu0.rename.RenamedOperands 135879963 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 611395498 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 146969281 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 9373 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 124973310 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10906650 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 2656416 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 2518561 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 22027855 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 23660512 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 18424443 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1639164 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 2432445 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 129487187 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1661777 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 127665829 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 454854 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10484678 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 21309646 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 116701 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 189931503 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.672168 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 0.963951 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 65546472 55.23% 55.23% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 22156727 18.67% 73.90% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 21116341 17.79% 91.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 8802658 7.42% 99.11% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1056849 0.89% 100.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 28 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 116041258 61.10% 61.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 32572628 17.15% 78.25% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 29941917 15.76% 94.01% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 10293469 5.42% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1082195 0.57% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 36 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 118679075 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 189931503 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 8808229 40.49% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 130 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 40.49% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 5336848 24.53% 65.02% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 7610455 34.98% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 10298963 43.90% 43.90% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 129 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 43.91% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 5415712 23.09% 66.99% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 7742693 33.01% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 2272 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 62565826 65.84% 65.84% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 87588 0.09% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 1 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 7159 0.01% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 65.94% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 17417081 18.33% 84.27% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 14944992 15.73% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 86175456 67.50% 67.50% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 106512 0.08% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 7179 0.01% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.59% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 23410232 18.34% 85.93% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 17964178 14.07% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 95024919 # Type of FU issued -system.cpu0.iq.rate 0.780596 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 21755662 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.228947 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 330903688 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 107369307 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 93061278 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 32300 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 11278 # Number of floating instruction queue writes +system.cpu0.iq.FU_type_0::total 127665829 # Type of FU issued +system.cpu0.iq.rate 0.661560 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 23457497 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.183741 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 469142790 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 141641253 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 124187141 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 32722 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 11272 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 9724 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 116757282 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 21027 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 347087 # Number of loads that had data forwarded from stores +system.cpu0.iq.int_alu_accesses 151099696 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 21358 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 349091 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1857425 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2513 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 18755 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 953252 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1883461 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2555 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 18950 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 972383 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 101364 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 327888 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 113459 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 340118 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1003033 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 1539075 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 172884 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 98621711 # Number of instructions dispatched to IQ +system.cpu0.iew.iewSquashCycles 2480228 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 1536268 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 176000 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 131320075 # Number of instructions dispatched to IQ system.cpu0.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 17680232 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 15386939 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 849096 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 24467 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 126834 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 18755 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 265533 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 373430 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 638963 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 94008948 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 16992930 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 954343 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewDispLoadInsts 23660512 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 18424443 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 851631 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 275041 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 650454 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 171145 # number of nop insts executed -system.cpu0.iew.exec_refs 31760151 # number of memory reference insts executed -system.cpu0.iew.exec_branches 15805524 # Number of branches executed -system.cpu0.iew.exec_stores 14767221 # Number of stores executed -system.cpu0.iew.exec_rate 0.772250 # Inst execution rate -system.cpu0.iew.wb_sent 93501427 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 93071002 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 48393961 # num instructions producing a value -system.cpu0.iew.wb_consumers 79995949 # num instructions consuming a value +system.cpu0.iew.exec_nop 171111 # number of nop insts executed +system.cpu0.iew.exec_refs 40767921 # number of memory reference insts executed +system.cpu0.iew.exec_branches 24572908 # Number of branches executed +system.cpu0.iew.exec_stores 17785097 # Number of stores executed +system.cpu0.iew.exec_rate 0.656213 # Inst execution rate +system.cpu0.iew.wb_sent 126104266 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 124196865 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 63208416 # num instructions producing a value +system.cpu0.iew.wb_consumers 102222094 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.764545 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.604955 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.643584 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.618344 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 7948634 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 1519729 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 585621 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 117035605 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766100 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.480781 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 9488534 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 1545076 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 597321 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 186809549 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.646573 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.344397 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 75174289 64.23% 64.23% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 23319780 19.93% 84.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 7849886 6.71% 90.86% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 3044520 2.60% 93.47% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 3180912 2.72% 96.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 1406827 1.20% 97.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 1102407 0.94% 98.33% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 520278 0.44% 98.77% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1436706 1.23% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 128903317 69.00% 69.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 31993486 17.13% 86.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 12242174 6.55% 92.68% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 3077822 1.65% 94.33% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 4650551 2.49% 96.82% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 2601023 1.39% 98.21% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 1367878 0.73% 98.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 526295 0.28% 99.23% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1447003 0.77% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 117035605 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 74499569 # Number of instructions committed -system.cpu0.commit.committedOps 89660931 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 186809549 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 99693903 # Number of instructions committed +system.cpu0.commit.committedOps 120785976 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 30256494 # Number of memory references committed -system.cpu0.commit.loads 15822807 # Number of loads committed -system.cpu0.commit.membars 627513 # Number of memory barriers committed -system.cpu0.commit.branches 15208996 # Number of branches committed +system.cpu0.commit.refs 39229111 # Number of memory references committed +system.cpu0.commit.loads 21777051 # Number of loads committed +system.cpu0.commit.membars 629182 # Number of memory barriers committed +system.cpu0.commit.branches 23976855 # Number of branches committed system.cpu0.commit.fp_insts 9708 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 77458658 # Number of committed integer instructions. -system.cpu0.commit.function_calls 1847857 # Number of function calls committed. +system.cpu0.commit.int_insts 105625598 # Number of committed integer instructions. +system.cpu0.commit.function_calls 4749745 # Number of function calls committed. system.cpu0.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu0.commit.op_class_0::IntAlu 59311896 66.15% 66.15% # Class of committed instruction -system.cpu0.commit.op_class_0::IntMult 85382 0.10% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::IntDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShift 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMisc 7159 0.01% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.25% # Class of committed instruction -system.cpu0.commit.op_class_0::MemRead 15822807 17.65% 83.90% # Class of committed instruction -system.cpu0.commit.op_class_0::MemWrite 14433687 16.10% 100.00% # Class of committed instruction +system.cpu0.commit.op_class_0::IntAlu 81445291 67.43% 67.43% # Class of committed instruction +system.cpu0.commit.op_class_0::IntMult 104395 0.09% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::IntDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShift 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMisc 7179 0.01% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.52% # Class of committed instruction +system.cpu0.commit.op_class_0::MemRead 21777051 18.03% 85.55% # Class of committed instruction +system.cpu0.commit.op_class_0::MemWrite 17452060 14.45% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu0.commit.op_class_0::total 89660931 # Class of committed instruction -system.cpu0.commit.bw_lim_events 1436706 # number cycles where commit BW limit reached -system.cpu0.rob.rob_reads 209187674 # The number of ROB reads -system.cpu0.rob.rob_writes 196861250 # The number of ROB writes -system.cpu0.timesIdled 121559 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 3054749 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5129022957 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 74377875 # Number of Instructions Simulated -system.cpu0.committedOps 89539237 # Number of Ops (including micro ops) Simulated -system.cpu0.cpi 1.636694 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 1.636694 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.610988 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.610988 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 104549028 # number of integer regfile reads -system.cpu0.int_regfile_writes 56469550 # number of integer regfile writes -system.cpu0.fp_regfile_reads 8161 # number of floating regfile reads +system.cpu0.commit.op_class_0::total 120785976 # Class of committed instruction +system.cpu0.commit.bw_lim_events 1447003 # number cycles where commit BW limit reached +system.cpu0.rob.rob_reads 292572702 # The number of ROB reads +system.cpu0.rob.rob_writes 263669539 # The number of ROB writes +system.cpu0.timesIdled 123127 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 3045365 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5057813082 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 99572209 # Number of Instructions Simulated +system.cpu0.committedOps 120664282 # Number of Ops (including micro ops) Simulated +system.cpu0.cpi 1.938060 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 1.938060 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.515980 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.515980 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 137228019 # number of integer regfile reads +system.cpu0.int_regfile_writes 78727155 # number of integer regfile writes +system.cpu0.fp_regfile_reads 8192 # number of floating regfile reads system.cpu0.fp_regfile_writes 2264 # number of floating regfile writes -system.cpu0.cc_regfile_reads 331224109 # number of cc regfile reads -system.cpu0.cc_regfile_writes 38421528 # number of cc regfile writes -system.cpu0.misc_regfile_reads 166953922 # number of misc regfile reads -system.cpu0.misc_regfile_writes 1191250 # number of misc regfile writes -system.cpu0.dcache.tags.replacements 674914 # number of replacements -system.cpu0.dcache.tags.tagsinuse 486.328727 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 27281228 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 675426 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 40.391143 # Average number of references to valid blocks. -system.cpu0.dcache.tags.warmup_cycle 277646000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 486.328727 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.949861 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.949861 # Average percentage of cache occupancy +system.cpu0.cc_regfile_reads 446969794 # number of cc regfile reads +system.cpu0.cc_regfile_writes 47254034 # number of cc regfile writes +system.cpu0.misc_regfile_reads 263157526 # number of misc regfile reads +system.cpu0.misc_regfile_writes 1194331 # number of misc regfile writes +system.cpu0.dcache.tags.replacements 673421 # number of replacements +system.cpu0.dcache.tags.tagsinuse 483.801587 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 36230548 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 673933 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 53.759866 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 274448500 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.801587 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.944925 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.944925 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 191 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 21 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 180 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 310 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 22 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 60112887 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 60112887 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 14700771 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 14700771 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 11392924 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 11392924 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 295732 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 295732 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354072 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 354072 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 350987 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 350987 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 26093695 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 26093695 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 26389427 # number of overall hits -system.cpu0.dcache.overall_hits::total 26389427 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 607182 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 607182 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1803068 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1803068 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141599 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 141599 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24346 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 24346 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21181 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21181 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 2410250 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2410250 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 2551849 # number of overall misses -system.cpu0.dcache.overall_misses::total 2551849 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8154354688 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 8154354688 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26135736531 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 26135736531 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 384171142 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 384171142 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 484170513 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 484170513 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 824000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.StoreCondFailReq_miss_latency::total 824000 # number of StoreCondFailReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34290091219 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34290091219 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34290091219 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34290091219 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 15307953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 15307953 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 13195992 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 13195992 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 437331 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.SoftPFReq_accesses::total 437331 # number of SoftPFReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 378418 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 378418 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372168 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 372168 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 28503945 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 28503945 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 28941276 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 28941276 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.039664 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.039664 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.136638 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.136638 # miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323780 # miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323780 # miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064336 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064336 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056912 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056912 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.084558 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.084558 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.088173 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.088173 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13429.836010 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13429.836010 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14495.147455 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 14495.147455 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15779.641091 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15779.641091 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22858.718332 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22858.718332 # average StoreCondReq miss latency +system.cpu0.dcache.tags.tag_accesses 78023145 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 78023145 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 20647656 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 20647656 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 14394101 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 14394101 # number of WriteReq hits +system.cpu0.dcache.SoftPFReq_hits::cpu0.data 296444 # number of SoftPFReq hits +system.cpu0.dcache.SoftPFReq_hits::total 296444 # number of SoftPFReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 354739 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 354739 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 351671 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 351671 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 35041757 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 35041757 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 35338201 # number of overall hits +system.cpu0.dcache.overall_hits::total 35338201 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 609728 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 609728 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1806132 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1806132 # number of WriteReq misses +system.cpu0.dcache.SoftPFReq_misses::cpu0.data 141710 # number of SoftPFReq misses +system.cpu0.dcache.SoftPFReq_misses::total 141710 # number of SoftPFReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 24359 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 24359 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 21165 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 21165 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 2415860 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 2415860 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 2557570 # number of overall misses +system.cpu0.dcache.overall_misses::total 2557570 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8120126000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8120126000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 26313440366 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 26313440366 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 385463000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 385463000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 480627500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 480627500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::cpu0.data 430000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.StoreCondFailReq_miss_latency::total 430000 # number of StoreCondFailReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 34433566366 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34433566366 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34433566366 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34433566366 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 21257384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 21257384 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 16200233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 16200233 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 438154 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.SoftPFReq_accesses::total 438154 # number of SoftPFReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 379098 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 379098 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 372836 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 372836 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 37457617 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 37457617 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 37895771 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 37895771 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.028683 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.028683 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.111488 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.111488 # miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.323425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.323425 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.064255 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.064255 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.056768 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.056768 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.064496 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.064496 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.067490 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.067490 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13317.620316 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13317.620316 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 14568.946437 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 14568.946437 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 15824.253869 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 15824.253869 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 22708.599102 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 22708.599102 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::cpu0.data inf # average StoreCondFailReq miss latency system.cpu0.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14226.777811 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 14226.777811 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13437.351199 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 13437.351199 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 781 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3670700 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 43 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 191761 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.162791 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 19.142057 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 14253.129886 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 14253.129886 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 13463.391565 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 13463.391565 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 747 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3913122 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 47 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 192454 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.893617 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.332765 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 492000 # number of writebacks -system.cpu0.dcache.writebacks::total 492000 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 239081 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 239081 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1490741 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1490741 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18153 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18153 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1729822 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1729822 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1729822 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1729822 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 368101 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 368101 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312327 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 312327 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98325 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 98325 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6193 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 21181 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 680428 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 680428 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 778753 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 778753 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 17965 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 34679 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4128121038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4128121038 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5207818329 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5207818329 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1570971031 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1570971031 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 91940502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 91940502 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 451443987 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 451443987 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 794000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 794000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9335939367 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 9335939367 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10906910398 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10906910398 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 3693380750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3693380750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2688166013 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2688166013 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 6381546763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6381546763 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.024046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.024046 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.023668 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224830 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224830 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016366 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016366 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056912 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056912 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.023871 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.023871 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026908 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.026908 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11214.642280 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11214.642280 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 16674.249517 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 16674.249517 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 15977.330598 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 15977.330598 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 14845.874697 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 14845.874697 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21313.629526 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21313.629526 # average StoreCondReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 491417 # number of writebacks +system.cpu0.dcache.writebacks::total 491417 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 243049 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 243049 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1494093 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1494093 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 18165 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 18165 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1737142 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1737142 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1737142 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1737142 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 366679 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 366679 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 312039 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 312039 # number of WriteReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::cpu0.data 98387 # number of SoftPFReq MSHR misses +system.cpu0.dcache.SoftPFReq_mshr_misses::total 98387 # number of SoftPFReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6194 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6194 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 21165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 21165 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 678718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 678718 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 777105 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 777105 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 29394 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 55521 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4291687500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4291687500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5394914387 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5394914387 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu0.data 1614083000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 1614083000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 96183500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 96183500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 459474500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 459474500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 418000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 418000 # number of StoreCondFailReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9686601887 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9686601887 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11300684887 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 11300684887 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 5681056500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 5681056500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 4312326500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 4312326500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 9993383000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 9993383000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.017249 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.017249 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.019261 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.019261 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu0.data 0.224549 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.224549 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.016339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.016339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.056768 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.056768 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.018120 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.018120 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.020506 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.020506 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11704.208586 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11704.208586 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 17289.231112 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 17289.231112 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu0.data 16405.449907 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 16405.449907 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 15528.495318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15528.495318 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 21709.166076 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 21709.166076 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 13720.686637 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 13720.686637 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14005.609478 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14005.609478 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 205587.573059 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 205587.573059 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 160833.194508 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 160833.194508 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 184017.611898 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 184017.611898 # average overall mshr uncacheable latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 14271.909522 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 14271.909522 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 14542.030854 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 14542.030854 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 193272.657685 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193272.657685 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 165052.493589 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 165052.493589 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data 179992.849552 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 179992.849552 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1200530 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.748320 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 34431245 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1201042 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 28.667811 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6414143250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748320 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999508 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999508 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 1208444 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.748718 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 69666115 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 1208956 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 57.625021 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6421480000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.748718 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.999509 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999509 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 133 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 148 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 147 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 72552920 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 72552920 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 34431245 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34431245 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34431245 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34431245 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34431245 # number of overall hits -system.cpu0.icache.overall_hits::total 34431245 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 1244682 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1244682 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 1244682 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1244682 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 1244682 # number of overall misses -system.cpu0.icache.overall_misses::total 1244682 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12221339030 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 12221339030 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 12221339030 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 12221339030 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 12221339030 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 12221339030 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 35675927 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 35675927 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 35675927 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 35675927 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 35675927 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 35675927 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.034889 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.034889 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.034889 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.034889 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.034889 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.034889 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9818.844516 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 9818.844516 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 9818.844516 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9818.844516 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 9818.844516 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1349229 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 432 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 105227 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 11 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 12.822080 # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets 39.272727 # average number of cycles each access was blocked +system.cpu0.icache.tags.tag_accesses 143059850 # Number of tag accesses +system.cpu0.icache.tags.data_accesses 143059850 # Number of data accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 69666115 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 69666115 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 69666115 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 69666115 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 69666115 # number of overall hits +system.cpu0.icache.overall_hits::total 69666115 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 1259322 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1259322 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 1259322 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1259322 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 1259322 # number of overall misses +system.cpu0.icache.overall_misses::total 1259322 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12306647041 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 12306647041 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 12306647041 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 12306647041 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 12306647041 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 12306647041 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 70925437 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 70925437 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 70925437 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 70925437 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 70925437 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 70925437 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.017756 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.017756 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.017756 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.017756 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.017756 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.017756 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 9772.438694 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 9772.438694 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 9772.438694 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 9772.438694 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 9772.438694 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 1459740 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 453 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 110714 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 10 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.184782 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets 45.300000 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 43614 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 43614 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 43614 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 43614 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 43614 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 43614 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1201068 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 1201068 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 1201068 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 1201068 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 1201068 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 1201068 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu0.icache.ReadReq_mshr_uncacheable::total 3002 # number of ReadReq MSHR uncacheable -system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses -system.cpu0.icache.overall_mshr_uncacheable_misses::total 3002 # number of overall MSHR uncacheable misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 10504795288 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 10504795288 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10504795288 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 10504795288 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 10504795288 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 10504795288 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265434748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265434748 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265434748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 265434748 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.033666 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.033666 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.033666 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.033666 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 8746.211945 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 8746.211945 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 8746.211945 # average overall mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average ReadReq mshr uncacheable latency -system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88419.303131 # average ReadReq mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88419.303131 # average overall mshr uncacheable latency -system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88419.303131 # average overall mshr uncacheable latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 50344 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 50344 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 50344 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 50344 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 50344 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 50344 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 1208978 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1208978 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 1208978 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1208978 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 1208978 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1208978 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable +system.cpu0.icache.ReadReq_mshr_uncacheable::total 3004 # number of ReadReq MSHR uncacheable +system.cpu0.icache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses +system.cpu0.icache.overall_mshr_uncacheable_misses::total 3004 # number of overall MSHR uncacheable misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 11179466333 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 11179466333 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 11179466333 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 11179466333 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 11179466333 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 11179466333 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 265874998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 265874998 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 265874998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 265874998 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.017046 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.017046 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.017046 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.017046 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 9247.038683 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 9247.038683 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 9247.038683 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average ReadReq mshr uncacheable latency +system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total 88506.990013 # average ReadReq mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst 88506.990013 # average overall mshr uncacheable latency +system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total 88506.990013 # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l2cache.prefetcher.num_hwpf_issued 1764126 # number of hwpf issued -system.cpu0.l2cache.prefetcher.pfIdentified 1768652 # number of prefetch candidates identified -system.cpu0.l2cache.prefetcher.pfBufferHit 4013 # number of redundant prefetches already in prefetch queue +system.cpu0.l2cache.prefetcher.num_hwpf_issued 1763942 # number of hwpf issued +system.cpu0.l2cache.prefetcher.pfIdentified 1769107 # number of prefetch candidates identified +system.cpu0.l2cache.prefetcher.pfBufferHit 4567 # number of redundant prefetches already in prefetch queue system.cpu0.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu0.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu0.l2cache.prefetcher.pfSpanPage 220332 # number of prefetches not generated due to page crossing -system.cpu0.l2cache.tags.replacements 264213 # number of replacements -system.cpu0.l2cache.tags.tagsinuse 16022.712569 # Cycle average of tags in use -system.cpu0.l2cache.tags.total_refs 2093032 # Total number of references to valid blocks. -system.cpu0.l2cache.tags.sampled_refs 280442 # Sample count of references to valid blocks. -system.cpu0.l2cache.tags.avg_refs 7.463333 # Average number of references to valid blocks. +system.cpu0.l2cache.prefetcher.pfSpanPage 220637 # number of prefetches not generated due to page crossing +system.cpu0.l2cache.tags.replacements 266650 # number of replacements +system.cpu0.l2cache.tags.tagsinuse 16052.098762 # Cycle average of tags in use +system.cpu0.l2cache.tags.total_refs 3449668 # Total number of references to valid blocks. +system.cpu0.l2cache.tags.sampled_refs 282876 # Sample count of references to valid blocks. +system.cpu0.l2cache.tags.avg_refs 12.194983 # Average number of references to valid blocks. system.cpu0.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l2cache.tags.occ_blocks::writebacks 9357.549400 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 12.830885 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.990255 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 3887.194071 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1642.708300 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1121.439658 # Average occupied blocks per requestor -system.cpu0.l2cache.tags.occ_percent::writebacks 0.571139 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000783 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000060 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.237255 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.100263 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.068447 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_percent::total 0.977949 # Average percentage of cache occupancy -system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1027 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1023 8 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15194 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 39 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 304 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 426 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 258 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 3 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 5 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 450 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4677 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7327 # Occupied blocks per task id -system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2684 # Occupied blocks per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.062683 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000488 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.927368 # Percentage of cache occupancy per task id -system.cpu0.l2cache.tags.tag_accesses 41624222 # Number of tag accesses -system.cpu0.l2cache.tags.data_accesses 41624222 # Number of data accesses -system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 49855 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 11685 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.inst 1152127 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::cpu0.data 374018 # number of ReadReq hits -system.cpu0.l2cache.ReadReq_hits::total 1587685 # number of ReadReq hits -system.cpu0.l2cache.Writeback_hits::writebacks 491993 # number of Writeback hits -system.cpu0.l2cache.Writeback_hits::total 491993 # number of Writeback hits -system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28477 # number of UpgradeReq hits -system.cpu0.l2cache.UpgradeReq_hits::total 28477 # number of UpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1602 # number of SCUpgradeReq hits -system.cpu0.l2cache.SCUpgradeReq_hits::total 1602 # number of SCUpgradeReq hits -system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210193 # number of ReadExReq hits -system.cpu0.l2cache.ReadExReq_hits::total 210193 # number of ReadExReq hits -system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 49855 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.itb.walker 11685 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.inst 1152127 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::cpu0.data 584211 # number of demand (read+write) hits -system.cpu0.l2cache.demand_hits::total 1797878 # number of demand (read+write) hits -system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 49855 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.itb.walker 11685 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.inst 1152127 # number of overall hits -system.cpu0.l2cache.overall_hits::cpu0.data 584211 # number of overall hits -system.cpu0.l2cache.overall_hits::total 1797878 # number of overall hits -system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 397 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 143 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.inst 48926 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::cpu0.data 98504 # number of ReadReq misses -system.cpu0.l2cache.ReadReq_misses::total 147970 # number of ReadReq misses -system.cpu0.l2cache.Writeback_misses::writebacks 2 # number of Writeback misses -system.cpu0.l2cache.Writeback_misses::total 2 # number of Writeback misses -system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27483 # number of UpgradeReq misses -system.cpu0.l2cache.UpgradeReq_misses::total 27483 # number of UpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19577 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeReq_misses::total 19577 # number of SCUpgradeReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.SCUpgradeFailReq_misses::total 2 # number of SCUpgradeFailReq misses -system.cpu0.l2cache.ReadExReq_misses::cpu0.data 46426 # number of ReadExReq misses -system.cpu0.l2cache.ReadExReq_misses::total 46426 # number of ReadExReq misses -system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 397 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.itb.walker 143 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.inst 48926 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::cpu0.data 144930 # number of demand (read+write) misses -system.cpu0.l2cache.demand_misses::total 194396 # number of demand (read+write) misses -system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 397 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.itb.walker 143 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.inst 48926 # number of overall misses -system.cpu0.l2cache.overall_misses::cpu0.data 144930 # number of overall misses -system.cpu0.l2cache.overall_misses::total 194396 # number of overall misses -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 10907493 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 3478500 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.inst 2401346947 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::cpu0.data 2853426397 # number of ReadReq miss cycles -system.cpu0.l2cache.ReadReq_miss_latency::total 5269159337 # number of ReadReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 505786782 # number of UpgradeReq miss cycles -system.cpu0.l2cache.UpgradeReq_miss_latency::total 505786782 # number of UpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 394596383 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 394596383 # number of SCUpgradeReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 773499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 773499 # number of SCUpgradeFailReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2617489063 # number of ReadExReq miss cycles -system.cpu0.l2cache.ReadExReq_miss_latency::total 2617489063 # number of ReadExReq miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 10907493 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 3478500 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2401346947 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::cpu0.data 5470915460 # number of demand (read+write) miss cycles -system.cpu0.l2cache.demand_miss_latency::total 7886648400 # number of demand (read+write) miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 10907493 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 3478500 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2401346947 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::cpu0.data 5470915460 # number of overall miss cycles -system.cpu0.l2cache.overall_miss_latency::total 7886648400 # number of overall miss cycles -system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50252 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 11828 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.inst 1201053 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::cpu0.data 472522 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.ReadReq_accesses::total 1735655 # number of ReadReq accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::writebacks 491995 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.Writeback_accesses::total 491995 # number of Writeback accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55960 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.UpgradeReq_accesses::total 55960 # number of UpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21179 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeReq_accesses::total 21179 # number of SCUpgradeReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 2 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256619 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.ReadExReq_accesses::total 256619 # number of ReadExReq accesses(hits+misses) -system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50252 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 11828 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.inst 1201053 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::cpu0.data 729141 # number of demand (read+write) accesses -system.cpu0.l2cache.demand_accesses::total 1992274 # number of demand (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50252 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 11828 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.inst 1201053 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::cpu0.data 729141 # number of overall (read+write) accesses -system.cpu0.l2cache.overall_accesses::total 1992274 # number of overall (read+write) accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.012090 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.inst 0.040736 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::cpu0.data 0.208464 # miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_miss_rate::total 0.085253 # miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_miss_rate::writebacks 0.000004 # miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_miss_rate::total 0.000004 # miss rate for Writeback accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.491119 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.491119 # miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924359 # miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924359 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.tags.occ_blocks::writebacks 9287.877050 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.dtb.walker 13.757624 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.itb.walker 0.215297 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.inst 4106.053527 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.data 1602.376504 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_blocks::cpu0.l2cache.prefetcher 1041.818760 # Average occupied blocks per requestor +system.cpu0.l2cache.tags.occ_percent::writebacks 0.566887 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.dtb.walker 0.000840 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.inst 0.250614 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.data 0.097801 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::cpu0.l2cache.prefetcher 0.063588 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_percent::total 0.979742 # Average percentage of cache occupancy +system.cpu0.l2cache.tags.occ_task_id_blocks::1022 1056 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1023 12 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_blocks::1024 15158 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::1 44 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::2 321 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::3 415 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1022::4 276 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::2 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1023::3 6 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::1 414 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::2 4651 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::3 7186 # Occupied blocks per task id +system.cpu0.l2cache.tags.age_task_id_blocks_1024::4 2852 # Occupied blocks per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1022 0.064453 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1023 0.000732 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.occ_task_id_percent::1024 0.925171 # Percentage of cache occupancy per task id +system.cpu0.l2cache.tags.tag_accesses 63497786 # Number of tag accesses +system.cpu0.l2cache.tags.data_accesses 63497786 # Number of data accesses +system.cpu0.l2cache.ReadReq_hits::cpu0.dtb.walker 50315 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::cpu0.itb.walker 12479 # number of ReadReq hits +system.cpu0.l2cache.ReadReq_hits::total 62794 # number of ReadReq hits +system.cpu0.l2cache.Writeback_hits::writebacks 491416 # number of Writeback hits +system.cpu0.l2cache.Writeback_hits::total 491416 # number of Writeback hits +system.cpu0.l2cache.UpgradeReq_hits::cpu0.data 28453 # number of UpgradeReq hits +system.cpu0.l2cache.UpgradeReq_hits::total 28453 # number of UpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::cpu0.data 1608 # number of SCUpgradeReq hits +system.cpu0.l2cache.SCUpgradeReq_hits::total 1608 # number of SCUpgradeReq hits +system.cpu0.l2cache.ReadExReq_hits::cpu0.data 210730 # number of ReadExReq hits +system.cpu0.l2cache.ReadExReq_hits::total 210730 # number of ReadExReq hits +system.cpu0.l2cache.ReadCleanReq_hits::cpu0.inst 1158323 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadCleanReq_hits::total 1158323 # number of ReadCleanReq hits +system.cpu0.l2cache.ReadSharedReq_hits::cpu0.data 372689 # number of ReadSharedReq hits +system.cpu0.l2cache.ReadSharedReq_hits::total 372689 # number of ReadSharedReq hits +system.cpu0.l2cache.demand_hits::cpu0.dtb.walker 50315 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.itb.walker 12479 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.inst 1158323 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::cpu0.data 583419 # number of demand (read+write) hits +system.cpu0.l2cache.demand_hits::total 1804536 # number of demand (read+write) hits +system.cpu0.l2cache.overall_hits::cpu0.dtb.walker 50315 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.itb.walker 12479 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.inst 1158323 # number of overall hits +system.cpu0.l2cache.overall_hits::cpu0.data 583419 # number of overall hits +system.cpu0.l2cache.overall_hits::total 1804536 # number of overall hits +system.cpu0.l2cache.ReadReq_misses::cpu0.dtb.walker 419 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::cpu0.itb.walker 174 # number of ReadReq misses +system.cpu0.l2cache.ReadReq_misses::total 593 # number of ReadReq misses +system.cpu0.l2cache.UpgradeReq_misses::cpu0.data 27292 # number of UpgradeReq misses +system.cpu0.l2cache.UpgradeReq_misses::total 27292 # number of UpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::cpu0.data 19556 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeReq_misses::total 19556 # number of SCUpgradeReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::cpu0.data 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses +system.cpu0.l2cache.ReadExReq_misses::cpu0.data 45826 # number of ReadExReq misses +system.cpu0.l2cache.ReadExReq_misses::total 45826 # number of ReadExReq misses +system.cpu0.l2cache.ReadCleanReq_misses::cpu0.inst 50641 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadCleanReq_misses::total 50641 # number of ReadCleanReq misses +system.cpu0.l2cache.ReadSharedReq_misses::cpu0.data 98477 # number of ReadSharedReq misses +system.cpu0.l2cache.ReadSharedReq_misses::total 98477 # number of ReadSharedReq misses +system.cpu0.l2cache.demand_misses::cpu0.dtb.walker 419 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.itb.walker 174 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.inst 50641 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::cpu0.data 144303 # number of demand (read+write) misses +system.cpu0.l2cache.demand_misses::total 195537 # number of demand (read+write) misses +system.cpu0.l2cache.overall_misses::cpu0.dtb.walker 419 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.itb.walker 174 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.inst 50641 # number of overall misses +system.cpu0.l2cache.overall_misses::cpu0.data 144303 # number of overall misses +system.cpu0.l2cache.overall_misses::total 195537 # number of overall misses +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.dtb.walker 11008500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::cpu0.itb.walker 4405500 # number of ReadReq miss cycles +system.cpu0.l2cache.ReadReq_miss_latency::total 15414000 # number of ReadReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::cpu0.data 502449500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.UpgradeReq_miss_latency::total 502449500 # number of UpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::cpu0.data 396768500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeReq_miss_latency::total 396768500 # number of SCUpgradeReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::cpu0.data 399000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_miss_latency::total 399000 # number of SCUpgradeFailReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::cpu0.data 2648910998 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadExReq_miss_latency::total 2648910998 # number of ReadExReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::cpu0.inst 2424883999 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadCleanReq_miss_latency::total 2424883999 # number of ReadCleanReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::cpu0.data 2835688998 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.ReadSharedReq_miss_latency::total 2835688998 # number of ReadSharedReq miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.dtb.walker 11008500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.itb.walker 4405500 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.inst 2424883999 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::cpu0.data 5484599996 # number of demand (read+write) miss cycles +system.cpu0.l2cache.demand_miss_latency::total 7924897995 # number of demand (read+write) miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.dtb.walker 11008500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.itb.walker 4405500 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.inst 2424883999 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::cpu0.data 5484599996 # number of overall miss cycles +system.cpu0.l2cache.overall_miss_latency::total 7924897995 # number of overall miss cycles +system.cpu0.l2cache.ReadReq_accesses::cpu0.dtb.walker 50734 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::cpu0.itb.walker 12653 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.ReadReq_accesses::total 63387 # number of ReadReq accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::writebacks 491416 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.Writeback_accesses::total 491416 # number of Writeback accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::cpu0.data 55745 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.UpgradeReq_accesses::total 55745 # number of UpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::cpu0.data 21164 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeReq_accesses::total 21164 # number of SCUpgradeReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::cpu0.data 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::cpu0.data 256556 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadExReq_accesses::total 256556 # number of ReadExReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::cpu0.inst 1208964 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadCleanReq_accesses::total 1208964 # number of ReadCleanReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::cpu0.data 471166 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.ReadSharedReq_accesses::total 471166 # number of ReadSharedReq accesses(hits+misses) +system.cpu0.l2cache.demand_accesses::cpu0.dtb.walker 50734 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.itb.walker 12653 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.inst 1208964 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::cpu0.data 727722 # number of demand (read+write) accesses +system.cpu0.l2cache.demand_accesses::total 2000073 # number of demand (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.dtb.walker 50734 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.itb.walker 12653 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.inst 1208964 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::cpu0.data 727722 # number of overall (read+write) accesses +system.cpu0.l2cache.overall_accesses::total 2000073 # number of overall (read+write) accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::cpu0.itb.walker 0.013752 # miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_miss_rate::total 0.009355 # miss rate for ReadReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::cpu0.data 0.489587 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_miss_rate::total 0.489587 # miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::cpu0.data 0.924022 # miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_miss_rate::total 0.924022 # miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.180914 # miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_miss_rate::total 0.180914 # miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.012090 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.040736 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198768 # miss rate for demand accesses -system.cpu0.l2cache.demand_miss_rate::total 0.097575 # miss rate for demand accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.007900 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.012090 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.040736 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198768 # miss rate for overall accesses -system.cpu0.l2cache.overall_miss_rate::total 0.097575 # miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 24325.174825 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.inst 49081.203184 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.data 28967.619559 # average ReadReq miss latency -system.cpu0.l2cache.ReadReq_avg_miss_latency::total 35609.646124 # average ReadReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18403.623404 # average UpgradeReq miss latency -system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18403.623404 # average UpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20156.121112 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20156.121112 # average SCUpgradeReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 386749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 386749.500000 # average SCUpgradeFailReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 56379.810085 # average ReadExReq miss latency -system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 56379.810085 # average ReadExReq miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency -system.cpu0.l2cache.demand_avg_miss_latency::total 40570.013786 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 27474.793451 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 24325.174825 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 49081.203184 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 37748.674947 # average overall miss latency -system.cpu0.l2cache.overall_avg_miss_latency::total 40570.013786 # average overall miss latency -system.cpu0.l2cache.blocked_cycles::no_mshrs 227 # number of cycles access was blocked +system.cpu0.l2cache.ReadExReq_miss_rate::cpu0.data 0.178620 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_miss_rate::total 0.178620 # miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::cpu0.inst 0.041888 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_miss_rate::total 0.041888 # miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::cpu0.data 0.209007 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_miss_rate::total 0.209007 # miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.itb.walker 0.013752 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.inst 0.041888 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::cpu0.data 0.198294 # miss rate for demand accesses +system.cpu0.l2cache.demand_miss_rate::total 0.097765 # miss rate for demand accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.dtb.walker 0.008259 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.itb.walker 0.013752 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.inst 0.041888 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::cpu0.data 0.198294 # miss rate for overall accesses +system.cpu0.l2cache.overall_miss_rate::total 0.097765 # miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::cpu0.itb.walker 25318.965517 # average ReadReq miss latency +system.cpu0.l2cache.ReadReq_avg_miss_latency::total 25993.254637 # average ReadReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::cpu0.data 18410.138502 # average UpgradeReq miss latency +system.cpu0.l2cache.UpgradeReq_avg_miss_latency::total 18410.138502 # average UpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::cpu0.data 20288.837186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_miss_latency::total 20288.837186 # average SCUpgradeReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu0.data 399000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_miss_latency::total 399000 # average SCUpgradeFailReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::cpu0.data 57803.670362 # average ReadExReq miss latency +system.cpu0.l2cache.ReadExReq_avg_miss_latency::total 57803.670362 # average ReadExReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::cpu0.inst 47883.809542 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadCleanReq_avg_miss_latency::total 47883.809542 # average ReadCleanReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::cpu0.data 28795.444601 # average ReadSharedReq miss latency +system.cpu0.l2cache.ReadSharedReq_avg_miss_latency::total 28795.444601 # average ReadSharedReq miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency +system.cpu0.l2cache.demand_avg_miss_latency::total 40528.892205 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.dtb.walker 26273.269690 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.itb.walker 25318.965517 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.inst 47883.809542 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::cpu0.data 38007.525803 # average overall miss latency +system.cpu0.l2cache.overall_avg_miss_latency::total 40528.892205 # average overall miss latency +system.cpu0.l2cache.blocked_cycles::no_mshrs 236 # number of cycles access was blocked system.cpu0.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.blocked::no_mshrs 7 # number of cycles access was blocked +system.cpu0.l2cache.blocked::no_mshrs 8 # number of cycles access was blocked system.cpu0.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 32.428571 # average number of cycles each access was blocked +system.cpu0.l2cache.avg_blocked_cycles::no_mshrs 29.500000 # average number of cycles each access was blocked system.cpu0.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l2cache.fast_writes 0 # number of fast writes performed system.cpu0.l2cache.cache_copies 0 # number of cache copies performed -system.cpu0.l2cache.writebacks::writebacks 192333 # number of writebacks -system.cpu0.l2cache.writebacks::total 192333 # number of writebacks +system.cpu0.l2cache.writebacks::writebacks 193260 # number of writebacks +system.cpu0.l2cache.writebacks::total 193260 # number of writebacks system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.dtb.walker 1 # number of ReadReq MSHR hits system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.itb.walker 1 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.inst 30 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::cpu0.data 734 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadReq_mshr_hits::total 766 # number of ReadReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 5918 # number of ReadExReq MSHR hits -system.cpu0.l2cache.ReadExReq_mshr_hits::total 5918 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::cpu0.data 6054 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadExReq_mshr_hits::total 6054 # number of ReadExReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::cpu0.inst 30 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadCleanReq_mshr_hits::total 30 # number of ReadCleanReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::cpu0.data 713 # number of ReadSharedReq MSHR hits +system.cpu0.l2cache.ReadSharedReq_mshr_hits::total 713 # number of ReadSharedReq MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.dtb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.itb.walker 1 # number of demand (read+write) MSHR hits system.cpu0.l2cache.demand_mshr_hits::cpu0.inst 30 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6652 # number of demand (read+write) MSHR hits -system.cpu0.l2cache.demand_mshr_hits::total 6684 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::cpu0.data 6767 # number of demand (read+write) MSHR hits +system.cpu0.l2cache.demand_mshr_hits::total 6799 # number of demand (read+write) MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.dtb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.itb.walker 1 # number of overall MSHR hits system.cpu0.l2cache.overall_mshr_hits::cpu0.inst 30 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6652 # number of overall MSHR hits -system.cpu0.l2cache.overall_mshr_hits::total 6684 # number of overall MSHR hits -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 396 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 142 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.inst 48896 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.data 97770 # number of ReadReq MSHR misses -system.cpu0.l2cache.ReadReq_mshr_misses::total 147204 # number of ReadReq MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::writebacks 2 # number of Writeback MSHR misses -system.cpu0.l2cache.Writeback_mshr_misses::total 2 # number of Writeback MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of HardPFReq MSHR misses -system.cpu0.l2cache.HardPFReq_mshr_misses::total 231819 # number of HardPFReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27483 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27483 # number of UpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19577 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19577 # number of SCUpgradeReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 2 # number of SCUpgradeFailReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 40508 # number of ReadExReq MSHR misses -system.cpu0.l2cache.ReadExReq_mshr_misses::total 40508 # number of ReadExReq MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 396 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 142 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 48896 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::cpu0.data 138278 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.demand_mshr_misses::total 187712 # number of demand (read+write) MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 396 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 142 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 48896 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.data 138278 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 231819 # number of overall MSHR misses -system.cpu0.l2cache.overall_mshr_misses::total 419531 # number of overall MSHR misses -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 20967 # number of ReadReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 16714 # number of WriteReq MSHR uncacheable -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 37681 # number of overall MSHR uncacheable misses -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 2542000 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.inst 2076482303 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.data 2175990950 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 4263319752 # number of ReadReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15030655008 # number of HardPFReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 535907154 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 535907154 # number of UpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 292472580 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 292472580 # number of SCUpgradeReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 643499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 643499 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1596975176 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1596975176 # number of ReadExReq MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 2542000 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2076482303 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3772966126 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.demand_mshr_miss_latency::total 5860294928 # number of demand (read+write) MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8304499 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 2542000 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2076482303 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3772966126 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15030655008 # number of overall MSHR miss cycles -system.cpu0.l2cache.overall_mshr_miss_latency::total 20890949936 # number of overall MSHR miss cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 241524750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 3549350250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 3790875000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 2559965955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 2559965955 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 241524750 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 6109316205 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 6350840955 # number of overall MSHR uncacheable cycles -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.data 0.206911 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.084812 # mshr miss rate for ReadReq accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::writebacks 0.000004 # mshr miss rate for Writeback accesses -system.cpu0.l2cache.Writeback_mshr_miss_rate::total 0.000004 # mshr miss rate for Writeback accesses +system.cpu0.l2cache.overall_mshr_hits::cpu0.data 6767 # number of overall MSHR hits +system.cpu0.l2cache.overall_mshr_hits::total 6799 # number of overall MSHR hits +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.dtb.walker 418 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::cpu0.itb.walker 173 # number of ReadReq MSHR misses +system.cpu0.l2cache.ReadReq_mshr_misses::total 591 # number of ReadReq MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::writebacks 8374 # number of CleanEvict MSHR misses +system.cpu0.l2cache.CleanEvict_mshr_misses::total 8374 # number of CleanEvict MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of HardPFReq MSHR misses +system.cpu0.l2cache.HardPFReq_mshr_misses::total 232540 # number of HardPFReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::cpu0.data 27292 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.UpgradeReq_mshr_misses::total 27292 # number of UpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::cpu0.data 19556 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeReq_mshr_misses::total 19556 # number of SCUpgradeReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::cpu0.data 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::cpu0.data 39772 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadExReq_mshr_misses::total 39772 # number of ReadExReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::cpu0.inst 50611 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadCleanReq_mshr_misses::total 50611 # number of ReadCleanReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::cpu0.data 97764 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.ReadSharedReq_mshr_misses::total 97764 # number of ReadSharedReq MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.dtb.walker 418 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.itb.walker 173 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.inst 50611 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::cpu0.data 137536 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.demand_mshr_misses::total 188738 # number of demand (read+write) MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.dtb.walker 418 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.itb.walker 173 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.inst 50611 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.data 137536 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::cpu0.l2cache.prefetcher 232540 # number of overall MSHR misses +system.cpu0.l2cache.overall_mshr_misses::total 421278 # number of overall MSHR misses +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.ReadReq_mshr_uncacheable::total 32398 # number of ReadReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.WriteReq_mshr_uncacheable::total 26127 # number of WriteReq MSHR uncacheable +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.overall_mshr_uncacheable_misses::total 58525 # number of overall MSHR uncacheable misses +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::cpu0.itb.walker 3355000 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_miss_latency::total 11834500 # number of ReadReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.HardPFReq_mshr_miss_latency::total 15228773142 # number of HardPFReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::cpu0.data 539452500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.UpgradeReq_mshr_miss_latency::total 539452500 # number of UpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::cpu0.data 299483497 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_latency::total 299483497 # number of SCUpgradeReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu0.data 327000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 327000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::cpu0.data 1648200500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadExReq_mshr_miss_latency::total 1648200500 # number of ReadExReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::cpu0.inst 2120543999 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadCleanReq_mshr_miss_latency::total 2120543999 # number of ReadCleanReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::cpu0.data 2210587998 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.ReadSharedReq_mshr_miss_latency::total 2210587998 # number of ReadSharedReq MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.itb.walker 3355000 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.inst 2120543999 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::cpu0.data 3858788498 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.demand_mshr_miss_latency::total 5991166997 # number of demand (read+write) MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.dtb.walker 8479500 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.itb.walker 3355000 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.inst 2120543999 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.data 3858788498 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 15228773142 # number of overall MSHR miss cycles +system.cpu0.l2cache.overall_mshr_miss_latency::total 21219940139 # number of overall MSHR miss cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.inst 243342000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::cpu0.data 5445807000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_uncacheable_latency::total 5689149000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::cpu0.data 4113464958 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.WriteReq_mshr_uncacheable_latency::total 4113464958 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.inst 243342000 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::cpu0.data 9559271958 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.overall_mshr_uncacheable_latency::total 9802613958 # number of overall MSHR uncacheable cycles +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.ReadReq_mshr_miss_rate::total 0.009324 # mshr miss rate for ReadReq accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu0.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu0.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.491119 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.491119 # mshr miss rate for UpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924359 # mshr miss rate for SCUpgradeReq accesses -system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924359 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::cpu0.data 0.489587 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.UpgradeReq_mshr_miss_rate::total 0.489587 # mshr miss rate for UpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.924022 # mshr miss rate for SCUpgradeReq accesses +system.cpu0.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.924022 # mshr miss rate for SCUpgradeReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu0.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.157853 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.157853 # mshr miss rate for ReadExReq accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for demand accesses -system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094220 # mshr miss rate for demand accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.007880 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.012005 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.040711 # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.189645 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::cpu0.data 0.155023 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadExReq_mshr_miss_rate::total 0.155023 # mshr miss rate for ReadExReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadCleanReq_mshr_miss_rate::total 0.041863 # mshr miss rate for ReadCleanReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::cpu0.data 0.207494 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.ReadSharedReq_mshr_miss_rate::total 0.207494 # mshr miss rate for ReadSharedReq accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for demand accesses +system.cpu0.l2cache.demand_mshr_miss_rate::total 0.094366 # mshr miss rate for demand accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.dtb.walker 0.008239 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.itb.walker 0.013673 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.inst 0.041863 # mshr miss rate for overall accesses +system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.data 0.188995 # mshr miss rate for overall accesses system.cpu0.l2cache.overall_mshr_miss_rate::cpu0.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210579 # mshr miss rate for overall accesses -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.data 22256.223279 # average ReadReq mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 28961.983044 # average ReadReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average HardPFReq mshr miss latency -system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 64837.890803 # average HardPFReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19499.587163 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19499.587163 # average UpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 14939.601573 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14939.601573 # average SCUpgradeReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 321749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 321749.500000 # average SCUpgradeFailReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 39423.698430 # average ReadExReq mshr miss latency -system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 39423.698430 # average ReadExReq mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency -system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31219.607313 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20970.957071 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 17901.408451 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 42467.324587 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 27285.368070 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 64837.890803 # average overall mshr miss latency -system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 49795.962482 # average overall mshr miss latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 197570.289452 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 180801.974531 # average ReadReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 153162.974453 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 153162.974453 # average WriteReq mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 80454.613591 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 176167.600133 # average overall mshr uncacheable latency -system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 168542.261485 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_mshr_miss_rate::total 0.210631 # mshr miss rate for overall accesses +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average ReadReq mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_miss_latency::total 20024.534687 # average ReadReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average HardPFReq mshr miss latency +system.cpu0.l2cache.HardPFReq_avg_mshr_miss_latency::total 65488.832640 # average HardPFReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu0.data 19765.957057 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.UpgradeReq_avg_mshr_miss_latency::total 19765.957057 # average UpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 15314.148957 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15314.148957 # average SCUpgradeReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu0.data 327000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 327000 # average SCUpgradeFailReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::cpu0.data 41441.227497 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadExReq_avg_mshr_miss_latency::total 41441.227497 # average ReadExReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 41898.875719 # average ReadCleanReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 22611.472505 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 22611.472505 # average ReadSharedReq mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency +system.cpu0.l2cache.demand_avg_mshr_miss_latency::total 31743.300220 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.dtb.walker 20285.885167 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.itb.walker 19393.063584 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.inst 41898.875719 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.data 28056.570629 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 65488.832640 # average overall mshr miss latency +system.cpu0.l2cache.overall_avg_mshr_miss_latency::total 50370.397075 # average overall mshr miss latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 185269.340682 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 175601.858139 # average ReadReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 157441.151223 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 157441.151223 # average WriteReq mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.inst 81005.992011 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::cpu0.data 172173.987464 # average overall mshr uncacheable latency +system.cpu0.l2cache.overall_avg_mshr_uncacheable_latency::total 167494.471730 # average overall mshr uncacheable latency system.cpu0.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.toL2Bus.trans_dist::ReadReq 1907833 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadResp 1820754 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteResp 16714 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::Writeback 491995 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::HardPFReq 299768 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeReq 92116 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43624 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeResp 114864 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 16 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExReq 284068 # Transaction distribution -system.cpu0.toL2Bus.trans_dist::ReadExResp 270286 # Transaction distribution -system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 2408123 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2274201 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 27655 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 111764 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_count::total 4821743 # Packet count per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 76915296 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82255660 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 47312 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 201008 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.pkt_size::total 159419276 # Cumulative packet size per connected master and slave (bytes) -system.cpu0.toL2Bus.snoops 687931 # Total snoops (count) -system.cpu0.toL2Bus.snoop_fanout::samples 3186793 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::mean 1.203876 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::stdev 0.402878 # Request fanout histogram +system.cpu0.toL2Bus.trans_dist::ReadReq 116134 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadResp 1839025 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::WriteResp 26127 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::Writeback 864426 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::CleanEvict 1492254 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::HardPFReq 304971 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeReq 91775 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeReq 43512 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeResp 114568 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExReq 284553 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadExResp 270414 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadCleanReq 1208978 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::ReadSharedReq 592867 # Transaction distribution +system.cpu0.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu0.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 3608808 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 2486821 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 28899 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 112519 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_count::total 6237047 # Packet count per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.cpu0.l2cache.cpu_side 77421632 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.cpu0.l2cache.cpu_side 82196692 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.cpu0.l2cache.cpu_side 50612 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.cpu0.l2cache.cpu_side 202936 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.pkt_size::total 159871872 # Cumulative packet size per connected master and slave (bytes) +system.cpu0.toL2Bus.snoops 1179844 # Total snoops (count) +system.cpu0.toL2Bus.snoop_fanout::samples 5097277 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::mean 1.224281 # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::stdev 0.417108 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::1 2537081 79.61% 79.61% # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::2 649712 20.39% 100.00% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::1 3954053 77.57% 77.57% # Request fanout histogram +system.cpu0.toL2Bus.snoop_fanout::2 1143224 22.43% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu0.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu0.toL2Bus.snoop_fanout::total 3186793 # Request fanout histogram -system.cpu0.toL2Bus.reqLayer0.occupancy 1807599924 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoop_fanout::total 5097277 # Request fanout histogram +system.cpu0.toL2Bus.reqLayer0.occupancy 2520550941 # Layer occupancy (ticks) system.cpu0.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.snoopLayer0.occupancy 112679999 # Layer occupancy (ticks) +system.cpu0.toL2Bus.snoopLayer0.occupancy 112317000 # Layer occupancy (ticks) system.cpu0.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer0.occupancy 1808718407 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer0.occupancy 1816757420 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer1.occupancy 1166698241 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer1.occupancy 1173564387 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer2.occupancy 15837483 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer2.occupancy 16253983 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu0.toL2Bus.respLayer3.occupancy 61547958 # Layer occupancy (ticks) +system.cpu0.toL2Bus.respLayer3.occupancy 61816936 # Layer occupancy (ticks) system.cpu0.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.cpu1.branchPred.lookups 35319894 # Number of BP lookups -system.cpu1.branchPred.condPredicted 12619407 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 374072 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 19615876 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 15617711 # Number of BTB hits +system.cpu1.branchPred.lookups 6152669 # Number of BP lookups +system.cpu1.branchPred.condPredicted 3868120 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 360109 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 3337115 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 2452438 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 79.617709 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 12648833 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 10709 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 73.489766 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 1042883 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 10537 # Number of incorrect RAS predictions. system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1608,89 +1636,91 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 24259 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 24259 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11332 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 6025 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksSquashedBefore 6902 # Table walks squashed before starting -system.cpu1.dtb.walker.walkWaitTime::samples 17357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::mean 400.040330 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::stdev 2564.899375 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0-4095 16829 96.96% 96.96% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::4096-8191 181 1.04% 98.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::8192-12287 173 1.00% 99.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::12288-16383 71 0.41% 99.41% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::16384-20479 28 0.16% 99.57% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::20480-24575 5 0.03% 99.60% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::24576-28671 45 0.26% 99.86% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::28672-32767 6 0.03% 99.89% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::32768-36863 14 0.08% 99.97% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::36864-40959 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::40960-45055 2 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walks 24322 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 24322 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 11233 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 5990 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksSquashedBefore 7099 # Table walks squashed before starting +system.cpu1.dtb.walker.walkWaitTime::samples 17223 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::mean 438.425361 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::stdev 2740.461547 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0-4095 16689 96.90% 96.90% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::4096-8191 124 0.72% 97.62% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::8192-12287 219 1.27% 98.89% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::12288-16383 86 0.50% 99.39% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::16384-20479 20 0.12% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::20480-24575 13 0.08% 99.58% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::24576-28671 39 0.23% 99.81% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::28672-32767 13 0.08% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::32768-36863 16 0.09% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::45056-49151 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu1.dtb.walker.walkWaitTime::49152-53247 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::53248-57343 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 17357 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 5295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 9383.568650 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 7860.112601 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 8293.617199 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::0-32767 5259 99.32% 99.32% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::32768-65535 29 0.55% 99.87% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::65536-98303 3 0.06% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::163840-196607 3 0.06% 99.98% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::294912-327679 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 5295 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walksPending::samples 69596834880 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::mean 0.389063 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::stdev 0.490087 # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::0 42554298056 61.14% 61.14% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::1 27024786824 38.83% 99.97% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::2 11219000 0.02% 99.99% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::3 3252000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::4 913000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::5 701500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::6 719000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::7 299000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::8 99500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::9 182000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::10 50000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::11 63500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::12 106500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::13 34000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::14 15000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::15 96000 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.dtb.walker.walksPending::total 69596834880 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1939 74.63% 74.63% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 659 25.37% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 2598 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24259 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkWaitTime::53248-57343 2 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 17223 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 5609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10144.232484 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 8674.966878 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6379.427582 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::0-8191 2437 43.45% 43.45% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::8192-16383 2571 45.84% 89.29% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::16384-24575 453 8.08% 97.36% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::24576-32767 115 2.05% 99.41% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::32768-40959 3 0.05% 99.47% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::40960-49151 25 0.45% 99.91% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::90112-98303 4 0.07% 99.98% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::106496-114687 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 5609 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walksPending::samples 69613371380 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::mean 0.373428 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::stdev 0.487046 # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::0 43658416792 62.72% 62.72% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::1 25935559588 37.26% 99.97% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::2 12091000 0.02% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::3 3523500 0.01% 99.99% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::4 1046500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::5 593000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::6 908500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::7 323500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::8 151000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::9 143500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::10 80500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::11 88500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::12 153000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::13 38000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::14 28000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::15 226500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.dtb.walker.walksPending::total 69613371380 # Table walker pending requests distribution +system.cpu1.dtb.walker.walkPageSizes::4K 1968 73.85% 73.85% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 697 26.15% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 2665 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 24322 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24259 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2598 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 24322 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 2665 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2598 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 26857 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 2665 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 26987 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 11166498 # DTB read hits -system.cpu1.dtb.read_misses 21069 # DTB read misses -system.cpu1.dtb.write_hits 7306223 # DTB write hits -system.cpu1.dtb.write_misses 3190 # DTB write misses +system.cpu1.dtb.read_hits 5224196 # DTB read hits +system.cpu1.dtb.read_misses 21002 # DTB read misses +system.cpu1.dtb.write_hits 4300766 # DTB write hits +system.cpu1.dtb.write_misses 3320 # DTB write misses system.cpu1.dtb.flush_tlb 66 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2022 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 70 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 623 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2043 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 67 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 616 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 374 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 11187567 # DTB read accesses -system.cpu1.dtb.write_accesses 7309413 # DTB write accesses +system.cpu1.dtb.perms_faults 364 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 5245198 # DTB read accesses +system.cpu1.dtb.write_accesses 4304086 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 18472721 # DTB hits -system.cpu1.dtb.misses 24259 # DTB misses -system.cpu1.dtb.accesses 18496980 # DTB accesses +system.cpu1.dtb.hits 9524962 # DTB hits +system.cpu1.dtb.misses 24322 # DTB misses +system.cpu1.dtb.accesses 9549284 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1720,63 +1750,58 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 6817 # Table walker walks requested -system.cpu1.itb.walker.walksShort 6817 # Table walker walks initiated with short descriptors -system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4075 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2679 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksSquashedBefore 63 # Table walks squashed before starting -system.cpu1.itb.walker.walkWaitTime::samples 6754 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::mean 138.510512 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::stdev 1194.021921 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0-2047 6631 98.18% 98.18% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::2048-4095 35 0.52% 98.70% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::4096-6143 28 0.41% 99.11% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::6144-8191 28 0.41% 99.53% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::8192-10239 11 0.16% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::10240-12287 8 0.12% 99.81% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::12288-14335 4 0.06% 99.87% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::14336-16383 2 0.03% 99.90% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::20480-22527 2 0.03% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::22528-24575 2 0.03% 99.96% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::24576-26623 2 0.03% 99.99% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::26624-28671 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 6754 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 1229 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 9949.958503 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 8666.714001 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 5833.930601 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::0-4095 208 16.92% 16.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-8191 175 14.24% 31.16% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::8192-12287 520 42.31% 73.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-16383 258 20.99% 94.47% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::16384-20479 10 0.81% 95.28% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::20480-24575 3 0.24% 95.52% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::24576-28671 30 2.44% 97.97% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::28672-32767 16 1.30% 99.27% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::32768-36863 2 0.16% 99.43% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::36864-40959 5 0.41% 99.84% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::40960-45055 1 0.08% 99.92% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::61440-65535 1 0.08% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 1229 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walksPending::samples 18026373328 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::mean 0.989122 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::stdev 0.103762 # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::0 196149764 1.09% 1.09% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::1 17830158064 98.91% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::2 65500 0.00% 100.00% # Table walker pending requests distribution -system.cpu1.itb.walker.walksPending::total 18026373328 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 995 85.33% 85.33% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 171 14.67% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 1166 # Table walker page sizes translated +system.cpu1.itb.walker.walks 6842 # Table walker walks requested +system.cpu1.itb.walker.walksShort 6842 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walksShortTerminationLevel::Level1 4094 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 2680 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walksSquashedBefore 68 # Table walks squashed before starting +system.cpu1.itb.walker.walkWaitTime::samples 6774 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::mean 241.142604 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::stdev 1918.263476 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0-4095 6651 98.18% 98.18% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::4096-8191 49 0.72% 98.91% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::8192-12287 35 0.52% 99.42% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::12288-16383 15 0.22% 99.65% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::16384-20479 5 0.07% 99.72% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::20480-24575 10 0.15% 99.87% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::24576-28671 5 0.07% 99.94% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::28672-32767 2 0.03% 99.97% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::36864-40959 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::49152-53247 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 6774 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 1233 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11141.524736 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9875.363796 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6280.061079 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::0-8191 357 28.95% 28.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::8192-16383 797 64.64% 93.59% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::16384-24575 18 1.46% 95.05% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::24576-32767 48 3.89% 98.95% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::32768-40959 5 0.41% 99.35% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::40960-49151 7 0.57% 99.92% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::65536-73727 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 1233 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksPending::samples 18042065828 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::mean 0.988332 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::stdev 0.107619 # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::0 210878764 1.17% 1.17% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::1 17830879064 98.83% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::2 267500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::3 19000 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::4 21500 0.00% 100.00% # Table walker pending requests distribution +system.cpu1.itb.walker.walksPending::total 18042065828 # Table walker pending requests distribution +system.cpu1.itb.walker.walkPageSizes::4K 995 85.41% 85.41% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 170 14.59% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 1165 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6817 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6817 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 6842 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 6842 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1166 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1166 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 7983 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 45723303 # ITB inst hits -system.cpu1.itb.inst_misses 6817 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 1165 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 8007 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 10488200 # ITB inst hits +system.cpu1.itb.inst_misses 6842 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1785,1005 +1810,1037 @@ system.cpu1.itb.flush_tlb 66 # Nu system.cpu1.itb.flush_tlb_mva 917 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1199 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1196 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 537 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 530 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 45730120 # ITB inst accesses -system.cpu1.itb.hits 45723303 # DTB hits -system.cpu1.itb.misses 6817 # DTB misses -system.cpu1.itb.accesses 45730120 # DTB accesses -system.cpu1.numCycles 113567718 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 10495042 # ITB inst accesses +system.cpu1.itb.hits 10488200 # DTB hits +system.cpu1.itb.misses 6842 # DTB misses +system.cpu1.itb.accesses 10495042 # DTB accesses +system.cpu1.numCycles 43023242 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 11092326 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 115445294 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 35319894 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 28266544 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 98824380 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3951464 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 84431 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.MiscStallCycles 39920 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 219438 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 325443 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 27387 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 45722696 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 133886 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2307 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 112589057 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.268755 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.334526 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 9545006 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 31536140 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 6152669 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 3495321 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 31308638 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 988880 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 91081 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.MiscStallCycles 40105 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 214294 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 338691 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 30719 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 10487595 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 131638 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2429 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 42062974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.911933 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.224898 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 52059388 46.24% 46.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 15346880 13.63% 59.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 8047278 7.15% 67.02% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 37135511 32.98% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 24350235 57.89% 57.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 6287044 14.95% 72.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 2205515 5.24% 78.08% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 9220180 21.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 112589057 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.311003 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.016533 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 14201102 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 65884249 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 29361473 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 1323272 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1818961 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 906595 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 159892 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 74422628 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 1448245 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1818961 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 18946447 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 2582249 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 60294532 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 25904145 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3042723 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 61245605 # Number of instructions processed by rename -system.cpu1.rename.SquashedInsts 312742 # Number of squashed instructions processed by rename -system.cpu1.rename.ROBFullEvents 326990 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 51393 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LQFullEvents 18938 # Number of times rename has blocked due to LQ full -system.cpu1.rename.SQFullEvents 1837973 # Number of times rename has blocked due to SQ full -system.cpu1.rename.RenamedOperands 61569183 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 287884146 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 65513638 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 1660 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 58022651 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 3546532 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 1914472 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 1838523 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 13613893 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 11512865 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7756589 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 697877 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 945772 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60208856 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 646860 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 59677362 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 148586 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 4522679 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 7282133 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 53722 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 112589057 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.530046 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 0.866401 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 42062974 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.143008 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.733002 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 8267663 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 20626897 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11490517 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1337775 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 340122 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 874675 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 157334 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 30100708 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1379443 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 340122 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 10041900 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2603998 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 14921640 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11019721 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3135593 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 28621166 # Number of instructions processed by rename +system.cpu1.rename.SquashedInsts 281517 # Number of squashed instructions processed by rename +system.cpu1.rename.ROBFullEvents 330506 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 50454 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LQFullEvents 20125 # Number of times rename has blocked due to LQ full +system.cpu1.rename.SQFullEvents 1923436 # Number of times rename has blocked due to SQ full +system.cpu1.rename.RenamedOperands 29030542 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 132294985 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 32813170 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 1657 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 25609862 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 3420680 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 453393 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 375590 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 3438293 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 5562789 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 4719499 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 701110 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 705314 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 27634808 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 626900 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 27144127 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 143701 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 2955966 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 6891737 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 53840 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 42062974 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.645321 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 0.965357 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 76211299 67.69% 67.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 17665370 15.69% 83.38% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 14473056 12.85% 96.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3891466 3.46% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 347848 0.31% 100.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 18 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 26343154 62.63% 62.63% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 7337268 17.44% 80.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 5660550 13.46% 93.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2402263 5.71% 99.24% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 319725 0.76% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 14 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::8 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 5 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 112589057 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 42062974 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 3478019 44.85% 44.85% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 614 0.01% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 44.86% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 1940620 25.03% 69.89% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 2334930 30.11% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 1996325 32.40% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 609 0.01% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 32.40% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1885144 30.59% 63.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 2280359 37.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 67 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 40635841 68.09% 68.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 52797 0.09% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.18% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 4119 0.01% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.19% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 11419177 19.13% 87.32% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7565361 12.68% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 17084879 62.94% 62.94% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 34880 0.13% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 63.07% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 4083 0.02% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 63.09% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 5473288 20.16% 83.25% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 4546930 16.75% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 59677362 # Type of FU issued -system.cpu1.iq.rate 0.525478 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7754183 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.129935 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 239840869 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 65386915 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 57545759 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 5681 # Number of floating instruction queue reads +system.cpu1.iq.FU_type_0::total 27144127 # Type of FU issued +system.cpu1.iq.rate 0.630918 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 6162437 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.227027 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 102651570 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 31226183 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 26510239 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 5796 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 2046 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 1784 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 67427880 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 3598 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 109848 # Number of loads that had data forwarded from stores +system.cpu1.iq.int_alu_accesses 33302783 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 3714 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 106694 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 624171 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 851 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 10604 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 419293 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 599497 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 782 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 10594 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 400513 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 57328 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 95447 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 46755 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 99859 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1818961 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 659321 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 119824 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 60910908 # Number of instructions dispatched to IQ +system.cpu1.iew.iewSquashCycles 340122 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 663664 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 112730 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 28316728 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 11512865 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7756589 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 325462 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 12815 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 97459 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 10604 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 81282 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 152799 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 234081 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59327650 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 11286961 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 325473 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewDispLoadInsts 5562789 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 4719499 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 329074 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 12650 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 90576 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 10594 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 71921 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 150578 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 222499 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 26808358 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 5342958 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 311471 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 55192 # number of nop insts executed -system.cpu1.iew.exec_refs 18774109 # number of memory reference insts executed -system.cpu1.iew.exec_branches 12866831 # Number of branches executed -system.cpu1.iew.exec_stores 7487148 # Number of stores executed -system.cpu1.iew.exec_rate 0.522399 # Inst execution rate -system.cpu1.iew.wb_sent 59146208 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 57547543 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 28211344 # num instructions producing a value -system.cpu1.iew.wb_consumers 43350974 # num instructions consuming a value +system.cpu1.iew.exec_nop 55020 # number of nop insts executed +system.cpu1.iew.exec_refs 9813397 # number of memory reference insts executed +system.cpu1.iew.exec_branches 4108906 # Number of branches executed +system.cpu1.iew.exec_stores 4470439 # Number of stores executed +system.cpu1.iew.exec_rate 0.623113 # Inst execution rate +system.cpu1.iew.wb_sent 26632744 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 26512023 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 13415515 # num instructions producing a value +system.cpu1.iew.wb_consumers 21195279 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.506724 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.650766 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.616226 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.632948 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 4198450 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 593138 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 217301 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 110549070 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.509875 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.177384 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 2659330 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 573060 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 205791 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 41503303 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.610529 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.356545 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 82464476 74.60% 74.60% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 15679600 14.18% 88.78% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 6499039 5.88% 94.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 896756 0.81% 95.47% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 2234307 2.02% 97.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 1661965 1.50% 98.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 498497 0.45% 99.44% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 155172 0.14% 99.58% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 459258 0.42% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 29410485 70.86% 70.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 7042051 16.97% 87.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2116509 5.10% 92.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 864843 2.08% 95.01% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 769424 1.85% 96.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 435639 1.05% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 276731 0.67% 98.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 147889 0.36% 98.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 439732 1.06% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 110549070 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 45875888 # Number of instructions committed -system.cpu1.commit.committedOps 56366249 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 41503303 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 20778200 # Number of instructions committed +system.cpu1.commit.committedOps 25338954 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 18225990 # Number of memory references committed -system.cpu1.commit.loads 10888694 # Number of loads committed -system.cpu1.commit.membars 231720 # Number of memory barriers committed -system.cpu1.commit.branches 12659864 # Number of branches committed +system.cpu1.commit.refs 9282278 # Number of memory references committed +system.cpu1.commit.loads 4963292 # Number of loads committed +system.cpu1.commit.membars 229830 # Number of memory barriers committed +system.cpu1.commit.branches 3902679 # Number of branches committed system.cpu1.commit.fp_insts 1784 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 50354679 # Number of committed integer instructions. -system.cpu1.commit.function_calls 3453612 # Number of function calls committed. +system.cpu1.commit.int_insts 22267919 # Number of committed integer instructions. +system.cpu1.commit.function_calls 549742 # Number of function calls committed. system.cpu1.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu1.commit.op_class_0::IntAlu 38084418 67.57% 67.57% # Class of committed instruction -system.cpu1.commit.op_class_0::IntMult 51722 0.09% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::IntDiv 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatMult 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMult 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShift 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 67.66% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMisc 4119 0.01% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.67% # Class of committed instruction -system.cpu1.commit.op_class_0::MemRead 10888694 19.32% 86.98% # Class of committed instruction -system.cpu1.commit.op_class_0::MemWrite 7337296 13.02% 100.00% # Class of committed instruction +system.cpu1.commit.op_class_0::IntAlu 16018762 63.22% 63.22% # Class of committed instruction +system.cpu1.commit.op_class_0::IntMult 33831 0.13% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::IntDiv 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatMult 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMult 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShift 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 63.35% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMisc 4083 0.02% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.37% # Class of committed instruction +system.cpu1.commit.op_class_0::MemRead 4963292 19.59% 82.96% # Class of committed instruction +system.cpu1.commit.op_class_0::MemWrite 4318986 17.04% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu1.commit.op_class_0::total 56366249 # Class of committed instruction -system.cpu1.commit.bw_lim_events 459258 # number cycles where commit BW limit reached -system.cpu1.rob.rob_reads 150434096 # The number of ROB reads -system.cpu1.rob.rob_writes 123166009 # The number of ROB writes -system.cpu1.timesIdled 67345 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 978661 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 5136638072 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 45842675 # Number of Instructions Simulated -system.cpu1.committedOps 56333036 # Number of Ops (including micro ops) Simulated -system.cpu1.cpi 2.477336 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 2.477336 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.403659 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.403659 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 62490093 # number of integer regfile reads -system.cpu1.int_regfile_writes 39068646 # number of integer regfile writes -system.cpu1.fp_regfile_reads 1381 # number of floating regfile reads +system.cpu1.commit.op_class_0::total 25338954 # Class of committed instruction +system.cpu1.commit.bw_lim_events 439732 # number cycles where commit BW limit reached +system.cpu1.rob.rob_reads 67911551 # The number of ROB reads +system.cpu1.rob.rob_writes 56552827 # The number of ROB writes +system.cpu1.timesIdled 67532 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 960268 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 5207215501 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 20744987 # Number of Instructions Simulated +system.cpu1.committedOps 25305741 # Number of Ops (including micro ops) Simulated +system.cpu1.cpi 2.073910 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 2.073910 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.482181 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.482181 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 29917814 # number of integer regfile reads +system.cpu1.int_regfile_writes 16874088 # number of integer regfile writes +system.cpu1.fp_regfile_reads 1382 # number of floating regfile reads system.cpu1.fp_regfile_writes 516 # number of floating regfile writes -system.cpu1.cc_regfile_reads 211116899 # number of cc regfile reads -system.cpu1.cc_regfile_writes 18233735 # number of cc regfile writes -system.cpu1.misc_regfile_reads 156287903 # number of misc regfile reads -system.cpu1.misc_regfile_writes 421035 # number of misc regfile writes -system.cpu1.dcache.tags.replacements 227457 # number of replacements -system.cpu1.dcache.tags.tagsinuse 483.345523 # Cycle average of tags in use -system.cpu1.dcache.tags.total_refs 17322126 # Total number of references to valid blocks. -system.cpu1.dcache.tags.sampled_refs 227768 # Sample count of references to valid blocks. -system.cpu1.dcache.tags.avg_refs 76.051623 # Average number of references to valid blocks. -system.cpu1.dcache.tags.warmup_cycle 89024511500 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.tags.occ_blocks::cpu1.data 483.345523 # Average occupied blocks per requestor -system.cpu1.dcache.tags.occ_percent::cpu1.data 0.944034 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_percent::total 0.944034 # Average percentage of cache occupancy -system.cpu1.dcache.tags.occ_task_id_blocks::1024 311 # Occupied blocks per task id +system.cpu1.cc_regfile_reads 95785070 # number of cc regfile reads +system.cpu1.cc_regfile_writes 9455596 # number of cc regfile writes +system.cpu1.misc_regfile_reads 60806398 # number of misc regfile reads +system.cpu1.misc_regfile_writes 422782 # number of misc regfile writes +system.cpu1.dcache.tags.replacements 228231 # number of replacements +system.cpu1.dcache.tags.tagsinuse 478.409113 # Cycle average of tags in use +system.cpu1.dcache.tags.total_refs 8403253 # Total number of references to valid blocks. +system.cpu1.dcache.tags.sampled_refs 228545 # Sample count of references to valid blocks. +system.cpu1.dcache.tags.avg_refs 36.768483 # Average number of references to valid blocks. +system.cpu1.dcache.tags.warmup_cycle 103444079500 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.tags.occ_blocks::cpu1.data 478.409113 # Average occupied blocks per requestor +system.cpu1.dcache.tags.occ_percent::cpu1.data 0.934393 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_percent::total 0.934393 # Average percentage of cache occupancy +system.cpu1.dcache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id system.cpu1.dcache.tags.age_task_id_blocks_1024::2 282 # Occupied blocks per task id -system.cpu1.dcache.tags.age_task_id_blocks_1024::3 29 # Occupied blocks per task id -system.cpu1.dcache.tags.occ_task_id_percent::1024 0.607422 # Percentage of cache occupancy per task id -system.cpu1.dcache.tags.tag_accesses 36423981 # Number of tag accesses -system.cpu1.dcache.tags.data_accesses 36423981 # Number of data accesses -system.cpu1.dcache.ReadReq_hits::cpu1.data 10467087 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 10467087 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 6561195 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 6561195 # number of WriteReq hits -system.cpu1.dcache.SoftPFReq_hits::cpu1.data 65021 # number of SoftPFReq hits -system.cpu1.dcache.SoftPFReq_hits::total 65021 # number of SoftPFReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 88659 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 88659 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80691 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 80691 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 17028282 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 17028282 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 17093303 # number of overall hits -system.cpu1.dcache.overall_hits::total 17093303 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 254533 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 254533 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 479063 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 479063 # number of WriteReq misses -system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35844 # number of SoftPFReq misses -system.cpu1.dcache.SoftPFReq_misses::total 35844 # number of SoftPFReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19098 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 19098 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23509 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 23509 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 733596 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 733596 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 769440 # number of overall misses -system.cpu1.dcache.overall_misses::total 769440 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 3958996431 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 3958996431 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 10579018157 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 10579018157 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 370185734 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 370185734 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 549251321 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 549251321 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 798500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.StoreCondFailReq_miss_latency::total 798500 # number of StoreCondFailReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 14538014588 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 14538014588 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 14538014588 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 14538014588 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 10721620 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 10721620 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 7040258 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 7040258 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 100865 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.SoftPFReq_accesses::total 100865 # number of SoftPFReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 107757 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 107757 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 104200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 104200 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 17761878 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 17761878 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 17862743 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 17862743 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023740 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023740 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.068046 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.068046 # miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.355366 # miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_miss_rate::total 0.355366 # miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.177232 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.177232 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.225614 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.225614 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.041302 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.041302 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.043075 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.043075 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15553.961298 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15553.961298 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22082.728487 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 22082.728487 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19383.481726 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19383.481726 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23363.448934 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23363.448934 # average StoreCondReq miss latency +system.cpu1.dcache.tags.age_task_id_blocks_1024::3 32 # Occupied blocks per task id +system.cpu1.dcache.tags.occ_task_id_percent::1024 0.613281 # Percentage of cache occupancy per task id +system.cpu1.dcache.tags.tag_accesses 18586968 # Number of tag accesses +system.cpu1.dcache.tags.data_accesses 18586968 # Number of data accesses +system.cpu1.dcache.ReadReq_hits::cpu1.data 4548259 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 4548259 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 3563356 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 3563356 # number of WriteReq hits +system.cpu1.dcache.SoftPFReq_hits::cpu1.data 63759 # number of SoftPFReq hits +system.cpu1.dcache.SoftPFReq_hits::total 63759 # number of SoftPFReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 87271 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 87271 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79516 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79516 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 8111615 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 8111615 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 8175374 # number of overall hits +system.cpu1.dcache.overall_hits::total 8175374 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 254647 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 254647 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 480567 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 480567 # number of WriteReq misses +system.cpu1.dcache.SoftPFReq_misses::cpu1.data 35928 # number of SoftPFReq misses +system.cpu1.dcache.SoftPFReq_misses::total 35928 # number of SoftPFReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 19211 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 19211 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 23462 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 23462 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 735214 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 735214 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 771142 # number of overall misses +system.cpu1.dcache.overall_misses::total 771142 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4017153000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 4017153000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 11025282924 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 11025282924 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 376163500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 376163500 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 545526500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 545526500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::cpu1.data 528500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.StoreCondFailReq_miss_latency::total 528500 # number of StoreCondFailReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 15042435924 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 15042435924 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 15042435924 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 15042435924 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 4802906 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 4802906 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4043923 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4043923 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::cpu1.data 99687 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.SoftPFReq_accesses::total 99687 # number of SoftPFReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 106482 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 106482 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 102978 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 102978 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 8846829 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 8846829 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 8946516 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 8946516 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.053019 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.053019 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.118837 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.118837 # miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::cpu1.data 0.360408 # miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_miss_rate::total 0.360408 # miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.180415 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.180415 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.227835 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.227835 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.083105 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.083105 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.086195 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.086195 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15775.379250 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15775.379250 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22942.238905 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 22942.238905 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 19580.630889 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 19580.630889 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 23251.491774 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 23251.491774 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::cpu1.data inf # average StoreCondFailReq miss latency system.cpu1.dcache.StoreCondFailReq_avg_miss_latency::total inf # average StoreCondFailReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 19817.467091 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 19817.467091 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 18894.279720 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 18894.279720 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 393 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 1480475 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 42 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 48784 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.357143 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 30.347552 # average number of cycles each access was blocked +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20459.942172 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20459.942172 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 19506.700354 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 19506.700354 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 359 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 1638919 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 40 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 49248 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.975000 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 33.278895 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 138868 # number of writebacks -system.cpu1.dcache.writebacks::total 138868 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91268 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 91268 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375164 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 375164 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13545 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13545 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 466432 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 466432 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 466432 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 466432 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163265 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 163265 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 103899 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 103899 # number of WriteReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32275 # number of SoftPFReq MSHR misses -system.cpu1.dcache.SoftPFReq_mshr_misses::total 32275 # number of SoftPFReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5553 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5553 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23509 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 23509 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 267164 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 267164 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 299439 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 299439 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.ReadReq_mshr_uncacheable::total 17059 # number of ReadReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable -system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses -system.cpu1.dcache.overall_mshr_uncacheable_misses::total 31400 # number of overall MSHR uncacheable misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2133861458 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2133861458 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2484196176 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2484196176 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 503074190 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 503074190 # number of SoftPFReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 95947255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 95947255 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 512832179 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 512832179 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 777500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 777500 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4618057634 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 4618057634 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5121131824 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 5121131824 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 2900210250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 2900210250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 2419067503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 2419067503 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 5319277753 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 5319277753 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.015228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.015228 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.014758 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.014758 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.319982 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.319982 # mshr miss rate for SoftPFReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.051533 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.051533 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.225614 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.225614 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.015041 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.015041 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.016763 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.016763 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13069.925936 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13069.925936 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23909.721711 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 23909.721711 # average WriteReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 15587.116654 # average SoftPFReq mshr miss latency -system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 15587.116654 # average SoftPFReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 17278.453989 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 17278.453989 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 21814.291505 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 21814.291505 # average StoreCondReq mshr miss latency +system.cpu1.dcache.writebacks::writebacks 137260 # number of writebacks +system.cpu1.dcache.writebacks::total 137260 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 91413 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 91413 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 375801 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 375801 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 13808 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 13808 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 467214 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 467214 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 467214 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 467214 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163234 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 163234 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104766 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 104766 # number of WriteReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::cpu1.data 32551 # number of SoftPFReq MSHR misses +system.cpu1.dcache.SoftPFReq_mshr_misses::total 32551 # number of SoftPFReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5403 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5403 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 23462 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 23462 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 268000 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 268000 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 300551 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 300551 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.ReadReq_mshr_uncacheable::total 5603 # number of ReadReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable +system.cpu1.dcache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses +system.cpu1.dcache.overall_mshr_uncacheable_misses::total 10511 # number of overall MSHR uncacheable misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2247760000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2247760000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2639771935 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2639771935 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 542309000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.SoftPFReq_mshr_miss_latency::total 542309000 # number of SoftPFReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 101732500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 101732500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 522075500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 522075500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 517500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 517500 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 4887531935 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 4887531935 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 5429840935 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 5429840935 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 989470000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 989470000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 857954500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 857954500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 1847424500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 1847424500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033987 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.033987 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025907 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.025907 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.326532 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.SoftPFReq_mshr_miss_rate::total 0.326532 # mshr miss rate for SoftPFReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050741 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.050741 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.227835 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.227835 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.030293 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.030293 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.033594 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.033594 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13770.170430 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 13770.170430 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 25196.838049 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 25196.838049 # average WriteReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 16660.286934 # average SoftPFReq mshr miss latency +system.cpu1.dcache.SoftPFReq_avg_mshr_miss_latency::total 16660.286934 # average SoftPFReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 18828.891357 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 18828.891357 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 22251.960617 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 22251.960617 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17285.478710 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17285.478710 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17102.420940 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17102.420940 # average overall mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 170010.566270 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 170010.566270 # average ReadReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 168681.926156 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 168681.926156 # average WriteReq mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 169403.750096 # average overall mshr uncacheable latency -system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 169403.750096 # average overall mshr uncacheable latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18237.059459 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18237.059459 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18066.288034 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18066.288034 # average overall mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 176596.466179 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total 176596.466179 # average ReadReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 174807.355338 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total 174807.355338 # average WriteReq mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 175761.059842 # average overall mshr uncacheable latency +system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total 175761.059842 # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.icache.tags.replacements 671809 # number of replacements -system.cpu1.icache.tags.tagsinuse 498.529348 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 45027049 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 672321 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 66.972546 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 78856865000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.529348 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973690 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.973690 # Average percentage of cache occupancy +system.cpu1.icache.tags.replacements 661426 # number of replacements +system.cpu1.icache.tags.tagsinuse 498.525577 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 9800007 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 661938 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 14.805023 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 78861824000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 498.525577 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.973683 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.973683 # Average percentage of cache occupancy system.cpu1.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::2 495 # Occupied blocks per task id system.cpu1.icache.tags.age_task_id_blocks_1024::3 17 # Occupied blocks per task id system.cpu1.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu1.icache.tags.tag_accesses 92117192 # Number of tag accesses -system.cpu1.icache.tags.data_accesses 92117192 # Number of data accesses -system.cpu1.icache.ReadReq_hits::cpu1.inst 45027049 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 45027049 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 45027049 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 45027049 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 45027049 # number of overall hits -system.cpu1.icache.overall_hits::total 45027049 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 695384 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 695384 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 695384 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 695384 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 695384 # number of overall misses -system.cpu1.icache.overall_misses::total 695384 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6371214084 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6371214084 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6371214084 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6371214084 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6371214084 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6371214084 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 45722433 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 45722433 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 45722433 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 45722433 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 45722433 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 45722433 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.015209 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.015209 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.015209 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.015209 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.015209 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.015209 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9162.152255 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 9162.152255 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 9162.152255 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9162.152255 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 9162.152255 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 596666 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 27 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 49414 # number of cycles access was blocked +system.cpu1.icache.tags.tag_accesses 21636569 # Number of tag accesses +system.cpu1.icache.tags.data_accesses 21636569 # Number of data accesses +system.cpu1.icache.ReadReq_hits::cpu1.inst 9800007 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 9800007 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 9800007 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 9800007 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 9800007 # number of overall hits +system.cpu1.icache.overall_hits::total 9800007 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 687303 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 687303 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 687303 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 687303 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 687303 # number of overall misses +system.cpu1.icache.overall_misses::total 687303 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6263235013 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6263235013 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6263235013 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6263235013 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6263235013 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6263235013 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 10487310 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 10487310 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 10487310 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 10487310 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 10487310 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 10487310 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.065537 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.065537 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.065537 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.065537 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.065537 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.065537 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 9112.771242 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 9112.771242 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 9112.771242 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 9112.771242 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 9112.771242 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 638996 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 564 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 53890 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 12.074837 # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets 27 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.857413 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets 564 # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 23058 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 23058 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 23058 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 23058 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 23058 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 23058 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 672326 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 672326 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 672326 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 672326 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 672326 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 672326 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable -system.cpu1.icache.ReadReq_mshr_uncacheable::total 100 # number of ReadReq MSHR uncacheable -system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses -system.cpu1.icache.overall_mshr_uncacheable_misses::total 100 # number of overall MSHR uncacheable misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5482686465 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5482686465 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5482686465 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5482686465 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5482686465 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5482686465 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8677000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8677000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8677000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 8677000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014705 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014705 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014705 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014705 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8154.803570 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8154.803570 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 8154.803570 # average overall mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average ReadReq mshr uncacheable latency -system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 86770 # average ReadReq mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 86770 # average overall mshr uncacheable latency -system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 86770 # average overall mshr uncacheable latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 25354 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 25354 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 25354 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 25354 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 25354 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 25354 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 661949 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 661949 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 661949 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 661949 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 661949 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 661949 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable +system.cpu1.icache.ReadReq_mshr_uncacheable::total 102 # number of ReadReq MSHR uncacheable +system.cpu1.icache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses +system.cpu1.icache.overall_mshr_uncacheable_misses::total 102 # number of overall MSHR uncacheable misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5721508360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5721508360 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5721508360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5721508360 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5721508360 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5721508360 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 8594000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 8594000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 8594000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 8594000 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.063119 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.063119 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.063119 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.063119 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 8643.427757 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 8643.427757 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 8643.427757 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average ReadReq mshr uncacheable latency +system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total 84254.901961 # average ReadReq mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst 84254.901961 # average overall mshr uncacheable latency +system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total 84254.901961 # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l2cache.prefetcher.num_hwpf_issued 264317 # number of hwpf issued -system.cpu1.l2cache.prefetcher.pfIdentified 265106 # number of prefetch candidates identified -system.cpu1.l2cache.prefetcher.pfBufferHit 699 # number of redundant prefetches already in prefetch queue +system.cpu1.l2cache.prefetcher.num_hwpf_issued 269622 # number of hwpf issued +system.cpu1.l2cache.prefetcher.pfIdentified 270613 # number of prefetch candidates identified +system.cpu1.l2cache.prefetcher.pfBufferHit 884 # number of redundant prefetches already in prefetch queue system.cpu1.l2cache.prefetcher.pfInCache 0 # number of redundant prefetches already in cache/mshr dropped system.cpu1.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size -system.cpu1.l2cache.prefetcher.pfSpanPage 68110 # number of prefetches not generated due to page crossing -system.cpu1.l2cache.tags.replacements 61852 # number of replacements -system.cpu1.l2cache.tags.tagsinuse 15537.791452 # Cycle average of tags in use -system.cpu1.l2cache.tags.total_refs 937119 # Total number of references to valid blocks. -system.cpu1.l2cache.tags.sampled_refs 76426 # Sample count of references to valid blocks. -system.cpu1.l2cache.tags.avg_refs 12.261783 # Average number of references to valid blocks. +system.cpu1.l2cache.prefetcher.pfSpanPage 67787 # number of prefetches not generated due to page crossing +system.cpu1.l2cache.tags.replacements 66660 # number of replacements +system.cpu1.l2cache.tags.tagsinuse 15577.889137 # Cycle average of tags in use +system.cpu1.l2cache.tags.total_refs 1655246 # Total number of references to valid blocks. +system.cpu1.l2cache.tags.sampled_refs 81265 # Sample count of references to valid blocks. +system.cpu1.l2cache.tags.avg_refs 20.368498 # Average number of references to valid blocks. system.cpu1.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l2cache.tags.occ_blocks::writebacks 6612.049075 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 15.719968 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.202712 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4939.798550 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2550.027939 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1417.993208 # Average occupied blocks per requestor -system.cpu1.l2cache.tags.occ_percent::writebacks 0.403567 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000959 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000134 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.301501 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.155641 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.086547 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_percent::total 0.948352 # Average percentage of cache occupancy -system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1249 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1023 36 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13289 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 878 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 355 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 9 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 11 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 16 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8497 # Occupied blocks per task id -system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4330 # Occupied blocks per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.076233 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.002197 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811096 # Percentage of cache occupancy per task id -system.cpu1.l2cache.tags.tag_accesses 18910778 # Number of tag accesses -system.cpu1.l2cache.tags.data_accesses 18910778 # Number of data accesses -system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19107 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7219 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.inst 650283 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::cpu1.data 128648 # number of ReadReq hits -system.cpu1.l2cache.ReadReq_hits::total 805257 # number of ReadReq hits -system.cpu1.l2cache.Writeback_hits::writebacks 138868 # number of Writeback hits -system.cpu1.l2cache.Writeback_hits::total 138868 # number of Writeback hits -system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 1925 # number of UpgradeReq hits -system.cpu1.l2cache.UpgradeReq_hits::total 1925 # number of UpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1050 # number of SCUpgradeReq hits -system.cpu1.l2cache.SCUpgradeReq_hits::total 1050 # number of SCUpgradeReq hits -system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38271 # number of ReadExReq hits -system.cpu1.l2cache.ReadExReq_hits::total 38271 # number of ReadExReq hits -system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19107 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7219 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.inst 650283 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::cpu1.data 166919 # number of demand (read+write) hits -system.cpu1.l2cache.demand_hits::total 843528 # number of demand (read+write) hits -system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19107 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7219 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.inst 650283 # number of overall hits -system.cpu1.l2cache.overall_hits::cpu1.data 166919 # number of overall hits -system.cpu1.l2cache.overall_hits::total 843528 # number of overall hits -system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 427 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 276 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.inst 22038 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::cpu1.data 72420 # number of ReadReq misses -system.cpu1.l2cache.ReadReq_misses::total 95161 # number of ReadReq misses -system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29112 # number of UpgradeReq misses -system.cpu1.l2cache.UpgradeReq_misses::total 29112 # number of UpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22458 # number of SCUpgradeReq misses -system.cpu1.l2cache.SCUpgradeReq_misses::total 22458 # number of SCUpgradeReq misses +system.cpu1.l2cache.tags.occ_blocks::writebacks 6747.638156 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.dtb.walker 12.637913 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.itb.walker 2.167789 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.inst 4673.355619 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.data 2625.058292 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_blocks::cpu1.l2cache.prefetcher 1517.031368 # Average occupied blocks per requestor +system.cpu1.l2cache.tags.occ_percent::writebacks 0.411843 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.dtb.walker 0.000771 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.itb.walker 0.000132 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.inst 0.285239 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.data 0.160221 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::cpu1.l2cache.prefetcher 0.092592 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_percent::total 0.950799 # Average percentage of cache occupancy +system.cpu1.l2cache.tags.occ_task_id_blocks::1022 1291 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1023 24 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_blocks::1024 13290 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::2 17 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::3 868 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1022::4 406 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::2 8 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::3 12 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::2 470 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::3 8605 # Occupied blocks per task id +system.cpu1.l2cache.tags.age_task_id_blocks_1024::4 4215 # Occupied blocks per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1022 0.078796 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1023 0.001465 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.occ_task_id_percent::1024 0.811157 # Percentage of cache occupancy per task id +system.cpu1.l2cache.tags.tag_accesses 30536660 # Number of tag accesses +system.cpu1.l2cache.tags.data_accesses 30536660 # Number of data accesses +system.cpu1.l2cache.ReadReq_hits::cpu1.dtb.walker 19077 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::cpu1.itb.walker 7323 # number of ReadReq hits +system.cpu1.l2cache.ReadReq_hits::total 26400 # number of ReadReq hits +system.cpu1.l2cache.Writeback_hits::writebacks 137259 # number of Writeback hits +system.cpu1.l2cache.Writeback_hits::total 137259 # number of Writeback hits +system.cpu1.l2cache.UpgradeReq_hits::cpu1.data 2433 # number of UpgradeReq hits +system.cpu1.l2cache.UpgradeReq_hits::total 2433 # number of UpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::cpu1.data 1103 # number of SCUpgradeReq hits +system.cpu1.l2cache.SCUpgradeReq_hits::total 1103 # number of SCUpgradeReq hits +system.cpu1.l2cache.ReadExReq_hits::cpu1.data 38090 # number of ReadExReq hits +system.cpu1.l2cache.ReadExReq_hits::total 38090 # number of ReadExReq hits +system.cpu1.l2cache.ReadCleanReq_hits::cpu1.inst 639615 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadCleanReq_hits::total 639615 # number of ReadCleanReq hits +system.cpu1.l2cache.ReadSharedReq_hits::cpu1.data 127678 # number of ReadSharedReq hits +system.cpu1.l2cache.ReadSharedReq_hits::total 127678 # number of ReadSharedReq hits +system.cpu1.l2cache.demand_hits::cpu1.dtb.walker 19077 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.itb.walker 7323 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.inst 639615 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::cpu1.data 165768 # number of demand (read+write) hits +system.cpu1.l2cache.demand_hits::total 831783 # number of demand (read+write) hits +system.cpu1.l2cache.overall_hits::cpu1.dtb.walker 19077 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.itb.walker 7323 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.inst 639615 # number of overall hits +system.cpu1.l2cache.overall_hits::cpu1.data 165768 # number of overall hits +system.cpu1.l2cache.overall_hits::total 831783 # number of overall hits +system.cpu1.l2cache.ReadReq_misses::cpu1.dtb.walker 431 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::cpu1.itb.walker 286 # number of ReadReq misses +system.cpu1.l2cache.ReadReq_misses::total 717 # number of ReadReq misses +system.cpu1.l2cache.Writeback_misses::writebacks 1 # number of Writeback misses +system.cpu1.l2cache.Writeback_misses::total 1 # number of Writeback misses +system.cpu1.l2cache.UpgradeReq_misses::cpu1.data 29127 # number of UpgradeReq misses +system.cpu1.l2cache.UpgradeReq_misses::total 29127 # number of UpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::cpu1.data 22358 # number of SCUpgradeReq misses +system.cpu1.l2cache.SCUpgradeReq_misses::total 22358 # number of SCUpgradeReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::cpu1.data 1 # number of SCUpgradeFailReq misses system.cpu1.l2cache.SCUpgradeFailReq_misses::total 1 # number of SCUpgradeFailReq misses -system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35228 # number of ReadExReq misses -system.cpu1.l2cache.ReadExReq_misses::total 35228 # number of ReadExReq misses -system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 427 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.itb.walker 276 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.inst 22038 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::cpu1.data 107648 # number of demand (read+write) misses -system.cpu1.l2cache.demand_misses::total 130389 # number of demand (read+write) misses -system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 427 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.itb.walker 276 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.inst 22038 # number of overall misses -system.cpu1.l2cache.overall_misses::cpu1.data 107648 # number of overall misses -system.cpu1.l2cache.overall_misses::total 130389 # number of overall misses -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9785994 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5538750 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.inst 913296236 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::cpu1.data 1683125409 # number of ReadReq miss cycles -system.cpu1.l2cache.ReadReq_miss_latency::total 2611746389 # number of ReadReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 548231087 # number of UpgradeReq miss cycles -system.cpu1.l2cache.UpgradeReq_miss_latency::total 548231087 # number of UpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449027944 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449027944 # number of SCUpgradeReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 763500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 763500 # number of SCUpgradeFailReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1429440182 # number of ReadExReq miss cycles -system.cpu1.l2cache.ReadExReq_miss_latency::total 1429440182 # number of ReadExReq miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9785994 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5538750 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.inst 913296236 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::cpu1.data 3112565591 # number of demand (read+write) miss cycles -system.cpu1.l2cache.demand_miss_latency::total 4041186571 # number of demand (read+write) miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9785994 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5538750 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.inst 913296236 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::cpu1.data 3112565591 # number of overall miss cycles -system.cpu1.l2cache.overall_miss_latency::total 4041186571 # number of overall miss cycles -system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19534 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7495 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.inst 672321 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::cpu1.data 201068 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.ReadReq_accesses::total 900418 # number of ReadReq accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::writebacks 138868 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.Writeback_accesses::total 138868 # number of Writeback accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31037 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.UpgradeReq_accesses::total 31037 # number of UpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23508 # number of SCUpgradeReq accesses(hits+misses) -system.cpu1.l2cache.SCUpgradeReq_accesses::total 23508 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_misses::cpu1.data 35752 # number of ReadExReq misses +system.cpu1.l2cache.ReadExReq_misses::total 35752 # number of ReadExReq misses +system.cpu1.l2cache.ReadCleanReq_misses::cpu1.inst 22316 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadCleanReq_misses::total 22316 # number of ReadCleanReq misses +system.cpu1.l2cache.ReadSharedReq_misses::cpu1.data 73485 # number of ReadSharedReq misses +system.cpu1.l2cache.ReadSharedReq_misses::total 73485 # number of ReadSharedReq misses +system.cpu1.l2cache.demand_misses::cpu1.dtb.walker 431 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.itb.walker 286 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.inst 22316 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::cpu1.data 109237 # number of demand (read+write) misses +system.cpu1.l2cache.demand_misses::total 132270 # number of demand (read+write) misses +system.cpu1.l2cache.overall_misses::cpu1.dtb.walker 431 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.itb.walker 286 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.inst 22316 # number of overall misses +system.cpu1.l2cache.overall_misses::cpu1.data 109237 # number of overall misses +system.cpu1.l2cache.overall_misses::total 132270 # number of overall misses +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.dtb.walker 9445500 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::cpu1.itb.walker 5864000 # number of ReadReq miss cycles +system.cpu1.l2cache.ReadReq_miss_latency::total 15309500 # number of ReadReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::cpu1.data 555921000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.UpgradeReq_miss_latency::total 555921000 # number of UpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::cpu1.data 449033000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeReq_miss_latency::total 449033000 # number of SCUpgradeReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::cpu1.data 501000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_miss_latency::total 501000 # number of SCUpgradeFailReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::cpu1.data 1528833498 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadExReq_miss_latency::total 1528833498 # number of ReadExReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::cpu1.inst 894673000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadCleanReq_miss_latency::total 894673000 # number of ReadCleanReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::cpu1.data 1746677998 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.ReadSharedReq_miss_latency::total 1746677998 # number of ReadSharedReq miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.dtb.walker 9445500 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.itb.walker 5864000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.inst 894673000 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::cpu1.data 3275511496 # number of demand (read+write) miss cycles +system.cpu1.l2cache.demand_miss_latency::total 4185493996 # number of demand (read+write) miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.dtb.walker 9445500 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.itb.walker 5864000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.inst 894673000 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::cpu1.data 3275511496 # number of overall miss cycles +system.cpu1.l2cache.overall_miss_latency::total 4185493996 # number of overall miss cycles +system.cpu1.l2cache.ReadReq_accesses::cpu1.dtb.walker 19508 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::cpu1.itb.walker 7609 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.ReadReq_accesses::total 27117 # number of ReadReq accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::writebacks 137260 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.Writeback_accesses::total 137260 # number of Writeback accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::cpu1.data 31560 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.UpgradeReq_accesses::total 31560 # number of UpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::cpu1.data 23461 # number of SCUpgradeReq accesses(hits+misses) +system.cpu1.l2cache.SCUpgradeReq_accesses::total 23461 # number of SCUpgradeReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::cpu1.data 1 # number of SCUpgradeFailReq accesses(hits+misses) system.cpu1.l2cache.SCUpgradeFailReq_accesses::total 1 # number of SCUpgradeFailReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73499 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.ReadExReq_accesses::total 73499 # number of ReadExReq accesses(hits+misses) -system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19534 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7495 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.inst 672321 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::cpu1.data 274567 # number of demand (read+write) accesses -system.cpu1.l2cache.demand_accesses::total 973917 # number of demand (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19534 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7495 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.inst 672321 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::cpu1.data 274567 # number of overall (read+write) accesses -system.cpu1.l2cache.overall_accesses::total 973917 # number of overall (read+write) accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.036825 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.inst 0.032779 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::cpu1.data 0.360177 # miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_miss_rate::total 0.105685 # miss rate for ReadReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.937977 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.937977 # miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.955334 # miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.955334 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.ReadExReq_accesses::cpu1.data 73842 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadExReq_accesses::total 73842 # number of ReadExReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::cpu1.inst 661931 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadCleanReq_accesses::total 661931 # number of ReadCleanReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::cpu1.data 201163 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.ReadSharedReq_accesses::total 201163 # number of ReadSharedReq accesses(hits+misses) +system.cpu1.l2cache.demand_accesses::cpu1.dtb.walker 19508 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.itb.walker 7609 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.inst 661931 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::cpu1.data 275005 # number of demand (read+write) accesses +system.cpu1.l2cache.demand_accesses::total 964053 # number of demand (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.dtb.walker 19508 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.itb.walker 7609 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.inst 661931 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::cpu1.data 275005 # number of overall (read+write) accesses +system.cpu1.l2cache.overall_accesses::total 964053 # number of overall (read+write) accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::cpu1.itb.walker 0.037587 # miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_miss_rate::total 0.026441 # miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_miss_rate::writebacks 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_miss_rate::total 0.000007 # miss rate for Writeback accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::cpu1.data 0.922909 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_miss_rate::total 0.922909 # miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::cpu1.data 0.952986 # miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_miss_rate::total 0.952986 # miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::cpu1.data 1 # miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_miss_rate::total 1 # miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.479299 # miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_miss_rate::total 0.479299 # miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.036825 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.032779 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.392065 # miss rate for demand accesses -system.cpu1.l2cache.demand_miss_rate::total 0.133881 # miss rate for demand accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.021859 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.036825 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.032779 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.392065 # miss rate for overall accesses -system.cpu1.l2cache.overall_miss_rate::total 0.133881 # miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20067.934783 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.inst 41441.883837 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.data 23241.168310 # average ReadReq miss latency -system.cpu1.l2cache.ReadReq_avg_miss_latency::total 27445.554261 # average ReadReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 18831.790567 # average UpgradeReq miss latency -system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 18831.790567 # average UpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 19994.119868 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 19994.119868 # average SCUpgradeReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 763500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 763500 # average SCUpgradeFailReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 40576.819064 # average ReadExReq miss latency -system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 40576.819064 # average ReadExReq miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency -system.cpu1.l2cache.demand_avg_miss_latency::total 30993.309029 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 22918.018735 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20067.934783 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 41441.883837 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 28914.290939 # average overall miss latency -system.cpu1.l2cache.overall_avg_miss_latency::total 30993.309029 # average overall miss latency -system.cpu1.l2cache.blocked_cycles::no_mshrs 61 # number of cycles access was blocked +system.cpu1.l2cache.ReadExReq_miss_rate::cpu1.data 0.484169 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_miss_rate::total 0.484169 # miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::cpu1.inst 0.033713 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_miss_rate::total 0.033713 # miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::cpu1.data 0.365301 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_miss_rate::total 0.365301 # miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.itb.walker 0.037587 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.inst 0.033713 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::cpu1.data 0.397218 # miss rate for demand accesses +system.cpu1.l2cache.demand_miss_rate::total 0.137202 # miss rate for demand accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.dtb.walker 0.022094 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.itb.walker 0.037587 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.inst 0.033713 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::cpu1.data 0.397218 # miss rate for overall accesses +system.cpu1.l2cache.overall_miss_rate::total 0.137202 # miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::cpu1.itb.walker 20503.496503 # average ReadReq miss latency +system.cpu1.l2cache.ReadReq_avg_miss_latency::total 21352.161785 # average ReadReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::cpu1.data 19086.105675 # average UpgradeReq miss latency +system.cpu1.l2cache.UpgradeReq_avg_miss_latency::total 19086.105675 # average UpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::cpu1.data 20083.773146 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_miss_latency::total 20083.773146 # average SCUpgradeReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::cpu1.data 501000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_miss_latency::total 501000 # average SCUpgradeFailReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::cpu1.data 42762.181081 # average ReadExReq miss latency +system.cpu1.l2cache.ReadExReq_avg_miss_latency::total 42762.181081 # average ReadExReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::cpu1.inst 40091.100556 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadCleanReq_avg_miss_latency::total 40091.100556 # average ReadCleanReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::cpu1.data 23769.177356 # average ReadSharedReq miss latency +system.cpu1.l2cache.ReadSharedReq_avg_miss_latency::total 23769.177356 # average ReadSharedReq miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency +system.cpu1.l2cache.demand_avg_miss_latency::total 31643.562380 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.dtb.walker 21915.313225 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.itb.walker 20503.496503 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.inst 40091.100556 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::cpu1.data 29985.366643 # average overall miss latency +system.cpu1.l2cache.overall_avg_miss_latency::total 31643.562380 # average overall miss latency +system.cpu1.l2cache.blocked_cycles::no_mshrs 124 # number of cycles access was blocked system.cpu1.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu1.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 12.200000 # average number of cycles each access was blocked +system.cpu1.l2cache.avg_blocked_cycles::no_mshrs 24.800000 # average number of cycles each access was blocked system.cpu1.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l2cache.fast_writes 0 # number of fast writes performed system.cpu1.l2cache.cache_copies 0 # number of cache copies performed -system.cpu1.l2cache.writebacks::writebacks 35144 # number of writebacks -system.cpu1.l2cache.writebacks::total 35144 # number of writebacks -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.dtb.walker 1 # number of ReadReq MSHR hits +system.cpu1.l2cache.writebacks::writebacks 39050 # number of writebacks +system.cpu1.l2cache.writebacks::total 39050 # number of writebacks system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.itb.walker 13 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.inst 16 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::cpu1.data 141 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadReq_mshr_hits::total 171 # number of ReadReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 736 # number of ReadExReq MSHR hits -system.cpu1.l2cache.ReadExReq_mshr_hits::total 736 # number of ReadExReq MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.dtb.walker 1 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::cpu1.data 854 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadExReq_mshr_hits::total 854 # number of ReadExReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::cpu1.inst 14 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadCleanReq_mshr_hits::total 14 # number of ReadCleanReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::cpu1.data 144 # number of ReadSharedReq MSHR hits +system.cpu1.l2cache.ReadSharedReq_mshr_hits::total 144 # number of ReadSharedReq MSHR hits system.cpu1.l2cache.demand_mshr_hits::cpu1.itb.walker 13 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 16 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::cpu1.data 877 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.demand_mshr_hits::total 907 # number of demand (read+write) MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.dtb.walker 1 # number of overall MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.inst 14 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::cpu1.data 998 # number of demand (read+write) MSHR hits +system.cpu1.l2cache.demand_mshr_hits::total 1025 # number of demand (read+write) MSHR hits system.cpu1.l2cache.overall_mshr_hits::cpu1.itb.walker 13 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 16 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::cpu1.data 877 # number of overall MSHR hits -system.cpu1.l2cache.overall_mshr_hits::total 907 # number of overall MSHR hits -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 426 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 263 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.inst 22022 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.data 72279 # number of ReadReq MSHR misses -system.cpu1.l2cache.ReadReq_mshr_misses::total 94990 # number of ReadReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of HardPFReq MSHR misses -system.cpu1.l2cache.HardPFReq_mshr_misses::total 36425 # number of HardPFReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29112 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29112 # number of UpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22458 # number of SCUpgradeReq MSHR misses -system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22458 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.overall_mshr_hits::cpu1.inst 14 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::cpu1.data 998 # number of overall MSHR hits +system.cpu1.l2cache.overall_mshr_hits::total 1025 # number of overall MSHR hits +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.dtb.walker 431 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::cpu1.itb.walker 273 # number of ReadReq MSHR misses +system.cpu1.l2cache.ReadReq_mshr_misses::total 704 # number of ReadReq MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::writebacks 1 # number of Writeback MSHR misses +system.cpu1.l2cache.Writeback_mshr_misses::total 1 # number of Writeback MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::writebacks 3034 # number of CleanEvict MSHR misses +system.cpu1.l2cache.CleanEvict_mshr_misses::total 3034 # number of CleanEvict MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of HardPFReq MSHR misses +system.cpu1.l2cache.HardPFReq_mshr_misses::total 37433 # number of HardPFReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::cpu1.data 29127 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.UpgradeReq_mshr_misses::total 29127 # number of UpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::cpu1.data 22358 # number of SCUpgradeReq MSHR misses +system.cpu1.l2cache.SCUpgradeReq_mshr_misses::total 22358 # number of SCUpgradeReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::cpu1.data 1 # number of SCUpgradeFailReq MSHR misses system.cpu1.l2cache.SCUpgradeFailReq_mshr_misses::total 1 # number of SCUpgradeFailReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34492 # number of ReadExReq MSHR misses -system.cpu1.l2cache.ReadExReq_mshr_misses::total 34492 # number of ReadExReq MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 426 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 263 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22022 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::cpu1.data 106771 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.demand_mshr_misses::total 129482 # number of demand (read+write) MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 426 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 263 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22022 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.data 106771 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 36425 # number of overall MSHR misses -system.cpu1.l2cache.overall_mshr_misses::total 165907 # number of overall MSHR misses -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 17059 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 17159 # number of ReadReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 14341 # number of WriteReq MSHR uncacheable -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 31400 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 31500 # number of overall MSHR uncacheable misses -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 3664750 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.inst 767719764 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.data 1208019590 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 1986398104 # number of ReadReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1404338548 # number of HardPFReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 484116716 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 484116716 # number of UpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 336604833 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 336604833 # number of SCUpgradeReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 672500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 672500 # number of SCUpgradeFailReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1121552915 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1121552915 # number of ReadExReq MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 3664750 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 767719764 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2329572505 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.demand_mshr_miss_latency::total 3107951019 # number of demand (read+write) MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6994000 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 3664750 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 767719764 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2329572505 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1404338548 # number of overall MSHR miss cycles -system.cpu1.l2cache.overall_mshr_miss_latency::total 4512289567 # number of overall MSHR miss cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7885000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 2763450750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 2771335750 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 2311397498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 2311397498 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7885000 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 5074848248 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 5082733248 # number of overall MSHR uncacheable cycles -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.data 0.359475 # mshr miss rate for ReadReq accesses -system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.105495 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadExReq_mshr_misses::cpu1.data 34898 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadExReq_mshr_misses::total 34898 # number of ReadExReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::cpu1.inst 22302 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadCleanReq_mshr_misses::total 22302 # number of ReadCleanReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::cpu1.data 73341 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.ReadSharedReq_mshr_misses::total 73341 # number of ReadSharedReq MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.dtb.walker 431 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.itb.walker 273 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.inst 22302 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::cpu1.data 108239 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.demand_mshr_misses::total 131245 # number of demand (read+write) MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.dtb.walker 431 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.itb.walker 273 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.inst 22302 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.data 108239 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::cpu1.l2cache.prefetcher 37433 # number of overall MSHR misses +system.cpu1.l2cache.overall_mshr_misses::total 168678 # number of overall MSHR misses +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::cpu1.data 5603 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.ReadReq_mshr_uncacheable::total 5705 # number of ReadReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.WriteReq_mshr_uncacheable::total 4908 # number of WriteReq MSHR uncacheable +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::cpu1.data 10511 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.overall_mshr_uncacheable_misses::total 10613 # number of overall MSHR uncacheable misses +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::cpu1.itb.walker 4063500 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_miss_latency::total 10923000 # number of ReadReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.HardPFReq_mshr_miss_latency::total 1619868588 # number of HardPFReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::cpu1.data 495927500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.UpgradeReq_mshr_miss_latency::total 495927500 # number of UpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::cpu1.data 345361500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_latency::total 345361500 # number of SCUpgradeReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::cpu1.data 435000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_latency::total 435000 # number of SCUpgradeFailReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::cpu1.data 1215520500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadExReq_mshr_miss_latency::total 1215520500 # number of ReadExReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::cpu1.inst 760109500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadCleanReq_mshr_miss_latency::total 760109500 # number of ReadCleanReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::cpu1.data 1300287998 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.ReadSharedReq_mshr_miss_latency::total 1300287998 # number of ReadSharedReq MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.itb.walker 4063500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.inst 760109500 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::cpu1.data 2515808498 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.demand_mshr_miss_latency::total 3286840998 # number of demand (read+write) MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.dtb.walker 6859500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.itb.walker 4063500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.inst 760109500 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.data 2515808498 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1619868588 # number of overall MSHR miss cycles +system.cpu1.l2cache.overall_mshr_miss_latency::total 4906709586 # number of overall MSHR miss cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.inst 7829000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::cpu1.data 944359000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_uncacheable_latency::total 952188000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::cpu1.data 821025498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.WriteReq_mshr_uncacheable_latency::total 821025498 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.inst 7829000 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::cpu1.data 1765384498 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.overall_mshr_uncacheable_latency::total 1773213498 # number of overall MSHR uncacheable cycles +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.ReadReq_mshr_miss_rate::total 0.025962 # mshr miss rate for ReadReq accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::writebacks 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.Writeback_mshr_miss_rate::total 0.000007 # mshr miss rate for Writeback accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.cpu1.l2cache.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for HardPFReq accesses system.cpu1.l2cache.HardPFReq_mshr_miss_rate::total inf # mshr miss rate for HardPFReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.937977 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.937977 # mshr miss rate for UpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.955334 # mshr miss rate for SCUpgradeReq accesses -system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.955334 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::cpu1.data 0.922909 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.UpgradeReq_mshr_miss_rate::total 0.922909 # mshr miss rate for UpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.952986 # mshr miss rate for SCUpgradeReq accesses +system.cpu1.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.952986 # mshr miss rate for SCUpgradeReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SCUpgradeFailReq accesses system.cpu1.l2cache.SCUpgradeFailReq_mshr_miss_rate::total 1 # mshr miss rate for SCUpgradeFailReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.469285 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.469285 # mshr miss rate for ReadExReq accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for demand accesses -system.cpu1.l2cache.demand_mshr_miss_rate::total 0.132950 # mshr miss rate for demand accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.021808 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035090 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.032755 # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.388870 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::cpu1.data 0.472604 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadExReq_mshr_miss_rate::total 0.472604 # mshr miss rate for ReadExReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadCleanReq_mshr_miss_rate::total 0.033692 # mshr miss rate for ReadCleanReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::cpu1.data 0.364585 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.ReadSharedReq_mshr_miss_rate::total 0.364585 # mshr miss rate for ReadSharedReq accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for demand accesses +system.cpu1.l2cache.demand_mshr_miss_rate::total 0.136139 # mshr miss rate for demand accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.dtb.walker 0.022094 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.itb.walker 0.035879 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.inst 0.033692 # mshr miss rate for overall accesses +system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.data 0.393589 # mshr miss rate for overall accesses system.cpu1.l2cache.overall_mshr_miss_rate::cpu1.l2cache.prefetcher inf # mshr miss rate for overall accesses -system.cpu1.l2cache.overall_mshr_miss_rate::total 0.170350 # mshr miss rate for overall accesses -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.data 16713.285878 # average ReadReq mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 20911.654953 # average ReadReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average HardPFReq mshr miss latency -system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 38554.249774 # average HardPFReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 16629.455757 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 16629.455757 # average UpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 14988.192760 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 14988.192760 # average SCUpgradeReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 672500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 672500 # average SCUpgradeFailReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 32516.320161 # average ReadExReq mshr miss latency -system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 32516.320161 # average ReadExReq mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency -system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 24002.958087 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 16417.840376 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 13934.410646 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34861.491418 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 21818.401111 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 38554.249774 # average overall mshr miss latency -system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 27197.704539 # average overall mshr miss latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161993.712996 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 161509.164287 # average ReadReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 161174.081166 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 161174.081166 # average WriteReq mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 78850 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 161619.370955 # average overall mshr uncacheable latency -system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 161356.611048 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_mshr_miss_rate::total 0.174968 # mshr miss rate for overall accesses +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average ReadReq mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_miss_latency::total 15515.625000 # average ReadReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average HardPFReq mshr miss latency +system.cpu1.l2cache.HardPFReq_avg_mshr_miss_latency::total 43273.811557 # average HardPFReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17026.384454 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.UpgradeReq_avg_mshr_miss_latency::total 17026.384454 # average UpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 15446.887020 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 15446.887020 # average SCUpgradeReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::cpu1.data 435000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.SCUpgradeFailReq_avg_mshr_miss_latency::total 435000 # average SCUpgradeFailReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::cpu1.data 34830.663648 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadExReq_avg_mshr_miss_latency::total 34830.663648 # average ReadExReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 34082.571070 # average ReadCleanReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 17729.346450 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 17729.346450 # average ReadSharedReq mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency +system.cpu1.l2cache.demand_avg_mshr_miss_latency::total 25043.552120 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.dtb.walker 15915.313225 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.itb.walker 14884.615385 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.inst 34082.571070 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.data 23243.087039 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 43273.811557 # average overall mshr miss latency +system.cpu1.l2cache.overall_avg_mshr_miss_latency::total 29089.208942 # average overall mshr miss latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 168545.243619 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.ReadReq_avg_mshr_uncacheable_latency::total 166904.119194 # average ReadReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 167283.108802 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.WriteReq_avg_mshr_uncacheable_latency::total 167283.108802 # average WriteReq mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.inst 76754.901961 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::cpu1.data 167955.903149 # average overall mshr uncacheable latency +system.cpu1.l2cache.overall_avg_mshr_uncacheable_latency::total 167079.383586 # average overall mshr uncacheable latency system.cpu1.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.toL2Bus.trans_dist::ReadReq 1277963 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadResp 964810 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteResp 14341 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::Writeback 138868 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFReq 45574 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::HardPFResp 1 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeReq 76215 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43067 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeResp 89621 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 21 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExReq 96319 # Transaction distribution -system.cpu1.toL2Bus.trans_dist::ReadExResp 79290 # Transaction distribution -system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1344847 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 942237 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 16928 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42916 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_count::total 2346928 # Packet count per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 43030144 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29597157 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 29980 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78136 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.pkt_size::total 72735417 # Cumulative packet size per connected master and slave (bytes) -system.cpu1.toL2Bus.snoops 628857 # Total snoops (count) -system.cpu1.toL2Bus.snoop_fanout::samples 1745350 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::mean 1.328609 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::stdev 0.469708 # Request fanout histogram +system.cpu1.toL2Bus.trans_dist::ReadReq 70770 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadResp 942311 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::WriteResp 4908 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::Writeback 510267 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::CleanEvict 868505 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::HardPFReq 48336 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeReq 75730 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeReq 43006 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeResp 89941 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::SCUpgradeFailReq 13 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExReq 96740 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadExResp 79738 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadCleanReq 661949 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::ReadSharedReq 536905 # Transaction distribution +system.cpu1.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.cpu1.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 1973224 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 988189 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 17063 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 42721 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_count::total 3021197 # Packet count per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.cpu1.l2cache.cpu_side 42365216 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.cpu1.l2cache.cpu_side 29405313 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.itb.walker.dma::system.cpu1.l2cache.cpu_side 30436 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size_system.cpu1.dtb.walker.dma::system.cpu1.l2cache.cpu_side 78032 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.pkt_size::total 71878997 # Cumulative packet size per connected master and slave (bytes) +system.cpu1.toL2Bus.snoops 1156869 # Total snoops (count) +system.cpu1.toL2Bus.snoop_fanout::samples 2994555 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::mean 1.368102 # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::stdev 0.482289 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::1 1171812 67.14% 67.14% # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::2 573538 32.86% 100.00% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::1 1892252 63.19% 63.19% # Request fanout histogram +system.cpu1.toL2Bus.snoop_fanout::2 1102303 36.81% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.cpu1.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.cpu1.toL2Bus.snoop_fanout::total 1745350 # Request fanout histogram -system.cpu1.toL2Bus.reqLayer0.occupancy 748369465 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoop_fanout::total 2994555 # Request fanout histogram +system.cpu1.toL2Bus.reqLayer0.occupancy 1102178989 # Layer occupancy (ticks) system.cpu1.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.snoopLayer0.occupancy 88425999 # Layer occupancy (ticks) +system.cpu1.toL2Bus.snoopLayer0.occupancy 87567999 # Layer occupancy (ticks) system.cpu1.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer0.occupancy 1009581341 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer0.occupancy 993110829 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer1.occupancy 468876167 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer1.occupancy 449674318 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer2.occupancy 9538553 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer2.occupancy 9464978 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.cpu1.toL2Bus.respLayer3.occupancy 23419937 # Layer occupancy (ticks) +system.cpu1.toL2Bus.respLayer3.occupancy 23224976 # Layer occupancy (ticks) system.cpu1.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.iobus.trans_dist::ReadReq 31011 # Transaction distribution system.iobus.trans_dist::ReadResp 31011 # Transaction distribution system.iobus.trans_dist::WriteReq 59421 # Transaction distribution -system.iobus.trans_dist::WriteResp 23197 # Transaction distribution -system.iobus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution +system.iobus.trans_dist::WriteResp 59421 # Transaction distribution system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 56600 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 122 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) @@ -2874,23 +2931,23 @@ system.iobus.reqLayer25.occupancy 30680000 # La system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 102000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 198987475 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 187554438 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) system.iobus.respLayer0.occupancy 84715000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer3.occupancy 36777012 # Layer occupancy (ticks) +system.iobus.respLayer3.occupancy 36776000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36458 # number of replacements -system.iocache.tags.tagsinuse 14.446991 # Cycle average of tags in use +system.iocache.tags.tagsinuse 14.446879 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36474 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 254817991000 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 14.446991 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.902937 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.902937 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 254837974000 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 14.446879 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.902930 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.902930 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2898,49 +2955,49 @@ system.iocache.tags.tag_accesses 328284 # Nu system.iocache.tags.data_accesses 328284 # Number of data accesses system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses system.iocache.ReadReq_misses::total 252 # number of ReadReq misses -system.iocache.WriteInvalidateReq_misses::realview.ide 36224 # number of WriteInvalidateReq misses -system.iocache.WriteInvalidateReq_misses::total 36224 # number of WriteInvalidateReq misses +system.iocache.WriteLineReq_misses::realview.ide 36224 # number of WriteLineReq misses +system.iocache.WriteLineReq_misses::total 36224 # number of WriteLineReq misses system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses system.iocache.demand_misses::total 252 # number of demand (read+write) misses system.iocache.overall_misses::realview.ide 252 # number of overall misses system.iocache.overall_misses::total 252 # number of overall misses -system.iocache.ReadReq_miss_latency::realview.ide 32304877 # number of ReadReq miss cycles -system.iocache.ReadReq_miss_latency::total 32304877 # number of ReadReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::realview.ide 6652654586 # number of WriteInvalidateReq miss cycles -system.iocache.WriteInvalidateReq_miss_latency::total 6652654586 # number of WriteInvalidateReq miss cycles -system.iocache.demand_miss_latency::realview.ide 32304877 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 32304877 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::realview.ide 32304877 # number of overall miss cycles -system.iocache.overall_miss_latency::total 32304877 # number of overall miss cycles +system.iocache.ReadReq_miss_latency::realview.ide 32277877 # number of ReadReq miss cycles +system.iocache.ReadReq_miss_latency::total 32277877 # number of ReadReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 4275018561 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 4275018561 # number of WriteLineReq miss cycles +system.iocache.demand_miss_latency::realview.ide 32277877 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 32277877 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::realview.ide 32277877 # number of overall miss cycles +system.iocache.overall_miss_latency::total 32277877 # number of overall miss cycles system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::realview.ide 36224 # number of WriteInvalidateReq accesses(hits+misses) -system.iocache.WriteInvalidateReq_accesses::total 36224 # number of WriteInvalidateReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::realview.ide 36224 # number of WriteLineReq accesses(hits+misses) +system.iocache.WriteLineReq_accesses::total 36224 # number of WriteLineReq accesses(hits+misses) system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_miss_rate::realview.ide 1 # miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_miss_rate::total 1 # miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_miss_rate::realview.ide 1 # miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_miss_rate::total 1 # miss rate for WriteLineReq accesses system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses -system.iocache.ReadReq_avg_miss_latency::realview.ide 128193.956349 # average ReadReq miss latency -system.iocache.ReadReq_avg_miss_latency::total 128193.956349 # average ReadReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::realview.ide 183653.229516 # average WriteInvalidateReq miss latency -system.iocache.WriteInvalidateReq_avg_miss_latency::total 183653.229516 # average WriteInvalidateReq miss latency -system.iocache.demand_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 128193.956349 # average overall miss latency -system.iocache.overall_avg_miss_latency::realview.ide 128193.956349 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 128193.956349 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 22817 # number of cycles access was blocked +system.iocache.ReadReq_avg_miss_latency::realview.ide 128086.813492 # average ReadReq miss latency +system.iocache.ReadReq_avg_miss_latency::total 128086.813492 # average ReadReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 118016.192607 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 118016.192607 # average WriteLineReq miss latency +system.iocache.demand_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 128086.813492 # average overall miss latency +system.iocache.overall_avg_miss_latency::realview.ide 128086.813492 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 128086.813492 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 3477 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 6.562266 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -2948,619 +3005,625 @@ system.iocache.writebacks::writebacks 36206 # nu system.iocache.writebacks::total 36206 # number of writebacks system.iocache.ReadReq_mshr_misses::realview.ide 252 # number of ReadReq MSHR misses system.iocache.ReadReq_mshr_misses::total 252 # number of ReadReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::realview.ide 36224 # number of WriteInvalidateReq MSHR misses -system.iocache.WriteInvalidateReq_mshr_misses::total 36224 # number of WriteInvalidateReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::realview.ide 36224 # number of WriteLineReq MSHR misses +system.iocache.WriteLineReq_mshr_misses::total 36224 # number of WriteLineReq MSHR misses system.iocache.demand_mshr_misses::realview.ide 252 # number of demand (read+write) MSHR misses system.iocache.demand_mshr_misses::total 252 # number of demand (read+write) MSHR misses system.iocache.overall_mshr_misses::realview.ide 252 # number of overall MSHR misses system.iocache.overall_mshr_misses::total 252 # number of overall MSHR misses -system.iocache.ReadReq_mshr_miss_latency::realview.ide 19198877 # number of ReadReq MSHR miss cycles -system.iocache.ReadReq_mshr_miss_latency::total 19198877 # number of ReadReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 4768982610 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.WriteInvalidateReq_mshr_miss_latency::total 4768982610 # number of WriteInvalidateReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::realview.ide 19198877 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 19198877 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::realview.ide 19198877 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 19198877 # number of overall MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::realview.ide 19677877 # number of ReadReq MSHR miss cycles +system.iocache.ReadReq_mshr_miss_latency::total 19677877 # number of ReadReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 2463818561 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 2463818561 # number of WriteLineReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::realview.ide 19677877 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 19677877 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::realview.ide 19677877 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 19677877 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteInvalidateReq accesses -system.iocache.WriteInvalidateReq_mshr_miss_rate::total 1 # mshr miss rate for WriteInvalidateReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::realview.ide 1 # mshr miss rate for WriteLineReq accesses +system.iocache.WriteLineReq_mshr_miss_rate::total 1 # mshr miss rate for WriteLineReq accesses system.iocache.demand_mshr_miss_rate::realview.ide 1 # mshr miss rate for demand accesses system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses system.iocache.overall_mshr_miss_rate::realview.ide 1 # mshr miss rate for overall accesses system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 76186.019841 # average ReadReq mshr miss latency -system.iocache.ReadReq_avg_mshr_miss_latency::total 76186.019841 # average ReadReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide 131652.567635 # average WriteInvalidateReq mshr miss latency -system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total 131652.567635 # average WriteInvalidateReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::realview.ide 76186.019841 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 76186.019841 # average overall mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 78086.813492 # average ReadReq mshr miss latency +system.iocache.ReadReq_avg_mshr_miss_latency::total 78086.813492 # average ReadReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68016.192607 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68016.192607 # average WriteLineReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::realview.ide 78086.813492 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 78086.813492 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 130801 # number of replacements -system.l2c.tags.tagsinuse 64048.619051 # Cycle average of tags in use -system.l2c.tags.total_refs 351623 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 195125 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 1.802040 # Average number of references to valid blocks. +system.l2c.tags.replacements 136014 # number of replacements +system.l2c.tags.tagsinuse 64041.678257 # Cycle average of tags in use +system.l2c.tags.total_refs 410908 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 200324 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 2.051217 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 12682.907006 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 14.525676 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 2.048604 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5727.667382 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1961.871644 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 34750.097208 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.787095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.itb.walker 0.903255 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3571.469043 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 1470.884658 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 3857.457480 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.193526 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000222 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.087397 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.029936 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.530244 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.054496 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.022444 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.058860 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.977304 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1022 31466 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1023 31 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 32827 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::2 119 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::3 6139 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1022::4 25208 # Occupied blocks per task id +system.l2c.tags.occ_blocks::writebacks 12985.002975 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 12.737581 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 3.016987 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 6471.116722 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1893.814522 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.l2cache.prefetcher 32628.788989 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.896219 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 1.746917 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3305.203826 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 1817.254812 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.l2cache.prefetcher 4915.098707 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.198135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000194 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000046 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.098741 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028897 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.l2cache.prefetcher 0.497876 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000120 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000027 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.050433 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.027729 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.l2cache.prefetcher 0.074998 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.977198 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1022 30547 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1023 27 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 33736 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::2 132 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::3 6158 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1022::4 24257 # Occupied blocks per task id system.l2c.tags.age_task_id_blocks_1023::3 1 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 3 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 30 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 462 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 4937 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 27395 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1022 0.480133 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1023 0.000473 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.500900 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 5006121 # Number of tag accesses -system.l2c.tags.data_accesses 5006121 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 68 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 31569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 45303 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.l2cache.prefetcher 43197 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 68 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 33 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 16772 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 11005 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.l2cache.prefetcher 7251 # number of ReadReq hits -system.l2c.ReadReq_hits::total 155435 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 227479 # number of Writeback hits -system.l2c.Writeback_hits::total 227479 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2575 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 820 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 3395 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 255 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 98 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 353 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 3872 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 2196 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 6068 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 31569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 49175 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.l2cache.prefetcher 43197 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 68 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 33 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 16772 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 13201 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.l2cache.prefetcher 7251 # number of demand (read+write) hits -system.l2c.demand_hits::total 161503 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 169 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu0.inst 31569 # number of overall hits -system.l2c.overall_hits::cpu0.data 49175 # number of overall hits -system.l2c.overall_hits::cpu0.l2cache.prefetcher 43197 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 68 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 33 # number of overall hits -system.l2c.overall_hits::cpu1.inst 16772 # number of overall hits -system.l2c.overall_hits::cpu1.data 13201 # number of overall hits -system.l2c.overall_hits::cpu1.l2cache.prefetcher 7251 # number of overall hits -system.l2c.overall_hits::total 161503 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 27 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 5 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 17327 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 8118 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 11 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 5250 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 2138 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq misses -system.l2c.ReadReq_misses::total 171166 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 8455 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3870 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 12325 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 920 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 1168 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 2088 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 10724 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 8176 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 18900 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 27 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 5 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 17327 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 18842 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 11 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 5250 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10314 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) misses -system.l2c.demand_misses::total 190066 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 27 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 5 # number of overall misses -system.l2c.overall_misses::cpu0.inst 17327 # number of overall misses -system.l2c.overall_misses::cpu0.data 18842 # number of overall misses -system.l2c.overall_misses::cpu0.l2cache.prefetcher 128828 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 11 # number of overall misses -system.l2c.overall_misses::cpu1.itb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 5250 # number of overall misses -system.l2c.overall_misses::cpu1.data 10314 # number of overall misses -system.l2c.overall_misses::cpu1.l2cache.prefetcher 9461 # number of overall misses -system.l2c.overall_misses::total 190066 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 2599500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 443500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 1426835542 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 735252946 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 1206000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.itb.walker 97250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 448103000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 186224591 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 18394990666 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 7116778 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 2985907 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 10102685 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1350463 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 1030967 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 2381430 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 1037256751 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 678589231 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1715845982 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 2599500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 443500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 1426835542 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 1772509697 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 1206000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.itb.walker 97250 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 448103000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 864813822 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20110836648 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 2599500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 443500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 1426835542 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 1772509697 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14338160773 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 1206000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.itb.walker 97250 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 448103000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 864813822 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1256067564 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20110836648 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 196 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 73 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 48896 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 53421 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.l2cache.prefetcher 172025 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 79 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 34 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 22022 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 13143 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.l2cache.prefetcher 16712 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 326601 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 227479 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 227479 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 11030 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 4690 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 15720 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 1175 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 1266 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2441 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 14596 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 10372 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 24968 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 196 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 73 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 48896 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 68017 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.l2cache.prefetcher 172025 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 79 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 34 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 22022 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23515 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.l2cache.prefetcher 16712 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 351569 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 196 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 73 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 48896 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 68017 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.l2cache.prefetcher 172025 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 79 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 34 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 22022 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23515 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.l2cache.prefetcher 16712 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 351569 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.068493 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.354364 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.151963 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.029412 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.238398 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.162672 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.524083 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.766546 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.825160 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.784033 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.782979 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.922591 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.855387 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.734722 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.788276 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.756969 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.068493 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.354364 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.277019 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.029412 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.238398 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.438614 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.540622 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.137755 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.068493 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.354364 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.277019 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.748891 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.139241 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.029412 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.238398 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.438614 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.566120 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.540622 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 88700 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 82347.523634 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 90570.700419 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.itb.walker 97250 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 85352.952381 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 87102.240879 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 107468.718472 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 841.724187 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 771.552196 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 819.690467 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1467.894565 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 882.677226 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 1140.531609 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96722.934633 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82997.704379 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 90785.501693 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 105809.753707 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 96277.777778 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 88700 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 82347.523634 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 94072.269239 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 111296.929029 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 109636.363636 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.itb.walker 97250 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 85352.952381 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 83848.538104 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 132762.663989 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 105809.753707 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 234 # number of cycles access was blocked +system.l2c.tags.age_task_id_blocks_1023::4 26 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 2 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 23 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 442 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 5063 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 28206 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1022 0.466110 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1023 0.000412 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.514771 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 5562101 # Number of tag accesses +system.l2c.tags.data_accesses 5562101 # Number of data accesses +system.l2c.Writeback_hits::writebacks 232311 # number of Writeback hits +system.l2c.Writeback_hits::total 232311 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2454 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 792 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 3246 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 247 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 65 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 312 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 3756 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 1862 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 5618 # number of ReadExReq hits +system.l2c.ReadSharedReq_hits::cpu0.dtb.walker 184 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.itb.walker 89 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.inst 33340 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.data 45362 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu0.l2cache.prefetcher 43171 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.dtb.walker 54 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.itb.walker 50 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.inst 17322 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.data 11995 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::cpu1.l2cache.prefetcher 7539 # number of ReadSharedReq hits +system.l2c.ReadSharedReq_hits::total 159106 # number of ReadSharedReq hits +system.l2c.demand_hits::cpu0.dtb.walker 184 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 89 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 33340 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 49118 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.l2cache.prefetcher 43171 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 54 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 50 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 17322 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 13857 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.l2cache.prefetcher 7539 # number of demand (read+write) hits +system.l2c.demand_hits::total 164724 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 184 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 89 # number of overall hits +system.l2c.overall_hits::cpu0.inst 33340 # number of overall hits +system.l2c.overall_hits::cpu0.data 49118 # number of overall hits +system.l2c.overall_hits::cpu0.l2cache.prefetcher 43171 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 54 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 50 # number of overall hits +system.l2c.overall_hits::cpu1.inst 17322 # number of overall hits +system.l2c.overall_hits::cpu1.data 13857 # number of overall hits +system.l2c.overall_hits::cpu1.l2cache.prefetcher 7539 # number of overall hits +system.l2c.overall_hits::total 164724 # number of overall hits +system.l2c.UpgradeReq_misses::cpu0.data 8230 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3781 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 12011 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 840 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 1148 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1988 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 11269 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9058 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 20327 # number of ReadExReq misses +system.l2c.ReadSharedReq_misses::cpu0.dtb.walker 25 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.itb.walker 7 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.inst 17264 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.data 8071 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.dtb.walker 10 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.itb.walker 2 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.inst 4969 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.data 2483 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq misses +system.l2c.ReadSharedReq_misses::total 173860 # number of ReadSharedReq misses +system.l2c.demand_misses::cpu0.dtb.walker 25 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 7 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 17264 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 19340 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 4969 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11541 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) misses +system.l2c.demand_misses::total 194187 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 25 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 7 # number of overall misses +system.l2c.overall_misses::cpu0.inst 17264 # number of overall misses +system.l2c.overall_misses::cpu0.data 19340 # number of overall misses +system.l2c.overall_misses::cpu0.l2cache.prefetcher 130238 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu1.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu1.inst 4969 # number of overall misses +system.l2c.overall_misses::cpu1.data 11541 # number of overall misses +system.l2c.overall_misses::cpu1.l2cache.prefetcher 10791 # number of overall misses +system.l2c.overall_misses::total 194187 # number of overall misses +system.l2c.UpgradeReq_miss_latency::cpu0.data 7636500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 4088000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 11724500 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1275500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 739500 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 2015000 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 1086401000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 758222000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1844623000 # number of ReadExReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.dtb.walker 2203000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.itb.walker 699000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.inst 1415731001 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.data 721065000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.dtb.walker 855000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.itb.walker 165500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.inst 421639500 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.data 224776000 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of ReadSharedReq miss cycles +system.l2c.ReadSharedReq_miss_latency::total 18692667834 # number of ReadSharedReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 2203000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 699000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 1415731001 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 1807466000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 855000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.itb.walker 165500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 421639500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 982998000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20537290834 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 2203000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 699000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 1415731001 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 1807466000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.l2cache.prefetcher 14450210544 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 855000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.itb.walker 165500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 421639500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 982998000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.l2cache.prefetcher 1455323289 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20537290834 # number of overall miss cycles +system.l2c.Writeback_accesses::writebacks 232311 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 232311 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 10684 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4573 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 15257 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 1087 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 1213 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 2300 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 15025 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 10920 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 25945 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.dtb.walker 209 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.itb.walker 96 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.inst 50604 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.data 53433 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu0.l2cache.prefetcher 173409 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.dtb.walker 64 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.itb.walker 52 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.inst 22291 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.data 14478 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::cpu1.l2cache.prefetcher 18330 # number of ReadSharedReq accesses(hits+misses) +system.l2c.ReadSharedReq_accesses::total 332966 # number of ReadSharedReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 209 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 96 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 50604 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 68458 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.l2cache.prefetcher 173409 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 64 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 52 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 22291 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 25398 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.l2cache.prefetcher 18330 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 358911 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 209 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 96 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 50604 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 68458 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.l2cache.prefetcher 173409 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 64 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 52 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 22291 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 25398 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.l2cache.prefetcher 18330 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 358911 # number of overall (read+write) accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.770311 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.826810 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.787245 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.772769 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.946414 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.864348 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.750017 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.829487 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.783465 # miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.itb.walker 0.072917 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.inst 0.341159 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.151049 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.itb.walker 0.038462 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.inst 0.222915 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.171502 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_miss_rate::total 0.522155 # miss rate for ReadSharedReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.072917 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.341159 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.282509 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.itb.walker 0.038462 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.222915 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.454406 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.541045 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.119617 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.072917 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.341159 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.282509 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.l2cache.prefetcher 0.751045 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.156250 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.itb.walker 0.038462 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.222915 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.454406 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.l2cache.prefetcher 0.588707 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.541045 # miss rate for overall accesses +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 927.885784 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 1081.195451 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 976.146865 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 1518.452381 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 644.163763 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 1013.581489 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 96406.158488 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 83707.440936 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 90747.429527 # average ReadExReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.dtb.walker 88120 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.itb.walker 99857.142857 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.inst 82004.807750 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 89340.230455 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.dtb.walker 85500 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.itb.walker 82750 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.inst 84853.994768 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 90525.976641 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average ReadSharedReq miss latency +system.l2c.ReadSharedReq_avg_miss_latency::total 107515.632313 # average ReadSharedReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 105760.379603 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 88120 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 99857.142857 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 82004.807750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 93457.394002 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.l2cache.prefetcher 110952.337597 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 85500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.itb.walker 82750 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 84853.994768 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 85174.421627 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.l2cache.prefetcher 134864.543508 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 105760.379603 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 1319 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 2 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 21 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 117 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 62.809524 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 98707 # number of writebacks -system.l2c.writebacks::total 98707 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1.inst 9 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1.inst 9 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1.inst 9 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 27 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 5 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 17319 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 8118 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 11 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.itb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 5241 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 2138 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 171149 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 8455 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 3870 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 12325 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 920 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1168 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 2088 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 10724 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 8176 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 18900 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 27 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 5 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 17319 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 18842 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 11 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.itb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 5241 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10314 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 190049 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 27 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 5 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 17319 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 18842 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 128828 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 11 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.itb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 5241 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10314 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 9461 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 190049 # number of overall MSHR misses -system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3002 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu0.data 17965 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 100 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::cpu1.data 17055 # number of ReadReq MSHR uncacheable -system.l2c.ReadReq_mshr_uncacheable::total 38122 # number of ReadReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu0.data 16714 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::cpu1.data 14341 # number of WriteReq MSHR uncacheable -system.l2c.WriteReq_mshr_uncacheable::total 31055 # number of WriteReq MSHR uncacheable -system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3002 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu0.data 34679 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 100 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::cpu1.data 31396 # number of overall MSHR uncacheable misses -system.l2c.overall_mshr_uncacheable_misses::total 69177 # number of overall MSHR uncacheable misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 380000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 1209530708 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 633945550 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.itb.walker 84250 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 381902000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 159442409 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 16282699204 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 150732427 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 68800353 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 219532780 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 16443920 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 20736167 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 37180087 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 905183749 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 576557769 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1481741518 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 380000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 1209530708 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 1539129299 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 84250 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 381902000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 736000178 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 17764440722 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 2258000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 380000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 1209530708 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 1539129299 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 12753851063 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 1069000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 84250 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 381902000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 736000178 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1140236224 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 17764440722 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 181479250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 3198370250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5885000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 2430251250 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 5815985750 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 2250411545 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 2045879002 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 4296290547 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 181479250 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 5448781795 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5885000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 4476130252 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 10112276297 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.151963 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.162672 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.524031 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.766546 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.825160 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.784033 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.782979 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.922591 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.855387 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.734722 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.788276 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.756969 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.540574 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.137755 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.068493 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.354201 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.277019 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.748891 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.139241 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.029412 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.237989 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.438614 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.566120 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.540574 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 78091.346391 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 74575.495323 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 95137.565536 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 17827.608161 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 17777.868992 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 17811.990264 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 17873.826087 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 17753.567637 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 17806.555077 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 84407.287300 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 70518.318126 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 78399.022116 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 83629.629630 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 76000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 69838.368728 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 81686.089534 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 98999.061252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 97181.818182 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 84250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 72868.154932 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 71359.334691 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 120519.630483 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 93472.950250 # average overall mshr miss latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 178033.412190 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 142494.942832 # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 152562.450816 # average ReadReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 134642.308544 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 142659.438114 # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 138344.567606 # average WriteReq mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 60452.781479 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 157120.499294 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58850 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 142570.080647 # average overall mshr uncacheable latency -system.l2c.overall_avg_mshr_uncacheable_latency::total 146179.746115 # average overall mshr uncacheable latency +system.l2c.writebacks::writebacks 104474 # number of writebacks +system.l2c.writebacks::total 104474 # number of writebacks +system.l2c.ReadSharedReq_mshr_hits::cpu0.inst 5 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::cpu1.inst 10 # number of ReadSharedReq MSHR hits +system.l2c.ReadSharedReq_mshr_hits::total 15 # number of ReadSharedReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1.inst 10 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 15 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1.inst 10 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 15 # number of overall MSHR hits +system.l2c.CleanEvict_mshr_misses::writebacks 3557 # number of CleanEvict MSHR misses +system.l2c.CleanEvict_mshr_misses::total 3557 # number of CleanEvict MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 8230 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3781 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 12011 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 840 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 1148 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1988 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 11269 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9058 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 20327 # number of ReadExReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.dtb.walker 25 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.itb.walker 7 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.inst 17259 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.data 8071 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.dtb.walker 10 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.itb.walker 2 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.inst 4959 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.data 2483 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of ReadSharedReq MSHR misses +system.l2c.ReadSharedReq_mshr_misses::total 173845 # number of ReadSharedReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 25 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 7 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 17259 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 19340 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 4959 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 11541 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 194172 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 25 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 7 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 17259 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 19340 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.l2cache.prefetcher 130238 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 4959 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 11541 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.l2cache.prefetcher 10791 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 194172 # number of overall MSHR misses +system.l2c.ReadReq_mshr_uncacheable::cpu0.inst 3004 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu0.data 29394 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.inst 102 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::cpu1.data 5600 # number of ReadReq MSHR uncacheable +system.l2c.ReadReq_mshr_uncacheable::total 38100 # number of ReadReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu0.data 26127 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::cpu1.data 4908 # number of WriteReq MSHR uncacheable +system.l2c.WriteReq_mshr_uncacheable::total 31035 # number of WriteReq MSHR uncacheable +system.l2c.overall_mshr_uncacheable_misses::cpu0.inst 3004 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu0.data 55521 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.inst 102 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::cpu1.data 10508 # number of overall MSHR uncacheable misses +system.l2c.overall_mshr_uncacheable_misses::total 69135 # number of overall MSHR uncacheable misses +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 170692500 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 78410000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 249102500 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 17547003 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23836000 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 41383003 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 973711000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 667642000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1641353000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.itb.walker 629000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.inst 1242953501 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 640355000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.dtb.walker 755000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.itb.walker 145500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.inst 371358500 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 199946000 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of ReadSharedReq MSHR miss cycles +system.l2c.ReadSharedReq_mshr_miss_latency::total 16953339334 # number of ReadSharedReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 629000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 1242953501 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 1614066000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 755000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.itb.walker 145500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 371358500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 867588000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 18594692334 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 1953000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 629000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 1242953501 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 1614066000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.l2cache.prefetcher 13147830544 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 755000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.itb.walker 145500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 371358500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 867588000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.l2cache.prefetcher 1347413289 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 18594692334 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 189269500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 4916712000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 5992000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 843515500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 5955489000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 3669260542 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 737586502 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 4406847044 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 189269500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 8585972542 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 5992000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1581102002 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 10362336044 # number of overall MSHR uncacheable cycles +system.l2c.CleanEvict_mshr_miss_rate::writebacks inf # mshr miss rate for CleanEvict accesses +system.l2c.CleanEvict_mshr_miss_rate::total inf # mshr miss rate for CleanEvict accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.770311 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.826810 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.787245 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.772769 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.946414 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.864348 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.750017 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.829487 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.783465 # mshr miss rate for ReadExReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.151049 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.171502 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.522110 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.541003 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.119617 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.072917 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.341060 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.282509 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.l2cache.prefetcher 0.751045 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.156250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.itb.walker 0.038462 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.222466 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.454406 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.l2cache.prefetcher 0.588707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.541003 # mshr miss rate for overall accesses +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 20740.279465 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20737.900026 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20739.530430 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 20889.289286 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 20763.066202 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 20816.399899 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 86406.158488 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 73707.440936 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 80747.429527 # average ReadExReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 79340.230455 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 80525.976641 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 97519.855814 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 78120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 89857.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 72017.700968 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 83457.394002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.l2cache.prefetcher 100952.337597 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 75500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 72750 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 74885.763259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 75174.421627 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.l2cache.prefetcher 124864.543508 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 95764.025369 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data 167269.238620 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 150627.767857 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 156312.047244 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0.data 140439.412944 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 150282.498370 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 141996.038150 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.inst 63005.825566 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu0.data 154643.694134 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.inst 58745.098039 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 150466.501903 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 149885.528951 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.membus.trans_dist::ReadReq 209523 # Transaction distribution -system.membus.trans_dist::ReadResp 209522 # Transaction distribution -system.membus.trans_dist::WriteReq 31055 # Transaction distribution -system.membus.trans_dist::WriteResp 31055 # Transaction distribution -system.membus.trans_dist::Writeback 134913 # Transaction distribution -system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution -system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution -system.membus.trans_dist::UpgradeReq 78034 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 41651 # Transaction distribution -system.membus.trans_dist::UpgradeResp 14508 # Transaction distribution -system.membus.trans_dist::SCUpgradeFailReq 12 # Transaction distribution -system.membus.trans_dist::ReadExReq 38508 # Transaction distribution -system.membus.trans_dist::ReadExResp 18805 # Transaction distribution +system.membus.trans_dist::ReadReq 38100 # Transaction distribution +system.membus.trans_dist::ReadResp 212196 # Transaction distribution +system.membus.trans_dist::WriteReq 31035 # Transaction distribution +system.membus.trans_dist::WriteResp 31035 # Transaction distribution +system.membus.trans_dist::Writeback 140680 # Transaction distribution +system.membus.trans_dist::CleanEvict 16716 # Transaction distribution +system.membus.trans_dist::UpgradeReq 77066 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 41581 # Transaction distribution +system.membus.trans_dist::UpgradeResp 14111 # Transaction distribution +system.membus.trans_dist::SCUpgradeFailReq 1 # Transaction distribution +system.membus.trans_dist::ReadExReq 40212 # Transaction distribution +system.membus.trans_dist::ReadExResp 20215 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 174097 # Transaction distribution +system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 107912 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 40 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14300 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 648289 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 770541 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 108921 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 879462 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 14206 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 677829 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 799987 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 108934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 108934 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 908921 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 162793 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 320 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 18522228 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 18713941 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.iocache.mem_side::total 4636480 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 23350421 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 125464 # Total snoops (count) -system.membus.snoop_fanout::samples 569969 # Request fanout histogram +system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 28412 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 19154168 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 19345693 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.iocache.mem_side::total 2318144 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 21663837 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 125106 # Total snoops (count) +system.membus.snoop_fanout::samples 595969 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 569969 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 595969 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 569969 # Request fanout histogram -system.membus.reqLayer0.occupancy 81685500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 595969 # Request fanout histogram +system.membus.reqLayer0.occupancy 81639500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer1.occupancy 28500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 27500 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 12047488 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 11797490 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 1135057072 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 1030129184 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 1127535962 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 1147298884 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 37496988 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 64422049 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -3593,48 +3656,50 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped -system.toL2Bus.trans_dist::ReadReq 490298 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 490282 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 31055 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 31055 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 227479 # Transaction distribution -system.toL2Bus.trans_dist::WriteInvalidateReq 36263 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 81334 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 42004 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 123338 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeFailReq 34 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeFailResp 34 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 50269 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 50269 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 990291 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 371073 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 1361364 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 30980096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6355093 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 37335189 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 292587 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 958737 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.038087 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.191405 # Request fanout histogram +system.toL2Bus.trans_dist::ReadReq 38103 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 495292 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 31035 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 31035 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 373006 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 88968 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 80200 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 41893 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 122093 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeFailReq 23 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeFailResp 23 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 50895 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 50895 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 457205 # Transaction distribution +system.toL2Bus.trans_dist::InvalidateReq 36224 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 1082088 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 352339 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 1434427 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.l2cache.mem_side::system.l2c.cpu_side 31351112 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu1.l2cache.mem_side::system.l2c.cpu_side 6763093 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 38114205 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 462700 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 1239270 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.168619 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.374415 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 922222 96.19% 96.19% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 36515 3.81% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 1030306 83.14% 83.14% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 208964 16.86% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 958737 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 763418418 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 1239270 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 822017005 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 355500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 618495385 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 615196241 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 276060555 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 261600624 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 2070 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 2069 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 2756 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 2739 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |