diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini | 216 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 4110 |
2 files changed, 2274 insertions, 2052 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 7ff8826e3..98e6f2256 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 +eventq_index=0 [system.cpu0.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu0.fuPool.FUList0.opList [system.cpu0.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 [system.cpu0.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu0.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 [system.cpu0.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu0.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu0.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 [system.cpu0.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu0.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu0.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList4.opList [system.cpu0.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 [system.cpu0.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu0.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu0.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu0.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu0.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu0.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu0.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu0.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu0.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu0.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu0.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu0.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu0.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu0.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu0.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu0.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu0.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu0.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu0.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu0.fuPool.FUList6.opList [system.cpu0.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 [system.cpu0.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu0.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu0.fuPool.FUList8.opList [system.cpu0.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,18 +602,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=DerivO3CPU @@ -581,6 +647,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -645,6 +713,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -660,6 +729,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -682,18 +752,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -702,15 +775,18 @@ port=system.toL2Bus.slave[7] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu1.fuPool.FUList0 system.cpu1.fuPool.FUList1 system.cpu1.fuPool.FUList2 system.cpu1.fuPool.FUList3 system.cpu1.fuPool.FUList4 system.cpu1.fuPool.FUList5 system.cpu1.fuPool.FUList6 system.cpu1.fuPool.FUList7 system.cpu1.fuPool.FUList8 +eventq_index=0 [system.cpu1.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu1.fuPool.FUList0.opList [system.cpu1.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -719,16 +795,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList1.opList0 system.cpu1.fuPool.FUList1.opList1 [system.cpu1.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu1.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -737,22 +816,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList2.opList0 system.cpu1.fuPool.FUList2.opList1 system.cpu1.fuPool.FUList2.opList2 [system.cpu1.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu1.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu1.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -761,22 +844,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu1.fuPool.FUList3.opList0 system.cpu1.fuPool.FUList3.opList1 system.cpu1.fuPool.FUList3.opList2 [system.cpu1.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu1.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu1.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -785,10 +872,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList4.opList [system.cpu1.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -797,124 +886,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList5.opList00 system.cpu1.fuPool.FUList5.opList01 system.cpu1.fuPool.FUList5.opList02 system.cpu1.fuPool.FUList5.opList03 system.cpu1.fuPool.FUList5.opList04 system.cpu1.fuPool.FUList5.opList05 system.cpu1.fuPool.FUList5.opList06 system.cpu1.fuPool.FUList5.opList07 system.cpu1.fuPool.FUList5.opList08 system.cpu1.fuPool.FUList5.opList09 system.cpu1.fuPool.FUList5.opList10 system.cpu1.fuPool.FUList5.opList11 system.cpu1.fuPool.FUList5.opList12 system.cpu1.fuPool.FUList5.opList13 system.cpu1.fuPool.FUList5.opList14 system.cpu1.fuPool.FUList5.opList15 system.cpu1.fuPool.FUList5.opList16 system.cpu1.fuPool.FUList5.opList17 system.cpu1.fuPool.FUList5.opList18 system.cpu1.fuPool.FUList5.opList19 [system.cpu1.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu1.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu1.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu1.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu1.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu1.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu1.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu1.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu1.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu1.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu1.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu1.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu1.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu1.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu1.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu1.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu1.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu1.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu1.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -923,10 +1033,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu1.fuPool.FUList6.opList [system.cpu1.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -935,16 +1047,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu1.fuPool.FUList7.opList0 system.cpu1.fuPool.FUList7.opList1 [system.cpu1.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu1.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -953,10 +1068,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu1.fuPool.FUList8.opList [system.cpu1.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -967,6 +1084,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -989,14 +1107,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu1.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -1015,31 +1136,37 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -1052,6 +1179,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -1074,6 +1202,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -1083,6 +1212,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -1105,6 +1235,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -1112,6 +1243,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1123,6 +1255,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -1149,6 +1282,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -1160,19 +1294,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -1182,6 +1320,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -1191,6 +1330,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -1219,6 +1359,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -1228,8 +1369,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -1241,6 +1414,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -1256,6 +1430,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -1270,6 +1446,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -1279,6 +1456,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -1300,8 +1478,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -1310,6 +1490,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -1320,6 +1501,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1330,6 +1512,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1340,6 +1523,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1354,6 +1538,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1367,6 +1552,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1384,6 +1570,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1396,6 +1583,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1407,6 +1595,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1417,6 +1606,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1429,6 +1619,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1442,6 +1633,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1452,6 +1644,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1462,6 +1655,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1472,6 +1666,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1484,6 +1679,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1498,6 +1694,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1510,6 +1707,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1524,6 +1722,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1534,6 +1733,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1544,6 +1744,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1554,6 +1755,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1562,6 +1764,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1570,6 +1773,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1579,11 +1783,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 22f0dd0ff..fbdae72ae 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,118 +1,118 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 1.104766 # Number of seconds simulated -sim_ticks 1104765949000 # Number of ticks simulated -final_tick 1104765949000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 1104766159000 # Number of ticks simulated +final_tick 1104766159000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 62642 # Simulator instruction rate (inst/s) -host_op_rate 80640 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1123477436 # Simulator tick rate (ticks/s) -host_mem_usage 430892 # Number of bytes of host memory used -host_seconds 983.35 # Real time elapsed on the host -sim_insts 61598253 # Number of instructions simulated -sim_ops 79296895 # Number of ops (including micro ops) simulated +host_inst_rate 49697 # Simulator instruction rate (inst/s) +host_op_rate 63978 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 891289209 # Simulator tick rate (ticks/s) +host_mem_usage 450492 # Number of bytes of host memory used +host_seconds 1239.51 # Real time elapsed on the host +sim_insts 61600257 # Number of instructions simulated +sim_ops 79301805 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 408192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4366132 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406848 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5251248 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 409280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory system.physmem.bytes_read::total 59192932 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 408192 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406848 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815040 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268480 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu0.inst 409280 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267520 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295824 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294864 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6378 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68293 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6357 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82077 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6395 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory system.physmem.num_reads::total 6257980 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66695 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 66680 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823531 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44134945 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823516 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44134936 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 369483 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3952088 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4753267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53579613 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 369483 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368266 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 737749 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3863696 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370468 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3952666 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367339 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4752513 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53579603 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370468 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367339 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 737807 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3862827 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 15388 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 2724870 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6603954 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3863696 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44134945 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 6603084 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3862827 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44134936 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 369483 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3967476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7478138 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60183567 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 370468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3968054 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 753 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7477383 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60182687 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 6257980 # Number of read requests accepted -system.physmem.writeReqs 823531 # Number of write requests accepted +system.physmem.writeReqs 823516 # Number of write requests accepted system.physmem.readBursts 6257980 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 823531 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 398200448 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 2310272 # Total number of bytes read from write queue -system.physmem.bytesWritten 7402624 # Total number of bytes written to DRAM +system.physmem.writeBursts 823516 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 398158784 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 2351936 # Total number of bytes read from write queue +system.physmem.bytesWritten 7399168 # Total number of bytes written to DRAM system.physmem.bytesReadSys 59192932 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 7295824 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 36098 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 707850 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 12605 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 391110 # Per bank write bursts -system.physmem.perBankRdBursts::1 390863 # Per bank write bursts -system.physmem.perBankRdBursts::2 386866 # Per bank write bursts -system.physmem.perBankRdBursts::3 386878 # Per bank write bursts -system.physmem.perBankRdBursts::4 391778 # Per bank write bursts -system.physmem.perBankRdBursts::5 391417 # Per bank write bursts -system.physmem.perBankRdBursts::6 386925 # Per bank write bursts -system.physmem.perBankRdBursts::7 386783 # Per bank write bursts -system.physmem.perBankRdBursts::8 391442 # Per bank write bursts -system.physmem.perBankRdBursts::9 391216 # Per bank write bursts -system.physmem.perBankRdBursts::10 386574 # Per bank write bursts -system.physmem.perBankRdBursts::11 385570 # Per bank write bursts -system.physmem.perBankRdBursts::12 390981 # Per bank write bursts -system.physmem.perBankRdBursts::13 390596 # Per bank write bursts -system.physmem.perBankRdBursts::14 386700 # Per bank write bursts -system.physmem.perBankRdBursts::15 386183 # Per bank write bursts -system.physmem.perBankWrBursts::0 7188 # Per bank write bursts -system.physmem.perBankWrBursts::1 7193 # Per bank write bursts -system.physmem.perBankWrBursts::2 7297 # Per bank write bursts -system.physmem.perBankWrBursts::3 7231 # Per bank write bursts -system.physmem.perBankWrBursts::4 7835 # Per bank write bursts -system.physmem.perBankWrBursts::5 7450 # Per bank write bursts -system.physmem.perBankWrBursts::6 7370 # Per bank write bursts -system.physmem.perBankWrBursts::7 7176 # Per bank write bursts -system.physmem.perBankWrBursts::8 7508 # Per bank write bursts -system.physmem.perBankWrBursts::9 7517 # Per bank write bursts -system.physmem.perBankWrBursts::10 6849 # Per bank write bursts -system.physmem.perBankWrBursts::11 6596 # Per bank write bursts -system.physmem.perBankWrBursts::12 7160 # Per bank write bursts -system.physmem.perBankWrBursts::13 6824 # Per bank write bursts -system.physmem.perBankWrBursts::14 7287 # Per bank write bursts -system.physmem.perBankWrBursts::15 7185 # Per bank write bursts +system.physmem.bytesWrittenSys 7294864 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 36749 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 707898 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 12570 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 391105 # Per bank write bursts +system.physmem.perBankRdBursts::1 391040 # Per bank write bursts +system.physmem.perBankRdBursts::2 387008 # Per bank write bursts +system.physmem.perBankRdBursts::3 386856 # Per bank write bursts +system.physmem.perBankRdBursts::4 391768 # Per bank write bursts +system.physmem.perBankRdBursts::5 391357 # Per bank write bursts +system.physmem.perBankRdBursts::6 387221 # Per bank write bursts +system.physmem.perBankRdBursts::7 386642 # Per bank write bursts +system.physmem.perBankRdBursts::8 391438 # Per bank write bursts +system.physmem.perBankRdBursts::9 391160 # Per bank write bursts +system.physmem.perBankRdBursts::10 385906 # Per bank write bursts +system.physmem.perBankRdBursts::11 385319 # Per bank write bursts +system.physmem.perBankRdBursts::12 390977 # Per bank write bursts +system.physmem.perBankRdBursts::13 390642 # Per bank write bursts +system.physmem.perBankRdBursts::14 386557 # Per bank write bursts +system.physmem.perBankRdBursts::15 386235 # Per bank write bursts +system.physmem.perBankWrBursts::0 7173 # Per bank write bursts +system.physmem.perBankWrBursts::1 7194 # Per bank write bursts +system.physmem.perBankWrBursts::2 7298 # Per bank write bursts +system.physmem.perBankWrBursts::3 7217 # Per bank write bursts +system.physmem.perBankWrBursts::4 7815 # Per bank write bursts +system.physmem.perBankWrBursts::5 7451 # Per bank write bursts +system.physmem.perBankWrBursts::6 7359 # Per bank write bursts +system.physmem.perBankWrBursts::7 7185 # Per bank write bursts +system.physmem.perBankWrBursts::8 7499 # Per bank write bursts +system.physmem.perBankWrBursts::9 7507 # Per bank write bursts +system.physmem.perBankWrBursts::10 6838 # Per bank write bursts +system.physmem.perBankWrBursts::11 6616 # Per bank write bursts +system.physmem.perBankWrBursts::12 7156 # Per bank write bursts +system.physmem.perBankWrBursts::13 6834 # Per bank write bursts +system.physmem.perBankWrBursts::14 7291 # Per bank write bursts +system.physmem.perBankWrBursts::15 7179 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 1104764856500 # Total gap between requests +system.physmem.totGap 1104765054500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 105 # Read request sizes (log2) @@ -126,29 +126,29 @@ system.physmem.writePktSize::2 756836 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 66695 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 548369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 494073 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 445478 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1468713 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1058783 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1047686 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1043195 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 25365 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 25416 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 9815 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 9549 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 9391 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9130 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8948 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 8825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 8725 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 275 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 14 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 14 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66680 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 551365 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 495534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 447275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1468617 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1056766 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1046048 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1041328 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24902 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24744 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 9802 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 9495 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 9368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 9115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 8928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 8808 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 8712 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 281 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 115 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 11 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see @@ -159,547 +159,563 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 5113 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 5240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5459 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5567 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 5221 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 5252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 5230 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 5182 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 5176 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 5159 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 5136 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 5142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 5135 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 5146 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 5137 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 5175 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 5192 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 5171 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5537 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 167 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 5114 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5795 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5243 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5570 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5230 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5229 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5171 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5180 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5142 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5141 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5145 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5146 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5183 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5206 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5519 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 159 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 16 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 71125 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 5702.673097 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 368.783347 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 12967.835637 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 25909 36.43% 36.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14850 20.88% 57.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 3162 4.45% 61.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2234 3.14% 64.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1545 2.17% 67.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1302 1.83% 68.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 996 1.40% 70.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1191 1.67% 71.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 629 0.88% 72.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 663 0.93% 73.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 567 0.80% 74.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 536 0.75% 75.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 288 0.40% 75.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 263 0.37% 76.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 175 0.25% 76.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 373 0.52% 76.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 125 0.18% 77.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 132 0.19% 77.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 91 0.13% 77.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 197 0.28% 77.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 57 0.08% 77.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 541 0.76% 78.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 41 0.06% 78.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 225 0.32% 78.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 27 0.04% 78.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 110 0.15% 79.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 22 0.03% 79.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 111 0.16% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 16 0.02% 79.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 61 0.09% 79.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 267 0.38% 79.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 16 0.02% 79.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 40 0.06% 79.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 17 0.02% 79.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 50 0.07% 79.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 11 0.02% 79.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 22 0.03% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 7 0.01% 79.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 43 0.06% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 4 0.01% 80.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 15 0.02% 80.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 8 0.01% 80.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 32 0.04% 80.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 7 0.01% 80.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 30 0.04% 80.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 5 0.01% 80.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 157 0.22% 80.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 6 0.01% 80.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 17 0.02% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 2 0.00% 80.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 36 0.05% 80.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 17 0.02% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 7 0.01% 80.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 88 0.12% 80.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 7 0.01% 80.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 8 0.01% 80.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 39 0.05% 80.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 6 0.01% 80.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 80.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 181 0.25% 81.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 9 0.01% 81.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 12 0.02% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 12 0.02% 81.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 102 0.14% 81.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 17 0.02% 81.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 25 0.04% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 81.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 11 0.02% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 5 0.01% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 3 0.00% 81.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 10 0.01% 81.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 19 0.03% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 2 0.00% 81.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 6 0.01% 81.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 5 0.01% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 161 0.23% 81.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 6 0.01% 81.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 13 0.02% 81.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 9 0.01% 81.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 14 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.00% 81.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 16 0.02% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 81.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 18 0.03% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 5 0.01% 81.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 8 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 5 0.01% 81.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 150 0.21% 81.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 81.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 12 0.02% 82.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 13 0.02% 82.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 95 0.13% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 7 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 23 0.03% 82.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 70891 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 5720.862056 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 370.371771 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 12983.455583 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 25780 36.37% 36.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 14831 20.92% 57.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 3170 4.47% 61.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 2175 3.07% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 1493 2.11% 66.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 1297 1.83% 68.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 1053 1.49% 70.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 1149 1.62% 71.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 657 0.93% 72.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 651 0.92% 73.71% # Bytes accessed per row activation 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3 0.00% 80.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 91 0.13% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 80.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 20 0.03% 80.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 6 0.01% 80.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 46 0.06% 80.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 11 0.02% 80.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 27 0.04% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 5 0.01% 80.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 37 0.05% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 12 0.02% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 18 0.03% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 12 0.02% 80.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 201 0.28% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 6 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 17 0.02% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 8 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 92 0.13% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 19 0.03% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 20 0.03% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 13 0.02% 81.23% # Bytes accessed per row activation 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15 0.02% 81.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 8 0.01% 81.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 84 0.12% 81.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 5 0.01% 81.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.01% 81.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 5 0.01% 81.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 19 0.03% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 2 0.00% 81.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 81.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 138 0.19% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 4 0.01% 81.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 11 0.02% 81.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 12 0.02% 81.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 85 0.12% 82.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 8 0.01% 82.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 6 0.01% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 5 0.01% 82.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 96 0.14% 82.21% # Bytes accessed per row activation system.physmem.bytesPerActivate::6464-6471 4 0.01% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 11 0.02% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 3 0.00% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 112 0.16% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 9 0.01% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 20 0.03% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 8 0.01% 82.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 28 0.04% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 4 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 2 0.00% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 94 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 6 0.01% 82.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 10 0.01% 82.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 92 0.13% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 3 0.00% 82.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 3 0.00% 82.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 20 0.03% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7751 2 0.00% 82.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7815 2 0.00% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7879 4 0.01% 82.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 30 0.04% 82.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8007 6 0.01% 82.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 8 0.01% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8135 1 0.00% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 249 0.35% 83.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8320-8327 1 0.00% 83.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 31 0.04% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8640-8647 1 0.00% 83.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 16 0.02% 83.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8832-8839 3 0.00% 83.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8896-8903 1 0.00% 83.33% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::10112-10119 3 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 94 0.13% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10375 1 0.00% 83.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 94 0.13% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 15 0.02% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10816-10823 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10880-10887 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 6 0.01% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11072-11079 2 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11136-11143 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 147 0.21% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11328-11335 3 0.00% 84.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 15 0.02% 84.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11584-11591 1 0.00% 84.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11840-11847 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11904-11911 1 0.00% 84.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 79 0.11% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12096-12103 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12224-12231 1 0.00% 84.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 162 0.23% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12416-12423 1 0.00% 84.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 20 0.03% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12672-12679 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12736-12743 1 0.00% 84.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 68 0.10% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12871 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12928-12935 1 0.00% 84.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 20 0.03% 84.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13184-13191 1 0.00% 84.81% # Bytes accessed per row activation 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-system.physmem.bytesPerActivate::17152-17159 13 0.02% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17280-17287 1 0.00% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17351 1 0.00% 86.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 156 0.22% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17472-17479 2 0.00% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17536-17543 1 0.00% 86.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 80 0.11% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17792-17799 1 0.00% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17856-17863 1 0.00% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 14 0.02% 86.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 31 0.04% 86.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 2 0.00% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 86.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 219 0.31% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18496-18503 1 0.00% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 6 0.01% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18752-18759 1 0.00% 87.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 15 0.02% 87.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 87.07% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::50944-50951 2 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51008-51015 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51328-51335 1 0.00% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51456-51463 4 0.01% 99.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51520-51527 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51584-51591 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51648-51655 1 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51712-51719 2 0.00% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51904-51911 2 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::51968-51975 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::52160-52167 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52352-52359 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52672-52679 1 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 71125 # Bytes accessed per row activation -system.physmem.totQLat 151840872500 # Total ticks spent queuing -system.physmem.totMemAccLat 191562815000 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 31109410000 # Total ticks spent in databus transfers -system.physmem.totBankLat 8612532500 # Total ticks spent accessing banks -system.physmem.avgQLat 24404.33 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1384.23 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::52416-52423 1 0.00% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 70891 # Bytes accessed per row activation +system.physmem.totQLat 151784626000 # Total ticks spent queuing +system.physmem.totMemAccLat 191524282250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 31106155000 # Total ticks spent in databus transfers +system.physmem.totBankLat 8633501250 # Total ticks spent accessing banks +system.physmem.avgQLat 24397.84 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1387.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30788.56 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 360.44 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30785.59 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 360.40 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 6.70 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 53.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 6.60 # Average system write bandwidth in MiByte/s @@ -708,14 +724,14 @@ system.physmem.busUtil 2.87 # Da system.physmem.busUtilRead 2.82 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.05 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 11.06 # Average write queue length when enqueuing -system.physmem.readRowHits 6168484 # Number of row buffer hits during reads -system.physmem.writeRowHits 97939 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.13 # Average write queue length when enqueuing +system.physmem.readRowHits 6167948 # Number of row buffer hits during reads +system.physmem.writeRowHits 98004 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.14 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 84.66 # Row buffer hit rate for writes -system.physmem.avgGap 156006.94 # Average gap between requests +system.physmem.writeRowHitRate 84.77 # Row buffer hit rate for writes +system.physmem.avgGap 156007.30 # Average gap between requests system.physmem.pageHitRate 98.88 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 3.92 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 3.90 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -734,286 +750,286 @@ system.realview.nvmem.bw_inst_read::total 406 # I system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 62369736 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306752 # Transaction distribution -system.membus.trans_dist::ReadResp 7306752 # Transaction distribution -system.membus.trans_dist::WriteReq 767894 # Transaction distribution -system.membus.trans_dist::WriteResp 767894 # Transaction distribution -system.membus.trans_dist::Writeback 66695 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33888 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17695 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12605 # Transaction distribution -system.membus.trans_dist::ReadExReq 138070 # Transaction distribution -system.membus.trans_dist::ReadExResp 137680 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382518 # Packet count per connected master and slave (bytes) +system.membus.throughput 62368825 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306736 # Transaction distribution +system.membus.trans_dist::ReadResp 7306736 # Transaction distribution +system.membus.trans_dist::WriteReq 767886 # Transaction distribution +system.membus.trans_dist::WriteResp 767886 # Transaction distribution +system.membus.trans_dist::Writeback 66680 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33856 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17703 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12570 # Transaction distribution +system.membus.trans_dist::ReadExReq 138080 # Transaction distribution +system.membus.trans_dist::ReadExResp 137692 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382504 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11632 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971209 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366229 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971133 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366129 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555925 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389781 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555825 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389767 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23264 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729972 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20145177 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729012 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20144183 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68903961 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68903961 # Total data (bytes) +system.membus.tot_pkt_size::total 68902967 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68902967 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1487006499 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486954500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 9880000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9891500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 749500 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 747500 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 8612723499 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8614133500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 4837509170 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4838543340 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13760375954 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13759512942 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) system.l2c.tags.replacements 72740 # number of replacements -system.l2c.tags.tagsinuse 53853.567584 # Cycle average of tags in use -system.l2c.tags.total_refs 1839137 # Total number of references to valid blocks. +system.l2c.tags.tagsinuse 53860.173191 # Cycle average of tags in use +system.l2c.tags.total_refs 1837966 # Total number of references to valid blocks. system.l2c.tags.sampled_refs 137924 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.334423 # Average number of references to valid blocks. +system.l2c.tags.avg_refs 13.325933 # Average number of references to valid blocks. system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39512.680536 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.162068 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257969 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4009.847433 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2829.767621 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 7.955070 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3709.355619 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3778.541270 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602916 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000079 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061185 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043179 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056600 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057656 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821740 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22065 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4358 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386342 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166614 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 30647 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5089 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590258 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198399 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403772 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581386 # number of Writeback hits -system.l2c.Writeback_hits::total 581386 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1334 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 750 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2084 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 191 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 137 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 328 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48317 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58643 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106960 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22065 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4358 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386342 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214931 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 30647 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5089 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590258 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 257042 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510732 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22065 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4358 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386342 # number of overall hits -system.l2c.overall_hits::cpu0.data 214931 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 30647 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5089 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590258 # number of overall hits -system.l2c.overall_hits::cpu1.data 257042 # number of overall hits -system.l2c.overall_hits::total 1510732 # number of overall hits +system.l2c.tags.occ_blocks::writebacks 39518.362493 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.391068 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.010261 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4016.186215 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2832.215798 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 8.504423 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3702.179063 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3777.323870 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.603002 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000082 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061282 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043216 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000130 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056491 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057637 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821841 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 22002 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4348 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 385872 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166544 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 31083 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5052 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 589425 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198327 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1402653 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581363 # number of Writeback hits +system.l2c.Writeback_hits::total 581363 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1344 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 738 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2082 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 204 # number of SCUpgradeReq hits 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hits +system.l2c.demand_hits::total 1509630 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 22002 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4348 # number of overall hits +system.l2c.overall_hits::cpu0.inst 385872 # number of overall hits +system.l2c.overall_hits::cpu0.data 214889 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 31083 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5052 # number of overall hits +system.l2c.overall_hits::cpu1.inst 589425 # number of overall hits +system.l2c.overall_hits::cpu1.data 256959 # number of overall hits +system.l2c.overall_hits::total 1509630 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6260 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6384 # number of ReadReq misses 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rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030489 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.017624 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.794706 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835201 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.811386 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769324 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750909 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.761974 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566974 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567689 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.567366 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.098705 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000688 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015937 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244601 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000359 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010589 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.244617 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.098705 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 63156.973522 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65507.251603 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62685.936512 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10025.485283 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10089.113917 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.462688 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10013.555730 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10063.934625 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10033.371429 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57735.641497 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 69024.341151 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63933.038618 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 65673.076923 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 146833.333333 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 59274.492568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 58229.813886 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 66250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62752.611999 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68760.708362 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63743.202567 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 171110152435 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 184524186173 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036720 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030405 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.017630 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.792848 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.836509 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.810762 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.756272 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.753758 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.566902 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567738 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567361 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098774 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000591 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000689 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015999 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244699 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000418 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010577 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244636 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.098774 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 62578.188661 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 65201.487138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62839.467228 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10021.691291 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10093.271186 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10051.992377 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10015.216430 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10048.609524 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10028.535613 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 57372.440322 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 68943.264778 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 63723.943645 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67788.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 65333.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60646.955690 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 57847.178613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 86173.076923 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 62894.699254 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 68663.625030 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63589.376948 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1204,61 +1220,61 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 136691596 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708551 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708550 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581386 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33382 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18023 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51405 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258959 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258959 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785985 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073715 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13547 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55934 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1193885 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4802054 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14684 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 71694 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8011498 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25134272 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847315 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17444 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88312 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38184256 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47797126 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20356 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 122632 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 146211713 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146211713 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4800508 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894625900 # Layer occupancy (ticks) +system.toL2Bus.throughput 136617428 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2707473 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2707472 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767886 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767886 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581363 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33341 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18047 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51388 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258982 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258982 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 785116 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073701 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13590 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55763 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1192186 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801848 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72416 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8009257 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25105344 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34847157 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 17404 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88060 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38129856 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47787842 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 20208 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 124384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146120255 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146120255 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4810056 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4893985918 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1771371395 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1769514129 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1514575770 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1514543493 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9208452 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9260456 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34011429 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33892454 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2689519761 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2685747678 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3237226447 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3237154790 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9617950 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9609448 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41300207 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41592193 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 46298101 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7950 # Transaction distribution -system.iobus.trans_dist::WriteResp 7950 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46298079 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278155 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278155 # Transaction distribution +system.iobus.trans_dist::WriteReq 7945 # Transaction distribution +system.iobus.trans_dist::WriteResp 7945 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30446 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) @@ -1281,11 +1297,11 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382518 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382504 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572214 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572200 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40164 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) @@ -1308,12 +1324,12 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389781 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389767 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148565 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148565 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148551 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148551 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21348000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 4017000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -1361,42 +1377,42 @@ system.iobus.reqLayer23.occupancy 8000 # La system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374568000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 2374559000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16664438046 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16664463058 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6002691 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4577903 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 294712 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3771820 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2913648 # Number of BTB hits +system.cpu0.branchPred.lookups 5998612 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575425 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295221 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3794321 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2910648 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.247801 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672509 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28479 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.710642 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 672923 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 29222 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8905508 # DTB read hits -system.cpu0.dtb.read_misses 28991 # DTB read misses -system.cpu0.dtb.write_hits 5140500 # DTB write hits -system.cpu0.dtb.write_misses 5723 # DTB write misses +system.cpu0.dtb.read_hits 8906772 # DTB read hits +system.cpu0.dtb.read_misses 28714 # DTB read misses +system.cpu0.dtb.write_hits 5141355 # DTB write hits +system.cpu0.dtb.write_misses 5491 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1824 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 969 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 309 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 924 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 556 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8934499 # DTB read accesses -system.cpu0.dtb.write_accesses 5146223 # DTB write accesses +system.cpu0.dtb.perms_faults 586 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8935486 # DTB read accesses +system.cpu0.dtb.write_accesses 5146846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14046008 # DTB hits -system.cpu0.dtb.misses 34714 # DTB misses -system.cpu0.dtb.accesses 14080722 # DTB accesses -system.cpu0.itb.inst_hits 4219281 # ITB inst hits -system.cpu0.itb.inst_misses 5089 # ITB inst misses +system.cpu0.dtb.hits 14048127 # DTB hits +system.cpu0.dtb.misses 34205 # DTB misses +system.cpu0.dtb.accesses 14082332 # DTB accesses +system.cpu0.itb.inst_hits 4217878 # ITB inst hits +system.cpu0.itb.inst_misses 5102 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1405,530 +1421,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1343 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1349 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1465 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1453 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4224370 # ITB inst accesses -system.cpu0.itb.hits 4219281 # DTB hits -system.cpu0.itb.misses 5089 # DTB misses -system.cpu0.itb.accesses 4224370 # DTB accesses -system.cpu0.numCycles 69432037 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4222980 # ITB inst accesses +system.cpu0.itb.hits 4217878 # DTB hits +system.cpu0.itb.misses 5102 # DTB misses +system.cpu0.itb.accesses 4222980 # DTB accesses +system.cpu0.numCycles 69399845 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11713503 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32019404 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6002691 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3586157 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7516730 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1449804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61386 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19631994 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4874 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 46872 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1335943 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 243 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4217707 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157539 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.000563 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.381156 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11707943 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32011744 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998612 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3583571 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7516048 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1450698 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 61322 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19616707 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4844 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 46699 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1334001 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 291 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4216315 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157019 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2077 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001115 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381687 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33842541 81.84% 81.84% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565579 1.37% 83.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 816874 1.98% 85.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676358 1.64% 86.82% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 772843 1.87% 88.69% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 558608 1.35% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 669211 1.62% 91.66% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 351371 0.85% 92.51% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098427 7.49% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33820062 81.83% 81.83% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 563590 1.36% 83.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 816833 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 678550 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 773451 1.87% 88.69% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 557877 1.35% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 667950 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351268 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3099000 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41351812 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086454 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.461162 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12216999 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20826551 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6820783 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 510850 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 976629 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935170 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64759 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40012064 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213022 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 976629 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12786291 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5985032 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12800887 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6711570 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2091403 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38907337 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 435425 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1163203 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39252215 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175728295 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 161804372 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 3955 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30935092 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8317122 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411284 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370379 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5367119 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7645996 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5688511 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1121166 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1220161 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36823164 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895382 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37236653 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80347 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6279547 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13158300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256522 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41351812 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.900484 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514831 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41328581 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086436 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.461265 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12211654 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20807916 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6822131 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 509652 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977228 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 934234 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64577 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40012411 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212282 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977228 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12781253 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5974864 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12788176 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6710782 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2096278 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38908722 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1870 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 435924 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1167673 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 74 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39248766 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175739111 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 161807828 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 3998 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938690 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8310075 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411292 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370393 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5377655 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7648768 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5690459 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1124911 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1238842 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36825251 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895403 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37248866 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80758 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6273186 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13119240 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256527 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41328581 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901286 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.515261 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26282952 63.56% 63.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5688374 13.76% 77.32% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3116432 7.54% 84.85% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2466494 5.96% 90.82% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2112034 5.11% 95.92% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 939185 2.27% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 506930 1.23% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 184996 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54415 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26256934 63.53% 63.53% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5686623 13.76% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3113893 7.53% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2469463 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128203 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 923425 2.23% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 509489 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185211 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55340 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41351812 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41328581 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27736 2.59% 2.59% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 453 0.04% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842113 78.49% 81.12% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 202594 18.88% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 26660 2.48% 2.48% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 451 0.04% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.52% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 843359 78.54% 81.06% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 203361 18.94% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22326150 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46947 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 4 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22336119 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46932 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9362954 25.14% 85.37% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447671 14.63% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9364529 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5448283 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37236653 # Type of FU issued -system.cpu0.iq.rate 0.536304 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1072896 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028813 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117004426 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44005967 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34332716 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8422 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4624 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3857 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38252914 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4421 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307648 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37248866 # Type of FU issued +system.cpu0.iq.rate 0.536728 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1073831 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028829 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117006401 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44001611 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34345325 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8483 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4644 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3871 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265951 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4467 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306869 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1368398 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2491 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13086 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537466 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1369766 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2413 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 12945 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 538318 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192854 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5939 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192768 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5933 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 976629 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4337522 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100010 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37836354 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83498 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7645996 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5688511 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571219 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39755 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 6621 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13086 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 149491 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 117486 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 266977 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36859042 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9220953 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 377611 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977228 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4326370 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 99368 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37837801 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83554 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7648768 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5690459 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571361 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39650 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 5884 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 12945 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150463 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117241 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267704 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36870822 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9222297 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 378044 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117808 # number of nop insts executed -system.cpu0.iew.exec_refs 14621413 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4853789 # Number of branches executed -system.cpu0.iew.exec_stores 5400460 # Number of stores executed -system.cpu0.iew.exec_rate 0.530865 # Inst execution rate -system.cpu0.iew.wb_sent 36664720 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34336573 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18306413 # num instructions producing a value -system.cpu0.iew.wb_consumers 35193198 # num instructions consuming a value +system.cpu0.iew.exec_nop 117147 # number of nop insts executed +system.cpu0.iew.exec_refs 14623543 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855012 # Number of branches executed +system.cpu0.iew.exec_stores 5401246 # Number of stores executed +system.cpu0.iew.exec_rate 0.531281 # Inst execution rate +system.cpu0.iew.wb_sent 36677243 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34349196 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18314277 # num instructions producing a value +system.cpu0.iew.wb_consumers 35200184 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.494535 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520169 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.494946 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520289 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6085996 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638860 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 231074 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40375183 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775004 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.739173 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6083137 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638876 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 231723 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40351353 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775579 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.741147 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28737053 71.18% 71.18% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5697190 14.11% 85.29% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1882101 4.66% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 980199 2.43% 92.37% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 786708 1.95% 94.32% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 526531 1.30% 95.63% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 398386 0.99% 96.61% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216969 0.54% 97.15% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1150046 2.85% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28712298 71.16% 71.16% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5699883 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1888088 4.68% 89.96% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 980743 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 789976 1.96% 94.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 505077 1.25% 95.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395357 0.98% 96.58% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219519 0.54% 97.12% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1160412 2.88% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40375183 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23683551 # Number of instructions committed -system.cpu0.commit.committedOps 31290943 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40351353 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23685352 # Number of instructions committed +system.cpu0.commit.committedOps 31295648 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11428643 # Number of memory references committed -system.cpu0.commit.loads 6277598 # Number of loads committed -system.cpu0.commit.membars 229694 # Number of memory barriers committed -system.cpu0.commit.branches 4245889 # Number of branches committed +system.cpu0.commit.refs 11431143 # Number of memory references committed +system.cpu0.commit.loads 6279002 # Number of loads committed +system.cpu0.commit.membars 229688 # Number of memory barriers committed +system.cpu0.commit.branches 4246153 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27646853 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489416 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1150046 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27651273 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489419 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1160412 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75750709 # The number of ROB reads -system.cpu0.rob.rob_writes 75732466 # The number of ROB writes -system.cpu0.timesIdled 364061 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 28080225 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2140058132 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23602809 # Number of Instructions Simulated -system.cpu0.committedOps 31210201 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23602809 # Number of Instructions Simulated -system.cpu0.cpi 2.941685 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.941685 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.339941 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.339941 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171807193 # number of integer regfile reads -system.cpu0.int_regfile_writes 34081987 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3237 # number of floating regfile reads -system.cpu0.fp_regfile_writes 886 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13003191 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451099 # number of misc regfile writes -system.cpu0.icache.tags.replacements 392605 # number of replacements -system.cpu0.icache.tags.tagsinuse 510.965142 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3793600 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393117 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.650053 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 7051834000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.965142 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.997979 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3793600 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3793600 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3793600 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3793600 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3793600 # number of overall hits -system.cpu0.icache.overall_hits::total 3793600 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423979 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423979 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423979 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423979 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423979 # number of overall misses -system.cpu0.icache.overall_misses::total 423979 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5892352014 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5892352014 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5892352014 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5892352014 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5892352014 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5892352014 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4217579 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4217579 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4217579 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4217579 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4217579 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100527 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100527 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100527 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100527 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100527 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13897.744969 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13897.744969 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13897.744969 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13897.744969 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3802 # number of cycles access was blocked +system.cpu0.rob.rob_reads 75718589 # The number of ROB reads +system.cpu0.rob.rob_writes 75736714 # The number of ROB writes +system.cpu0.timesIdled 363087 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 28071264 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2140090760 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23604610 # Number of Instructions Simulated +system.cpu0.committedOps 31214906 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23604610 # Number of Instructions Simulated +system.cpu0.cpi 2.940097 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.940097 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.340125 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.340125 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171854579 # number of integer regfile reads +system.cpu0.int_regfile_writes 34094081 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3288 # number of floating regfile reads +system.cpu0.fp_regfile_writes 904 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13012931 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451079 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392190 # number of replacements +system.cpu0.icache.tags.tagsinuse 510.931857 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3792228 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 392702 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.656758 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 7054061250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 510.931857 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.997914 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3792228 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3792228 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3792228 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3792228 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3792228 # number of overall hits +system.cpu0.icache.overall_hits::total 3792228 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423961 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423961 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423961 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423961 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423961 # number of overall misses +system.cpu0.icache.overall_misses::total 423961 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5895815248 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5895815248 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5895815248 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5895815248 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4216189 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4216189 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4216189 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4216189 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4216189 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100556 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100556 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100556 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100556 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100556 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13906.503777 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13906.503777 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13906.503777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13906.503777 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13906.503777 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3717 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 164 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 174 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 23.182927 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.362069 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30839 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30839 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30839 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30839 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30839 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30839 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393140 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393140 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393140 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393140 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393140 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4794002596 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4794002596 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4794002596 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093215 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093215 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093215 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093215 # mshr miss rate for overall accesses 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demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4798060362 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4798060362 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8923500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8923500 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093146 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093146 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093146 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12217.416250 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12217.416250 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12217.416250 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 276287 # number of replacements -system.cpu0.dcache.tags.tagsinuse 459.684046 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 9258198 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 276799 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 33.447368 # Average number of references to valid blocks. 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# number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3158747 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139141 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139141 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137092 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137092 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8937021 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8937021 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8937021 # number of overall hits -system.cpu0.dcache.overall_hits::total 8937021 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 392090 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 392090 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1584925 # number of WriteReq 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15.568144 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 78.442748 # average number of cycles each access was blocked +system.cpu0.dcache.tags.occ_blocks::cpu0.data 459.475838 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.897414 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781234 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781234 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3158881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3158881 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139214 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139214 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137082 # 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StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7466 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1977131 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1977131 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1977131 # number of overall misses +system.cpu0.dcache.overall_misses::total 1977131 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5519617945 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5519617945 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 79664471073 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 79664471073 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 90084987 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 90084987 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45897132 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45897132 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 85184089018 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 85184089018 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 85184089018 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 85184089018 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6172471 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6172471 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744775 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744775 # number of WriteReq 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accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334240 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334240 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.058863 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.058863 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051651 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051651 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181102 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181102 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181102 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181102 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14108.118468 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 50233.162540 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10346.271621 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6147.486204 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 43084.696471 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 43084.696471 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 10884 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 8688 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 601 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 128 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 18.109817 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 67.875000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256484 # number of writebacks -system.cpu0.dcache.writebacks::total 256484 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203289 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203289 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454440 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454440 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 445 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 445 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657729 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657729 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657729 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657729 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188801 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188801 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130485 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130485 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8285 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8285 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7449 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7449 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319286 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319286 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319286 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319286 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2419086873 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5310990170 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68672765 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30919365 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30919365 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7730077043 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7730077043 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7730077043 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7730077043 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504888791 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504888791 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131913883 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131913883 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636802674 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636802674 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030598 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030598 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.writebacks::writebacks 256502 # number of writebacks +system.cpu0.dcache.writebacks::total 256502 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202469 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202469 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1455378 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1455378 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 427 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657847 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657847 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657847 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657847 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188768 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188768 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130516 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130516 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8280 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7466 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7466 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319284 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319284 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319284 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2415025620 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2415025620 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5290299960 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5290299960 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 68915513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 68915513 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30963868 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30963868 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7705325580 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7705325580 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7705325580 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7705325580 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504357282 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504357282 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131166881 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131166881 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14635524163 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14635524163 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030582 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030582 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027507 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027507 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056029 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051535 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029255 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029255 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12812.892268 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40701.921064 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8288.806880 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4150.807491 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24210.510461 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24210.510461 # average overall mshr miss latency +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.055976 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051651 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029246 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029246 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12793.617668 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 40533.727359 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8323.129589 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4147.316903 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24133.140339 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24133.140339 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1936,38 +1952,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 8781819 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7169373 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406881 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 5765537 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 4953289 # Number of BTB hits +system.cpu1.branchPred.lookups 8777296 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7163659 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407085 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5785994 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4951432 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 85.912015 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772113 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42948 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.576169 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773226 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42749 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42694682 # DTB read hits -system.cpu1.dtb.read_misses 36199 # DTB read misses -system.cpu1.dtb.write_hits 6825983 # DTB write hits -system.cpu1.dtb.write_misses 10603 # DTB write misses +system.cpu1.dtb.read_hits 42697243 # DTB read hits +system.cpu1.dtb.read_misses 36228 # DTB read misses +system.cpu1.dtb.write_hits 6821056 # DTB write hits +system.cpu1.dtb.write_misses 10680 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2691 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 287 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2016 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2677 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 313 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 664 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42730881 # DTB read accesses -system.cpu1.dtb.write_accesses 6836586 # DTB write accesses +system.cpu1.dtb.perms_faults 642 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42733471 # DTB read accesses +system.cpu1.dtb.write_accesses 6831736 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49520665 # DTB hits -system.cpu1.dtb.misses 46802 # DTB misses -system.cpu1.dtb.accesses 49567467 # DTB accesses -system.cpu1.itb.inst_hits 7578103 # ITB inst hits -system.cpu1.itb.inst_misses 5415 # ITB inst misses +system.cpu1.dtb.hits 49518299 # DTB hits +system.cpu1.dtb.misses 46908 # DTB misses +system.cpu1.dtb.accesses 49565207 # DTB accesses +system.cpu1.itb.inst_hits 7578630 # ITB inst hits +system.cpu1.itb.inst_misses 5358 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1976,114 +1992,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1532 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1531 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1496 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1501 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7583518 # ITB inst accesses -system.cpu1.itb.hits 7578103 # DTB hits -system.cpu1.itb.misses 5415 # DTB misses -system.cpu1.itb.accesses 7583518 # DTB accesses -system.cpu1.numCycles 409882606 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583988 # ITB inst accesses +system.cpu1.itb.hits 7578630 # DTB hits +system.cpu1.itb.misses 5358 # DTB misses +system.cpu1.itb.accesses 7583988 # DTB accesses +system.cpu1.numCycles 409868912 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 18878139 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 60299044 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 8781819 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5725402 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13123323 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3309042 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 63154 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78443797 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5020 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42366 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1440662 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 193 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7576329 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 547353 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2737 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.645293 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.969526 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18867977 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60276924 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8777296 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5724658 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13120224 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3305222 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63128 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78446194 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5050 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 41923 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1438516 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 233 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7576833 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 547191 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2712 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.645142 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.969298 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101145087 88.52% 88.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796077 0.70% 89.22% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 936773 0.82% 90.04% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1687391 1.48% 91.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1395150 1.22% 92.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 571856 0.50% 93.24% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1930284 1.69% 94.93% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 409373 0.36% 95.28% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5389117 4.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 101131185 88.52% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796172 0.70% 89.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 937688 0.82% 90.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1689020 1.48% 91.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1395475 1.22% 92.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 568258 0.50% 93.24% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1928403 1.69% 94.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410429 0.36% 95.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5387292 4.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114261108 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.021425 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.147113 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20196476 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 79405562 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 11967958 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 523276 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2167836 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1103528 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98181 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 69822224 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326370 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2167836 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 21386304 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 34427825 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40782107 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11206546 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4290490 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 65904089 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18821 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 671145 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3046869 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 355 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 69217965 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 302501585 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 280690851 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 6493 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49057579 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20160386 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444741 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387793 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7877859 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12590402 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 7938263 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1041211 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1447247 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 60694774 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157845 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 87723814 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 94478 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13427979 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 35976172 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277080 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114261108 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.767749 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513486 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114243922 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021415 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147064 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20194584 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 79395702 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11966487 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 522966 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2164183 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104463 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98170 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69803405 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 327162 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2164183 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21384110 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 34428627 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40773355 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11205851 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4287796 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65891244 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18827 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 669159 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3045569 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1057 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69207054 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302452168 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 280640301 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 6501 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49057788 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20149266 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444930 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388060 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7871220 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12589854 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7931577 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1030582 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1486229 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60667262 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1158299 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712047 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93594 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13406861 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35899906 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277508 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114243922 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.767761 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.513174 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84436887 73.90% 73.90% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8271726 7.24% 81.14% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4125209 3.61% 84.75% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3692140 3.23% 87.98% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10373138 9.08% 97.06% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1967895 1.72% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1041724 0.91% 99.69% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 276233 0.24% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 76156 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 84413448 73.89% 73.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8278708 7.25% 81.14% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4125885 3.61% 84.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3695285 3.23% 87.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10373691 9.08% 97.06% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1966586 1.72% 98.78% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039954 0.91% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 274624 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75741 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114261108 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114243922 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32226 0.41% 0.41% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.42% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32139 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 997 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.42% # attempts to use FU when none available @@ -2111,13 +2127,13 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7551636 95.89% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290793 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551678 95.88% 96.30% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 291209 3.70% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 36606472 41.73% 42.09% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59249 0.07% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36599204 41.73% 42.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59264 0.07% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.15% # Type of FU issued @@ -2130,376 +2146,376 @@ system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.15% # Ty system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.15% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.15% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43568189 49.67% 91.82% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7174305 8.18% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.15% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43568617 49.67% 91.83% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7169368 8.17% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 87723814 # Type of FU issued -system.cpu1.iq.rate 0.214022 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7875649 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.089778 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 297709996 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 75289267 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53144243 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15477 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8000 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 95277128 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8273 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 341654 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712047 # Type of FU issued +system.cpu1.iq.rate 0.214000 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7876023 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089794 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 297668917 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75240910 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53134013 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15426 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 7990 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6798 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265766 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8242 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342419 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2834942 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3919 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17226 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1098203 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2834348 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3679 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17028 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1091492 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31919752 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 674526 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31919677 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 675013 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2167836 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 26657812 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361941 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 61957280 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112544 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12590402 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 7938263 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869014 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64925 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 4205 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17226 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200285 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154811 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355096 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 85998990 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43064757 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1724824 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2164183 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 26656099 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 359793 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61930029 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112185 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12589854 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7931577 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869499 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 63855 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3879 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17028 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201052 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154389 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 355441 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989380 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43067298 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1722667 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104661 # number of nop insts executed -system.cpu1.iew.exec_refs 50176981 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6911907 # Number of branches executed -system.cpu1.iew.exec_stores 7112224 # Number of stores executed -system.cpu1.iew.exec_rate 0.209814 # Inst execution rate -system.cpu1.iew.wb_sent 85240093 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53151046 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29713379 # num instructions producing a value -system.cpu1.iew.wb_consumers 52980753 # num instructions consuming a value +system.cpu1.iew.exec_nop 104468 # number of nop insts executed +system.cpu1.iew.exec_refs 50174734 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912361 # Number of branches executed +system.cpu1.iew.exec_stores 7107436 # Number of stores executed +system.cpu1.iew.exec_rate 0.209797 # Inst execution rate +system.cpu1.iew.wb_sent 85230326 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53140811 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29705560 # num instructions producing a value +system.cpu1.iew.wb_consumers 52974804 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.129674 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560833 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.129653 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560749 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13311701 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880765 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310263 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112093272 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.429609 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.397405 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13285222 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880791 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 310591 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 112079739 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.429663 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.397726 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95372912 85.08% 85.08% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8221460 7.33% 92.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2092695 1.87% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1254196 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1248841 1.11% 96.52% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 572620 0.51% 97.03% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 992421 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 531111 0.47% 98.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1807016 1.61% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 95362610 85.08% 85.08% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8223786 7.34% 92.42% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2087568 1.86% 94.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1250330 1.12% 95.40% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1251085 1.12% 96.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 572828 0.51% 97.03% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991388 0.88% 97.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 531334 0.47% 98.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1808810 1.61% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112093272 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38065083 # Number of instructions committed -system.cpu1.commit.committedOps 48156333 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 112079739 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38065286 # Number of instructions committed +system.cpu1.commit.committedOps 48156538 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16595520 # Number of memory references committed -system.cpu1.commit.loads 9755460 # Number of loads committed +system.cpu1.commit.refs 16595591 # Number of memory references committed +system.cpu1.commit.loads 9755506 # Number of loads committed system.cpu1.commit.membars 190120 # Number of memory barriers committed -system.cpu1.commit.branches 5967695 # Number of branches committed +system.cpu1.commit.branches 5967745 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42691207 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534629 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1807016 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42691339 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534627 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1808810 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 170710273 # The number of ROB reads -system.cpu1.rob.rob_writes 125186848 # The number of ROB writes -system.cpu1.timesIdled 1415125 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295621498 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1799013115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37995444 # Number of Instructions Simulated -system.cpu1.committedOps 48086694 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37995444 # Number of Instructions Simulated -system.cpu1.cpi 10.787678 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.787678 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092698 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092698 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 384930549 # number of integer regfile reads -system.cpu1.int_regfile_writes 55277579 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5074 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2336 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18448778 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405411 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596659 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.521199 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 6934084 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 597171 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 11.611555 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74930526000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.521199 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.938518 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 6934084 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 6934084 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 6934084 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 6934084 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 6934084 # number of overall hits -system.cpu1.icache.overall_hits::total 6934084 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 642197 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 642197 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 642197 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 642197 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 642197 # number of overall misses -system.cpu1.icache.overall_misses::total 642197 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8716898620 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8716898620 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8716898620 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8716898620 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7576281 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7576281 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7576281 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7576281 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7576281 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084764 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084764 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084764 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084764 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084764 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13573.558612 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13573.558612 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13573.558612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.558612 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13573.558612 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3156 # number of cycles access was blocked +system.cpu1.rob.rob_reads 170668638 # The number of ROB reads +system.cpu1.rob.rob_writes 125130415 # The number of ROB writes +system.cpu1.timesIdled 1414400 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295624990 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1799026779 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995647 # Number of Instructions Simulated +system.cpu1.committedOps 48086899 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995647 # Number of Instructions Simulated +system.cpu1.cpi 10.787260 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.787260 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092702 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092702 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384897666 # number of integer regfile reads +system.cpu1.int_regfile_writes 55271640 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5031 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2324 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18454230 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405462 # number of misc regfile writes +system.cpu1.icache.tags.replacements 595825 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.685801 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6935518 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 596337 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.630199 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74918873000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.685801 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938839 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6935518 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6935518 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6935518 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6935518 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6935518 # number of overall hits +system.cpu1.icache.overall_hits::total 6935518 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 641267 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 641267 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 641267 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 641267 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 641267 # number of overall misses +system.cpu1.icache.overall_misses::total 641267 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8704460293 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8704460293 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8704460293 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8704460293 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8704460293 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8704460293 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7576785 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7576785 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7576785 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7576785 # number of demand (read+write) accesses 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overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13573.847232 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13573.847232 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2595 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 190 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 176 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.610526 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.744318 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44987 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 44987 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 44987 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 44987 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 44987 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 597210 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 597210 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 597210 # number of demand (read+write) MSHR misses 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0.125382 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100347 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100347 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15198.034566 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15198.034566 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 51471.767133 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 51471.767133 # average WriteReq miss latency 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blocked +system.cpu1.dcache.blocked::no_mshrs 3289 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.877166 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 115.630952 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324902 # number of writebacks -system.cpu1.dcache.writebacks::total 324902 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170345 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170345 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396167 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1396167 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1435 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1435 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1566512 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1566512 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1566512 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1566512 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228371 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 228371 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161692 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161692 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12502 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12502 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10574 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10574 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 390063 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 390063 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 390063 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 390063 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2847018297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2847018297 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7247965426 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7247965426 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 87929505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 87929505 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31688093 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31688093 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10094983723 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 10094983723 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10094983723 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 10094983723 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925175261 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925175261 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25838951416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25838951416 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194764126677 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194764126677 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026235 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028384 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112335 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100256 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027085 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027085 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027085 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12466.636731 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12466.636731 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44825.751589 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44825.751589 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7033.235082 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7033.235082 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 2996.793361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 2996.793361 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25880.392970 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25880.392970 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324862 # number of writebacks +system.cpu1.dcache.writebacks::total 324862 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168849 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168849 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395866 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395866 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1456 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1564715 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1564715 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1564715 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1564715 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228362 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228362 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161625 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161625 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12531 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12531 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10581 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10581 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389987 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389987 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389987 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389987 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2843265804 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2843265804 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 7240277216 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88160756 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31863585 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 10083543020 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 10083543020 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168925167755 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25834747063 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194759914818 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026228 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028372 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112330 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100319 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027076 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027076 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12450.695843 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 44796.765451 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7035.412657 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3011.396371 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 25856.100383 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 25856.100383 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2521,18 +2537,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 612781961046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612781961046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 612781961046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 612762276058 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 612762276058 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 612762276058 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41730 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41714 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48851 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48863 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |