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author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
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committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
commit | 9954eb74df98c4749651eb78098595f78d642105 (patch) | |
tree | 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
parent | 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff) | |
download | gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz |
stats: update stale config.ini files, eio and few other stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
4 files changed, 18 insertions, 16 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 9332ae5c7..06829ebfc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -210,7 +210,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -551,7 +551,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -661,7 +661,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -844,7 +844,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=2 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=6 prefetch_on_access=false @@ -1185,7 +1185,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=1 -is_top_level=true +is_read_only=true max_miss_count=0 mshrs=2 prefetch_on_access=false @@ -1295,7 +1295,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=12 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=16 prefetch_on_access=true @@ -1408,7 +1408,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=false hit_latency=50 -is_top_level=true +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false @@ -1443,7 +1443,7 @@ demand_mshr_reserve=1 eventq_index=0 forward_snoops=true hit_latency=20 -is_top_level=false +is_read_only=false max_miss_count=0 mshrs=20 prefetch_on_access=false diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index d6745503c..b6712dc14 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -23,6 +23,7 @@ warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist +warn: CP14 unimplemented crn[4], opc1[4], crm[0], opc2[0] warn: Not doing anything for miscreg ACTLR warn: Not doing anything for write of miscreg ACTLR warn: instruction 'mcr bpiall' unimplemented @@ -31,6 +32,7 @@ warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] +warn: allocating bonus target for snoop warn: Returning zero for read from miscreg pmcr warn: Ignoring write to miscreg pmcntenclr warn: Ignoring write to miscreg pmintenclr diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index cd7aeb29d..3ad068601 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2625378187500 because m5_exit instruction encountered +Exiting @ tick 2625394935000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 51ea3fd8c..82662bafe 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.625395 # Nu sim_ticks 2625394935000 # Number of ticks simulated final_tick 2625394935000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 95356 # Simulator instruction rate (inst/s) -host_op_rate 115687 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2080724894 # Simulator tick rate (ticks/s) -host_mem_usage 655064 # Number of bytes of host memory used -host_seconds 1261.77 # Real time elapsed on the host +host_inst_rate 71798 # Simulator instruction rate (inst/s) +host_op_rate 87106 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1566670818 # Simulator tick rate (ticks/s) +host_mem_usage 647044 # Number of bytes of host memory used +host_seconds 1675.78 # Real time elapsed on the host sim_insts 120317196 # Number of instructions simulated sim_ops 145970023 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -774,9 +774,9 @@ system.cpu0.iew.iewDispNonSpecInsts 851631 # Nu system.cpu0.iew.iewIQFullEvents 24928 # Number of times the IQ has become full, causing a stall system.cpu0.iew.iewLSQFullEvents 129599 # Number of times the LSQ has become full, causing a stall system.cpu0.iew.memOrderViolationEvents 18950 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 275041 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedTakenIncorrect 275039 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 375413 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 650454 # Number of branch mispredicts detected at execute +system.cpu0.iew.branchMispredicts 650452 # Number of branch mispredicts detected at execute system.cpu0.iew.iewExecutedInsts 126634007 # Number of executed instructions system.cpu0.iew.iewExecLoadInsts 22982824 # Number of load instructions executed system.cpu0.iew.iewExecSquashedInsts 968597 # Number of squashed instructions skipped in execute |