regressions: update stats due to branch predictor changes

The actual statistical values are being updated for only two tests belonging
to sparc architecture and inorder cpu: 00.hello and 02.insttest. For others
the patch updates config.ini and name changes to statistical variables.

3 files changed, 74 insertions, 60 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 691cf1068..86e60df6e 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000
 type=LinuxArmSystem
 children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
 atags_addr=256
-boot_loader=/gem5/dist/binaries/boot.arm
+boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
 clock=1000
 dtb_filename=
@@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 multi_proc=true
 num_work_ids=16
 readfile=tests/halt.sh
@@ -65,27 +65,23 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/gem5/dist/disks/linux-arm-ael.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
 read_only=true
 
 [system.cpu0]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
 LSQDepCheckShift=4
-RASSize=16
 SQEntries=32
 SSITSize=1024
 activity=0
 backComSize=5
+branchPred=system.cpu0.branchPred
 cachePorts=200
 checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
 clock=500
 commitToDecodeDelay=1
 commitToFetchDelay=1
@@ -108,23 +104,15 @@ forwardComSize=5
 fuPool=system.cpu0.fuPool
 function_trace=false
 function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
 iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-instShiftAmt=2
 interrupts=system.cpu0.interrupts
 isa=system.cpu0.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu0.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -136,7 +124,6 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
-predType=tournament
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -165,6 +152,24 @@ workload=
 dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
+[system.cpu0.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
 [system.cpu0.dcache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
@@ -523,22 +528,18 @@ type=ExeTracer
 
 [system.cpu1]
 type=DerivO3CPU
-children=dcache dtb fuPool icache interrupts isa itb tracer
-BTBEntries=4096
-BTBTagSize=16
+children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
 LSQDepCheckShift=4
-RASSize=16
 SQEntries=32
 SSITSize=1024
 activity=0
 backComSize=5
+branchPred=system.cpu1.branchPred
 cachePorts=200
 checker=Null
-choiceCtrBits=2
-choicePredictorSize=8192
 clock=500
 commitToDecodeDelay=1
 commitToFetchDelay=1
@@ -561,23 +562,15 @@ forwardComSize=5
 fuPool=system.cpu1.fuPool
 function_trace=false
 function_trace_start=0
-globalCtrBits=2
-globalHistoryBits=13
-globalPredictorSize=8192
 iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-instShiftAmt=2
 interrupts=system.cpu1.interrupts
 isa=system.cpu1.isa
 issueToExecuteDelay=1
 issueWidth=8
 itb=system.cpu1.itb
-localCtrBits=2
-localHistoryBits=11
-localHistoryTableSize=2048
-localPredictorSize=2048
 max_insts_all_threads=0
 max_insts_any_thread=0
 max_loads_all_threads=0
@@ -589,7 +582,6 @@ numPhysIntRegs=256
 numROBEntries=192
 numRobs=1
 numThreads=1
-predType=tournament
 profile=0
 progress_interval=0
 renameToDecodeDelay=1
@@ -618,6 +610,24 @@ workload=
 dcache_port=system.cpu1.dcache.cpu_side
 icache_port=system.cpu1.icache.cpu_side
 
+[system.cpu1.branchPred]
+type=BranchPredictor
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+choiceCtrBits=2
+choicePredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+instShiftAmt=2
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+numThreads=1
+predType=tournament
+
 [system.cpu1.dcache]
 type=BaseCache
 addr_ranges=0:18446744073709551615
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index 7a0146bc3..a480bab99 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -1,12 +1,14 @@
+Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout
+Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan  4 2013 21:17:24
-gem5 started Jan  5 2013 02:00:26
-gem5 executing on u200540
+gem5 compiled Jan 23 2013 19:43:25
+gem5 started Jan 23 2013 22:02:35
+gem5 executing on ribera.cs.wisc.edu
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2603185215000 because m5_exit instruction encountered
+Exiting @ tick 1092968826500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 69e508f78..572fe69c1 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.092969                       # Nu
 sim_ticks                                1092968826500                       # Number of ticks simulated
 final_tick                               1092968826500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  64747                       # Simulator instruction rate (inst/s)
-host_op_rate                                    83356                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1148881552                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 415112                       # Number of bytes of host memory used
-host_seconds                                   951.33                       # Real time elapsed on the host
+host_inst_rate                                  49884                       # Simulator instruction rate (inst/s)
+host_op_rate                                    64220                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              885142778                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 458008                       # Number of bytes of host memory used
+host_seconds                                  1234.79                       # Real time elapsed on the host
 sim_insts                                    61595972                       # Number of instructions simulated
 sim_ops                                      79298956                       # Number of ops (including micro ops) simulated
 system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
@@ -663,6 +663,15 @@ system.cf0.dma_read_txs                             0                       # Nu
 system.cf0.dma_write_full_pages                     0                       # Number of full page size DMA writes.
 system.cf0.dma_write_bytes                          0                       # Number of bytes transfered via DMA writes.
 system.cf0.dma_write_txs                            0                       # Number of DMA write transactions.
+system.cpu0.branchPred.lookups                6012491                       # Number of BP lookups
+system.cpu0.branchPred.condPredicted          4585363                       # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect           296577                       # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups             3765620                       # Number of BTB lookups
+system.cpu0.branchPred.BTBHits                2919015                       # Number of BTB hits
+system.cpu0.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu0.branchPred.BTBHitPct            77.517514                       # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS                 674578                       # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect             28863                       # Number of incorrect RAS predictions.
 system.cpu0.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu0.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu0.dtb.read_hits                     8918270                       # DTB read hits
@@ -708,14 +717,6 @@ system.cpu0.itb.accesses                      4231537                       # DT
 system.cpu0.numCycles                        67785734                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.BPredUnit.lookups                 6012491                       # Number of BP lookups
-system.cpu0.BPredUnit.condPredicted           4585363                       # Number of conditional branches predicted
-system.cpu0.BPredUnit.condIncorrect            296577                       # Number of conditional branches incorrect
-system.cpu0.BPredUnit.BTBLookups              3765620                       # Number of BTB lookups
-system.cpu0.BPredUnit.BTBHits                 2919015                       # Number of BTB hits
-system.cpu0.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.BPredUnit.usedRAS                  674578                       # Number of times the RAS was used to get a target.
-system.cpu0.BPredUnit.RASInCorrect              28863                       # Number of incorrect RAS predictions.
 system.cpu0.fetch.icacheStallCycles          11763968                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu0.fetch.Insts                      32049970                       # Number of instructions fetch has processed
 system.cpu0.fetch.Branches                    6012491                       # Number of branches that fetch encountered
@@ -1233,6 +1234,15 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total          inf
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total          inf                       # average overall mshr uncacheable latency
 system.cpu0.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu1.branchPred.lookups                8781590                       # Number of BP lookups
+system.cpu1.branchPred.condPredicted          7165099                       # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect           410272                       # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups             5784510                       # Number of BTB lookups
+system.cpu1.branchPred.BTBHits                4949628                       # Number of BTB hits
+system.cpu1.branchPred.BTBCorrect                   0                       # Number of correct BTB predictions (this stat may not work properly.
+system.cpu1.branchPred.BTBHitPct            85.566937                       # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS                 773605                       # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect             42847                       # Number of incorrect RAS predictions.
 system.cpu1.dtb.inst_hits                           0                       # ITB inst hits
 system.cpu1.dtb.inst_misses                         0                       # ITB inst misses
 system.cpu1.dtb.read_hits                    42721233                       # DTB read hits
@@ -1278,14 +1288,6 @@ system.cpu1.itb.accesses                      7589581                       # DT
 system.cpu1.numCycles                       406854445                       # number of cpu cycles simulated
 system.cpu1.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu1.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu1.BPredUnit.lookups                 8781590                       # Number of BP lookups
-system.cpu1.BPredUnit.condPredicted           7165099                       # Number of conditional branches predicted
-system.cpu1.BPredUnit.condIncorrect            410272                       # Number of conditional branches incorrect
-system.cpu1.BPredUnit.BTBLookups              5784510                       # Number of BTB lookups
-system.cpu1.BPredUnit.BTBHits                 4949628                       # Number of BTB hits
-system.cpu1.BPredUnit.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.BPredUnit.usedRAS                  773605                       # Number of times the RAS was used to get a target.
-system.cpu1.BPredUnit.RASInCorrect              42847                       # Number of incorrect RAS predictions.
 system.cpu1.fetch.icacheStallCycles          18987687                       # Number of cycles fetch is stalled on an Icache miss
 system.cpu1.fetch.Insts                      60514486                       # Number of instructions fetch has processed
 system.cpu1.fetch.Branches                    8781590                       # Number of branches that fetch encountered