diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-01-07 13:05:54 -0500 |
| commit | 9f15510c2c0c346faf107a47486cc06d4921e7c9 (patch) | |
| tree | fab449df2fd9f1a698ce68437efec47e2d45d5f7 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 009970f59b86eac6c9a35eeb175dd9e3a3079d13 (diff) | |
| download | gem5-9f15510c2c0c346faf107a47486cc06d4921e7c9.tar.xz | |
stats: update stats for previous changes.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
4 files changed, 1601 insertions, 1622 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index f6cdc434a..691cf1068 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing +mem_ranges=0:134217727 memories=system.physmem system.realview.nvmem -midr_regval=890224640 multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,12 +65,12 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -96,7 +96,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -118,6 +117,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -155,6 +155,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu0.tracer trapLatency=13 @@ -171,21 +172,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -474,21 +470,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -497,6 +488,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -515,7 +523,7 @@ type=ExeTracer [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -541,7 +549,6 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -563,6 +570,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -600,6 +608,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu1.tracer trapLatency=13 @@ -616,21 +625,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -919,21 +923,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -942,6 +941,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -974,30 +990,25 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 clock=1000 forward_snoops=false -hash_delay=1 hit_latency=50 is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache @@ -1006,25 +1017,20 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.membus] type=CoherentBus @@ -1036,7 +1042,7 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake @@ -1166,11 +1172,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr index 523f8a126..e8e271d58 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simerr @@ -12,8 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index ac731cab9..7a0146bc3 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 21:14:52 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 5 2013 02:00:26 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2593146078000 because m5_exit instruction encountered +Exiting @ tick 2603185215000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 3f5cdc3ab..de425fd79 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,135 +1,131 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.593146 # Number of seconds simulated -sim_ticks 2593146078000 # Number of ticks simulated -final_tick 2593146078000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603185 # Number of seconds simulated +sim_ticks 2603185215000 # Number of ticks simulated +final_tick 2603185215000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 77303 # Simulator instruction rate (inst/s) -host_op_rate 99505 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 3178225665 # Simulator tick rate (ticks/s) -host_mem_usage 449664 # Number of bytes of host memory used -host_seconds 815.91 # Real time elapsed on the host -sim_insts 63072130 # Number of instructions simulated -sim_ops 81187111 # Number of ops (including micro ops) simulated +host_inst_rate 24146 # Simulator instruction rate (inst/s) +host_op_rate 31077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 996702828 # Simulator tick rate (ticks/s) +host_mem_usage 410224 # Number of bytes of host memory used +host_seconds 2611.80 # Real time elapsed on the host +sim_insts 63063952 # Number of instructions simulated +sim_ops 81166306 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395328 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4376500 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 426752 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5261232 # Number of bytes read from this memory -system.physmem.bytes_read::total 131572388 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395328 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 426752 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822080 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4282048 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 396288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4383412 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1088 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 425536 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5252400 # Number of bytes read from this memory +system.physmem.bytes_read::total 131570212 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 396288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 425536 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 821824 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4280832 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7311184 # Number of bytes written to this memory +system.physmem.bytes_written::total 7309968 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6177 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68455 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 15 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6668 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82233 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15302381 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66907 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6192 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 17 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6649 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82095 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15302347 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66888 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 824191 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46704090 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 152451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1687718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.itb.walker 25 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 164569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2028899 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50738518 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 152451 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 164569 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317020 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1651295 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6556 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1161576 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2819426 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1651295 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46704090 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 152451 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1694274 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 370 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.itb.walker 25 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 164569 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3190475 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53557944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15302381 # Total number of read requests seen -system.physmem.writeReqs 824191 # Total number of write requests seen -system.physmem.cpureqs 284713 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 979352384 # Total number of bytes read from memory -system.physmem.bytesWritten 52748224 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131572388 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7311184 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 335 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 14131 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956528 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 956655 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 956404 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956499 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956473 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 956086 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955879 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956080 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 957009 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 956354 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 956393 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 956606 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956350 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 956542 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 956247 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955941 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50875 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51001 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50801 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50933 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51869 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51569 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51383 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51546 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 52151 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51788 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51664 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51769 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51735 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51864 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51697 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51546 # Track writes on a per bank basis +system.physmem.num_writes::total 824172 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 46523977 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 74 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 152232 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1683865 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 418 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 163467 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 2017682 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50542010 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 152232 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 163467 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315699 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1644459 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 6530 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 1157096 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2808086 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1644459 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 46523977 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 295 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 152232 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1690395 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 418 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 163467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 3174778 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53350096 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15302347 # Total number of read requests seen +system.physmem.writeReqs 824172 # Total number of write requests seen +system.physmem.cpureqs 284728 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 979350208 # Total number of bytes read from memory +system.physmem.bytesWritten 52747008 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131570212 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7309968 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 346 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 14078 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956479 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 956691 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 956370 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956557 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956475 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 956110 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955970 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956102 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956952 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 956364 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 956322 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 956651 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 956317 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 956502 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 956203 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955936 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50835 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51032 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50766 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50996 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51864 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 51588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51454 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51566 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 52101 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51588 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51821 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51736 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51833 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51672 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51523 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1150487 # Number of times wr buffer was full causing retry -system.physmem.totGap 2593144762500 # Total gap between requests +system.physmem.numWrRetry 1182222 # Number of times wr buffer was full causing retry +system.physmem.totGap 2603183939000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163460 # Categorize read packet sizes +system.physmem.readPktSize::6 163426 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1907771 # categorize write packet sizes +system.physmem.writePktSize::2 1939506 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66907 # categorize write packet sizes +system.physmem.writePktSize::6 66888 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -138,29 +134,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 14131 # categorize neither packet sizes +system.physmem.neitherpktsize::6 14078 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15151641 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 94331 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 8809 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3486 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2848 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2557 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2313 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 1993 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 1407 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 1368 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 1369 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 6472 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 9621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 13063 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 592 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 97 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1062295 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 996413 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 951405 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 986255 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2765519 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2772335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5446641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 44668 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 31245 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30881 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30868 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 58473 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 38578 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 65793 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17450 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3001 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 33 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -174,60 +170,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 3183 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3385 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3534 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4027 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4248 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4407 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 3151 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3476 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3611 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3812 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4018 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4199 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4366 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 35834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 35834 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35834 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32652 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32450 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32301 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32002 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31587 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31428 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31249 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35833 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32564 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32454 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32358 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32022 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31816 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31468 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 47868619345 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 322210199345 # Sum of mem lat for all requests -system.physmem.totBusLat 61208184000 # Total cycles spent in databus access -system.physmem.totBankLat 213133396000 # Total cycles spent in bank access -system.physmem.avgQLat 3128.25 # Average queueing delay per request -system.physmem.avgBankLat 13928.42 # Average bank access latency per request +system.physmem.totQLat 332610890470 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 410507230470 # Sum of mem lat for all requests +system.physmem.totBusLat 61208004000 # Total cycles spent in databus access +system.physmem.totBankLat 16688336000 # Total cycles spent in bank access +system.physmem.avgQLat 21736.43 # Average queueing delay per request +system.physmem.avgBankLat 1090.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 21056.67 # Average memory access latency -system.physmem.avgRdBW 377.67 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 20.34 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 50.74 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 2.82 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 26827.03 # Average memory access latency +system.physmem.avgRdBW 376.21 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 20.26 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 50.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 2.81 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.49 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.12 # Average read queue length over time -system.physmem.avgWrQLen 10.88 # Average write queue length over time -system.physmem.readRowHits 15253448 # Number of row buffer hits during reads -system.physmem.writeRowHits 789566 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.busUtil 2.48 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.16 # Average read queue length over time +system.physmem.avgWrQLen 12.97 # Average write queue length over time +system.physmem.readRowHits 15255805 # Number of row buffer hits during reads +system.physmem.writeRowHits 789541 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.70 # Row buffer hit rate for reads system.physmem.writeRowHitRate 95.80 # Row buffer hit rate for writes -system.physmem.avgGap 160799.50 # Average gap between requests +system.physmem.avgGap 161422.56 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -239,258 +235,244 @@ system.realview.nvmem.num_reads::cpu1.inst 6 # system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory system.realview.nvmem.bw_read::cpu0.inst 25 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_read::cpu1.inst 148 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 173 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 172 # Total read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu0.inst 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_inst_read::cpu1.inst 148 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 173 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 172 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 148 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 173 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 73184 # number of replacements -system.l2c.tagsinuse 53096.266008 # Cycle average of tags in use -system.l2c.total_refs 1906265 # Total number of references to valid blocks. -system.l2c.sampled_refs 138351 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.778469 # Average number of references to valid blocks. +system.realview.nvmem.bw_total::total 172 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 73139 # number of replacements +system.l2c.tagsinuse 53098.784053 # Cycle average of tags in use +system.l2c.total_refs 1903330 # Total number of references to valid blocks. +system.l2c.sampled_refs 138315 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.760836 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37733.790025 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 7.219153 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.000341 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4206.047810 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2960.317078 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 11.178862 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.itb.walker 0.966447 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4058.933416 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4117.812877 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.575772 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000110 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 37803.409303 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 5.317240 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.004373 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4191.158517 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2951.048787 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 13.024682 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 4037.185847 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 4097.635305 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.576834 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000081 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064179 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045171 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000171 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061934 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.062833 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810185 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56635.066667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 109502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43407.603774 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 43161.341742 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40767.502356 # average overall mshr miss latency +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13393471796 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 1893563 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 172316371500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 185716295022 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036773 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030263 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016973 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.835298 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.856386 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.844342 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.783231 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.786003 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.784428 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.571798 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565799 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.568496 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.095451 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000623 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015189 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.246993 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000319 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010753 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.242351 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.095451 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 42313.900949 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 44452.303628 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 42058.111023 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10079.971605 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10142.215349 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.046238 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10064.283290 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10014.691781 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10042.830370 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36873.037733 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 42513.081479 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 39962.425613 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 64918.416667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 49668 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39324.442815 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37364.803873 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41966.073569 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 42659.334233 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40282.046935 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -695,27 +665,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9014303 # DTB read hits -system.cpu0.dtb.read_misses 34965 # DTB read misses -system.cpu0.dtb.write_hits 5253714 # DTB write hits -system.cpu0.dtb.write_misses 6399 # DTB write misses +system.cpu0.dtb.read_hits 9024363 # DTB read hits +system.cpu0.dtb.read_misses 35062 # DTB read misses +system.cpu0.dtb.write_hits 5257895 # DTB write hits +system.cpu0.dtb.write_misses 6477 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2155 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1094 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 321 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2160 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1059 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 311 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9049268 # DTB read accesses -system.cpu0.dtb.write_accesses 5260113 # DTB write accesses +system.cpu0.dtb.perms_faults 553 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9059425 # DTB read accesses +system.cpu0.dtb.write_accesses 5264372 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14268017 # DTB hits -system.cpu0.dtb.misses 41364 # DTB misses -system.cpu0.dtb.accesses 14309381 # DTB accesses -system.cpu0.itb.inst_hits 4294311 # ITB inst hits -system.cpu0.itb.inst_misses 5261 # ITB inst misses +system.cpu0.dtb.hits 14282258 # DTB hits +system.cpu0.dtb.misses 41539 # DTB misses +system.cpu0.dtb.accesses 14323797 # DTB accesses +system.cpu0.itb.inst_hits 4307156 # ITB inst hits +system.cpu0.itb.inst_misses 5205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -724,156 +694,156 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1385 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1360 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1364 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1401 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4299572 # ITB inst accesses -system.cpu0.itb.hits 4294311 # DTB hits -system.cpu0.itb.misses 5261 # DTB misses -system.cpu0.itb.accesses 4299572 # DTB accesses -system.cpu0.numCycles 69013505 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4312361 # ITB inst accesses +system.cpu0.itb.hits 4307156 # DTB hits +system.cpu0.itb.misses 5205 # DTB misses +system.cpu0.itb.accesses 4312361 # DTB accesses +system.cpu0.numCycles 69075583 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6123831 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4675790 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 298271 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3798227 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 2989296 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6134621 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4681383 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 299233 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3810859 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 2992358 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 685728 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 28375 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 11998527 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32710943 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6123831 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3675024 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7667644 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1480146 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 66638 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 21758305 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5862 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 53793 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 90248 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 221 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4292744 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 155269 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2401 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 42704543 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.988603 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.369673 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 688987 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 28743 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 12013253 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32740564 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6134621 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3681345 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7677557 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1482239 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 64559 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21828282 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5891 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 53864 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90312 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 236 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4305560 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 159104 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2370 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42798314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.987162 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.368020 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 35044149 82.06% 82.06% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 606065 1.42% 83.48% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 793528 1.86% 85.34% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 689319 1.61% 86.95% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 781424 1.83% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 567584 1.33% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 711320 1.67% 91.78% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 364019 0.85% 92.63% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3147135 7.37% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 35128127 82.08% 82.08% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 610328 1.43% 83.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 795353 1.86% 85.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689183 1.61% 86.97% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 781372 1.83% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 569733 1.33% 90.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 711695 1.66% 91.79% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 364225 0.85% 92.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3148298 7.36% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 42704543 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088734 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.473979 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12497333 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 21726841 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6896095 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 584636 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 999638 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 951812 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64726 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40836330 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213865 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 999638 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 13071648 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5812993 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 13759259 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6855374 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2205631 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 39711904 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2173 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 427558 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1242268 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 68 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40116309 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 179435830 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 179401258 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34572 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31681024 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8435284 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 457771 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 414521 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5443309 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7819363 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5820332 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1146243 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1242216 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 37575405 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 946067 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37951575 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 82274 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6366228 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13456450 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 257591 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 42704543 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.888701 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.500077 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42798314 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088810 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.473982 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12517044 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21792466 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6901256 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 586970 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1000578 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 954803 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64851 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40861344 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213562 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1000578 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 13092600 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5813788 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13806762 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6861684 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2222902 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39740402 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2257 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 444272 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1240471 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 77 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 40148585 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 179562690 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 179528337 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34353 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31678708 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8469876 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 458191 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 414927 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5465728 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7827563 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5820560 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1149873 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1213359 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37598856 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 946637 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37967135 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 82667 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6387129 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13438267 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 258027 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42798314 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.887118 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.498670 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 27159670 63.60% 63.60% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6000291 14.05% 77.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3232720 7.57% 85.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2489147 5.83% 91.05% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2132528 4.99% 96.04% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 950123 2.22% 98.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 497063 1.16% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 188710 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 54291 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27228481 63.62% 63.62% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 6024200 14.08% 77.70% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3238541 7.57% 85.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2496476 5.83% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2116280 4.94% 96.04% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 952748 2.23% 98.27% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 498209 1.16% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188721 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54658 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 42704543 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42798314 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 24659 2.31% 2.31% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 467 0.04% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 838061 78.41% 80.76% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 205631 19.24% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25719 2.40% 2.40% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 458 0.04% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.44% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 838558 78.31% 80.75% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 206136 19.25% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22793341 60.06% 60.20% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 48224 0.13% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22801553 60.06% 60.19% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48143 0.13% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.32% # Type of FU issued @@ -883,10 +853,10 @@ system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.32% # Ty system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 9 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.32% # Type of FU issued @@ -897,365 +867,365 @@ system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.32% # Ty system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.32% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.32% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 680 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9480747 24.98% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5576214 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9487186 24.99% 85.31% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5577397 14.69% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37951575 # Type of FU issued -system.cpu0.iq.rate 0.549915 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1068818 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028163 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 119791525 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44895833 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35071497 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8304 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4710 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3884 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38963714 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4335 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 318123 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37967135 # Type of FU issued +system.cpu0.iq.rate 0.549646 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070871 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028205 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119919123 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44940813 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 35094596 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8245 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4688 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3877 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38981568 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4289 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 319568 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1396327 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2506 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13403 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 544501 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1406645 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2495 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13426 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 546497 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149359 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5385 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2149373 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5419 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 999638 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4184428 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103741 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 38639126 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85944 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7819363 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5820332 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 614711 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 41414 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3290 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13403 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 151339 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 119425 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 270764 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37563861 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9331167 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 387714 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1000578 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4177293 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 102909 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38663154 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 84882 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7827563 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5820560 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 615194 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 41110 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3269 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13426 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 151880 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 119782 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 271662 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37584827 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9341263 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 382308 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117654 # number of nop insts executed -system.cpu0.iew.exec_refs 14857557 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4958494 # Number of branches executed -system.cpu0.iew.exec_stores 5526390 # Number of stores executed -system.cpu0.iew.exec_rate 0.544297 # Inst execution rate -system.cpu0.iew.wb_sent 37365472 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35075381 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18655901 # num instructions producing a value -system.cpu0.iew.wb_consumers 35819655 # num instructions consuming a value +system.cpu0.iew.exec_nop 117661 # number of nop insts executed +system.cpu0.iew.exec_refs 14871823 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4965899 # Number of branches executed +system.cpu0.iew.exec_stores 5530560 # Number of stores executed +system.cpu0.iew.exec_rate 0.544112 # Inst execution rate +system.cpu0.iew.wb_sent 37390069 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 35098473 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18662098 # num instructions producing a value +system.cpu0.iew.wb_consumers 35837598 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.508239 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520829 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.508117 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520741 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6205381 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 688476 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 234604 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 41741265 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.766601 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.727877 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6206788 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 688610 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 235451 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41797736 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.765444 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.723461 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 29720457 71.20% 71.20% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5963123 14.29% 85.49% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1948324 4.67% 90.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1002440 2.40% 92.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 789371 1.89% 94.45% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 520489 1.25% 95.69% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 393953 0.94% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 216687 0.52% 97.16% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1186421 2.84% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29752237 71.18% 71.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5970878 14.29% 85.47% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1965315 4.70% 90.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 999760 2.39% 92.56% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 803961 1.92% 94.48% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 518760 1.24% 95.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395530 0.95% 96.67% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 220150 0.53% 97.20% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1171145 2.80% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 41741265 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24264310 # Number of instructions committed -system.cpu0.commit.committedOps 31998915 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41797736 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 24265529 # Number of instructions committed +system.cpu0.commit.committedOps 31993822 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11698867 # Number of memory references committed -system.cpu0.commit.loads 6423036 # Number of loads committed -system.cpu0.commit.membars 234373 # Number of memory barriers committed -system.cpu0.commit.branches 4346960 # Number of branches committed +system.cpu0.commit.refs 11694981 # Number of memory references committed +system.cpu0.commit.loads 6420918 # Number of loads committed +system.cpu0.commit.membars 234476 # Number of memory barriers committed +system.cpu0.commit.branches 4347395 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28266871 # Number of committed integer instructions. -system.cpu0.commit.function_calls 499893 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1186421 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 28261624 # Number of committed integer instructions. +system.cpu0.commit.function_calls 500034 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1171145 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 77875275 # The number of ROB reads -system.cpu0.rob.rob_writes 77410136 # The number of ROB writes -system.cpu0.timesIdled 364830 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26308962 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5117234895 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24183568 # Number of Instructions Simulated -system.cpu0.committedOps 31918173 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24183568 # Number of Instructions Simulated -system.cpu0.cpi 2.853735 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.853735 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.350418 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.350418 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 175323075 # number of integer regfile reads -system.cpu0.int_regfile_writes 34853003 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3246 # number of floating regfile reads -system.cpu0.fp_regfile_writes 906 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13342715 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527371 # number of misc regfile writes -system.cpu0.icache.replacements 399233 # number of replacements -system.cpu0.icache.tagsinuse 511.592262 # Cycle average of tags in use -system.cpu0.icache.total_refs 3861943 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 399745 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.661016 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 6802423000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.592262 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999204 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999204 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3861943 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3861943 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3861943 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3861943 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3861943 # number of overall hits -system.cpu0.icache.overall_hits::total 3861943 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 430668 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 430668 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 430668 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 430668 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 430668 # number of overall misses -system.cpu0.icache.overall_misses::total 430668 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5857521993 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5857521993 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5857521993 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5857521993 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5857521993 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5857521993 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4292611 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4292611 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4292611 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4292611 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4292611 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4292611 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100328 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100328 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100328 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100328 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100328 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100328 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13601.015151 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13601.015151 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13601.015151 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13601.015151 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13601.015151 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 2687 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77942939 # The number of ROB reads +system.cpu0.rob.rob_writes 77403720 # The number of ROB writes +system.cpu0.timesIdled 364282 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26277269 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 5137251054 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 24184787 # Number of Instructions Simulated +system.cpu0.committedOps 31913080 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 24184787 # Number of Instructions Simulated +system.cpu0.cpi 2.856158 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.856158 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.350121 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.350121 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 175453235 # number of integer regfile reads +system.cpu0.int_regfile_writes 34873256 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3235 # number of floating regfile reads +system.cpu0.fp_regfile_writes 908 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13424511 # number of misc regfile reads +system.cpu0.misc_regfile_writes 527689 # number of misc regfile writes +system.cpu0.icache.replacements 399628 # number of replacements +system.cpu0.icache.tagsinuse 511.593033 # Cycle average of tags in use +system.cpu0.icache.total_refs 3873847 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 400140 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.681229 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 6818802000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.593033 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.999205 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999205 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3873847 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3873847 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3873847 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3873847 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3873847 # number of overall hits +system.cpu0.icache.overall_hits::total 3873847 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 431582 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 431582 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 431582 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 431582 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 431582 # number of overall misses +system.cpu0.icache.overall_misses::total 431582 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5855735994 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5855735994 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5855735994 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5855735994 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5855735994 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5855735994 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4305429 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4305429 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4305429 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4305429 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4305429 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4305429 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100241 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100241 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100241 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100241 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100241 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100241 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13568.072797 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13568.072797 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13568.072797 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13568.072797 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13568.072797 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2448 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 157 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 142 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.114650 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.239437 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30901 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30901 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30901 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30901 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30901 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30901 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 399767 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 399767 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 399767 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 399767 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 399767 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 399767 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4790784994 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4790784994 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4790784994 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4790784994 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4790784994 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4790784994 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31419 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31419 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31419 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31419 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31419 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31419 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 400163 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 400163 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 400163 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 400163 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 400163 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 400163 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4791432494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4791432494 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4791432494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4791432494 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4791432494 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4791432494 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7139500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7139500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7139500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7139500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093129 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093129 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093129 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093129 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11983.943132 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11983.943132 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11983.943132 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.092944 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.092944 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.092944 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.092944 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11973.701951 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11973.701951 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11973.701951 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 274937 # number of replacements -system.cpu0.dcache.tagsinuse 481.181813 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9516256 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 275449 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.548160 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 274722 # number of replacements +system.cpu0.dcache.tagsinuse 476.919366 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9525271 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 275234 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 34.607901 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 36452000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 481.181813 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.939808 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.939808 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5887183 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5887183 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3238358 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3238358 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173666 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 173666 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171542 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171542 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9125541 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9125541 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9125541 # number of overall hits -system.cpu0.dcache.overall_hits::total 9125541 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 390766 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 390766 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1582021 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1582021 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8872 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8872 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7743 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7743 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1972787 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1972787 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1972787 # number of overall misses -system.cpu0.dcache.overall_misses::total 1972787 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5377265000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5377265000 # 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number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6277949 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4820379 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4820379 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182538 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 182538 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179285 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179285 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11098328 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11098328 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11098328 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11098328 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062244 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.062244 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.328194 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.328194 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048604 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048604 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043188 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043188 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177755 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.177755 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177755 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.177755 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13760.831290 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13760.831290 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38483.314600 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38483.314600 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9943.924707 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9943.924707 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6518.855741 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6518.855741 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33586.330834 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33586.330834 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33586.330834 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8283 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3369 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 596 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 82 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.897651 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 41.085366 # average number of cycles each access was blocked +system.cpu0.dcache.occ_blocks::cpu0.data 476.919366 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.931483 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.931483 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5895102 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5895102 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3238989 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3238989 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174455 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174455 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171581 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171581 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 9134091 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 9134091 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 9134091 # number of overall hits +system.cpu0.dcache.overall_hits::total 9134091 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 390587 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 390587 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1579573 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1579573 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8896 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8896 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7728 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7728 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1970160 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1970160 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1970160 # number of overall misses +system.cpu0.dcache.overall_misses::total 1970160 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5389048500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5389048500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60454939374 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60454939374 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88150000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88150000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 50211500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 50211500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 65843987874 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 65843987874 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 65843987874 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 65843987874 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6285689 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6285689 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4818562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4818562 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183351 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183351 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179309 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 179309 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 11104251 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 11104251 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 11104251 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 11104251 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062139 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062139 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.327810 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.327810 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048519 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048519 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043099 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043099 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.177424 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.177424 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.177424 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.177424 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13797.306362 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13797.306362 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38272.963246 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38272.963246 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9908.947842 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9908.947842 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6497.347308 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6497.347308 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33420.629733 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33420.629733 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33420.629733 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8059 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2986 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 556 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.494604 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 37.325000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 255577 # number of writebacks -system.cpu0.dcache.writebacks::total 255577 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202032 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202032 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1450989 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1450989 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 498 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 498 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1653021 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1653021 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1653021 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1653021 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188734 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188734 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131032 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131032 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8374 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8374 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7739 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319766 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319766 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319766 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319766 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2333622500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2333622500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4054127491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4054127491 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66245000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66245000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34997500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34997500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6387749991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6387749991 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6387749991 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6387749991 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13431600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13431600500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199905877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199905877 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14631506377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14631506377 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027183 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027183 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045875 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043166 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043166 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028812 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028812 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028812 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12364.611040 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12364.611040 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30939.980241 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30939.980241 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7910.795319 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7910.795319 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4522.225094 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4522.225094 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19976.326411 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19976.326411 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 255180 # number of writebacks +system.cpu0.dcache.writebacks::total 255180 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202008 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 202008 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1448555 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1448555 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 484 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1650563 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1650563 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1650563 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1650563 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188579 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188579 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131018 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 131018 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8412 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8412 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7726 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7726 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319597 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319597 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319597 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319597 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2343972000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2343972000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4029495991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4029495991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66259000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66259000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 34759500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 34759500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6373467991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6373467991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6373467991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6373467991 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13432446000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13432446000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1199878877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1199878877 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14632324877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14632324877 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030001 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030001 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027190 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045879 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045879 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043088 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043088 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.028781 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028781 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.028781 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12429.655476 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12429.655476 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30755.285465 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30755.285465 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7876.723728 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7876.723728 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4499.029252 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4499.029252 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19942.202183 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19942.202183 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1265,27 +1235,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43030291 # DTB read hits -system.cpu1.dtb.read_misses 42638 # DTB read misses -system.cpu1.dtb.write_hits 6991861 # DTB write hits -system.cpu1.dtb.write_misses 11867 # DTB write misses +system.cpu1.dtb.read_hits 43034108 # DTB read hits +system.cpu1.dtb.read_misses 42641 # DTB read misses +system.cpu1.dtb.write_hits 7001737 # DTB write hits +system.cpu1.dtb.write_misses 11814 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2362 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2846 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.flush_entries 2370 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2838 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 322 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 690 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43072929 # DTB read accesses -system.cpu1.dtb.write_accesses 7003728 # DTB write accesses +system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43076749 # DTB read accesses +system.cpu1.dtb.write_accesses 7013551 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50022152 # DTB hits -system.cpu1.dtb.misses 54505 # DTB misses -system.cpu1.dtb.accesses 50076657 # DTB accesses -system.cpu1.itb.inst_hits 7786412 # ITB inst hits -system.cpu1.itb.inst_misses 5635 # ITB inst misses +system.cpu1.dtb.hits 50035845 # DTB hits +system.cpu1.dtb.misses 54455 # DTB misses +system.cpu1.dtb.accesses 50090300 # DTB accesses +system.cpu1.itb.inst_hits 7783284 # ITB inst hits +system.cpu1.itb.inst_misses 5669 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1294,538 +1264,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1584 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1520 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1542 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 7792047 # ITB inst accesses -system.cpu1.itb.hits 7786412 # DTB hits -system.cpu1.itb.misses 5635 # DTB misses -system.cpu1.itb.accesses 7792047 # DTB accesses -system.cpu1.numCycles 409024249 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7788953 # ITB inst accesses +system.cpu1.itb.hits 7783284 # DTB hits +system.cpu1.itb.misses 5669 # DTB misses +system.cpu1.itb.accesses 7788953 # DTB accesses +system.cpu1.numCycles 409060969 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9020667 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7346445 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 421687 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 5902094 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5066087 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9019142 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7341577 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 421290 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 5896961 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5059614 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 810235 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 44717 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 19548819 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 61628162 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9020667 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 5876322 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 13445282 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3432135 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 71958 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 78159434 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5756 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 48212 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 140837 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 164 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 7784486 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 545452 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3066 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 113770833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.663645 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 1.994153 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 812166 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 44802 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 19538569 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 61710735 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9019142 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5871780 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13457716 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3440559 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 72159 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78167878 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 5662 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 49809 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 140998 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 150 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7781352 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 538014 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3102 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113786982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.664391 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.995438 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100333102 88.19% 88.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 820750 0.72% 88.91% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 967014 0.85% 89.76% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1722421 1.51% 91.27% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1420935 1.25% 92.52% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 598048 0.53% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1962596 1.73% 94.77% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 435893 0.38% 95.16% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5510074 4.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100336589 88.18% 88.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 821334 0.72% 88.90% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 966420 0.85% 89.75% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1725152 1.52% 91.27% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1418529 1.25% 92.51% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 601242 0.53% 93.04% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1958088 1.72% 94.76% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 436465 0.38% 95.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5523163 4.85% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 113770833 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022054 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.150671 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 20932611 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77783544 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12260401 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 543319 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2250958 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1146967 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 100968 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 71503765 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 336196 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2250958 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22152530 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32126143 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 41276446 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11489660 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4475096 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 67542275 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19496 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 697256 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3178756 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32684 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 70870880 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 310023883 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 309964693 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 59190 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50213421 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 20657459 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 473589 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 413624 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8131877 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 12919526 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8160199 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1076421 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1515550 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 62172086 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1201080 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89161848 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 100982 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 13762748 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 36926540 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 280453 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 113770833 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.783697 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520241 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113786982 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022048 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.150860 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20926147 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 77797918 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12266013 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 542191 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2254713 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1149115 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100993 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 71511004 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 338807 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2254713 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22129407 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32117603 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41299485 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11510444 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4475330 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 67658360 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19594 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 697706 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3178110 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 32539 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 70993653 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 310596355 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 310537273 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59082 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 50200074 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20793579 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 474201 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 414075 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 8134070 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12921007 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8155176 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1083797 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1589261 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 62166896 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1195329 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89153414 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 99788 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13746763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 36760953 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 275268 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113786982 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.783512 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519359 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83205809 73.13% 73.13% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8622127 7.58% 80.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4341809 3.82% 84.53% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3750529 3.30% 87.83% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10472490 9.20% 97.03% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1973623 1.73% 98.77% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1061651 0.93% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 265825 0.23% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 76970 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83183185 73.10% 73.10% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8664055 7.61% 80.72% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4355929 3.83% 84.55% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3746204 3.29% 87.84% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10471181 9.20% 97.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1956933 1.72% 98.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1074012 0.94% 99.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 258436 0.23% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 77047 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 113770833 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113786982 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29803 0.38% 0.38% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 992 0.01% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7572506 95.90% 96.29% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 293239 3.71% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29283 0.37% 0.37% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 991 0.01% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7571422 95.88% 96.27% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 294824 3.73% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37491969 42.05% 42.40% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61148 0.07% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1700 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.47% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43923048 49.26% 91.73% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7369892 8.27% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37493479 42.06% 42.41% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 61246 0.07% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1694 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.48% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43910750 49.25% 91.73% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7372221 8.27% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89161848 # Type of FU issued -system.cpu1.iq.rate 0.217987 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7896540 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088564 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300131429 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 77144913 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 54450273 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14948 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8092 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6814 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96736439 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7887 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 357826 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89153414 # Type of FU issued +system.cpu1.iq.rate 0.217947 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7896520 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088572 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300129512 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 77117892 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54483079 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14896 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8093 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6803 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96728092 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7845 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 354516 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2919371 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4089 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17660 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1133342 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2925065 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4096 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17562 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1131401 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965401 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 692354 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31964883 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 695794 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2250958 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24192691 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 367138 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 63477454 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 113697 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 12919526 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8160199 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 893697 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 68960 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3858 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17660 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 208465 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 159370 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 367835 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 87401818 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43412086 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1760030 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2254713 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24187633 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 367329 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 63466208 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 114663 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12921007 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8155176 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 887376 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 69283 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3741 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17562 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 208254 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 160111 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 368365 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87428231 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43415449 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1725183 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 104288 # number of nop insts executed -system.cpu1.iew.exec_refs 50709476 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7088545 # Number of branches executed -system.cpu1.iew.exec_stores 7297390 # Number of stores executed -system.cpu1.iew.exec_rate 0.213684 # Inst execution rate -system.cpu1.iew.wb_sent 86601126 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 54457087 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30364436 # num instructions producing a value -system.cpu1.iew.wb_consumers 54295656 # num instructions consuming a value +system.cpu1.iew.exec_nop 103983 # number of nop insts executed +system.cpu1.iew.exec_refs 50722611 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7090027 # Number of branches executed +system.cpu1.iew.exec_stores 7307162 # Number of stores executed +system.cpu1.iew.exec_rate 0.213729 # Inst execution rate +system.cpu1.iew.wb_sent 86641966 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54489882 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30361493 # num instructions producing a value +system.cpu1.iew.wb_consumers 54263873 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.133139 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.559242 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.133207 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.559516 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 13692554 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 920627 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 322274 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111568344 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.442227 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.413238 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13678793 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 920061 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 321962 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111532269 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.442230 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.412276 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94375668 84.59% 84.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8446118 7.57% 92.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2197127 1.97% 94.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1290727 1.16% 95.29% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1277171 1.14% 96.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 591366 0.53% 96.96% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 1009730 0.91% 97.87% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 541366 0.49% 98.35% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1839071 1.65% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94330377 84.58% 84.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8440609 7.57% 92.14% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2214130 1.99% 94.13% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1297536 1.16% 95.29% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1275593 1.14% 96.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 591609 0.53% 96.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 995873 0.89% 97.86% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 566603 0.51% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1819939 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111568344 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38958201 # Number of instructions committed -system.cpu1.commit.committedOps 49338577 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111532269 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38948804 # Number of instructions committed +system.cpu1.commit.committedOps 49322865 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17027012 # Number of memory references committed -system.cpu1.commit.loads 10000155 # Number of loads committed -system.cpu1.commit.membars 202531 # Number of memory barriers committed -system.cpu1.commit.branches 6139960 # Number of branches committed +system.cpu1.commit.refs 17019717 # Number of memory references committed +system.cpu1.commit.loads 9995942 # Number of loads committed +system.cpu1.commit.membars 202353 # Number of memory barriers committed +system.cpu1.commit.branches 6138218 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43727423 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556605 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1839071 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 43713249 # Number of committed integer instructions. +system.cpu1.commit.function_calls 556359 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1819939 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 171645222 # The number of ROB reads -system.cpu1.rob.rob_writes 128401309 # The number of ROB writes -system.cpu1.timesIdled 1423775 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295253416 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4776625618 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38888562 # Number of Instructions Simulated -system.cpu1.committedOps 49268938 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38888562 # Number of Instructions Simulated -system.cpu1.cpi 10.517855 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.517855 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.095076 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.095076 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 391481129 # number of integer regfile reads -system.cpu1.int_regfile_writes 56596470 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2328 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18962770 # number of misc regfile reads -system.cpu1.misc_regfile_writes 430176 # number of misc regfile writes -system.cpu1.icache.replacements 614989 # number of replacements -system.cpu1.icache.tagsinuse 498.619037 # Cycle average of tags in use -system.cpu1.icache.total_refs 7122851 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 615501 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 11.572444 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74507010000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.619037 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.973865 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.973865 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7122851 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7122851 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7122851 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7122851 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7122851 # number of overall hits -system.cpu1.icache.overall_hits::total 7122851 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 661583 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 661583 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 661583 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 661583 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 661583 # number of overall misses -system.cpu1.icache.overall_misses::total 661583 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8883357995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8883357995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8883357995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8883357995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8883357995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8883357995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 7784434 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 7784434 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 7784434 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 7784434 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 7784434 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 7784434 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084988 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.084988 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084988 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.084988 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084988 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.084988 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13427.427844 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13427.427844 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13427.427844 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13427.427844 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13427.427844 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3547 # number of cycles access was blocked +system.cpu1.rob.rob_reads 171599349 # The number of ROB reads +system.cpu1.rob.rob_writes 128350222 # The number of ROB writes +system.cpu1.timesIdled 1423694 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295273987 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 4796667155 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38879165 # Number of Instructions Simulated +system.cpu1.committedOps 49253226 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38879165 # Number of Instructions Simulated +system.cpu1.cpi 10.521341 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.521341 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.095045 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.095045 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391632222 # number of integer regfile reads +system.cpu1.int_regfile_writes 56613239 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4857 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2306 # number of floating regfile writes +system.cpu1.misc_regfile_reads 19006571 # number of misc regfile reads +system.cpu1.misc_regfile_writes 429961 # number of misc regfile writes +system.cpu1.icache.replacements 614526 # number of replacements +system.cpu1.icache.tagsinuse 498.795598 # Cycle average of tags in use +system.cpu1.icache.total_refs 7119619 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 615038 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 11.575901 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74541182500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 498.795598 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.974210 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.974210 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7119619 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7119619 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7119619 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7119619 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7119619 # number of overall hits +system.cpu1.icache.overall_hits::total 7119619 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 661683 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 661683 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 661683 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 661683 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 661683 # number of overall misses +system.cpu1.icache.overall_misses::total 661683 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8857903496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8857903496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8857903496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8857903496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8857903496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8857903496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7781302 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7781302 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7781302 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7781302 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7781302 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7781302 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.085035 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.085035 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.085035 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.085035 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.085035 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.085035 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13386.929233 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13386.929233 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13386.929233 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13386.929233 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13386.929233 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2804 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 188 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 19.489011 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.914894 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46050 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 46050 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 46050 # 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number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7269169496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7269169496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7269169496 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7269169496 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2823500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 2823500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079072 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.079072 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079072 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.079072 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11809.552853 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11809.552853 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11809.552853 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 46618 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 46618 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 46618 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 46618 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 46618 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 46618 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 615065 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 615065 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 615065 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 615065 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 615065 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 615065 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7253593996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7253593996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7253593996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7253593996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7253593996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7253593996 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 2902500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 2902500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 2902500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 2902500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.079044 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.079044 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.079044 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.079044 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11793.215345 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11793.215345 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11793.215345 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 363437 # number of replacements -system.cpu1.dcache.tagsinuse 485.666262 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13086846 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 363802 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.972441 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 70623957000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 485.666262 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.948567 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.948567 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8551806 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8551806 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4291461 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4291461 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 103521 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 103521 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100890 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100890 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12843267 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12843267 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12843267 # number of overall hits -system.cpu1.dcache.overall_hits::total 12843267 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 401802 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 401802 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1565358 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1565358 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14225 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14225 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10942 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10942 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1967160 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1967160 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1967160 # number of overall misses -system.cpu1.dcache.overall_misses::total 1967160 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6026246000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6026246000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 64613580018 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 64613580018 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 131651000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 131651000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 58881000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 58881000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 70639826018 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 70639826018 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 70639826018 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 70639826018 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8953608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8953608 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5856819 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5856819 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 117746 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 117746 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111832 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111832 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14810427 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14810427 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14810427 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14810427 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044876 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.044876 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.267271 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.267271 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.120811 # 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average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9254.903339 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9254.903339 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5381.191738 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5381.191738 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 35909.547784 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35909.547784 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 35909.547784 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 28351 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 15005 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3227 # 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Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8556277 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8556277 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4290501 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4290501 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 104307 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 104307 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100808 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 100808 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12846778 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12846778 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12846778 # number of overall hits +system.cpu1.dcache.overall_hits::total 12846778 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 401782 # 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miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.132671 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.132671 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14995.710360 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14995.710360 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 40964.872491 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 40964.872491 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9248.448300 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9248.448300 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5367.158841 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5367.158841 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 35655.251306 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 35655.251306 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 35655.251306 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 28539 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 15177 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3269 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 166 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.730193 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 91.427711 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328383 # number of writebacks -system.cpu1.dcache.writebacks::total 328383 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170419 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170419 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1402227 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1402227 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1450 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1572646 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1572646 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1572646 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1572646 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231383 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 231383 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163131 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 163131 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12775 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12775 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10936 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10936 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 394514 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 394514 # 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number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196211421394 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025842 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025842 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108496 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108496 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097790 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097790 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026638 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026638 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026638 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12405.267457 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12405.267457 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32495.934004 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32495.934004 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7054.207436 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7054.207436 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3384.144111 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3384.144111 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20712.730626 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20712.730626 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 327455 # number of writebacks +system.cpu1.dcache.writebacks::total 327455 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170587 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 170587 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1400204 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1400204 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1432 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1432 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1570791 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1570791 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1570791 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1570791 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 231195 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 231195 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 163115 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 163115 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12746 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10902 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10902 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 394310 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 394310 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 394310 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 394310 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2860496500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2860496500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5258978708 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5258978708 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89750500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89750500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 36721500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 36721500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 8119475208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 8119475208 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 8119475208 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 8119475208 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169298302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169298302500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 27190030960 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 27190030960 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 196488333460 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 196488333460 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025809 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025809 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027865 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097590 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097590 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026621 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026621 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026621 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12372.657281 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12372.657281 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32240.926389 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 32240.926389 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7041.463989 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7041.463989 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3368.326912 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3368.326912 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20591.603581 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20591.603581 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1847,18 +1821,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1082174693399 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1082174693399 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1082174693399 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1162989936366 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1162989936366 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1162989936366 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43757 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43794 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53969 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 53929 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |