diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-08-19 03:52:36 -0400 |
| commit | b63631536d974f31cf99ee280271dc0f7b4c746f (patch) | |
| tree | ff83820d8dd75de8238e4b7ddaf3b91e4cf8374f /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 646c4a23ca44aab5468c896034288151c89be782 (diff) | |
| download | gem5-b63631536d974f31cf99ee280271dc0f7b4c746f.tar.xz | |
stats: Cumulative stats update
This patch updates the stats to reflect the: 1) addition of the
internal queue in SimpleMemory, 2) moving of the memory class outside
FSConfig, 3) fixing up of the 2D vector printing format, 4) specifying
burst size and interface width for the DRAM instead of relying on
cache-line size, 5) performing merging in the DRAM controller write
buffer, and 6) fixing how idle cycles are counted in the atomic and
timing CPU models.
The main reason for bundling them up is to minimise the changeset
size.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 3943 |
1 files changed, 1928 insertions, 2015 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 5451e0c81..0edabf3c5 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,150 +1,155 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.114023 # Number of seconds simulated -sim_ticks 1114022852000 # Number of ticks simulated -final_tick 1114022852000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.104038 # Number of seconds simulated +sim_ticks 1104038330000 # Number of ticks simulated +final_tick 1104038330000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 79652 # Simulator instruction rate (inst/s) -host_op_rate 102538 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1440387686 # Simulator tick rate (ticks/s) -host_mem_usage 404604 # Number of bytes of host memory used -host_seconds 773.42 # Real time elapsed on the host -sim_insts 61604368 # Number of instructions simulated -sim_ops 79304455 # Number of ops (including micro ops) simulated +host_inst_rate 80920 # Simulator instruction rate (inst/s) +host_op_rate 104171 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450259542 # Simulator tick rate (ticks/s) +host_mem_usage 402880 # Number of bytes of host memory used +host_seconds 761.27 # Real time elapsed on the host +sim_insts 61602211 # Number of instructions simulated +sim_ops 79302243 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 1024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409408 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4367220 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 410368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4366772 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 896 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 406208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5247536 # Number of bytes read from this memory -system.physmem.bytes_read::total 59191204 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409408 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 406208 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815616 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4263872 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405824 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5250416 # Number of bytes read from this memory +system.physmem.bytes_read::total 59194084 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 410368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405824 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 816192 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4267200 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7291216 # Number of bytes written to this memory +system.physmem.bytes_written::total 7294544 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 16 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6397 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68310 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6412 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68303 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 14 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6347 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 82019 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257953 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66623 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6341 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 82064 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257998 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66675 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823459 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43768208 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 919 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 115 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 367504 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3920225 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 804 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 364632 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4710438 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53132845 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 367504 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 364632 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 732136 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3827455 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15260 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2702228 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6544943 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3827455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43768208 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 919 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 115 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 367504 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3935485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 804 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 364632 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7412667 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 59677788 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257953 # Total number of read requests seen -system.physmem.writeReqs 823459 # Total number of write requests seen -system.physmem.cpureqs 242171 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508992 # Total number of bytes read from memory -system.physmem.bytesWritten 52701376 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59191204 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7291216 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 127 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12548 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 391049 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 391102 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391240 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391825 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 391535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 391243 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391065 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391488 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 391482 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390728 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 390299 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 390904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 390678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 391045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391022 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 49919 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 49928 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51967 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51963 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 52290 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 51965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51872 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51692 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51908 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51949 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51308 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51011 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51439 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51134 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51585 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51529 # Track writes on a per bank basis +system.physmem.num_writes::total 823511 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44164032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 696 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 174 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 371697 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3955272 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 812 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.itb.walker 58 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 367581 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4755646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53615968 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 371697 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 367581 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 739279 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3865083 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15398 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2726666 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6607147 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3865083 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44164032 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 696 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 174 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 371697 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3970670 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 812 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.itb.walker 58 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 367581 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7482313 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60223116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257998 # Total number of read requests accepted by DRAM controller +system.physmem.writeReqs 823511 # Total number of write requests accepted by DRAM controller +system.physmem.readBursts 6257998 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts +system.physmem.writeBursts 823511 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts +system.physmem.bytesRead 400511872 # Total number of bytes read from memory +system.physmem.bytesWritten 52704704 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59194084 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7294544 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 4191 # Number of DRAM read bursts serviced by write Q +system.physmem.neitherReadNorWrite 12574 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391107 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 391051 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 391031 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 390511 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391821 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 391470 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 391242 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 390250 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391441 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 391418 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390570 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 389084 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 390982 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 390746 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 391146 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 389937 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 7175 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 7210 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 7320 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 7294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 7815 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 7419 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 7389 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 7204 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 7511 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 7529 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 6860 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 6626 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 7171 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 6832 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 7294 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 7205 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32580 # Number of times wr buffer was full causing retry -system.physmem.totGap 1114021721000 # Total gap between requests +system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry +system.physmem.totGap 1104037196000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 163000 # Categorize read packet sizes +system.physmem.readPktSize::6 163045 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 756836 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 66623 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 508306 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 436400 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 409055 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1494610 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1111724 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1109849 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1096192 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 9300 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6855 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 11963 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 16960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 11777 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 8816 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 8727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 12128 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 5024 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 119 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 13 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.writePktSize::6 66675 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 510579 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 438231 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 410611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1497375 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1129368 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1114937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1085131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 10318 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 7846 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 12945 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17928 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 12334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 1651 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 1534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1452 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1390 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 94 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 72 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see @@ -156,366 +161,312 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2907 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3064 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3094 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3130 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3162 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3189 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3206 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35803 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32896 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32793 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32739 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32709 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32673 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32641 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 32614 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32597 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 38811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11677.106800 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 598.829081 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 25969.144286 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-95 10478 27.00% 27.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-159 4256 10.97% 37.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-223 2718 7.00% 44.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-287 2024 5.22% 50.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-351 1422 3.66% 53.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-415 1213 3.13% 56.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-479 997 2.57% 59.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-543 905 2.33% 61.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-607 654 1.69% 63.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-671 573 1.48% 65.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-735 456 1.17% 66.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-799 470 1.21% 67.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-863 308 0.79% 68.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-927 261 0.67% 68.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-991 192 0.49% 69.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1055 284 0.73% 70.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1119 136 0.35% 70.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1183 144 0.37% 70.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1247 111 0.29% 71.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1311 147 0.38% 71.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1375 83 0.21% 71.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1439 412 1.06% 72.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1503 1956 5.04% 77.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1567 510 1.31% 79.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1631 94 0.24% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1695 178 0.46% 79.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1759 53 0.14% 79.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1823 122 0.31% 80.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1887 38 0.10% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1951 83 0.21% 80.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-2015 40 0.10% 80.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2079 68 0.18% 80.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2143 23 0.06% 80.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2207 47 0.12% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2271 17 0.04% 81.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2335 43 0.11% 81.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2399 13 0.03% 81.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2463 28 0.07% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2527 13 0.03% 81.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2591 25 0.06% 81.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2655 10 0.03% 81.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2719 18 0.05% 81.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2783 7 0.02% 81.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2847 19 0.05% 81.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2911 4 0.01% 81.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2975 20 0.05% 81.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3039 6 0.02% 81.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3103 20 0.05% 81.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3167 6 0.02% 81.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3231 9 0.02% 81.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3295 7 0.02% 81.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3359 18 0.05% 81.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3423 3 0.01% 81.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3487 11 0.03% 81.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3551 6 0.02% 81.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3615 12 0.03% 81.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3679 6 0.02% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3743 2 0.01% 81.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3807 6 0.02% 81.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3871 7 0.02% 81.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3935 5 0.01% 81.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3999 10 0.03% 81.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4063 2 0.01% 81.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4127 40 0.10% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4191 1 0.00% 82.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4255 7 0.02% 82.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4319 2 0.01% 82.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4383 5 0.01% 82.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4447 3 0.01% 82.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4511 4 0.01% 82.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4575 3 0.01% 82.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4639 9 0.02% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4703 1 0.00% 82.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4767 2 0.01% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4831 2 0.01% 82.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4895 2 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4959 2 0.01% 82.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5023 5 0.01% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5087 1 0.00% 82.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5151 7 0.02% 82.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5215 4 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5279 2 0.01% 82.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5343 2 0.01% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5407 2 0.01% 82.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5471 2 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5535 2 0.01% 82.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5599 3 0.01% 82.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5663 3 0.01% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5727 2 0.01% 82.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5791 1 0.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5855 1 0.00% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5919 2 0.01% 82.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5983 2 0.01% 82.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6047 3 0.01% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6111 2 0.01% 82.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6175 5 0.01% 82.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6239 3 0.01% 82.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6303 4 0.01% 82.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6367 2 0.01% 82.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6431 4 0.01% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6495 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6559 1 0.00% 82.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6623 1 0.00% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6687 2 0.01% 82.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6751 2 0.01% 82.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6815 14 0.04% 82.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6879 3 0.01% 82.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6943 3 0.01% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-7007 2 0.01% 82.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7071 2 0.01% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7199 3 0.01% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7263 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7327 1 0.00% 82.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7455 6 0.02% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7519 1 0.00% 82.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7583 4 0.01% 82.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7711 6 0.02% 82.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7775 2 0.01% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7808-7839 2 0.01% 82.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7872-7903 2 0.01% 82.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7967 7 0.02% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8000-8031 1 0.00% 82.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8095 7 0.02% 82.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8128-8159 4 0.01% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8223 316 0.81% 83.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8256-8287 1 0.00% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8991 2 0.01% 83.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9247 5 0.01% 83.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9344-9375 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9503 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9695 1 0.00% 83.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-10015 2 0.01% 83.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10271 15 0.04% 83.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10368-10399 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10527 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10783 1 0.00% 83.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11039 3 0.01% 83.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11295 3 0.01% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11551 1 0.00% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11807 2 0.01% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12063 1 0.00% 83.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12319 5 0.01% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12575 1 0.00% 83.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12831 2 0.01% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12864-12895 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13087 1 0.00% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13343 2 0.01% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13504-13535 1 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13568-13599 1 0.00% 83.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14367 4 0.01% 83.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15135 3 0.01% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15391 1 0.00% 83.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15424-15455 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15744-15775 1 0.00% 83.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16671 3 0.01% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16927 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17183 1 0.00% 83.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17216-17247 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17344-17375 1 0.00% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17439 2 0.01% 83.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17695 2 0.01% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17728-17759 1 0.00% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17984-18015 1 0.00% 83.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18207 3 0.01% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18463 1 0.00% 83.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18560-18591 1 0.00% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18719 2 0.01% 83.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18975 2 0.01% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19231 1 0.00% 83.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19487 4 0.01% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19584-19615 1 0.00% 83.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19999 3 0.01% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20096-20127 1 0.00% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20255 1 0.00% 83.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20511 12 0.03% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20767 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21279 1 0.00% 83.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21535 2 0.01% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21791 1 0.00% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21952-21983 2 0.01% 83.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22047 1 0.00% 83.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22559 4 0.01% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22656-22687 1 0.00% 83.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22815 3 0.01% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23327 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23583 1 0.00% 83.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24000-24031 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24095 2 0.01% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24192-24223 1 0.00% 83.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24351 1 0.00% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24607 2 0.01% 83.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24704-24735 2 0.01% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25375 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25408-25439 1 0.00% 83.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25631 2 0.01% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25887 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26079 1 0.00% 83.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26143 4 0.01% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26304-26335 1 0.00% 83.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26399 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26655 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27167 3 0.01% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27423 2 0.01% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27456-27487 1 0.00% 83.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27679 2 0.01% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27935 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28447 1 0.00% 83.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28703 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28959 1 0.00% 83.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29471 2 0.01% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30495 1 0.00% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30528-30559 1 0.00% 83.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30751 3 0.01% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30943 1 0.00% 83.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-31007 2 0.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31040-31071 1 0.00% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31775 2 0.01% 83.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31808-31839 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32192-32223 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32287 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32384-32415 1 0.00% 83.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32543 2 0.01% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32799 2 0.01% 83.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33311 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33344-33375 1 0.00% 83.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33567 5 0.01% 83.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33600-33631 2 0.01% 83.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33664-33695 3 0.01% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33728-33759 2 0.01% 83.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33823 43 0.11% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34496-34527 1 0.00% 83.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34847 2 0.01% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35136-35167 1 0.00% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35871 1 0.00% 83.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36127 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36288-36319 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36383 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37824-37855 1 0.00% 83.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37919 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38175 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39232-39263 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39455 1 0.00% 84.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39519 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40256-40287 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40832-40863 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40991 1 0.00% 84.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41503 2 0.01% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41664-41695 1 0.00% 84.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42271 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43039 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44096-44127 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45599 1 0.00% 84.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46111 2 0.01% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46367 2 0.01% 84.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46879 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-47007 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48671 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48927 1 0.00% 84.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49183 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49472-49503 1 0.00% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51200-51231 2 0.01% 84.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::51776-51807 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52255 2 0.01% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53279 1 0.00% 84.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54528-54559 2 0.01% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::54784-54815 1 0.00% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56095 1 0.00% 84.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56320-56351 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57280-57311 1 0.00% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57600-57631 2 0.01% 84.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57792-57823 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::57856-57887 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::58624-58655 1 0.00% 84.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59840-59871 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59968-59999 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::60416-60447 1 0.00% 84.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::61440-61471 4 0.01% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62208-62239 1 0.00% 84.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62400-62431 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::62464-62495 1 0.00% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63488-63519 2 0.01% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::63744-63775 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::64512-64543 1 0.00% 84.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65152-65183 6 0.02% 84.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65280-65311 6 0.02% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65408-65439 1 0.00% 84.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65567 5797 14.94% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::129920-129951 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130880-130911 1 0.00% 99.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::130944-130975 1 0.00% 99.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131072-131103 326 0.84% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::131200-131231 1 0.00% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::132096-132127 2 0.01% 99.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::133632-133663 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::136576-136607 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::160768-160799 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::165568-165599 1 0.00% 99.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::169728-169759 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::175552-175583 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::189440-189471 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196352-196383 1 0.00% 99.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::196608-196639 6 0.02% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 38811 # Bytes accessed per row activation -system.physmem.totQLat 182252409750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 221627859750 # Sum of mem lat for all requests -system.physmem.totBusLat 31289130000 # Total cycles spent in databus access -system.physmem.totBankLat 8086320000 # Total cycles spent in bank access -system.physmem.avgQLat 29123.92 # Average queueing delay per request -system.physmem.avgBankLat 1292.19 # Average bank access latency per request +system.physmem.wrQLenPdf::0 5005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5036 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 5037 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 33 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 35262 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 11560.822642 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 608.575977 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 24356.197009 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-79 8749 24.81% 24.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-143 4356 12.35% 37.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-207 2652 7.52% 44.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-271 2010 5.70% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-335 1437 4.08% 54.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-399 1214 3.44% 57.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-463 927 2.63% 60.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-527 1120 3.18% 63.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-591 659 1.87% 65.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-655 617 1.75% 67.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-719 450 1.28% 68.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-783 454 1.29% 69.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-847 302 0.86% 70.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-911 302 0.86% 71.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-975 179 0.51% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1039 219 0.62% 72.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1103 133 0.38% 73.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1167 156 0.44% 73.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1231 97 0.28% 73.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1295 134 0.38% 74.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1359 73 0.21% 74.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1423 395 1.12% 75.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1487 262 0.74% 76.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1551 538 1.53% 77.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1615 109 0.31% 78.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1679 178 0.50% 78.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1743 51 0.14% 78.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1807 128 0.36% 79.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1871 49 0.14% 79.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1935 68 0.19% 79.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1999 39 0.11% 79.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2063 74 0.21% 79.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2127 17 0.05% 79.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2191 56 0.16% 79.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2255 22 0.06% 80.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2319 30 0.09% 80.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2383 13 0.04% 80.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2447 29 0.08% 80.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2511 10 0.03% 80.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2575 19 0.05% 80.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2639 9 0.03% 80.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2703 17 0.05% 80.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2767 7 0.02% 80.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2831 14 0.04% 80.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2895 6 0.02% 80.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2959 10 0.03% 80.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3023 4 0.01% 80.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3087 17 0.05% 80.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3151 3 0.01% 80.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3215 15 0.04% 80.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3279 4 0.01% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3343 7 0.02% 80.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3407 9 0.03% 80.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3471 11 0.03% 80.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3535 3 0.01% 80.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3599 7 0.02% 80.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3663 3 0.01% 80.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3727 11 0.03% 80.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3791 3 0.01% 80.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3855 4 0.01% 80.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3919 5 0.01% 80.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3983 13 0.04% 80.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4047 3 0.01% 80.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4111 28 0.08% 80.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4175 4 0.01% 80.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4239 7 0.02% 80.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4303 4 0.01% 80.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4367 3 0.01% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4431 1 0.00% 80.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4495 6 0.02% 81.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4559 4 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4623 2 0.01% 81.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4687 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4751 1 0.00% 81.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4815 6 0.02% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4879 4 0.01% 81.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4943 5 0.01% 81.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-5007 3 0.01% 81.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5135 4 0.01% 81.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5199 4 0.01% 81.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5263 2 0.01% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5327 1 0.00% 81.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5391 5 0.01% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5455 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5519 1 0.00% 81.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5583 4 0.01% 81.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5647 3 0.01% 81.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5711 1 0.00% 81.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5775 4 0.01% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5839 1 0.00% 81.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5903 2 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6031 2 0.01% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6095 1 0.00% 81.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6159 2 0.01% 81.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6223 3 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6287 2 0.01% 81.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6351 3 0.01% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6415 1 0.00% 81.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6464-6479 3 0.01% 81.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6543 1 0.00% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6671 2 0.01% 81.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6735 2 0.01% 81.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6799 16 0.05% 81.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6863 3 0.01% 81.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6927 5 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6991 3 0.01% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7055 1 0.00% 81.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7183 8 0.02% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7247 1 0.00% 81.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7311 1 0.00% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7439 3 0.01% 81.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7552-7567 5 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7616-7631 2 0.01% 81.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7695 3 0.01% 81.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7744-7759 2 0.01% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7808-7823 1 0.00% 81.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7872-7887 4 0.01% 81.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7951 6 0.02% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8000-8015 1 0.00% 81.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8079 7 0.02% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8128-8143 5 0.01% 81.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8207 318 0.90% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8384-8399 1 0.00% 82.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8463 41 0.12% 82.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8512-8527 122 0.35% 82.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8576-8591 8 0.02% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8719 1 0.00% 82.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8768-8783 3 0.01% 82.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9231 3 0.01% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9487 1 0.00% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9743 2 0.01% 82.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9999 1 0.00% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10255 2 0.01% 82.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10767 2 0.01% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11023 1 0.00% 82.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11279 2 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11535 2 0.01% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12047 2 0.01% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12303 1 0.00% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12736-12751 1 0.00% 82.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13071 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13583 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13839 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14351 1 0.00% 82.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14607 1 0.00% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15375 2 0.01% 82.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15616-15631 1 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16399 2 0.01% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16512-16527 1 0.00% 82.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17423 3 0.01% 82.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17679 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17935 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18447 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18880-18895 1 0.00% 82.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19136-19151 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19215 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19727 1 0.00% 82.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19904-19919 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20239 1 0.00% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20495 2 0.01% 82.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20928-20943 1 0.00% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-21007 2 0.01% 82.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21312-21327 1 0.00% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21519 2 0.01% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22031 1 0.00% 83.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22543 3 0.01% 83.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23567 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23823 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24128-24143 1 0.00% 83.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24591 4 0.01% 83.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24847 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25024-25039 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25103 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25359 1 0.00% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26304-26319 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26368-26383 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26639 1 0.00% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26688-26703 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27200-27215 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27407 1 0.00% 83.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27663 2 0.01% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27968-27983 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28096-28111 1 0.00% 83.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28687 3 0.01% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29455 1 0.00% 83.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29711 1 0.00% 83.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29952-29967 3 0.01% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30400-30415 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30479 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30735 1 0.00% 83.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31247 2 0.01% 83.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31759 3 0.01% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32000-32015 1 0.00% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32271 1 0.00% 83.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32527 1 0.00% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32640-32655 1 0.00% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32783 2 0.01% 83.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32896-32911 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33039 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33295 1 0.00% 83.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33536-33551 9 0.03% 83.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33600-33615 9 0.03% 83.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33664-33679 3 0.01% 83.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33728-33743 3 0.01% 83.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33807 23 0.07% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36879 1 0.00% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37568-37583 1 0.00% 83.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37903 2 0.01% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39232-39247 1 0.00% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39695 1 0.00% 83.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42752-42767 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43535 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44239 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44559 1 0.00% 83.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45583 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46400-46415 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46863 1 0.00% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47119 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47247 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47311 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47424-47439 1 0.00% 83.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47887 1 0.00% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48143 2 0.01% 83.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48320-48335 2 0.01% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49039 1 0.00% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49600-49615 1 0.00% 83.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49920-49935 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::52864-52879 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::53504-53519 1 0.00% 83.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54272-54287 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54464-54479 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::54784-54799 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::58368-58383 1 0.00% 83.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60160-60175 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60672-60687 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::60928-60943 1 0.00% 83.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::64512-64527 1 0.00% 83.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65024-65039 10 0.03% 83.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65408-65423 6 0.02% 83.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::65536-65551 5666 16.07% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::68672-68687 1 0.00% 99.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::69120-69135 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::72128-72143 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73088-73103 1 0.00% 99.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73920-73935 20 0.06% 99.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::73984-73999 91 0.26% 99.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74048-74063 61 0.17% 99.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::74112-74127 4 0.01% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 35262 # Bytes accessed per row activation +system.physmem.totQLat 121597245250 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 160506894000 # Sum of mem lat for all requests +system.physmem.totBusLat 31269035000 # Total cycles spent in databus access +system.physmem.totBankLat 7640613750 # Total cycles spent in bank access +system.physmem.avgQLat 19443.72 # Average queueing delay per request +system.physmem.avgBankLat 1221.75 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 35416.11 # Average memory access latency -system.physmem.avgRdBW 359.52 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 47.31 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 53.13 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.54 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 25665.47 # Average memory access latency +system.physmem.avgRdBW 362.77 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 47.74 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 53.62 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 3.18 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.20 # Average read queue length over time -system.physmem.avgWrQLen 11.52 # Average write queue length over time -system.physmem.readRowHits 6237911 # Number of row buffer hits during reads -system.physmem.writeRowHits 804550 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 97.70 # Row buffer hit rate for writes -system.physmem.avgGap 157316.33 # Average gap between requests +system.physmem.busUtil 3.21 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.15 # Average read queue length over time +system.physmem.avgWrQLen 12.74 # Average write queue length over time +system.physmem.readRowHits 6235456 # Number of row buffer hits during reads +system.physmem.writeRowHits 98940 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 12.01 # Row buffer hit rate for writes +system.physmem.avgGap 155904.23 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -525,307 +476,309 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 345 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 402 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 345 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 402 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 57 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 345 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 402 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 61845817 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 7306747 # Transaction distribution -system.membus.trans_dist::ReadResp 7306747 # Transaction distribution -system.membus.trans_dist::WriteReq 767893 # Transaction distribution -system.membus.trans_dist::WriteResp 767893 # Transaction distribution -system.membus.trans_dist::Writeback 66623 # Transaction distribution -system.membus.trans_dist::UpgradeReq 33809 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 17757 # Transaction distribution -system.membus.trans_dist::UpgradeResp 12548 # Transaction distribution -system.membus.trans_dist::ReadExReq 138043 # Transaction distribution -system.membus.trans_dist::ReadExResp 137663 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 62410733 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 7306749 # Transaction distribution +system.membus.trans_dist::ReadResp 7306749 # Transaction distribution +system.membus.trans_dist::WriteReq 767894 # Transaction distribution +system.membus.trans_dist::WriteResp 767894 # Transaction distribution +system.membus.trans_dist::Writeback 66675 # Transaction distribution +system.membus.trans_dist::UpgradeReq 33869 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 17715 # Transaction distribution +system.membus.trans_dist::UpgradeResp 12574 # Transaction distribution +system.membus.trans_dist::ReadExReq 138085 # Transaction distribution +system.membus.trans_dist::ReadExResp 137703 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 2382522 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1970999 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 11642 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 4366027 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.local_cpu_timer.pio 842 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1971187 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 4366211 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 12189696 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 12189696 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.bridge.slave 2382510 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.nvmem.port 14 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.physmem.port 14160695 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.gic.pio 11650 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.a9scu.pio 4 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::system.realview.local_cpu_timer.pio 850 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 16555723 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 16555907 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 2389789 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17723636 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 23284 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 20138869 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.local_cpu_timer.pio 1684 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 17729844 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 20145057 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 48758784 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.bridge.slave 2389777 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.nvmem.port 448 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.physmem.port 66482420 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.gic.pio 23300 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.a9scu.pio 8 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::system.realview.local_cpu_timer.pio 1700 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 68897653 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 68897653 # Total data (bytes) +system.membus.tot_pkt_size::total 68903841 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 68903841 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1475761000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1475612500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.membus.reqLayer1.occupancy 7500 # Layer occupancy (ticks) +system.membus.reqLayer1.occupancy 7000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 8620588249 # Layer occupancy (ticks) -system.membus.reqLayer2.utilization 0.8 # Layer utilization (%) -system.membus.reqLayer3.occupancy 9828000 # Layer occupancy (ticks) -system.membus.reqLayer3.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 9865000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer4.occupancy 3000 # Layer occupancy (ticks) +system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) +system.membus.reqLayer5.occupancy 750000 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 756000 # Layer occupancy (ticks) -system.membus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.membus.respLayer1.occupancy 4823074562 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 8618805999 # Layer occupancy (ticks) +system.membus.reqLayer6.utilization 0.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 4854602214 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.4 # Layer utilization (%) -system.membus.respLayer2.occupancy 13762899732 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 13760099489 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.2 # Layer utilization (%) -system.l2c.tags.replacements 72713 # number of replacements -system.l2c.tags.tagsinuse 53848.744123 # Cycle average of tags in use -system.l2c.tags.total_refs 1839089 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 137893 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.337073 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 39490.919089 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 5.921030 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000842 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4011.444595 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 2831.104153 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.348710 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 3706.565293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 3793.440412 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.602584 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000090 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.061210 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.043199 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000143 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.056558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.057883 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.821667 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 22072 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4261 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386985 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166655 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 31010 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5009 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 589730 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 198052 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1403774 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 581377 # number of Writeback hits -system.l2c.Writeback_hits::total 581377 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1341 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 735 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2076 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 150 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 360 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48293 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58659 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106952 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 22072 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4261 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386985 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214948 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 31010 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5009 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 589730 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256711 # number of demand (read+write) hits -system.l2c.demand_hits::total 1510726 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 22072 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4261 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386985 # number of overall hits -system.l2c.overall_hits::cpu0.data 214948 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 31010 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5009 # number of overall hits -system.l2c.overall_hits::cpu1.inst 589730 # number of overall hits -system.l2c.overall_hits::cpu1.data 256711 # number of overall hits -system.l2c.overall_hits::total 1510726 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 16 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6279 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6380 # number of ReadReq misses +system.l2c.tags.replacements 72758 # number of replacements +system.l2c.tags.tagsinuse 53808.125296 # Cycle average of tags in use +system.l2c.tags.total_refs 1836602 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 137939 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.314596 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 39514.415699 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 4.446892 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.itb.walker 0.257540 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 4002.916228 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 2827.365052 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 9.413975 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.itb.walker 0.918976 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 3679.171285 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 3769.219649 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.602942 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000068 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.itb.walker 0.000004 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.061080 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.043142 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000144 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.itb.walker 0.000014 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.056140 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.057514 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.821047 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21860 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4237 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 386435 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166509 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 4932 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 588366 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198248 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1401466 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581263 # number of Writeback hits +system.l2c.Writeback_hits::total 581263 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1335 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 743 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2078 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 202 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 141 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 343 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48314 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58639 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106953 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21860 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 4237 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 386435 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214823 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 30879 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 4932 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 588366 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256887 # number of demand (read+write) hits +system.l2c.demand_hits::total 1508419 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 21860 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 4237 # number of overall hits +system.l2c.overall_hits::cpu0.inst 386435 # number of overall hits +system.l2c.overall_hits::cpu0.data 214823 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 30879 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 4932 # number of overall hits +system.l2c.overall_hits::cpu1.inst 588366 # number of overall hits +system.l2c.overall_hits::cpu1.data 256887 # number of overall hits +system.l2c.overall_hits::total 1508419 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 12 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6295 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 14 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6315 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6308 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.data 6244 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25250 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5158 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 3783 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8941 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 636 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 418 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1054 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63263 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76953 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140216 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 16 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6279 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69643 # number of demand (read+write) misses +system.l2c.ReadReq_misses::total 25258 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5140 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3782 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8922 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 633 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 424 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63292 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 77006 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140298 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 12 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6295 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69673 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 14 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6315 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83197 # number of demand (read+write) misses -system.l2c.demand_misses::total 165466 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 16 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6279 # number of overall misses -system.l2c.overall_misses::cpu0.data 69643 # number of overall misses +system.l2c.demand_misses::cpu1.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6308 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83250 # number of demand (read+write) misses +system.l2c.demand_misses::total 165556 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 12 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6295 # number of overall misses +system.l2c.overall_misses::cpu0.data 69673 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 14 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6315 # number of overall misses -system.l2c.overall_misses::cpu1.data 83197 # number of overall misses -system.l2c.overall_misses::total 165466 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 1558000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 130250 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 460466000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 469540999 # 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number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 16503554515 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 17509941014 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 6406999 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13406106487 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2451249 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 180075874176 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 193540119667 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000724 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000469 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015959 # 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average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 57958.733083 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 84656.250000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 52875 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60670.132250 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55256.139729 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 103785.714286 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64637.823054 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59496.725662 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 57958.733083 # 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mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.793822 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.835801 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.811091 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.758084 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.750442 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.755000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567102 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.567702 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.567431 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.244763 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000453 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.itb.walker 0.000203 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010596 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.098854 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000549 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000708 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016019 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.244763 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63333.601415 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 62313.837775 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10026.084436 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10043.826811 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10033.605358 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.261792 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10017.551561 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 54626.471718 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59325.717217 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 57205.767923 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 67125 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 60666.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 60320.259100 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 55210.093446 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 76732.142857 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.itb.walker 76250 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 64543.088399 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 59625.117816 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 57983.064782 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -1016,64 +981,64 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 135543504 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 2708876 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2708875 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 767893 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 767893 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 581377 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 33332 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 18117 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 51449 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 258856 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 258856 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side 787342 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side 1073883 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma 13468 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma 55968 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.icache.mem_side 1192763 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side 4801194 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma 14594 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma 72477 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count 8011689 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side 25176640 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side 34854805 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma 17052 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma 88352 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side 38149824 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side 47763808 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma 20036 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma 124096 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size 146194613 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 146194613 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 4803948 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 4894718895 # Layer occupancy (ticks) +system.toL2Bus.throughput 136659470 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 2706207 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2706206 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 767894 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 767894 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 581263 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 33352 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 18058 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 51410 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 258939 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 258939 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 786305 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 1073575 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 13268 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 55413 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 1190023 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 4801593 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.itb.walker.dma::system.l2c.cpu_side 14394 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 72130 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8006701 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 25142464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 34843867 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 16960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 87488 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 38062080 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 47776006 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.itb.walker.dma::system.l2c.cpu_side 19732 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu1.dtb.walker.dma::system.l2c.cpu_side 123572 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 146072169 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 146072169 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 4805124 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 4892877936 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.4 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1774755611 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1772488367 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1516721983 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1516304011 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 9224710 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 9043467 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 34035182 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 33687702 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer4.occupancy 2687171756 # Layer occupancy (ticks) +system.toL2Bus.respLayer4.occupancy 2681029210 # Layer occupancy (ticks) system.toL2Bus.respLayer4.utilization 0.2 # Layer utilization (%) -system.toL2Bus.respLayer5.occupancy 3246383092 # Layer occupancy (ticks) +system.toL2Bus.respLayer5.occupancy 3243394678 # Layer occupancy (ticks) system.toL2Bus.respLayer5.utilization 0.3 # Layer utilization (%) -system.toL2Bus.respLayer6.occupancy 9605952 # Layer occupancy (ticks) +system.toL2Bus.respLayer6.occupancy 9483701 # Layer occupancy (ticks) system.toL2Bus.respLayer6.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer7.occupancy 41732428 # Layer occupancy (ticks) +system.toL2Bus.respLayer7.occupancy 41522672 # Layer occupancy (ticks) system.toL2Bus.respLayer7.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 45913386 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 7278157 # Transaction distribution -system.iobus.trans_dist::ReadResp 7278157 # Transaction distribution -system.iobus.trans_dist::WriteReq 7946 # Transaction distribution -system.iobus.trans_dist::WriteResp 7946 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) +system.iobus.throughput 46328621 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 7278159 # Transaction distribution +system.iobus.trans_dist::ReadResp 7278159 # Transaction distribution +system.iobus.trans_dist::WriteReq 7950 # Transaction distribution +system.iobus.trans_dist::WriteResp 7950 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 30460 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 8026 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 724 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) @@ -1093,38 +1058,14 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 2382510 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 2382522 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.realview.clcd.dma::total 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart.pio 30448 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.realview_io.pio 8024 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.timer1.pio 726 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.kmi1.pio 494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::system.iocache.cpu_side 12189696 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 14572206 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count::total 14572218 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 40178 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 16052 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 1448 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) @@ -1144,42 +1085,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 2389777 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 2389789 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.realview.clcd.dma::total 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart.pio 40166 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.realview_io.pio 16048 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.timer1.pio 1452 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.kmi1.pio 271 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::system.iocache.cpu_side 48758784 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 51148561 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 51148561 # Total data (bytes) -system.iobus.reqLayer0.occupancy 21350000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size::total 51148573 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 51148573 # Total data (bytes) +system.iobus.reqLayer0.occupancy 21360000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 4018000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 4019000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 34000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 369000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 368000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1220,43 +1137,43 @@ system.iobus.reqLayer22.utilization 0.0 # La system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer25.occupancy 6094848000 # Layer occupancy (ticks) -system.iobus.reqLayer25.utilization 0.5 # Layer utilization (%) -system.iobus.respLayer0.occupancy 2374564000 # Layer occupancy (ticks) +system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) +system.iobus.respLayer0.occupancy 2374572000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.2 # Layer utilization (%) -system.iobus.respLayer1.occupancy 16693526268 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 16699589511 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) -system.cpu0.branchPred.lookups 6007013 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4581243 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296095 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3784394 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2916091 # Number of BTB hits +system.cpu0.branchPred.lookups 6002321 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4576737 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 295742 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3785758 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2914394 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.055692 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 673819 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28621 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 76.983104 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673290 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28745 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8911671 # DTB read hits -system.cpu0.dtb.read_misses 28579 # DTB read misses -system.cpu0.dtb.write_hits 5140325 # DTB write hits -system.cpu0.dtb.write_misses 5457 # DTB write misses +system.cpu0.dtb.read_hits 8907919 # DTB read hits +system.cpu0.dtb.read_misses 28331 # DTB read misses +system.cpu0.dtb.write_hits 5140728 # DTB write hits +system.cpu0.dtb.write_misses 5464 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 1825 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 935 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1828 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 958 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 555 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8940250 # DTB read accesses -system.cpu0.dtb.write_accesses 5145782 # DTB write accesses +system.cpu0.dtb.perms_faults 551 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8936250 # DTB read accesses +system.cpu0.dtb.write_accesses 5146192 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051996 # DTB hits -system.cpu0.dtb.misses 34036 # DTB misses -system.cpu0.dtb.accesses 14086032 # DTB accesses -system.cpu0.itb.inst_hits 4224524 # ITB inst hits -system.cpu0.itb.inst_misses 5106 # ITB inst misses +system.cpu0.dtb.hits 14048647 # DTB hits +system.cpu0.dtb.misses 33795 # DTB misses +system.cpu0.dtb.accesses 14082442 # DTB accesses +system.cpu0.itb.inst_hits 4222709 # ITB inst hits +system.cpu0.itb.inst_misses 5005 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1265,534 +1182,530 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1346 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1348 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1478 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1494 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4229630 # ITB inst accesses -system.cpu0.itb.hits 4224524 # DTB hits -system.cpu0.itb.misses 5106 # DTB misses -system.cpu0.itb.accesses 4229630 # DTB accesses -system.cpu0.numCycles 69191123 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4227714 # ITB inst accesses +system.cpu0.itb.hits 4222709 # DTB hits +system.cpu0.itb.misses 5005 # DTB misses +system.cpu0.itb.accesses 4227714 # DTB accesses +system.cpu0.numCycles 69175889 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11726999 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32040106 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6007013 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3589910 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7522223 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1454890 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 60839 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 19594371 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4906 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 47034 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 1322790 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 216 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4222942 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157135 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2060 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41323427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.001891 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.382270 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11717201 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32026454 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6002321 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3587684 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7519324 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1452827 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60860 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 19607589 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5035 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47006 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 1325879 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 324 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4221110 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157905 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2000 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41325646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.001484 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.381957 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33808589 81.81% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 565594 1.37% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 817189 1.98% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676917 1.64% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774557 1.87% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 561158 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668023 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352527 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3098873 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33813760 81.82% 81.82% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 565868 1.37% 83.19% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 817164 1.98% 85.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676151 1.64% 86.81% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772838 1.87% 88.68% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 560246 1.36% 90.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 669817 1.62% 91.65% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351583 0.85% 92.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3098219 7.50% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41323427 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.086818 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.463067 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12228313 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20776644 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6830919 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 507068 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 980483 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935966 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64632 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40044073 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213118 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 980483 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12794933 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5974902 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12785484 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6719608 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2068017 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38935181 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 1840 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 426390 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1152446 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 100 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39283995 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175854037 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175819876 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34161 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30939461 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8344533 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411347 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370357 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5351975 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7655764 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5689444 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1124222 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1281984 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36848399 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895286 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37254672 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 81509 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6299557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13203578 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256355 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41323427 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901539 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.514633 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41325646 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.086769 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.462971 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12221128 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20791110 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6824454 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 510238 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 978716 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 935346 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64732 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40027040 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 212951 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 978716 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12790081 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5972534 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12789547 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6714080 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2080688 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38920228 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1875 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 436221 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1152507 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 84 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39264921 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175790758 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175756522 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34236 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30938700 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8326220 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 411215 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370279 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5370420 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7651291 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5689186 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1120456 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1254854 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36835170 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895288 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37251130 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 81272 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6287660 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13163035 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 256365 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41325646 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.901405 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.514906 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26248165 63.52% 63.52% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5684023 13.75% 77.27% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3115322 7.54% 84.81% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2467752 5.97% 90.78% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2139591 5.18% 95.96% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 926164 2.24% 98.20% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 502996 1.22% 99.42% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 185723 0.45% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 53691 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 26248472 63.52% 63.52% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5690851 13.77% 77.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3114453 7.54% 84.82% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2470786 5.98% 90.80% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2128163 5.15% 95.95% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 926108 2.24% 98.19% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 506651 1.23% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185379 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 54783 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41323427 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41325646 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27493 2.57% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 452 0.04% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.61% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 842638 78.71% 81.32% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 200034 18.68% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 27685 2.59% 2.59% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 452 0.04% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 842164 78.64% 81.27% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 200566 18.73% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22336809 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46914 0.13% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 6 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 3 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.22% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.22% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22335497 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46969 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 7 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 704 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9369783 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5448235 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9366005 25.14% 85.37% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5449722 14.63% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37254672 # Type of FU issued -system.cpu0.iq.rate 0.538431 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070617 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028738 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 117010237 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44051144 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34347967 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8478 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4654 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3872 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38268613 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4462 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307627 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37251130 # Type of FU issued +system.cpu0.iq.rate 0.538499 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070867 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028747 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 117005145 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 44025943 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34344840 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8484 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4662 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3874 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38265319 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4464 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 307168 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1377452 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2519 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13094 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537577 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1372814 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2493 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13018 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 537400 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192819 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5737 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192818 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5781 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 980483 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4321779 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 103852 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37861161 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 83824 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7655764 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5689444 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571291 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 39684 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 13815 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13094 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150380 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118124 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 268504 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36875907 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9227090 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 378765 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 978716 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4319425 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 103424 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37848942 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 83231 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7651291 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5689186 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571145 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39872 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 13404 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13018 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 150227 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 117595 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 267822 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36871306 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9223534 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 379824 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 117476 # number of nop insts executed -system.cpu0.iew.exec_refs 14627584 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4856181 # Number of branches executed -system.cpu0.iew.exec_stores 5400494 # Number of stores executed -system.cpu0.iew.exec_rate 0.532957 # Inst execution rate -system.cpu0.iew.wb_sent 36680744 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34351839 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18317228 # num instructions producing a value -system.cpu0.iew.wb_consumers 35218038 # num instructions consuming a value +system.cpu0.iew.exec_nop 118484 # number of nop insts executed +system.cpu0.iew.exec_refs 14624342 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4855002 # Number of branches executed +system.cpu0.iew.exec_stores 5400808 # Number of stores executed +system.cpu0.iew.exec_rate 0.533008 # Inst execution rate +system.cpu0.iew.wb_sent 36677174 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34348714 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18316479 # num instructions producing a value +system.cpu0.iew.wb_consumers 35213732 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.496478 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.520109 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.496542 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.520152 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6105741 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638931 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232529 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40342944 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775737 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.743782 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6093987 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638923 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 232030 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40346930 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.775643 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740681 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28719843 71.19% 71.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5706970 14.15% 85.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1863125 4.62% 89.95% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 981446 2.43% 92.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 776304 1.92% 94.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 515472 1.28% 95.59% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 394004 0.98% 96.57% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 214891 0.53% 97.10% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1170889 2.90% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28704762 71.14% 71.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5702920 14.13% 85.28% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1886389 4.68% 89.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 981050 2.43% 92.39% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 790069 1.96% 94.34% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 509429 1.26% 95.61% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 395100 0.98% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 219754 0.54% 97.13% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1157457 2.87% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40342944 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23687602 # Number of instructions committed -system.cpu0.commit.committedOps 31295507 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40346930 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23686340 # Number of instructions committed +system.cpu0.commit.committedOps 31294803 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11430179 # Number of memory references committed -system.cpu0.commit.loads 6278312 # Number of loads committed -system.cpu0.commit.membars 229695 # Number of memory barriers committed -system.cpu0.commit.branches 4246577 # Number of branches committed +system.cpu0.commit.refs 11430263 # Number of memory references committed +system.cpu0.commit.loads 6278477 # Number of loads committed +system.cpu0.commit.membars 229716 # Number of memory barriers committed +system.cpu0.commit.branches 4246456 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27650890 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489495 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1170889 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27650320 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489514 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1157457 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75722045 # The number of ROB reads -system.cpu0.rob.rob_writes 75784919 # The number of ROB writes -system.cpu0.timesIdled 368023 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27867696 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2158812857 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23606860 # Number of Instructions Simulated -system.cpu0.committedOps 31214765 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23606860 # Number of Instructions Simulated -system.cpu0.cpi 2.930975 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.930975 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.341183 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.341183 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171887932 # number of integer regfile reads -system.cpu0.int_regfile_writes 34101589 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3230 # number of floating regfile reads -system.cpu0.fp_regfile_writes 874 # number of floating regfile writes -system.cpu0.misc_regfile_reads 12983242 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451267 # number of misc regfile writes -system.cpu0.icache.tags.replacements 393301 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.011114 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 3798020 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 393813 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 9.644222 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 6979217250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.011114 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.998069 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3798020 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3798020 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3798020 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3798020 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3798020 # number of overall hits -system.cpu0.icache.overall_hits::total 3798020 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 424793 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 424793 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 424793 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 424793 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 424793 # number of overall misses -system.cpu0.icache.overall_misses::total 424793 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5908836480 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5908836480 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5908836480 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5908836480 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5908836480 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5908836480 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4222813 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4222813 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4222813 # 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Number of Instructions Simulated +system.cpu0.cpi 2.930487 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.930487 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.341240 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.341240 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171860544 # number of integer regfile reads +system.cpu0.int_regfile_writes 34096305 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3262 # number of floating regfile reads +system.cpu0.fp_regfile_writes 892 # number of floating regfile writes +system.cpu0.misc_regfile_reads 13010065 # number of misc regfile reads +system.cpu0.misc_regfile_writes 451140 # number of misc regfile writes +system.cpu0.icache.tags.replacements 392795 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.002835 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 3796668 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 393307 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 9.653192 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 6982777250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 511.002835 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.998052 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.998052 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3796668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3796668 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3796668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3796668 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3796668 # number of overall hits +system.cpu0.icache.overall_hits::total 3796668 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 424314 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 424314 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4220982 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4220982 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4220982 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4220982 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100525 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100525 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100525 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100525 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100525 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100525 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13909.247623 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13909.247623 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13909.247623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13909.247623 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13909.247623 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3930 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 182 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 194 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.620879 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 20.257732 # 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mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093185 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12213.247010 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12213.247010 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12213.247010 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # 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miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181017 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.181017 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14112.470701 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 14112.470701 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48800.330267 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 48800.330267 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10077.307868 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10077.307868 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6151.624635 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6151.624635 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 41921.363163 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41921.363163 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 41921.363163 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9474 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 7234 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 614 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 133 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.429967 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 54.390977 # average number of cycles each access was blocked +system.cpu0.dcache.tags.replacements 276222 # number of replacements +system.cpu0.dcache.tags.tagsinuse 460.530312 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 9262144 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 276734 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 33.469483 # Average number of references to valid blocks. +system.cpu0.dcache.tags.warmup_cycle 42960250 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.tags.occ_blocks::cpu0.data 460.530312 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.899473 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.899473 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5781621 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5781621 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3159389 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3159389 # 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number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8742 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7480 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7480 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1976616 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1976616 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1976616 # number of overall misses +system.cpu0.dcache.overall_misses::total 1976616 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5523901183 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5523901183 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 77315448541 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 77315448541 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88125732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88125732 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 45924629 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 45924629 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 82839349724 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 82839349724 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 82839349724 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 82839349724 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6173411 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6173411 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744215 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147889 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144557 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10917626 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10917626 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10917626 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10917626 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063464 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.334054 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.334054 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059112 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059112 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051744 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051744 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.181048 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.181048 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.181048 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.181048 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 14099.137760 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 14099.137760 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 48784.818359 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 48784.818359 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10080.728895 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10080.728895 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6139.656283 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6139.656283 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 41909.682874 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 41909.682874 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 41909.682874 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 11704 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 6407 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 613 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 131 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 19.092985 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 48.908397 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256588 # number of writebacks -system.cpu0.dcache.writebacks::total 256588 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203202 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 203202 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454368 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1454368 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 460 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657570 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1657570 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657570 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1657570 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188820 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188820 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130419 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130419 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8297 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8297 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7522 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7522 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 319239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 319239 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 319239 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 319239 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2408343372 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2408343372 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110867707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110867707 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66642015 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66642015 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31254873 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31254873 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 3000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7519211079 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7519211079 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7519211079 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7519211079 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504631783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504631783 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180253969 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180253969 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14684885752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14684885752 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030571 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030571 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027491 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056028 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.052006 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.052006 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029233 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029233 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029233 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.704862 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.704862 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39188.060842 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39188.060842 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8032.061589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8032.061589 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4155.128024 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4155.128024 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23553.547903 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23553.547903 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256512 # number of writebacks +system.cpu0.dcache.writebacks::total 256512 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 203095 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 203095 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1454344 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1454344 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 453 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 453 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1657439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1657439 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1657439 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1657439 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188695 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188695 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130482 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130482 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8289 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7480 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7480 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319177 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319177 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319177 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319177 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2406687867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2406687867 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5110325446 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5110325446 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66640768 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66640768 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 30961371 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 30961371 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7517013313 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7517013313 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7517013313 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7517013313 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13504611525 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13504611525 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1131834379 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1131834379 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14636445904 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14636445904 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030566 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027503 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056049 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051744 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051744 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029235 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029235 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029235 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12754.380704 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12754.380704 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 39164.984028 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 39164.984028 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8039.663168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8039.663168 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4139.220722 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4139.220722 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23551.237442 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23551.237442 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1800,38 +1713,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9066954 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7451944 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 406719 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6049384 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5236824 # Number of BTB hits +system.cpu1.branchPred.lookups 8782132 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7168426 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 407819 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 5819499 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 4955017 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.567889 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772531 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 42321 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 85.145079 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 773793 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 42171 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42909677 # DTB read hits -system.cpu1.dtb.read_misses 36560 # DTB read misses -system.cpu1.dtb.write_hits 6823585 # DTB write hits -system.cpu1.dtb.write_misses 10691 # DTB write misses +system.cpu1.dtb.read_hits 42691295 # DTB read hits +system.cpu1.dtb.read_misses 36496 # DTB read misses +system.cpu1.dtb.write_hits 6824033 # DTB write hits +system.cpu1.dtb.write_misses 10597 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2017 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2608 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 306 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2020 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2612 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 305 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 688 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42946237 # DTB read accesses -system.cpu1.dtb.write_accesses 6834276 # DTB write accesses +system.cpu1.dtb.perms_faults 657 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42727791 # DTB read accesses +system.cpu1.dtb.write_accesses 6834630 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49733262 # DTB hits -system.cpu1.dtb.misses 47251 # DTB misses -system.cpu1.dtb.accesses 49780513 # DTB accesses -system.cpu1.itb.inst_hits 8323198 # ITB inst hits -system.cpu1.itb.inst_misses 5400 # ITB inst misses +system.cpu1.dtb.hits 49515328 # DTB hits +system.cpu1.dtb.misses 47093 # DTB misses +system.cpu1.dtb.accesses 49562421 # DTB accesses +system.cpu1.itb.inst_hits 7577708 # ITB inst hits +system.cpu1.itb.inst_misses 5297 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1844,109 +1757,109 @@ system.cpu1.itb.flush_entries 1529 # Nu system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1523 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1545 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8328598 # ITB inst accesses -system.cpu1.itb.hits 8323198 # DTB hits -system.cpu1.itb.misses 5400 # DTB misses -system.cpu1.itb.accesses 8328598 # DTB accesses -system.cpu1.numCycles 410695591 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 7583005 # ITB inst accesses +system.cpu1.itb.hits 7577708 # DTB hits +system.cpu1.itb.misses 5297 # DTB misses +system.cpu1.itb.accesses 7583005 # DTB accesses +system.cpu1.numCycles 408491180 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19628666 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 66104666 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9066954 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6009355 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14131573 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3952223 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 62853 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77248707 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4835 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 42228 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 1436171 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 176 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8321388 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 704092 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2736 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 115246116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.694374 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.038205 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 18854224 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 60287918 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 8782132 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 5728810 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 13124144 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3307681 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 62009 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77240238 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4754 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42673 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 1437796 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 160 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 7575877 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 546214 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2648 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 113028448 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.652235 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 1.978835 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 101121884 87.74% 87.74% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 796637 0.69% 88.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 937162 0.81% 89.25% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1885853 1.64% 90.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1499695 1.30% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 570142 0.49% 92.68% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2110638 1.83% 94.51% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410756 0.36% 94.87% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5913349 5.13% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 99911588 88.40% 88.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796149 0.70% 89.10% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 938672 0.83% 89.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1688468 1.49% 91.42% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1396344 1.24% 92.66% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 570472 0.50% 93.16% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1929580 1.71% 94.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410359 0.36% 95.23% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5386816 4.77% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 115246116 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022077 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.160958 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21155925 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 78195753 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12775663 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 524358 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2594417 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1105836 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98153 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 75067660 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 326745 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2594417 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22501379 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33242741 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40762154 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11860446 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4284979 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69913296 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 18816 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 670004 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3042907 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 379 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73978163 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 321899381 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 321840484 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58897 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49060581 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24917582 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444517 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387690 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7870912 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13163327 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8127092 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1028302 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1543452 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63442447 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157372 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89134089 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 93553 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16181139 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45168283 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 276533 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 115246116 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.773424 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.513958 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 113028448 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.021499 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.147587 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 20182430 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78186513 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 11968696 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524734 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2166075 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1104186 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 97997 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 69821372 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 325725 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2166075 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 21372370 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 33233612 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40763249 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11209012 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4284130 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 65907040 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18855 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668466 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3042854 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 1130 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 69218982 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 302521919 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 302462653 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59266 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49058929 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 20160053 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 444772 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 387840 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7873214 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12591353 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 7935523 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036537 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1457992 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 60681374 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1157953 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 87712578 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 93570 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 13421216 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 35924412 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 277156 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 113028448 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.776022 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519284 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 84850695 73.63% 73.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8420843 7.31% 80.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4255514 3.69% 84.63% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3817238 3.31% 87.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10566074 9.17% 97.11% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1932638 1.68% 98.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1074262 0.93% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 253370 0.22% 99.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75482 0.07% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83202776 73.61% 73.61% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8275815 7.32% 80.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4119768 3.64% 84.58% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3698740 3.27% 87.85% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10372542 9.18% 97.03% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1968067 1.74% 98.77% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1039899 0.92% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 275618 0.24% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 75223 0.07% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 115246116 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 113028448 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 32069 0.41% 0.41% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 32070 0.41% 0.41% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 996 0.01% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.42% # attempts to use FU when none available @@ -1975,395 +1888,395 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.42% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.42% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.42% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7550960 95.79% 96.21% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 298953 3.79% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7550021 95.87% 96.29% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 292311 3.71% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 314062 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37650996 42.24% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59191 0.07% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 11 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.66% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43937068 49.29% 91.95% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7171235 8.05% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 314062 0.36% 0.36% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 36603154 41.73% 42.09% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59244 0.07% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1508 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.16% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43563118 49.67% 91.82% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7171472 8.18% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89134089 # Type of FU issued -system.cpu1.iq.rate 0.217032 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7882978 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088440 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 301522554 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80789150 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53744584 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 15343 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8026 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6801 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96694852 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 8153 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 340284 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 87712578 # Type of FU issued +system.cpu1.iq.rate 0.214723 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7875398 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.089786 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 296453915 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 75268930 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53141218 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 15550 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8086 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6819 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 95265602 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 8312 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 341261 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3407112 # Number of loads squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2835568 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3737 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 16742 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1286559 # Number of stores squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17004 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1095143 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31912923 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 915604 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31913350 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 674872 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2594417 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25467221 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 361914 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64703269 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112618 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13163327 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8127092 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869000 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 64609 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 6290 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 16742 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 200151 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 154994 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 355145 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86813167 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43279828 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2320922 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2166075 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 25455774 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 362563 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 61943028 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 112233 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12591353 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 7935523 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 869270 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64753 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 6199 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17004 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 201423 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 154723 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 356146 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 85989556 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43061283 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1723022 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103450 # number of nop insts executed -system.cpu1.iew.exec_refs 50389574 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6997831 # Number of branches executed -system.cpu1.iew.exec_stores 7109746 # Number of stores executed -system.cpu1.iew.exec_rate 0.211381 # Inst execution rate -system.cpu1.iew.wb_sent 85834090 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53751385 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29958578 # num instructions producing a value -system.cpu1.iew.wb_consumers 53322000 # num instructions consuming a value +system.cpu1.iew.exec_nop 103701 # number of nop insts executed +system.cpu1.iew.exec_refs 50171461 # number of memory reference insts executed +system.cpu1.iew.exec_branches 6912906 # Number of branches executed +system.cpu1.iew.exec_stores 7110178 # Number of stores executed +system.cpu1.iew.exec_rate 0.210505 # Inst execution rate +system.cpu1.iew.wb_sent 85230378 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53148037 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29710424 # num instructions producing a value +system.cpu1.iew.wb_consumers 52969976 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.130879 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.561843 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.130108 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560892 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 16054832 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880839 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 310229 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 112651699 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.427506 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.393608 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 13294883 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880797 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 311444 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 110862373 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.434393 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.404754 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 95929787 85.16% 85.16% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8195439 7.28% 92.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2121242 1.88% 94.31% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1255081 1.11% 95.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1260461 1.12% 96.55% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 575308 0.51% 97.06% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 943355 0.84% 97.90% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 590559 0.52% 98.42% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1780467 1.58% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94147475 84.92% 84.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8220753 7.42% 92.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2089215 1.88% 94.22% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1249683 1.13% 95.35% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1247924 1.13% 96.48% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 575753 0.52% 96.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 991767 0.89% 97.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 529898 0.48% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1809905 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 112651699 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38067147 # Number of instructions committed -system.cpu1.commit.committedOps 48159329 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 110862373 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38066252 # Number of instructions committed +system.cpu1.commit.committedOps 48157821 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16596748 # Number of memory references committed -system.cpu1.commit.loads 9756215 # Number of loads committed -system.cpu1.commit.membars 190139 # Number of memory barriers committed -system.cpu1.commit.branches 5967970 # Number of branches committed +system.cpu1.commit.refs 16596165 # Number of memory references committed +system.cpu1.commit.loads 9755785 # Number of loads committed +system.cpu1.commit.membars 190126 # Number of memory barriers committed +system.cpu1.commit.branches 5967905 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42694003 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534679 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1780467 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42692526 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534650 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1809905 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 174041277 # The number of ROB reads -system.cpu1.rob.rob_writes 131120872 # The number of ROB writes -system.cpu1.timesIdled 1414866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 295449475 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1816711228 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37997508 # Number of Instructions Simulated -system.cpu1.committedOps 48089690 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37997508 # Number of Instructions Simulated -system.cpu1.cpi 10.808488 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.808488 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092520 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092520 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 388394171 # number of integer regfile reads -system.cpu1.int_regfile_writes 56329363 # number of integer regfile writes -system.cpu1.fp_regfile_reads 5049 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2330 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18495746 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405487 # number of misc regfile writes -system.cpu1.icache.tags.replacements 596092 # number of replacements -system.cpu1.icache.tags.tagsinuse 480.837460 # Cycle average of tags in use -system.cpu1.icache.tags.total_refs 7679654 # Total number of references to valid blocks. -system.cpu1.icache.tags.sampled_refs 596604 # Sample count of references to valid blocks. -system.cpu1.icache.tags.avg_refs 12.872280 # Average number of references to valid blocks. -system.cpu1.icache.tags.warmup_cycle 74828235500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.837460 # Average occupied blocks per requestor -system.cpu1.icache.tags.occ_percent::cpu1.inst 0.939136 # Average percentage of cache occupancy -system.cpu1.icache.tags.occ_percent::total 0.939136 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7679654 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7679654 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7679654 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7679654 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7679654 # number of overall hits -system.cpu1.icache.overall_hits::total 7679654 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641686 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641686 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641686 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641686 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641686 # number of overall misses -system.cpu1.icache.overall_misses::total 641686 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8725652874 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8725652874 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8725652874 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8725652874 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8725652874 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8725652874 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8321340 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8321340 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8321340 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8321340 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8321340 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8321340 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.077113 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.077113 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.077113 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.077113 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.077113 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.077113 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13598.010357 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13598.010357 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13598.010357 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13598.010357 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13598.010357 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 3474 # number of cycles access was blocked +system.cpu1.rob.rob_reads 169461098 # The number of ROB reads +system.cpu1.rob.rob_writes 125154390 # The number of ROB writes +system.cpu1.timesIdled 1414583 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 295462732 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1798949280 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37996613 # Number of Instructions Simulated +system.cpu1.committedOps 48088182 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37996613 # Number of Instructions Simulated +system.cpu1.cpi 10.750726 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.750726 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.093017 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.093017 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 384900722 # number of integer regfile reads +system.cpu1.int_regfile_writes 55276259 # number of integer regfile writes +system.cpu1.fp_regfile_reads 5045 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2312 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18451458 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405460 # number of misc regfile writes +system.cpu1.icache.tags.replacements 594712 # number of replacements +system.cpu1.icache.tags.tagsinuse 480.460982 # Cycle average of tags in use +system.cpu1.icache.tags.total_refs 6935744 # Total number of references to valid blocks. +system.cpu1.icache.tags.sampled_refs 595224 # Sample count of references to valid blocks. +system.cpu1.icache.tags.avg_refs 11.652326 # Average number of references to valid blocks. +system.cpu1.icache.tags.warmup_cycle 74833132000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.tags.occ_blocks::cpu1.inst 480.460982 # Average occupied blocks per requestor +system.cpu1.icache.tags.occ_percent::cpu1.inst 0.938400 # Average percentage of cache occupancy +system.cpu1.icache.tags.occ_percent::total 0.938400 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 6935744 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 6935744 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 6935744 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 6935744 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 6935744 # number of overall hits +system.cpu1.icache.overall_hits::total 6935744 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 640085 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 640085 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 640085 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 640085 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 640085 # number of overall misses +system.cpu1.icache.overall_misses::total 640085 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8700934064 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8700934064 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8700934064 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8700934064 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8700934064 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8700934064 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 7575829 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 7575829 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 7575829 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 7575829 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 7575829 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 7575829 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.084490 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.084490 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.084490 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.084490 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.084490 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.084490 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13593.404101 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13593.404101 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13593.404101 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13593.404101 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13593.404101 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2623 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 210 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 183 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 16.542857 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.333333 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 45060 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 45060 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 45060 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 45060 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 45060 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 45060 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 596626 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 596626 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 596626 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 596626 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 596626 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 596626 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7121155232 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7121155232 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7121155232 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7121155232 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7121155232 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7121155232 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3411250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3411250 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3411250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3411250 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071698 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071698 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071698 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071698 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11935.710532 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11935.710532 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11935.710532 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44828 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44828 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44828 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44828 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44828 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44828 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 595257 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 595257 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 595257 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 595257 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 595257 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 595257 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7103878279 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7103878279 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7103878279 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7103878279 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7103878279 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7103878279 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3410750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3410750 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3410750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3410750 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.078573 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.078573 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.078573 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.078573 # 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number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8709670 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8709670 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5697011 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5697011 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111511 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111511 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105477 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105477 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14406681 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14406681 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14406681 # 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miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273458 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125165 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100320 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100320 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135711 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135711 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135711 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135711 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15166.063354 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15166.063354 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48845.904123 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 48845.904123 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9275.508240 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9275.508240 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5022.341712 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5022.341712 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 42004.345406 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 42004.345406 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 42004.345406 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 29557 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 18184 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3279 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.014029 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 108.238095 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324789 # number of writebacks -system.cpu1.dcache.writebacks::total 324789 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 170095 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 170095 # 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number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6490016907 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88435503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88435503 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32057085 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32057085 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9329422958 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9329422958 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9329422958 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9329422958 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168915044006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168915044006 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 34787133815 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 34787133815 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 203702177821 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 203702177821 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026187 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026187 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028369 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112123 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112123 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100477 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027050 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027050 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12449.112600 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12449.112600 # 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average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23939.951291 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324751 # number of writebacks +system.cpu1.dcache.writebacks::total 324751 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 168850 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 168850 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1396175 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1396175 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1565025 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1565025 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1565025 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1565025 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228268 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161652 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161652 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12509 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12509 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10578 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10578 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389920 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389920 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389920 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389920 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2830993566 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2830993566 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 6516328872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 6516328872 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88639506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88639506 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31988580 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31988580 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9347322438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 9347322438 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9347322438 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 9347322438 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168914513007 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168914513007 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 25825904490 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 25825904490 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 194740417497 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 194740417497 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026212 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026212 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028376 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028376 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112187 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112187 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100283 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027068 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027068 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027068 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12402.060587 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12402.060587 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 40310.845965 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 40310.845965 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7086.058518 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7086.058518 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3024.066931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3024.066931 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23972.410848 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23972.410848 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -2371,12 +2284,12 @@ system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.iocache.tags.replacements 0 # number of replacements -system.iocache.tags.tagsinuse 0 # Cycle average of tags in use -system.iocache.tags.total_refs 0 # Total number of references to valid blocks. -system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. -system.iocache.tags.avg_refs nan # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.tags.replacements 0 # number of replacements +system.iocache.tags.tagsinuse 0 # Cycle average of tags in use +system.iocache.tags.total_refs 0 # Total number of references to valid blocks. +system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.tags.avg_refs nan # Average number of references to valid blocks. +system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2385,18 +2298,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 644226028268 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 644226028268 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 644226028268 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 644226028268 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 582931892511 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 582931892511 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 582931892511 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 582931892511 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41725 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41731 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48857 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48858 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |