diff options
| author | Ali Saidi <Ali.Saidi@ARM.com> | 2013-02-15 17:40:14 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2013-02-15 17:40:14 -0500 |
| commit | bd31a5dc18def5972967a595d65266d1f9ff05cb (patch) | |
| tree | 62897fcc906dfb88f50c52d4ba2129be7ccdc114 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 8cef39fb6742d834e383f533539ba90f72bbc7d9 (diff) | |
| download | gem5-bd31a5dc18def5972967a595d65266d1f9ff05cb.tar.xz | |
stats: update regressions for o3 changes in renaming and translation.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
3 files changed, 1493 insertions, 1487 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini index 86e60df6e..2403b9510 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm +boot_loader=/projects/pd/randd/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename= @@ -19,7 +19,7 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img +image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] @@ -1048,6 +1048,7 @@ children=badaddr_responder block_size=64 clock=1000 header_cycles=1 +system=system use_default_range=false width=8 default=system.membus.badaddr_responder.pio @@ -1073,25 +1074,27 @@ pio=system.membus.default [system.physmem] type=SimpleDRAM +activation_limit=4 addr_mapping=openmap banks_per_rank=8 clock=1000 conf_table_reported=true in_addr_map=true -lines_per_rowbuffer=64 -mem_sched_policy=fcfs +lines_per_rowbuffer=32 +mem_sched_policy=frfcfs null=false page_policy=open range=0:134217727 ranks_per_channel=2 read_buffer_size=32 -tBURST=4000 -tCL=14000 -tRCD=14000 +tBURST=5000 +tCL=13750 +tRCD=13750 tREFI=7800000 tRFC=300000 -tRP=14000 -tWTR=1000 +tRP=13750 +tWTR=7500 +tXAW=40000 write_buffer_size=32 write_thresh_perc=70 zero=false @@ -1221,7 +1224,7 @@ warn_access= pio=system.iobus.master[24] [system.realview.gic] -type=Gic +type=Pl390 clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 @@ -1500,6 +1503,7 @@ type=CoherentBus block_size=64 clock=500 header_cycles=1 +system=system use_default_range=false width=8 master=system.l2c.cpu_side diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout index a480bab99..d8e2a14f0 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout @@ -1,14 +1,12 @@ -Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simout -Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 22:02:35 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Feb 13 2013 11:38:19 +gem5 started Feb 13 2013 21:11:40 +gem5 executing on u200540-lin command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1092968826500 because m5_exit instruction encountered +Exiting @ tick 1102937390000 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index c67fcab1e..93139ea5d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,131 +1,149 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.103053 # Number of seconds simulated -sim_ticks 1103052934500 # Number of ticks simulated -final_tick 1103052934500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.102937 # Number of seconds simulated +sim_ticks 1102937390000 # Number of ticks simulated +final_tick 1102937390000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 84555 # Simulator instruction rate (inst/s) -host_op_rate 108843 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1514437253 # Simulator tick rate (ticks/s) -host_mem_usage 415912 # Number of bytes of host memory used -host_seconds 728.36 # Real time elapsed on the host -sim_insts 61586372 # Number of instructions simulated -sim_ops 79276491 # Number of ops (including micro ops) simulated +host_inst_rate 67484 # Simulator instruction rate (inst/s) +host_op_rate 86868 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1208579190 # Simulator tick rate (ticks/s) +host_mem_usage 412736 # Number of bytes of host memory used +host_seconds 912.59 # Real time elapsed on the host +sim_insts 61585042 # Number of instructions simulated +sim_ops 79274675 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 48758784 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 409536 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4368116 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 405952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5246000 # Number of bytes read from this memory -system.physmem.bytes_read::total 59190564 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 409536 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 405952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 815488 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4268032 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 408896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4378804 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 405888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5226160 # Number of bytes read from this memory +system.physmem.bytes_read::total 59180644 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 408896 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 405888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 814784 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4259456 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7295376 # Number of bytes written to this memory +system.physmem.bytes_written::total 7286800 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6094848 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6399 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68324 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6343 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81995 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6257943 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66688 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6389 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68491 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6342 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81685 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6257788 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66554 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823524 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 44203485 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 754 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 823390 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 44208116 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 638 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 116 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 371275 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3960024 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 1102 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 368026 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4755891 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 53660674 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 371275 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 368026 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 739301 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3869290 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 15412 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2729102 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6613804 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3869290 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 44203485 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 754 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 370734 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3970129 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1161 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 368006 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4738401 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 53657301 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 370734 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 368006 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 738740 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3861920 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 15413 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2729388 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6606721 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3861920 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 44208116 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 638 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 371275 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3975436 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 1102 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 368026 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 7484993 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 60274478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6257943 # Total number of read requests seen -system.physmem.writeReqs 823524 # Total number of write requests seen -system.physmem.cpureqs 281760 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 400508352 # Total number of bytes read from memory -system.physmem.bytesWritten 52705536 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 59190564 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7295376 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 71 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 12603 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 391392 # Track reads on a per bank basis +system.physmem.bw_total::cpu0.inst 370734 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3985543 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1161 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 368006 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 7467789 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 60264023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6257788 # Total number of read requests seen +system.physmem.writeReqs 823390 # Total number of write requests seen +system.physmem.cpureqs 281560 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 400498432 # Total number of bytes read from memory +system.physmem.bytesWritten 52696960 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 59180644 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7286800 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 12623 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 391400 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 391208 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 390903 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 391629 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 391534 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 390909 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 390959 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 391652 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 391399 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 390708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 390860 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 391237 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 391228 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 390865 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 391604 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 391517 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 390867 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 390930 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 391637 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 391401 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 390707 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 390849 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 391231 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 391237 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 390522 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 390463 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 391269 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 51397 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 51232 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 51042 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 51695 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51560 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50999 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51006 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51676 # Track writes on a per bank basis +system.physmem.perBankRdReqs::14 390468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 391265 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 51411 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 51226 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 51010 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 51681 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51542 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50958 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50977 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51664 # Track writes on a per bank basis system.physmem.perBankWrReqs::8 52039 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51354 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51498 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51880 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51836 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51352 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51491 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51878 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51845 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51250 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51165 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51895 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51172 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51894 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 2168609 # Number of times wr buffer was full causing retry -system.physmem.totGap 1103051731500 # Total gap between requests +system.physmem.numWrRetry 2242937 # Number of times wr buffer was full causing retry +system.physmem.totGap 1102936257500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 105 # Categorize read packet sizes system.physmem.readPktSize::3 6094848 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 162990 # Categorize read packet sizes +system.physmem.readPktSize::6 162835 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 2925445 # categorize write packet sizes +system.physmem.writePktSize::2 2999773 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 66688 # categorize write packet sizes +system.physmem.writePktSize::6 66554 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,29 +152,29 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 12603 # categorize neither packet sizes +system.physmem.neitherpktsize::6 12623 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 494466 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 430633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 391954 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1441360 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1085395 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1097883 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1063934 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 26865 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 24928 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 44608 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 63920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 44461 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 12221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 11894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16880 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6309 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 135 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 493621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 430392 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 391768 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1441431 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1086063 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1098338 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1064335 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 26976 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24854 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 44565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 63872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 44300 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 12061 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 11818 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 5993 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see @@ -170,309 +188,291 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 3069 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3226 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3394 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3530 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3628 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3843 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3929 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35805 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32835 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32737 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32276 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 32178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 32079 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31963 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31877 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2895 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2949 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2985 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3067 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3123 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3149 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35800 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35799 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32905 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32851 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32815 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32779 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 32733 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 32700 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 32677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 32651 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 198980528034 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 238811291784 # Sum of mem lat for all requests -system.physmem.totBusLat 31289360000 # Total cycles spent in databus access -system.physmem.totBankLat 8541403750 # Total cycles spent in bank access -system.physmem.avgQLat 31796.84 # Average queueing delay per request -system.physmem.avgBankLat 1364.91 # Average bank access latency per request +system.physmem.totQLat 199170690855 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 238991050855 # Sum of mem lat for all requests +system.physmem.totBusLat 31288540000 # Total cycles spent in databus access +system.physmem.totBankLat 8531820000 # Total cycles spent in bank access +system.physmem.avgQLat 31828.06 # Average queueing delay per request +system.physmem.avgBankLat 1363.41 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 38161.74 # Average memory access latency -system.physmem.avgRdBW 363.09 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 38191.47 # Average memory access latency +system.physmem.avgRdBW 363.12 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 47.78 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 53.66 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 6.61 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.21 # Data bus utilization in percentage system.physmem.avgRdQLen 0.22 # Average read queue length over time -system.physmem.avgWrQLen 10.13 # Average write queue length over time -system.physmem.readRowHits 6214096 # Number of row buffer hits during reads -system.physmem.writeRowHits 800077 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.24 # Average write queue length over time +system.physmem.readRowHits 6213872 # Number of row buffer hits during reads +system.physmem.writeRowHits 799892 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.15 # Row buffer hit rate for writes -system.physmem.avgGap 155765.99 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 384 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 448 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 58 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 348 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 406 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 58 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 348 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 406 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 58 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 348 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 406 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72694 # number of replacements -system.l2c.tagsinuse 53751.744794 # Cycle average of tags in use -system.l2c.total_refs 1868125 # Total number of references to valid blocks. -system.l2c.sampled_refs 137855 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.551376 # Average number of references to valid blocks. +system.physmem.avgGap 155756.04 # Average gap between requests +system.l2c.replacements 72539 # number of replacements +system.l2c.tagsinuse 53752.248637 # Cycle average of tags in use +system.l2c.total_refs 1841179 # Total number of references to valid blocks. +system.l2c.sampled_refs 137732 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.367838 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39374.569084 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 4.396186 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 39388.476412 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.826353 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000803 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4014.541431 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2824.438134 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 12.707800 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 3714.133429 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 3806.957928 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.600808 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.dtb.walker 0.000067 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 4008.993875 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2816.909683 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 12.612753 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3717.226162 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3804.202595 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.601020 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000058 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.061257 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.043098 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.056673 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.058090 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.820187 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 30721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 4484 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 386372 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166390 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 49432 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 5306 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 590682 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 197805 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1431192 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 580622 # number of Writeback hits -system.l2c.Writeback_hits::total 580622 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1197 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 732 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1929 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 193 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 144 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 337 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48357 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58516 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 106873 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 30721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 4484 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 386372 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214747 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 49432 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 5306 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 590682 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 256321 # number of demand (read+write) hits -system.l2c.demand_hits::total 1538065 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 30721 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 4484 # number of overall hits -system.l2c.overall_hits::cpu0.inst 386372 # number of overall hits -system.l2c.overall_hits::cpu0.data 214747 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 49432 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 5306 # number of overall hits -system.l2c.overall_hits::cpu1.inst 590682 # number of overall hits -system.l2c.overall_hits::cpu1.data 256321 # number of overall hits -system.l2c.overall_hits::total 1538065 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 13 # number of ReadReq misses +system.l2c.occ_percent::cpu0.inst 0.061172 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.042983 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000192 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.056720 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.058048 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.820194 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 21699 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 4247 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 385844 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166771 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 30512 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5160 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 591639 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198020 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1403892 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581178 # number of Writeback hits +system.l2c.Writeback_hits::total 581178 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1163 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 739 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1902 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 201 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 143 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 344 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48042 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58985 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 107027 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 21699 # 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number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050139238 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25325633830 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 26375773068 # number of WriteReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12406738561 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2100314 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154667521253 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 167081659295 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1050184240 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 25918449225 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 26968633465 # number of WriteReq MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5299167 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13458252297 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2070313 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 179992800833 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 193458422610 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000423 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000446 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015979 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036847 # 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average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10169.721546 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10107.776953 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10050.587597 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10037.573171 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10045.529858 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 36996.983462 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 41317.080364 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 39366.945281 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 54136.615385 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42892.739464 # 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average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46626 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42683.404048 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37783.852845 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56252 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46743.304762 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41934.145399 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40400.783708 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42892.739464 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37823.525502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 55464.450000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 47955.743610 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 41994.162067 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40496.088344 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -663,38 +663,38 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 6009414 # Number of BP lookups -system.cpu0.branchPred.condPredicted 4584575 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 296794 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 3746905 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 2916795 # Number of BTB hits +system.cpu0.branchPred.lookups 5998436 # Number of BP lookups +system.cpu0.branchPred.condPredicted 4575399 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 294209 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 3753379 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 2912017 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 77.845448 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 672462 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 28490 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 77.583878 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 673016 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 28669 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8911826 # DTB read hits -system.cpu0.dtb.read_misses 33481 # DTB read misses -system.cpu0.dtb.write_hits 5139826 # DTB write hits -system.cpu0.dtb.write_misses 6231 # DTB write misses +system.cpu0.dtb.read_hits 8902974 # DTB read hits +system.cpu0.dtb.read_misses 28685 # DTB read misses +system.cpu0.dtb.write_hits 5134917 # DTB write hits +system.cpu0.dtb.write_misses 5599 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2125 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 943 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 378 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 1816 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1018 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 297 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 509 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8945307 # DTB read accesses -system.cpu0.dtb.write_accesses 5146057 # DTB write accesses +system.cpu0.dtb.perms_faults 573 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8931659 # DTB read accesses +system.cpu0.dtb.write_accesses 5140516 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14051652 # DTB hits -system.cpu0.dtb.misses 39712 # DTB misses -system.cpu0.dtb.accesses 14091364 # DTB accesses -system.cpu0.itb.inst_hits 4224274 # ITB inst hits -system.cpu0.itb.inst_misses 5167 # ITB inst misses +system.cpu0.dtb.hits 14037891 # DTB hits +system.cpu0.dtb.misses 34284 # DTB misses +system.cpu0.dtb.accesses 14072175 # DTB accesses +system.cpu0.itb.inst_hits 4215172 # ITB inst hits +system.cpu0.itb.inst_misses 5141 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -703,113 +703,113 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1374 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1342 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1487 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1479 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4229441 # ITB inst accesses -system.cpu0.itb.hits 4224274 # DTB hits -system.cpu0.itb.misses 5167 # DTB misses -system.cpu0.itb.accesses 4229441 # DTB accesses -system.cpu0.numCycles 67942321 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4220313 # ITB inst accesses +system.cpu0.itb.hits 4215172 # DTB hits +system.cpu0.itb.misses 5141 # DTB misses +system.cpu0.itb.accesses 4220313 # DTB accesses +system.cpu0.numCycles 67779631 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 11770700 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 32037426 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6009414 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3589257 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7522750 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1459790 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 61665 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 20761422 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 4873 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 52782 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 85653 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 212 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4222584 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 157713 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2319 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 41308500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 1.002087 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.382378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 11746060 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 31992288 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 5998436 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3585033 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7509031 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1449341 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 60597 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 20626968 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4901 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 47542 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 85433 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 195 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4213506 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 157466 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2283 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 41121561 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.005038 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.385329 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33793144 81.81% 81.81% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 566641 1.37% 83.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 818694 1.98% 85.16% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 676082 1.64% 86.80% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 774764 1.88% 88.67% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 559890 1.36% 90.03% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 668973 1.62% 91.65% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 352395 0.85% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3097917 7.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33620027 81.76% 81.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 564307 1.37% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 815894 1.98% 85.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 676094 1.64% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 772709 1.88% 88.64% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 559273 1.36% 90.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 668674 1.63% 91.62% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 351557 0.85% 92.48% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3093026 7.52% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 41308500 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.088449 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.471539 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 12285141 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 20700852 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 6822655 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 515208 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 984644 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 935535 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 64887 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 40031733 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 213257 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 984644 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 12853776 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 5827758 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12754498 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6718585 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2169239 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 38928303 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2058 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 438319 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1238743 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 23 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 39288298 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 175811025 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 175776420 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34605 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 30930446 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8357851 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 411337 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 370395 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5357325 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7655234 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5687790 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1133384 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1222152 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 36851355 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 895739 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 37254250 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 80693 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6299190 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 13209610 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 256967 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 41308500 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.901854 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.509387 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 41121561 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088499 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.472004 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12250531 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 20568387 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6812697 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 512769 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 977177 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 933938 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 64793 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 39972827 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 213127 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 977177 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12817507 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5739937 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 12718334 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6708425 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2160181 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 38878118 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 1834 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 434730 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1233458 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39234243 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 175587138 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 175552572 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34566 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 30916046 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8318196 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 410984 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 370136 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5348015 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7641998 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5680264 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1129998 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1207028 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 36802265 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 895658 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37215076 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 80061 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6274404 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 13150521 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 257091 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 41121561 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.905002 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.512830 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 26145285 63.29% 63.29% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 5753076 13.93% 77.22% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3163283 7.66% 84.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2484845 6.02% 90.89% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2098538 5.08% 95.97% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 943313 2.28% 98.26% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 484190 1.17% 99.43% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 183544 0.44% 99.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52426 0.13% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 25997548 63.22% 63.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5725018 13.92% 77.14% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3161670 7.69% 84.83% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2471559 6.01% 90.84% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2093564 5.09% 95.93% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 947248 2.30% 98.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 486513 1.18% 99.42% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 185061 0.45% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53380 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 41308500 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 41121561 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 25686 2.41% 2.41% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 25811 2.41% 2.41% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 454 0.04% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.45% # attempts to use FU when none available @@ -838,13 +838,13 @@ system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.45% # at system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.45% # attempts to use FU when none available system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.45% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 841970 78.85% 81.30% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 199670 18.70% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841861 78.66% 81.12% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 202059 18.88% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52214 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22338200 59.96% 60.10% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 46968 0.13% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52149 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22315653 59.96% 60.10% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 46928 0.13% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.23% # Type of FU issued @@ -857,11 +857,11 @@ system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 17 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.23% # Type of FU issued @@ -870,363 +870,363 @@ system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.23% # Ty system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMisc 700 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 60.23% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 60.23% # Type of FU issued system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.23% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9368796 25.15% 85.38% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5447325 14.62% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9358800 25.15% 85.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5440823 14.62% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 37254250 # Type of FU issued -system.cpu0.iq.rate 0.548322 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1067780 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.028662 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 116996499 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 44054105 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 34350443 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8454 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4728 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3907 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 38265398 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 307211 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37215076 # Type of FU issued +system.cpu0.iq.rate 0.549060 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1070185 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028757 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 116727564 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 43980171 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34315180 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8451 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4750 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3900 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38228693 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4419 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 306291 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1378796 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 2415 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13078 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 537331 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1370106 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2445 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13123 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 533688 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2192757 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5650 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2192694 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5412 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 984644 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4190634 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 100027 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 37865226 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 85653 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7655234 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5687790 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 571722 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 40568 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3395 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13078 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 150532 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 118543 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 269075 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 36877414 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9226875 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 376836 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 977177 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4122288 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 97984 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 37816345 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 85218 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7641998 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5680264 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 571541 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39816 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2781 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13123 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 149547 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 116915 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 266462 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 36841770 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9218382 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 373306 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 118132 # number of nop insts executed -system.cpu0.iew.exec_refs 14626534 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4859341 # Number of branches executed -system.cpu0.iew.exec_stores 5399659 # Number of stores executed -system.cpu0.iew.exec_rate 0.542775 # Inst execution rate -system.cpu0.iew.wb_sent 36683533 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 34354350 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18308250 # num instructions producing a value -system.cpu0.iew.wb_consumers 35218685 # num instructions consuming a value +system.cpu0.iew.exec_nop 118422 # number of nop insts executed +system.cpu0.iew.exec_refs 14612857 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4852888 # Number of branches executed +system.cpu0.iew.exec_stores 5394475 # Number of stores executed +system.cpu0.iew.exec_rate 0.543552 # Inst execution rate +system.cpu0.iew.wb_sent 36648414 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34319080 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18273947 # num instructions producing a value +system.cpu0.iew.wb_consumers 35157700 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.505640 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.519845 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.506333 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.519771 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6121232 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 638772 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 232995 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 40323856 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.775878 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.738297 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6086541 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 638567 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 230552 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 40144384 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.778927 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.740713 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 28652168 71.06% 71.06% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 5718960 14.18% 85.24% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1913940 4.75% 89.98% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 975658 2.42% 92.40% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 781823 1.94% 94.34% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 527081 1.31% 95.65% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 383426 0.95% 96.60% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 217091 0.54% 97.14% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1153709 2.86% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 28480985 70.95% 70.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5711149 14.23% 85.17% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1913332 4.77% 89.94% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 974787 2.43% 92.37% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 784907 1.96% 94.32% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 524754 1.31% 95.63% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 386537 0.96% 96.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 218696 0.54% 97.14% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1149237 2.86% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 40323856 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 23679897 # Number of instructions committed -system.cpu0.commit.committedOps 31286376 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 40144384 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23670531 # Number of instructions committed +system.cpu0.commit.committedOps 31269562 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11426897 # Number of memory references committed -system.cpu0.commit.loads 6276438 # Number of loads committed -system.cpu0.commit.membars 229667 # Number of memory barriers committed -system.cpu0.commit.branches 4245099 # Number of branches committed +system.cpu0.commit.refs 11418468 # Number of memory references committed +system.cpu0.commit.loads 6271892 # Number of loads committed +system.cpu0.commit.membars 229609 # Number of memory barriers committed +system.cpu0.commit.branches 4243643 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 27642973 # Number of committed integer instructions. -system.cpu0.commit.function_calls 489349 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1153709 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27627358 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489165 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1149237 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 75726635 # The number of ROB reads -system.cpu0.rob.rob_writes 75801988 # The number of ROB writes -system.cpu0.timesIdled 359866 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 26633821 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2138121828 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 23599155 # Number of Instructions Simulated -system.cpu0.committedOps 31205634 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 23599155 # Number of Instructions Simulated -system.cpu0.cpi 2.879015 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 2.879015 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.347341 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.347341 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 171917289 # number of integer regfile reads -system.cpu0.int_regfile_writes 34107060 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3422 # number of floating regfile reads -system.cpu0.fp_regfile_writes 966 # number of floating regfile writes -system.cpu0.misc_regfile_reads 13053108 # number of misc regfile reads -system.cpu0.misc_regfile_writes 451057 # number of misc regfile writes -system.cpu0.icache.replacements 392744 # number of replacements -system.cpu0.icache.tagsinuse 511.016860 # Cycle average of tags in use -system.cpu0.icache.total_refs 3798516 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 393256 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.659143 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 75500320 # The number of ROB reads +system.cpu0.rob.rob_writes 75691570 # The number of ROB writes +system.cpu0.timesIdled 360084 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26658070 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2138053443 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23589789 # Number of Instructions Simulated +system.cpu0.committedOps 31188820 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23589789 # Number of Instructions Simulated +system.cpu0.cpi 2.873261 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.873261 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.348037 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.348037 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 171728285 # number of integer regfile reads +system.cpu0.int_regfile_writes 34072180 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3295 # number of floating regfile reads +system.cpu0.fp_regfile_writes 900 # number of floating regfile writes +system.cpu0.misc_regfile_reads 12998314 # number of misc regfile reads +system.cpu0.misc_regfile_writes 450987 # number of misc regfile writes +system.cpu0.icache.replacements 392135 # number of replacements +system.cpu0.icache.tagsinuse 511.076170 # Cycle average of tags in use +system.cpu0.icache.total_refs 3790159 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 392647 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.652841 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6563458000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.016860 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998080 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998080 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3798516 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3798516 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3798516 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3798516 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3798516 # number of overall hits -system.cpu0.icache.overall_hits::total 3798516 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 423935 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 423935 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 423935 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 423935 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 423935 # number of overall misses -system.cpu0.icache.overall_misses::total 423935 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5803194996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5803194996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5803194996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5803194996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5803194996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5803194996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4222451 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4222451 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4222451 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4222451 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4222451 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4222451 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100400 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.100400 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100400 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.100400 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100400 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.100400 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13688.879182 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13688.879182 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13688.879182 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13688.879182 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13688.879182 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3086 # number of cycles access was blocked +system.cpu0.icache.occ_blocks::cpu0.inst 511.076170 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998196 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998196 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3790159 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3790159 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3790159 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3790159 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3790159 # number of overall hits +system.cpu0.icache.overall_hits::total 3790159 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 423214 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 423214 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 423214 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 423214 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 423214 # number of overall misses +system.cpu0.icache.overall_misses::total 423214 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5793685997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5793685997 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5793685997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5793685997 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5793685997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5793685997 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4213373 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4213373 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4213373 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4213373 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4213373 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4213373 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.100445 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.100445 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.100445 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.100445 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.100445 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.100445 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13689.731429 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13689.731429 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13689.731429 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13689.731429 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13689.731429 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2401 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 163 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 146 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.932515 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.445205 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30660 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 30660 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 30660 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 30660 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 30660 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 30660 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 393275 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 393275 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 393275 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 393275 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 393275 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 393275 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4745687496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4745687496 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4745687496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4745687496 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4745687496 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4745687496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 30547 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 30547 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 30547 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 30547 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 30547 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 30547 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 392667 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 392667 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 392667 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 392667 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 392667 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 392667 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4739152997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4739152997 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4739152997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4739152997 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4739152997 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4739152997 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 7900500 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 7900500 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 7900500 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093139 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.093139 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093139 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.093139 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12067.096805 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12067.096805 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12067.096805 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.093195 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.093195 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.093195 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.093195 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12069.140002 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12069.140002 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12069.140002 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275861 # number of replacements -system.cpu0.dcache.tagsinuse 459.614904 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9266976 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276373 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 33.530685 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 43517000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 459.614904 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.897685 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.897685 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5785932 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5785932 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3160921 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3160921 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139137 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 139137 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137051 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 137051 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8946853 # 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miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051780 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180699 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.180699 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180699 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.180699 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13899.798197 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13899.798197 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38119.281243 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 38119.281243 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10051.566952 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10051.566952 # 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average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 69.950617 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 276137 # number of replacements +system.cpu0.dcache.tagsinuse 461.136878 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9254727 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276649 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.452957 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 43495000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 461.136878 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.900658 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.900658 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5777010 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5777010 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3157960 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3157960 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 139054 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 139054 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137010 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 137010 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8934970 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8934970 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8934970 # number of overall hits +system.cpu0.dcache.overall_hits::total 8934970 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 392909 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 392909 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1581686 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1581686 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8773 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8773 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7509 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7509 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1974595 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1974595 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1974595 # number of overall misses +system.cpu0.dcache.overall_misses::total 1974595 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5473319500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5473319500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 60618366371 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 60618366371 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 87499000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 87499000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 46786000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 46786000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 66091685871 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 66091685871 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 66091685871 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 66091685871 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6169919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6169919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4739646 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4739646 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 147827 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 147827 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 144519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 144519 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10909565 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10909565 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10909565 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10909565 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063681 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.063681 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333714 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333714 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059346 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059346 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.051959 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.051959 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.180997 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.180997 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.180997 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.180997 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13930.247207 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13930.247207 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 38325.158325 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 38325.158325 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9973.669212 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9973.669212 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 6230.656545 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 6230.656545 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33471.008420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33471.008420 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33471.008420 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9022 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2690 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 641 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 80 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 14.074883 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 33.625000 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256398 # number of writebacks -system.cpu0.dcache.writebacks::total 256398 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 202708 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 202708 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451928 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1451928 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 451 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 451 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1654636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1654636 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1654636 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1654636 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188268 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 188268 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130344 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 130344 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8324 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8324 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7483 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7483 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 318612 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 318612 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 318612 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 318612 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2372133500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2372133500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4018964492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4018964492 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 66568500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 66568500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31704000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31704000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6391097992 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6391097992 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6391097992 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6391097992 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13514906500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13514906500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180228378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180228378 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14695134878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14695134878 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030479 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030479 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027480 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056277 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056277 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051773 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051773 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029177 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029177 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029177 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12599.770009 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12599.770009 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30833.521236 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30833.521236 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7997.176838 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7997.176838 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4236.803421 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4236.803421 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20059.187953 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20059.187953 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256527 # number of writebacks +system.cpu0.dcache.writebacks::total 256527 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 204116 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 204116 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451395 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 471 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 471 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1655511 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1655511 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1655511 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1655511 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188793 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188793 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130291 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130291 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8302 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7505 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 319084 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 319084 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 319084 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 319084 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2371443000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2371443000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4036122491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4036122491 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 65692500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 65692500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 31776000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 31776000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6407565491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6407565491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6407565491 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6407565491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13513513000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13513513000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1180350378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1180350378 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14693863378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14693863378 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030599 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030599 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027490 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.056160 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.056160 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.051931 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.051931 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029248 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029248 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029248 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12561.074828 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12561.074828 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 30977.753575 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 30977.753575 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7912.852325 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7912.852325 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 4233.977348 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 4233.977348 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20081.124378 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 20081.124378 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1234,38 +1234,38 @@ system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 9060826 # Number of BP lookups -system.cpu1.branchPred.condPredicted 7443379 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 410189 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 6060421 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 5228505 # Number of BTB hits +system.cpu1.branchPred.lookups 9086614 # Number of BP lookups +system.cpu1.branchPred.condPredicted 7469023 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 411441 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 6087298 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 5252816 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 86.272967 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 772521 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 43024 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 86.291422 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 771111 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 43004 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 42893856 # DTB read hits -system.cpu1.dtb.read_misses 41286 # DTB read misses -system.cpu1.dtb.write_hits 6825448 # DTB write hits -system.cpu1.dtb.write_misses 11345 # DTB write misses +system.cpu1.dtb.read_hits 42908069 # DTB read hits +system.cpu1.dtb.read_misses 37093 # DTB read misses +system.cpu1.dtb.write_hits 6828111 # DTB write hits +system.cpu1.dtb.write_misses 10566 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2300 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 2725 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 348 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2002 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 2479 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 308 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 636 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 42935142 # DTB read accesses -system.cpu1.dtb.write_accesses 6836793 # DTB write accesses +system.cpu1.dtb.perms_faults 658 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 42945162 # DTB read accesses +system.cpu1.dtb.write_accesses 6838677 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 49719304 # DTB hits -system.cpu1.dtb.misses 52631 # DTB misses -system.cpu1.dtb.accesses 49771935 # DTB accesses -system.cpu1.itb.inst_hits 8340296 # ITB inst hits -system.cpu1.itb.inst_misses 5581 # ITB inst misses +system.cpu1.dtb.hits 49736180 # DTB hits +system.cpu1.dtb.misses 47659 # DTB misses +system.cpu1.dtb.accesses 49783839 # DTB accesses +system.cpu1.itb.inst_hits 8400139 # ITB inst hits +system.cpu1.itb.inst_misses 5511 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1274,114 +1274,114 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1543 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1527 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1561 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1516 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8345877 # ITB inst accesses -system.cpu1.itb.hits 8340296 # DTB hits -system.cpu1.itb.misses 5581 # DTB misses -system.cpu1.itb.accesses 8345877 # DTB accesses -system.cpu1.numCycles 408908787 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8405650 # ITB inst accesses +system.cpu1.itb.hits 8400139 # DTB hits +system.cpu1.itb.misses 5511 # DTB misses +system.cpu1.itb.accesses 8405650 # DTB accesses +system.cpu1.numCycles 408778710 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 19741855 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 65652351 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9060826 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6001026 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 14075401 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 3918937 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 65639 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 77552970 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 4686 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 46851 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 129796 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 89 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 8338330 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 726090 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3044 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 114288783 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.696009 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.038635 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 19802343 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 66108771 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9086614 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6023927 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14149480 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 3968467 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 63429 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 77260462 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4652 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 42943 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 130023 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 107 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8398224 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 741385 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2977 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 114156752 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.701240 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.046062 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 100220679 87.69% 87.69% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 798295 0.70% 88.39% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 938778 0.82% 89.21% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1873808 1.64% 90.85% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1510998 1.32% 92.17% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 574008 0.50% 92.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2116066 1.85% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 410869 0.36% 94.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 5845282 5.11% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 100014473 87.61% 87.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 796994 0.70% 88.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 939704 0.82% 89.13% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1889255 1.65% 90.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1506031 1.32% 92.11% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 574931 0.50% 92.61% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2131854 1.87% 94.48% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 410857 0.36% 94.84% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 5892653 5.16% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 114288783 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.022159 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.160555 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 21260604 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 77197159 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 12728983 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 527252 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 2574785 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1107873 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 98231 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 74815491 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 327601 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 2574785 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 22637961 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 32138028 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 40746993 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 11784015 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4407001 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 69468156 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 19628 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 681075 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3151682 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 32928 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 73408550 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 319754725 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 319695969 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58756 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 49044244 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 24364306 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 444465 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 387610 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 7946566 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 13166209 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8131289 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1039797 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1544280 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 63306558 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1157694 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 89041269 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 96485 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 16034557 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 45010776 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 277192 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 114288783 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.779090 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.516652 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 114156752 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022229 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.161723 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 21320888 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 76914540 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 12790943 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 524179 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2606202 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1106995 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 98605 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 75226388 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 330391 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2606202 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 22704982 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 31945118 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 40735326 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 11835422 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4329702 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 69763643 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 18779 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 668299 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3087296 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 338 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 73772994 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 321197839 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 321138769 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 59070 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49056932 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 24716062 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 445445 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 388435 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7877150 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13206045 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8148691 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1035919 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1598177 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 63545873 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1154873 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 89160933 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 94911 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 16250476 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 45782181 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 274059 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 114156752 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.781040 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.519067 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 83847546 73.36% 73.36% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 8475969 7.42% 80.78% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4322490 3.78% 84.56% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 3758453 3.29% 87.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10560015 9.24% 97.09% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1959947 1.71% 98.81% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1018953 0.89% 99.70% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 271832 0.24% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 73578 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 83738528 73.35% 73.35% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8425243 7.38% 80.73% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4289902 3.76% 84.49% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3781770 3.31% 87.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10587758 9.27% 97.08% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1962324 1.72% 98.80% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1024618 0.90% 99.70% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 272656 0.24% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 73953 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 114288783 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 114156752 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 29343 0.37% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 994 0.01% 0.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 29608 0.38% 0.38% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 998 0.01% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.39% # attempts to use FU when none available @@ -1409,395 +1409,399 @@ system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.39% # at system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.39% # attempts to use FU when none available system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.39% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7546096 95.87% 96.25% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 294849 3.75% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7547947 95.93% 96.32% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 289296 3.68% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313932 0.35% 0.35% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 37546524 42.17% 42.52% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 59182 0.07% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1504 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.59% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 43946850 49.36% 91.94% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7173254 8.06% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313997 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 37637940 42.21% 42.57% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59271 0.07% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 10 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 1 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 8 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1510 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.63% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 43972305 49.32% 91.95% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7175883 8.05% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 89041269 # Type of FU issued -system.cpu1.iq.rate 0.217753 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7871282 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.088400 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 300376626 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 80507257 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 53605393 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14907 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8010 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6781 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 96590759 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7860 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 340884 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 89160933 # Type of FU issued +system.cpu1.iq.rate 0.218115 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7867849 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.088243 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 300473883 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 80959646 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 53671142 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14975 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8034 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6858 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 96706888 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7897 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 342362 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 3415033 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3561 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 17027 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1294633 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3450901 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3895 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17010 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1308558 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31913246 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 874031 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31911884 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 888923 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 2574785 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 24237525 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 363690 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 64568060 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 112440 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 13166209 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8131289 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 869125 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 67667 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3747 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 17027 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 202949 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 155576 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 358525 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 86656974 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43263445 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2384295 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2606202 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24177339 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 360038 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 64805263 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 113338 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13206045 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8148691 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 865764 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 64951 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3491 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17010 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 203575 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 156879 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 360454 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 86736990 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43278008 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2423943 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 103808 # number of nop insts executed -system.cpu1.iew.exec_refs 50374669 # number of memory reference insts executed -system.cpu1.iew.exec_branches 6998395 # Number of branches executed -system.cpu1.iew.exec_stores 7111224 # Number of stores executed -system.cpu1.iew.exec_rate 0.211923 # Inst execution rate -system.cpu1.iew.wb_sent 85695257 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 53612174 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 29896757 # num instructions producing a value -system.cpu1.iew.wb_consumers 53335024 # num instructions consuming a value +system.cpu1.iew.exec_nop 104517 # number of nop insts executed +system.cpu1.iew.exec_refs 50391999 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7007502 # Number of branches executed +system.cpu1.iew.exec_stores 7113991 # Number of stores executed +system.cpu1.iew.exec_rate 0.212186 # Inst execution rate +system.cpu1.iew.wb_sent 85759457 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 53678000 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 29917161 # num instructions producing a value +system.cpu1.iew.wb_consumers 53364078 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.131110 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.560546 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.131313 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.560624 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 15938596 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 880502 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 313478 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 111713998 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.430926 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.399973 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 16174786 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 880814 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 314330 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 111550550 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.431692 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.400024 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 94998150 85.04% 85.04% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8214546 7.35% 92.39% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2111823 1.89% 94.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1251354 1.12% 95.40% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1240107 1.11% 96.51% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 568335 0.51% 97.02% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 995989 0.89% 97.91% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 499347 0.45% 98.36% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1834347 1.64% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 94808427 84.99% 84.99% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8234297 7.38% 92.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2114478 1.90% 94.27% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1250833 1.12% 95.39% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1245005 1.12% 96.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 571421 0.51% 97.02% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1000699 0.90% 97.92% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 504697 0.45% 98.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1820693 1.63% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 111713998 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38056856 # Number of instructions committed -system.cpu1.commit.committedOps 48140496 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 111550550 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38064892 # Number of instructions committed +system.cpu1.commit.committedOps 48155494 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 16587832 # Number of memory references committed -system.cpu1.commit.loads 9751176 # Number of loads committed -system.cpu1.commit.membars 190071 # Number of memory barriers committed -system.cpu1.commit.branches 5966416 # Number of branches committed -system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 42676497 # Number of committed integer instructions. -system.cpu1.commit.function_calls 534458 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1834347 # number cycles where commit BW limit reached +system.cpu1.commit.refs 16595277 # Number of memory references committed +system.cpu1.commit.loads 9755144 # Number of loads committed +system.cpu1.commit.membars 190149 # Number of memory barriers committed +system.cpu1.commit.branches 5967637 # Number of branches committed +system.cpu1.commit.fp_insts 6822 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 42690457 # Number of committed integer instructions. +system.cpu1.commit.function_calls 534638 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1820693 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 172914942 # The number of ROB reads -system.cpu1.rob.rob_writes 130824932 # The number of ROB writes -system.cpu1.timesIdled 1407670 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 294620004 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 1796556351 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 37987217 # Number of Instructions Simulated -system.cpu1.committedOps 48070857 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 37987217 # Number of Instructions Simulated -system.cpu1.cpi 10.764379 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.764379 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092899 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092899 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 387772369 # number of integer regfile reads -system.cpu1.int_regfile_writes 56145305 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4887 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2320 # number of floating regfile writes -system.cpu1.misc_regfile_reads 18518507 # number of misc regfile reads -system.cpu1.misc_regfile_writes 405334 # number of misc regfile writes -system.cpu1.icache.replacements 597077 # number of replacements -system.cpu1.icache.tagsinuse 480.917703 # Cycle average of tags in use -system.cpu1.icache.total_refs 7696282 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 597589 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 12.878888 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 74223543500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 480.917703 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.939292 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.939292 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 7696282 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 7696282 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 7696282 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 7696282 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 7696282 # number of overall hits -system.cpu1.icache.overall_hits::total 7696282 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 641998 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 641998 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 641998 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 641998 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 641998 # number of overall misses -system.cpu1.icache.overall_misses::total 641998 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8633779496 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 8633779496 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 8633779496 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 8633779496 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 8633779496 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 8633779496 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 8338280 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 8338280 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 8338280 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 8338280 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 8338280 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 8338280 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.076994 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.076994 # 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number of cycles access was blocked +system.cpu1.rob.rob_reads 173015978 # The number of ROB reads +system.cpu1.rob.rob_writes 131360292 # The number of ROB writes +system.cpu1.timesIdled 1408221 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 294621958 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1796461003 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 37995253 # Number of Instructions Simulated +system.cpu1.committedOps 48085855 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 37995253 # Number of Instructions Simulated +system.cpu1.cpi 10.758678 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.758678 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092948 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092948 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 388090475 # number of integer regfile reads +system.cpu1.int_regfile_writes 56232580 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4956 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 18472941 # number of misc regfile reads +system.cpu1.misc_regfile_writes 405527 # number of misc regfile writes +system.cpu1.icache.replacements 597992 # number of replacements +system.cpu1.icache.tagsinuse 480.750463 # Cycle average of tags in use +system.cpu1.icache.total_refs 7754983 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 598504 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 12.957278 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74232640500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 480.750463 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.938966 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.938966 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 7754983 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 7754983 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 7754983 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 7754983 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 7754983 # number of overall hits +system.cpu1.icache.overall_hits::total 7754983 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 643188 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 643188 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 643188 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 643188 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 643188 # number of overall misses +system.cpu1.icache.overall_misses::total 643188 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8662129496 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8662129496 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8662129496 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8662129496 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8662129496 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8662129496 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8398171 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8398171 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8398171 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8398171 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8398171 # 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average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13467.492391 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13467.492391 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 2692 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 172 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 184 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.203488 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 14.630435 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # 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number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7074093496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 7074093496 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7074093496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 7074093496 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7074093496 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 7074093496 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3068500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3068500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3068500 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071671 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.071671 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071671 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.071671 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11837.268154 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11837.268154 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11837.268154 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 44654 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 44654 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 44654 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 44654 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 44654 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 44654 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 598534 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 598534 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 598534 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 598534 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 598534 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 598534 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7093435997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7093435997 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7093435997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7093435997 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7093435997 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3098500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3098500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3098500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.071270 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.071270 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.071270 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.071270 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11851.350127 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11851.350127 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11851.350127 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # 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number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4138624 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97469 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 97469 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94858 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 94858 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12449158 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12449158 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12449158 # number of overall hits -system.cpu1.dcache.overall_hits::total 12449158 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 397542 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 397542 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1554744 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1554744 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13907 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 13907 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10598 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10598 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 1952286 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 1952286 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 1952286 # number of overall misses -system.cpu1.dcache.overall_misses::total 1952286 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6044984000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 6044984000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61833185511 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 61833185511 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129279000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 129279000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53828000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 53828000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 67878169511 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 67878169511 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 67878169511 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 67878169511 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 8708076 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 8708076 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5693368 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5693368 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111376 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 111376 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105456 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 105456 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14401444 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14401444 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14401444 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14401444 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045652 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045652 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273080 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273080 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.124865 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.124865 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100497 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100497 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135562 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135562 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135562 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135562 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15205.900257 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 15205.900257 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39770.653890 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 39770.653890 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9295.966060 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9295.966060 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5079.071523 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5079.071523 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 34768.558250 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34768.558250 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 34768.558250 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 26588 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 13412 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 3258 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 8.160835 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 82.790123 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360685 # number of replacements +system.cpu1.dcache.tagsinuse 474.635478 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12674649 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361036 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.106330 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 70356699000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 474.635478 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.927022 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.927022 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8306809 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8306809 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4139176 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4139176 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 97757 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 97757 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 94875 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 94875 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12445985 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12445985 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12445985 # number of overall hits +system.cpu1.dcache.overall_hits::total 12445985 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 399972 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 399972 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1557467 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1557467 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14022 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14022 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10623 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10623 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1957439 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1957439 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1957439 # number of overall misses +system.cpu1.dcache.overall_misses::total 1957439 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6115655000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 6115655000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 61487432499 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 61487432499 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129927000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129927000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 53882500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 53882500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 67603087499 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 67603087499 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 67603087499 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 67603087499 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8706781 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8706781 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5696643 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5696643 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 111779 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 111779 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 105498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 105498 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14403424 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14403424 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14403424 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14403424 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045938 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.045938 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273401 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.273401 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.125444 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.125444 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.100694 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.100694 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135901 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.135901 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135901 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.135901 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15290.207815 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 15290.207815 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 39479.123795 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 39479.123795 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9265.939238 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9265.939238 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5072.248894 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5072.248894 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 34536.497689 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 34536.497689 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 34536.497689 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 30853 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 12637 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3329 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 157 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 9.267948 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 80.490446 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 324224 # number of writebacks -system.cpu1.dcache.writebacks::total 324224 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 169594 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 169594 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1393339 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1393339 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1447 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1562933 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1562933 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1562933 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1562933 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 227948 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 227948 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161405 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 161405 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12460 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12460 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10596 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10596 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 389353 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 389353 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 389353 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 389353 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2844990000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2844990000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5144127207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5144127207 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88536000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88536000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32636000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32636000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7989117207 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7989117207 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7989117207 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7989117207 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168989822500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168989822500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35094178017 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35094178017 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204084000517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204084000517 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026177 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026177 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028350 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.111873 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.111873 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100478 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100478 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.027036 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027036 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.027036 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12480.872831 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12480.872831 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31870.928453 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31870.928453 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7105.617978 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7105.617978 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3080.030200 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3080.030200 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20518.956338 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20518.956338 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 324651 # number of writebacks +system.cpu1.dcache.writebacks::total 324651 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 171732 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 171732 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1395801 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1395801 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1444 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1444 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1567533 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1567533 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1567533 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1567533 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228240 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228240 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161666 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161666 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12578 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12578 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10618 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10618 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389906 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389906 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389906 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389906 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2856522500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2856522500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5131083207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5131083207 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 89046000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 89046000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 32648500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 32648500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7987605707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7987605707 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7987605707 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7987605707 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168990252000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168990252000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 35686741676 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 35686741676 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 204676993676 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 204676993676 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.026214 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.026214 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028379 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.112526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.112526 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.100646 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.100646 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.027070 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.027070 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.027070 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12515.433316 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12515.433316 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31738.789894 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31738.789894 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7079.503896 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7079.503896 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3074.825768 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3074.825768 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20485.977920 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20485.977920 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1819,18 +1823,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 539953604456 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 539953604456 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 539953604456 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 539953604456 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 540120016505 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 540120016505 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 540120016505 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 540120016505 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 41721 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 41707 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 48838 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 48866 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |