diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:21 -0400 |
| commit | d52adc4eb68c2733f9af4ac68834583c0a555f9d (patch) | |
| tree | 2ee5c3d271af63a3ef527c54950f57f406a05d90 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual | |
| parent | 88554790c34f6fef4ba6285927fb9742b90ab258 (diff) | |
| download | gem5-d52adc4eb68c2733f9af4ac68834583c0a555f9d.tar.xz | |
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt | 2928 |
1 files changed, 1464 insertions, 1464 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt index 8459be5ac..820ef6b3e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.616879 # Number of seconds simulated -sim_ticks 2616878893500 # Number of ticks simulated -final_tick 2616878893500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.004001 # Number of seconds simulated +sim_ticks 1004001369000 # Number of ticks simulated +final_tick 1004001369000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 63327 # Simulator instruction rate (inst/s) -host_op_rate 81506 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2627232906 # Simulator tick rate (ticks/s) -host_mem_usage 387740 # Number of bytes of host memory used -host_seconds 996.06 # Real time elapsed on the host -sim_insts 63077499 # Number of instructions simulated -sim_ops 81184436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 397632 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4358324 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 424512 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 5245616 # Number of bytes read from this memory -system.physmem.bytes_read::total 131538596 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 397632 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 424512 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 822144 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4254848 # Number of bytes written to this memory +host_inst_rate 89245 # Simulator instruction rate (inst/s) +host_op_rate 114826 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1450204701 # Simulator tick rate (ticks/s) +host_mem_usage 385792 # Number of bytes of host memory used +host_seconds 692.32 # Real time elapsed on the host +sim_insts 61785538 # Number of instructions simulated +sim_ops 79495701 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 44040192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 640 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 411712 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4381300 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 403392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 5239536 # Number of bytes read from this memory +system.physmem.bytes_read::total 54478052 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 411712 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 403392 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 815104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4277248 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 3012136 # Number of bytes written to this memory -system.physmem.bytes_written::total 7283984 # Number of bytes written to this memory -system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 6213 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 68171 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 6633 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 81989 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15301853 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 66482 # Number of write requests responded to by this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7304336 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 5505024 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 10 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 6433 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 68530 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 18 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 6303 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 81894 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5668214 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 66832 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 753034 # Number of write requests responded to by this memory -system.physmem.num_writes::total 823766 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 46280525 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.itb.walker 73 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 151949 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1665466 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 465 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 162221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 2004531 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50265450 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 151949 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 162221 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1625925 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 6496 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 1151041 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2783462 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1625925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 46280525 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.itb.walker 73 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 151949 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1671963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 465 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 162221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 3155573 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53048913 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory +system.physmem.num_writes::total 823604 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43864673 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 637 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 127 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 410071 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4363839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 1147 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 401784 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 5218654 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54260934 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 410071 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 401784 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 811855 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 4260201 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 16932 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2998092 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 7275225 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 4260201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43864673 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 127 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 410071 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4380771 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 1147 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 401784 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 8216746 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 61536159 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 384 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 448 # Number of bytes read from this memory @@ -75,246 +75,246 @@ system.realview.nvmem.bytes_inst_read::total 448 system.realview.nvmem.num_reads::cpu0.inst 1 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::cpu1.inst 6 # Number of read requests responded to by this memory system.realview.nvmem.num_reads::total 7 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 24 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 147 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 171 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 24 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 147 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 171 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 24 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 147 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 171 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 72648 # number of replacements -system.l2c.tagsinuse 53148.103120 # Cycle average of tags in use -system.l2c.total_refs 1925510 # Total number of references to valid blocks. -system.l2c.sampled_refs 137845 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.968660 # Average number of references to valid blocks. +system.realview.nvmem.bw_read::cpu0.inst 64 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 382 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 446 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 64 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 382 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 446 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 64 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 382 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 446 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 72797 # number of replacements +system.l2c.tagsinuse 53893.248657 # Cycle average of tags in use +system.l2c.total_refs 1879341 # Total number of references to valid blocks. +system.l2c.sampled_refs 137955 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.622855 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 37769.007236 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.dtb.walker 3.653962 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.872957 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4238.981277 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2955.984743 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 14.025683 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 4027.816705 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 4137.760558 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.576309 # Average percentage of cache occupancy +system.l2c.occ_blocks::writebacks 39653.380215 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 3.693619 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000676 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4026.678241 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2797.052262 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 11.937877 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 3656.015551 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3744.490216 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.605063 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000056 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.itb.walker 0.000013 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.064682 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.045105 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.dtb.walker 0.000214 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.061460 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.063137 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.810976 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 34723 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 5721 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 398866 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 166115 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 54785 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 6733 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 615111 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 202597 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1484651 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 585034 # number of Writeback hits -system.l2c.Writeback_hits::total 585034 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 1035 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 803 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1838 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu0.data 210 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu1.data 166 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 376 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 48272 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 58996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 107268 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 34723 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 5721 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 398866 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 214387 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 54785 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 6733 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 615111 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 261593 # number of demand (read+write) hits -system.l2c.demand_hits::total 1591919 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 34723 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 5721 # number of overall hits -system.l2c.overall_hits::cpu0.inst 398866 # number of overall hits -system.l2c.overall_hits::cpu0.data 214387 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 54785 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 6733 # number of overall hits -system.l2c.overall_hits::cpu1.inst 615111 # number of overall hits -system.l2c.overall_hits::cpu1.data 261593 # number of overall hits -system.l2c.overall_hits::total 1591919 # number of overall hits -system.l2c.ReadReq_misses::cpu0.dtb.walker 9 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 6086 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6313 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.dtb.walker 19 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 6595 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 6354 # number of ReadReq misses -system.l2c.ReadReq_misses::total 25379 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 5710 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 4349 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 10059 # number of UpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu0.data 787 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::cpu1.data 589 # number of SCUpgradeReq misses -system.l2c.SCUpgradeReq_misses::total 1376 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 63248 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 76888 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.dtb.walker 9 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 6086 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 69561 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.dtb.walker 19 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 6595 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 83242 # number of demand (read+write) misses -system.l2c.demand_misses::total 165515 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.dtb.walker 9 # number of overall misses -system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu0.inst 6086 # number of overall misses -system.l2c.overall_misses::cpu0.data 69561 # number of overall misses -system.l2c.overall_misses::cpu1.dtb.walker 19 # number of overall misses -system.l2c.overall_misses::cpu1.inst 6595 # number of overall misses -system.l2c.overall_misses::cpu1.data 83242 # number of overall misses -system.l2c.overall_misses::total 165515 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 469500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.itb.walker 164500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.inst 324649999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu0.data 331479497 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 999000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 350737499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 334001499 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 1342501494 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0.data 20494467 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 27361999 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 47856466 # number of UpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1618500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::cpu1.data 6981500 # number of SCUpgradeReq miss cycles -system.l2c.SCUpgradeReq_miss_latency::total 8600000 # number of SCUpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0.data 3367787487 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 4076466989 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 7444254476 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0.dtb.walker 469500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.itb.walker 164500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.inst 324649999 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu0.data 3699266984 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.dtb.walker 999000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 350737499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 4410468488 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 8786755970 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0.dtb.walker 469500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.itb.walker 164500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.inst 324649999 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu0.data 3699266984 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.dtb.walker 999000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 350737499 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 4410468488 # number of overall miss cycles -system.l2c.overall_miss_latency::total 8786755970 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 34732 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 5724 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 404952 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 172428 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 54804 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 6733 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 621706 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 208951 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1510030 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 585034 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 585034 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 6745 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 5152 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 11897 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu0.data 997 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu1.data 755 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1752 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 111520 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 135884 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247404 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 34732 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 5724 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 404952 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 283948 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 54804 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 6733 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 621706 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 344835 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1757434 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 34732 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 5724 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 404952 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 283948 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 54804 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 6733 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 621706 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 344835 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1757434 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000524 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015029 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.036612 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.010608 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.030409 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016807 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.846553 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.844138 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.845507 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.789368 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.780132 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.785388 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567145 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.565836 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566426 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000524 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015029 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.244978 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.010608 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.241397 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.094180 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000259 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000524 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015029 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.244978 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000347 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.010608 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.241397 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.094180 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 54833.333333 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53343.739566 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu0.data 52507.444480 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53182.334951 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 52565.549103 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 52898.124197 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3589.223643 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 6291.561049 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 4757.576896 # average UpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2056.543837 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 11853.140917 # average SCUpgradeReq miss latency -system.l2c.SCUpgradeReq_avg_miss_latency::total 6250 # average SCUpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53247.335679 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 53018.247178 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 53121.642376 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.itb.walker 54833.333333 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.inst 53343.739566 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu0.data 53180.186944 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 53182.334951 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 52983.691982 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 53087.369544 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52166.666667 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.itb.walker 54833.333333 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.inst 53343.739566 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0.data 53180.186944 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52578.947368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 53182.334951 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 52983.691982 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 53087.369544 # average overall miss latency +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.061442 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.042680 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000182 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.055786 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.057136 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.822346 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 32914 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 5095 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 390213 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 166351 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 51484 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 5864 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 597704 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 198321 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1447946 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 581607 # number of Writeback hits +system.l2c.Writeback_hits::total 581607 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 1028 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 797 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 1825 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu0.data 197 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu1.data 161 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 358 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 48089 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 58157 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 106246 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 32914 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 5095 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 390213 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 214440 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 51484 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 5864 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 597704 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 256478 # number of demand (read+write) hits +system.l2c.demand_hits::total 1554192 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 32914 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 5095 # number of overall hits +system.l2c.overall_hits::cpu0.inst 390213 # number of overall hits +system.l2c.overall_hits::cpu0.data 214440 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 51484 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 5864 # number of overall hits +system.l2c.overall_hits::cpu1.inst 597704 # number of overall hits +system.l2c.overall_hits::cpu1.data 256478 # number of overall hits +system.l2c.overall_hits::total 1554192 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 10 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 6309 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6299 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 18 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 6265 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 6179 # number of ReadReq misses +system.l2c.ReadReq_misses::total 25082 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 5132 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 3726 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 8858 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu0.data 658 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu1.data 399 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1057 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 63592 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 76934 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140526 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 10 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 6309 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 69891 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 18 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 6265 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 83113 # number of demand (read+write) misses +system.l2c.demand_misses::total 165608 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 10 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 6309 # number of overall misses +system.l2c.overall_misses::cpu0.data 69891 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 18 # number of overall misses +system.l2c.overall_misses::cpu1.inst 6265 # number of overall misses +system.l2c.overall_misses::cpu1.data 83113 # number of overall misses +system.l2c.overall_misses::total 165608 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0.dtb.walker 521500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.itb.walker 112000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 336617000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.data 331223999 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 949000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 333434500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 325052500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 1327910499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0.data 20016979 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 27954998 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 47971977 # number of UpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu0.data 1517000 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::cpu1.data 7957998 # number of SCUpgradeReq miss cycles +system.l2c.SCUpgradeReq_miss_latency::total 9474998 # number of SCUpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 3416178492 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 4069563497 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7485741989 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.dtb.walker 521500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.itb.walker 112000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.inst 336617000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 3747402491 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 949000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 333434500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 4394615997 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 8813652488 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.dtb.walker 521500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.itb.walker 112000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.inst 336617000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 3747402491 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 949000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 333434500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 4394615997 # number of overall miss cycles +system.l2c.overall_miss_latency::total 8813652488 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 32924 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 5097 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 396522 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 172650 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 51502 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 5864 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 603969 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 204500 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1473028 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 581607 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 581607 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 6160 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4523 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10683 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 855 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 560 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1415 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 111681 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 135091 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246772 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 32924 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 5097 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 396522 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 284331 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 51502 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 5864 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 603969 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 339591 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1719800 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 32924 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 5097 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 396522 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 284331 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 51502 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 5864 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 603969 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 339591 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1719800 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000304 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000392 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015911 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036484 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000350 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.010373 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030215 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.017028 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.833117 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.823790 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.829168 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.769591 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.712500 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.746996 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.569408 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.569498 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.569457 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000304 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000392 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015911 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.245809 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000350 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.010373 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.244744 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.096295 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000304 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000392 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015911 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.245809 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000350 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.010373 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.244744 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.096295 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0.dtb.walker 52150 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.itb.walker 56000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 53355.048344 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.data 52583.584537 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 52722.222222 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 53221.787709 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52606.004208 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 52942.767682 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0.data 3900.424591 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 7502.683306 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 5415.666855 # average UpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu0.data 2305.471125 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::cpu1.data 19944.857143 # average SCUpgradeReq miss latency +system.l2c.SCUpgradeReq_avg_miss_latency::total 8964.047304 # average SCUpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53720.255567 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 52896.814113 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53269.444722 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.itb.walker 56000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.inst 53355.048344 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu0.data 53617.811893 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 52722.222222 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 53221.787709 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 52875.193977 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 53219.968166 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.dtb.walker 52150 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.itb.walker 56000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.inst 53355.048344 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0.data 53617.811893 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 52722.222222 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 53221.787709 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 52875.193977 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 53219.968166 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -323,168 +323,168 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 66482 # number of writebacks -system.l2c.writebacks::total 66482 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0.inst 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu0.data 38 # number of ReadReq MSHR hits +system.l2c.writebacks::writebacks 66832 # number of writebacks +system.l2c.writebacks::total 66832 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0.inst 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu0.data 37 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.inst 7 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::cpu1.data 24 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits -system.l2c.demand_mshr_hits::cpu0.inst 5 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu0.data 38 # number of demand (read+write) MSHR hits +system.l2c.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu0.inst 7 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu0.data 37 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.inst 7 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu1.data 24 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0.inst 5 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu0.data 38 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0.inst 7 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu0.data 37 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.inst 7 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu1.data 24 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 74 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 9 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 3 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.inst 6081 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu0.data 6275 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 19 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 6588 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 6330 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 25305 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0.data 5710 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 4349 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 10059 # number of UpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 787 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 589 # number of SCUpgradeReq MSHR misses -system.l2c.SCUpgradeReq_mshr_misses::total 1376 # number of SCUpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0.data 63248 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 76888 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 140136 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0.dtb.walker 9 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.itb.walker 3 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.inst 6081 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu0.data 69523 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.dtb.walker 19 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 6588 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 83218 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 165441 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0.dtb.walker 9 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.itb.walker 3 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.inst 6081 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu0.data 69523 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.dtb.walker 19 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 6588 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 83218 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 165441 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 360000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 128000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 250196499 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253577000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 768500 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 270011999 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 255801000 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 1030842998 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 228550000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 174127500 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 402677500 # number of UpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 31488000 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 23619500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.SCUpgradeReq_mshr_miss_latency::total 55107500 # number of SCUpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2598832997 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3131766991 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5730599988 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 360000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 128000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.inst 250196499 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0.data 2852409997 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 768500 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 270011999 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 3387567991 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 6761442986 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 360000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 128000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.inst 250196499 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0.data 2852409997 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 768500 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 270011999 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 3387567991 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 6761442986 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5530000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12326566000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2170500 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154699599000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 167033865500 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1153697499 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31138895772 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 32292593271 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5530000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13480263499 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2170500 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185838494772 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 199326458771 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036392 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030294 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016758 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.846553 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.844138 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.845507 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.789368 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.780132 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.785388 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.567145 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.565836 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.566426 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.094138 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000259 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000524 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015017 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.244844 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000347 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010597 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.241327 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.094138 # mshr miss rate for overall accesses +system.l2c.overall_mshr_hits::total 75 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0.dtb.walker 10 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.inst 6302 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu0.data 6262 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 18 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 6258 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 6155 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 25007 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0.data 5132 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 3726 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 8858 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu0.data 658 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu1.data 399 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1057 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0.data 63592 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 76934 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 140526 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0.dtb.walker 10 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.inst 6302 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu0.data 69854 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 18 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 6258 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 83089 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 165533 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0.dtb.walker 10 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.inst 6302 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu0.data 69854 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 18 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 6258 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 83089 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 165533 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0.dtb.walker 400000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.itb.walker 88000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 259390500 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.data 253074999 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 729000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 256738000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 248671000 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 1019091499 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 205375466 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 149167996 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 354543462 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu0.data 26341496 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu1.data 15988493 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 42329989 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 2637739492 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 3117564497 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 5755303989 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.dtb.walker 400000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.itb.walker 88000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 259390500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 2890814491 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 729000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 256738000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 3366235497 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 6774395488 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.dtb.walker 400000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.itb.walker 88000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.inst 259390500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 2890814491 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 729000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 256738000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 3366235497 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 6774395488 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.inst 5539000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0.data 12385867978 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.inst 2149000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 154396291480 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 166789847458 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 1090238997 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 31486348998 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 32576587995 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.inst 5539000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 13476106975 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.inst 2149000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 185882640478 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 199366435453 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036270 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.030098 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016977 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.833117 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.823790 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.829168 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.769591 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.712500 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.746996 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.569408 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.569498 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.569457 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.245678 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.244674 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.096251 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000304 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.000392 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.015893 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.245678 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000350 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.010361 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.244674 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.096251 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40410.677291 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40410.900474 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40736.731792 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40026.269702 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40038.514601 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40031.563774 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40010.165184 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40101.018676 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40049.055233 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41089.568002 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40731.544467 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40893.132300 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40414.404184 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40401.462226 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40752.249330 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40018.602104 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40034.352120 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40025.227139 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40032.668693 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40071.411028 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40047.293283 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 41479.108882 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40522.584254 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40955.438773 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 42666.666667 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41143.972866 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41028.292752 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40447.368421 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40985.427899 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40707.154594 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40869.210087 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 44000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 41160.028562 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 41383.664371 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 41025.567274 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40513.611874 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40924.743030 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -507,27 +507,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9084291 # DTB read hits -system.cpu0.dtb.read_misses 36586 # DTB read misses -system.cpu0.dtb.write_hits 5291622 # DTB write hits -system.cpu0.dtb.write_misses 6420 # DTB write misses +system.cpu0.dtb.read_hits 8992964 # DTB read hits +system.cpu0.dtb.read_misses 35495 # DTB read misses +system.cpu0.dtb.write_hits 5204763 # DTB write hits +system.cpu0.dtb.write_misses 6364 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2157 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1431 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 301 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 2149 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1250 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 357 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 545 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9120877 # DTB read accesses -system.cpu0.dtb.write_accesses 5298042 # DTB write accesses +system.cpu0.dtb.perms_faults 536 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 9028459 # DTB read accesses +system.cpu0.dtb.write_accesses 5211127 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14375913 # DTB hits -system.cpu0.dtb.misses 43006 # DTB misses -system.cpu0.dtb.accesses 14418919 # DTB accesses -system.cpu0.itb.inst_hits 4432740 # ITB inst hits -system.cpu0.itb.inst_misses 5766 # ITB inst misses +system.cpu0.dtb.hits 14197727 # DTB hits +system.cpu0.dtb.misses 41859 # DTB misses +system.cpu0.dtb.accesses 14239586 # DTB accesses +system.cpu0.itb.inst_hits 4345219 # ITB inst hits +system.cpu0.itb.inst_misses 5468 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -536,542 +536,538 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1406 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1393 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1571 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1660 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 4438506 # ITB inst accesses -system.cpu0.itb.hits 4432740 # DTB hits -system.cpu0.itb.misses 5766 # DTB misses -system.cpu0.itb.accesses 4438506 # DTB accesses -system.cpu0.numCycles 73427885 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 4350687 # ITB inst accesses +system.cpu0.itb.hits 4345219 # DTB hits +system.cpu0.itb.misses 5468 # DTB misses +system.cpu0.itb.accesses 4350687 # DTB accesses +system.cpu0.numCycles 69454344 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.BPredUnit.lookups 6227156 # Number of BP lookups -system.cpu0.BPredUnit.condPredicted 4741082 # Number of conditional branches predicted -system.cpu0.BPredUnit.condIncorrect 330435 # Number of conditional branches incorrect -system.cpu0.BPredUnit.BTBLookups 3793257 # Number of BTB lookups -system.cpu0.BPredUnit.BTBHits 3054809 # Number of BTB hits +system.cpu0.BPredUnit.lookups 6140299 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 4680843 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 325697 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 3967848 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 3011514 # Number of BTB hits system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.BPredUnit.usedRAS 703344 # Number of times the RAS was used to get a target. -system.cpu0.BPredUnit.RASInCorrect 32160 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 12941361 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 33277959 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 6227156 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 3758153 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 7819599 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 1599392 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 82441 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 23494459 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 5895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingTrapStallCycles 62047 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 92342 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 197 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 4430967 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 174323 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 2958 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 45648361 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.940627 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.320252 # Number of instructions fetched each cycle (Total) +system.cpu0.BPredUnit.usedRAS 689087 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 31971 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 11903950 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 32719278 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 6140299 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 3700601 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 7697719 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 1567081 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 66811 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 21663795 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 4784 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 55267 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 90495 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 192 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 4343360 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 170443 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 2579 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 42607741 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.991445 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.370542 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 37836918 82.89% 82.89% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 627349 1.37% 84.26% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 824369 1.81% 86.07% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 703980 1.54% 87.61% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 786046 1.72% 89.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 579188 1.27% 90.60% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 721067 1.58% 92.18% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 372009 0.81% 93.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 3197435 7.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34918154 81.95% 81.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 615023 1.44% 83.40% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 811777 1.91% 85.30% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 689946 1.62% 86.92% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 788421 1.85% 88.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 570027 1.34% 90.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 709248 1.66% 91.77% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 365635 0.86% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 3139510 7.37% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 45648361 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.084806 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.453206 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 13430389 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 23511343 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 7018661 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 602696 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1085272 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 979924 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 65913 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 41505511 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 215463 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1085272 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 14040409 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 6748642 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 14460031 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 6960379 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 2353628 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 40289777 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 2418 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 473813 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 1332712 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 81 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 40678861 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 182059364 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 182024641 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 34723 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 31700311 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 8978549 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 462421 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 418498 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 5663645 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 7939186 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 5895346 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1154000 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1239736 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 38066358 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 944329 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 38270432 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 91181 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 6810597 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 14485199 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 255192 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 45648361 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.838375 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.464052 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 42607741 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.088408 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.471090 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 12410407 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 21637687 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 6924723 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 574768 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1060156 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 960041 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 65781 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 40808812 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 215037 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1060156 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 12993427 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 5870248 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 13615125 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 6864393 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 2204392 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 39624437 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 2198 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 433654 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 1244123 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 41 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 39987634 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 178950817 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 178916692 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 34125 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 31114791 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 8872842 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 451750 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 410482 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 5405254 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 7790925 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5788375 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1121917 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1222446 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 37402937 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 939151 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 37702557 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 87742 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 6716452 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 14173286 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 260083 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 42607741 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.884876 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.498206 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 29755811 65.18% 65.18% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 6343756 13.90% 79.08% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3236490 7.09% 86.17% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 2520305 5.52% 91.69% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 2106581 4.61% 96.31% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 935116 2.05% 98.36% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 513948 1.13% 99.48% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 183643 0.40% 99.88% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 52711 0.12% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27166804 63.76% 63.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 5957097 13.98% 77.74% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3214078 7.54% 85.28% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 2477962 5.82% 91.10% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 2111115 4.95% 96.06% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 940986 2.21% 98.26% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 497762 1.17% 99.43% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 188040 0.44% 99.87% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 53897 0.13% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 45648361 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 42607741 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 27042 2.53% 2.53% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 464 0.04% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.57% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 835512 78.03% 80.60% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207702 19.40% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 24897 2.34% 2.34% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 455 0.04% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 2.38% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 841667 79.11% 81.49% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 196890 18.51% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 52344 0.14% 0.14% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 22977707 60.04% 60.18% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 50299 0.13% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 12 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 9 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 682 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 9565645 24.99% 85.31% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 5623724 14.69% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 52279 0.14% 0.14% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 22610692 59.97% 60.11% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 48707 0.13% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 1 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 10 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 2 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 7 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 696 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.24% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 9470500 25.12% 85.36% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5519656 14.64% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 38270432 # Type of FU issued -system.cpu0.iq.rate 0.521198 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 1070720 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.027978 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 123385364 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 45829388 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 35329971 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 8465 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 4764 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 3918 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 39284390 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 4418 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 323676 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 37702557 # Type of FU issued +system.cpu0.iq.rate 0.542839 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 1063909 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.028218 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 119197860 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 45066260 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 34725350 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 8284 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 4664 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 3878 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 38709880 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 4307 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 311315 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 1511954 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3775 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 13508 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 616210 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 1483597 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3551 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 13024 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 603760 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 2149507 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 5450 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 2189792 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5367 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1085272 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 4652854 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 126877 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 39130245 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 91852 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 7939186 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 5895346 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 610877 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 49621 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 17387 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 13508 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 175421 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 130280 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 305701 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 37846246 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 9402583 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 424186 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1060156 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 4217100 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 98020 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 38461133 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 95338 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 7790925 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5788375 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 610075 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 39436 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 2994 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 13024 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 172050 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 129143 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 301193 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 37281122 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 9309198 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 421435 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 119558 # number of nop insts executed -system.cpu0.iew.exec_refs 14967440 # number of memory reference insts executed -system.cpu0.iew.exec_branches 4996145 # Number of branches executed -system.cpu0.iew.exec_stores 5564857 # Number of stores executed -system.cpu0.iew.exec_rate 0.515421 # Inst execution rate -system.cpu0.iew.wb_sent 37628600 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 35333889 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 18696932 # num instructions producing a value -system.cpu0.iew.wb_consumers 35648829 # num instructions consuming a value +system.cpu0.iew.exec_nop 119045 # number of nop insts executed +system.cpu0.iew.exec_refs 14772448 # number of memory reference insts executed +system.cpu0.iew.exec_branches 4922535 # Number of branches executed +system.cpu0.iew.exec_stores 5463250 # Number of stores executed +system.cpu0.iew.exec_rate 0.536772 # Inst execution rate +system.cpu0.iew.wb_sent 37065432 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 34729228 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 18441672 # num instructions producing a value +system.cpu0.iew.wb_consumers 35371865 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.481205 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.524475 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.500030 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.521366 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 6705821 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 689137 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 265687 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 44599494 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.717911 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.673991 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 6577828 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 679068 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 261125 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 41583448 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.756316 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.712971 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32451965 72.76% 72.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6077972 13.63% 86.39% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 1948934 4.37% 90.76% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1034999 2.32% 93.08% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 805126 1.81% 94.89% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 506776 1.14% 96.02% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 402342 0.90% 96.93% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 201836 0.45% 97.38% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1169544 2.62% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 29716852 71.46% 71.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 5893148 14.17% 85.64% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 1935709 4.65% 90.29% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 983715 2.37% 92.66% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 787040 1.89% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 514741 1.24% 95.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 394337 0.95% 96.73% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 216625 0.52% 97.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1141281 2.74% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 44599494 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 24278814 # Number of instructions committed -system.cpu0.commit.committedOps 32018477 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 41583448 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 23837222 # Number of instructions committed +system.cpu0.commit.committedOps 31450221 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 11706368 # Number of memory references committed -system.cpu0.commit.loads 6427232 # Number of loads committed -system.cpu0.commit.membars 234590 # Number of memory barriers committed -system.cpu0.commit.branches 4349138 # Number of branches committed +system.cpu0.commit.refs 11491943 # Number of memory references committed +system.cpu0.commit.loads 6307328 # Number of loads committed +system.cpu0.commit.membars 231960 # Number of memory barriers committed +system.cpu0.commit.branches 4279027 # Number of branches committed system.cpu0.commit.fp_insts 3838 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 28284672 # Number of committed integer instructions. -system.cpu0.commit.function_calls 500279 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1169544 # number cycles where commit BW limit reached +system.cpu0.commit.int_insts 27769802 # Number of committed integer instructions. +system.cpu0.commit.function_calls 489719 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1141281 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 81269635 # The number of ROB reads -system.cpu0.rob.rob_writes 78536158 # The number of ROB writes -system.cpu0.timesIdled 427323 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 27779524 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 5160286096 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 24198072 # Number of Instructions Simulated -system.cpu0.committedOps 31937735 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 24198072 # Number of Instructions Simulated -system.cpu0.cpi 3.034452 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 3.034452 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.329549 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.329549 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 176614966 # number of integer regfile reads -system.cpu0.int_regfile_writes 35097459 # number of integer regfile writes -system.cpu0.fp_regfile_reads 3370 # number of floating regfile reads -system.cpu0.fp_regfile_writes 922 # number of floating regfile writes -system.cpu0.misc_regfile_reads 47564974 # number of misc regfile reads -system.cpu0.misc_regfile_writes 527822 # number of misc regfile writes -system.cpu0.icache.replacements 405114 # number of replacements -system.cpu0.icache.tagsinuse 511.561657 # Cycle average of tags in use -system.cpu0.icache.total_refs 3991755 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 405626 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 9.840974 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 7272099000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.561657 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999144 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 3991755 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 3991755 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 3991755 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 3991755 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 3991755 # number of overall hits -system.cpu0.icache.overall_hits::total 3991755 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 439070 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 439070 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 439070 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 439070 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 439070 # number of overall misses -system.cpu0.icache.overall_misses::total 439070 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7078203996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7078203996 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7078203996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7078203996 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7078203996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7078203996 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 4430825 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 4430825 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 4430825 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 4430825 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 4430825 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 4430825 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.099094 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.099094 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.099094 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.099094 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.099094 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.099094 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 16120.900986 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 16120.900986 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 16120.900986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 16120.900986 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 16120.900986 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 1491997 # number of cycles access was blocked +system.cpu0.rob.rob_reads 77601886 # The number of ROB reads +system.cpu0.rob.rob_writes 77118702 # The number of ROB writes +system.cpu0.timesIdled 360842 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 26846603 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 1938505291 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 23756480 # Number of Instructions Simulated +system.cpu0.committedOps 31369479 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 23756480 # Number of Instructions Simulated +system.cpu0.cpi 2.923596 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 2.923596 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.342045 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.342045 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 173851540 # number of integer regfile reads +system.cpu0.int_regfile_writes 34503400 # number of integer regfile writes +system.cpu0.fp_regfile_reads 3265 # number of floating regfile reads +system.cpu0.fp_regfile_writes 914 # number of floating regfile writes +system.cpu0.misc_regfile_reads 46745590 # number of misc regfile reads +system.cpu0.misc_regfile_writes 520572 # number of misc regfile writes +system.cpu0.icache.replacements 396597 # number of replacements +system.cpu0.icache.tagsinuse 510.934010 # Cycle average of tags in use +system.cpu0.icache.total_refs 3914161 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 397109 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 9.856641 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 7097415000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 510.934010 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.997918 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.997918 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 3914161 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 3914161 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 3914161 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 3914161 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 3914161 # number of overall hits +system.cpu0.icache.overall_hits::total 3914161 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 429060 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 429060 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 429060 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 429060 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 429060 # number of overall misses +system.cpu0.icache.overall_misses::total 429060 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5859924996 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5859924996 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5859924996 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5859924996 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5859924996 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5859924996 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 4343221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 4343221 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 4343221 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 4343221 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 4343221 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 4343221 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.098788 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.098788 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.098788 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.098788 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.098788 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.098788 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13657.588673 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13657.588673 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13657.588673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13657.588673 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13657.588673 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 2603 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 170 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 172 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 8776.452941 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15.133721 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 33429 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 33429 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu0.inst 33429 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 33429 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu0.inst 33429 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 33429 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 405641 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 405641 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 405641 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 405641 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 405641 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 405641 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5425368997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5425368997 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5425368997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5425368997 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5425368997 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5425368997 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8328000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8328000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8328000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.overall_mshr_uncacheable_latency::total 8328000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091550 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.091550 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091550 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.091550 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 13374.804315 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 13374.804315 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 13374.804315 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 31940 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 31940 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 31940 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 31940 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 31940 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 31940 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 397120 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 397120 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 397120 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 397120 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 397120 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 397120 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4781055496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4781055496 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4781055496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4781055496 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4781055496 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 8271000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 8271000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 8271000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.overall_mshr_uncacheable_latency::total 8271000 # number of overall MSHR uncacheable cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.091434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.091434 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.091434 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.091434 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12039.321857 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12039.321857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12039.321857 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12039.321857 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 275935 # number of replacements -system.cpu0.dcache.tagsinuse 476.765535 # Cycle average of tags in use -system.cpu0.dcache.total_refs 9559328 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 276447 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 34.579243 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 51426000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 476.765535 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.931183 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.931183 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5939119 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5939119 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3227738 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3227738 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174834 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 174834 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171593 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 171593 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 9166857 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 9166857 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 9166857 # number of overall hits -system.cpu0.dcache.overall_hits::total 9166857 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 401304 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 401304 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 1595717 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1595717 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8980 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 8980 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7781 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7781 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 1997021 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1997021 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 1997021 # number of overall misses -system.cpu0.dcache.overall_misses::total 1997021 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7282608500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 7282608500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 71716653343 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 71716653343 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 113510500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 113510500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 89966000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 89966000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 78999261843 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 78999261843 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 78999261843 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 78999261843 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 6340423 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 6340423 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 4823455 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 4823455 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183814 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 183814 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 179374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 179374 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 11163878 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 11163878 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 11163878 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 11163878 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.063293 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.063293 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.330824 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.330824 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048854 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048854 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.043379 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.043379 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.178882 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.178882 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.178882 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.178882 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 18147.360854 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 18147.360854 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 44943.215710 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 44943.215710 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 12640.367483 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 12640.367483 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 11562.267061 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 11562.267061 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 39558.553387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 39558.553387 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 39558.553387 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7775987 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1662000 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1508 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 96 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 5156.490053 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 17312.500000 # average number of cycles each access was blocked +system.cpu0.dcache.replacements 275715 # number of replacements +system.cpu0.dcache.tagsinuse 460.505640 # Cycle average of tags in use +system.cpu0.dcache.total_refs 9383873 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 276227 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 33.971599 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 50121000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 460.505640 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.899425 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.899425 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5832717 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5832717 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3162819 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3162819 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 174349 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 174349 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 171411 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 171411 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 8995536 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8995536 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8995536 # number of overall hits +system.cpu0.dcache.overall_hits::total 8995536 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 389324 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 389324 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 1581862 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 1581862 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 8809 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 8809 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7464 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7464 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 1971186 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1971186 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 1971186 # number of overall misses +system.cpu0.dcache.overall_misses::total 1971186 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 5380617500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5380617500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 64543979864 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 64543979864 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 88840500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 88840500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 65914500 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 65914500 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 69924597364 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 69924597364 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 69924597364 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 69924597364 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6222041 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6222041 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4744681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4744681 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 183158 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 183158 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 178875 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 178875 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 10966722 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 10966722 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 10966722 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 10966722 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.062572 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.062572 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.333397 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.333397 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.048095 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.048095 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.041727 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.041727 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.179742 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.179742 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.179742 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.179742 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13820.410506 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13820.410506 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 40802.535154 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 40802.535154 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10085.196958 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10085.196958 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 8830.988746 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 8830.988746 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 35473.363429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35473.363429 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 35473.363429 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7710 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 3643 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 580 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 95 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.293103 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 38.347368 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 256111 # number of writebacks -system.cpu0.dcache.writebacks::total 256111 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 211639 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 211639 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1464558 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 1464558 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 529 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 529 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu0.data 1676197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1676197 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu0.data 1676197 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1676197 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189665 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 189665 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 131159 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 131159 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8451 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7774 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7774 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 320824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 320824 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 320824 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 320824 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2812273446 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2812273446 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4676498504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4676498504 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 79208005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 79208005 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 65545528 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 65545528 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::cpu0.data 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.StoreCondFailReq_mshr_miss_latency::total 2000 # number of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7488771950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7488771950 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7488771950 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7488771950 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13454662000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13454662000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1295219899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1295219899 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14749881899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14749881899 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.029914 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.029914 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027192 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045976 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.043340 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.043340 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.028738 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.028738 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.028738 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 14827.582559 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14827.582559 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35655.185721 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35655.185721 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 9372.619217 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 9372.619217 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 8431.377412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 8431.377412 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 23342.305906 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 23342.305906 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 256563 # number of writebacks +system.cpu0.dcache.writebacks::total 256563 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 201019 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 201019 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1451459 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1451459 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 444 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 444 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 1652478 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1652478 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 1652478 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1652478 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 188305 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 188305 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 130403 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 130403 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 8365 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 8365 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7460 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 318708 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 318708 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 318708 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 318708 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2330576500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2330576500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4457768490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4457768490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 67402500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 67402500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 50994500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 50994500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6788344990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 6788344990 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6788344990 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 6788344990 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13509879500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13509879500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1216585395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1216585395 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 14726464895 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14726464895 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.030264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.030264 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.027484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.027484 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.045671 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.045671 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.041705 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.041705 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029061 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029061 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029061 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12376.604445 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12376.604445 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 34184.554727 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34184.554727 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 8057.680813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8057.680813 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6835.723861 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6835.723861 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 21299.575128 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21299.575128 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -1081,27 +1077,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 43437526 # DTB read hits -system.cpu1.dtb.read_misses 44897 # DTB read misses -system.cpu1.dtb.write_hits 7020721 # DTB write hits -system.cpu1.dtb.write_misses 11707 # DTB write misses +system.cpu1.dtb.read_hits 43128318 # DTB read hits +system.cpu1.dtb.read_misses 43709 # DTB read misses +system.cpu1.dtb.write_hits 6848528 # DTB write hits +system.cpu1.dtb.write_misses 11704 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 2363 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 4220 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 316 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 3032 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 376 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 641 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 43482423 # DTB read accesses -system.cpu1.dtb.write_accesses 7032428 # DTB write accesses +system.cpu1.dtb.perms_faults 614 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 43172027 # DTB read accesses +system.cpu1.dtb.write_accesses 6860232 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 50458247 # DTB hits -system.cpu1.dtb.misses 56604 # DTB misses -system.cpu1.dtb.accesses 50514851 # DTB accesses -system.cpu1.itb.inst_hits 9182577 # ITB inst hits -system.cpu1.itb.inst_misses 6227 # ITB inst misses +system.cpu1.dtb.hits 49976846 # DTB hits +system.cpu1.dtb.misses 55413 # DTB misses +system.cpu1.dtb.accesses 50032259 # DTB accesses +system.cpu1.itb.inst_hits 9000425 # ITB inst hits +system.cpu1.itb.inst_misses 6008 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1110,538 +1106,542 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1587 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1553 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1649 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1639 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 9188804 # ITB inst accesses -system.cpu1.itb.hits 9182577 # DTB hits -system.cpu1.itb.misses 6227 # DTB misses -system.cpu1.itb.accesses 9188804 # DTB accesses -system.cpu1.numCycles 420121858 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 9006433 # ITB inst accesses +system.cpu1.itb.hits 9000425 # DTB hits +system.cpu1.itb.misses 6008 # DTB misses +system.cpu1.itb.accesses 9006433 # DTB accesses +system.cpu1.numCycles 411196854 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 9688118 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 7965440 # Number of conditional branches predicted -system.cpu1.BPredUnit.condIncorrect 469703 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 6737081 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 5659691 # Number of BTB hits +system.cpu1.BPredUnit.lookups 9419862 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 7750034 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 456519 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 6563236 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 5515830 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.BPredUnit.usedRAS 834304 # Number of times the RAS was used to get a target. -system.cpu1.BPredUnit.RASInCorrect 51249 # Number of incorrect RAS predictions. -system.cpu1.fetch.icacheStallCycles 22081738 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 71759711 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 9688118 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 6493995 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 15294978 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 4586075 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 88967 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 80951772 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 5897 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingTrapStallCycles 52783 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 142728 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 134 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 9180482 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 856181 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 3761 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 121742103 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.711584 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.060066 # Number of instructions fetched each cycle (Total) +system.cpu1.BPredUnit.usedRAS 808543 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 49558 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 20407169 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 70137907 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 9419862 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 6324373 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 14954252 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 4469714 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 69962 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 78537497 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4608 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 48031 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 137349 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 105 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 8998373 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 846947 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 3472 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 117207584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.722166 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.072596 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 106455334 87.44% 87.44% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 840434 0.69% 88.13% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 1014558 0.83% 88.97% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 2075766 1.71% 90.67% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1622971 1.33% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 608124 0.50% 92.50% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 2270082 1.86% 94.37% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 458736 0.38% 94.75% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 6396098 5.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 102261187 87.25% 87.25% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 819653 0.70% 87.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 985556 0.84% 88.79% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 2033886 1.74% 90.52% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1605966 1.37% 91.89% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 588504 0.50% 92.40% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 2242580 1.91% 94.31% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 432923 0.37% 94.68% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 6237329 5.32% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 121742103 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.023060 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.170807 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 23726811 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 80682083 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 13746238 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 564864 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 3022107 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 1180909 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 102849 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 80937245 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 340282 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 3022107 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 25270664 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 33976360 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 42200569 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 12677087 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 4595316 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 74576204 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 20275 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 711120 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 3286160 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 33636 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 79110058 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 343673709 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 343614714 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 58995 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 50196787 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 28913271 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 480316 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 419400 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 8402630 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 14031046 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 8540774 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 1078770 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1484758 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 67259946 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 1207834 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 91753969 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 112690 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 18841154 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 53684147 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 287920 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 121742103 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.753675 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.492082 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 117207584 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.022908 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.170570 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 22086254 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 78170196 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 13474165 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 527031 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 2949938 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 1142917 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 100567 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 79224649 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 333390 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 2949938 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 23604711 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 32726720 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 41122515 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 12389079 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 4414621 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 72870010 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 19270 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 676690 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 3162757 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 33999 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 77285870 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 335898709 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 335839792 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 58917 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 49079142 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 28206728 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 460869 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 403889 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 7994466 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 13706939 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 8341114 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 1036889 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1489334 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 65799753 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1184242 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 90434427 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 105475 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 18495331 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 52692216 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 284904 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 117207584 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.771575 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.509324 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 89993106 73.92% 73.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 9114072 7.49% 81.41% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 4553910 3.74% 85.15% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 4000568 3.29% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 10707495 8.80% 97.23% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1970764 1.62% 98.85% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 1044074 0.86% 99.71% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 282783 0.23% 99.94% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 75331 0.06% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 86216438 73.56% 73.56% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 8629120 7.36% 80.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 4443515 3.79% 84.71% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 3900369 3.33% 88.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 10705508 9.13% 97.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1918417 1.64% 98.81% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 1028985 0.88% 99.69% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 292713 0.25% 99.94% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 72519 0.06% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 121742103 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 117207584 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 28572 0.36% 0.36% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 997 0.01% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 7569076 95.94% 96.31% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 290938 3.69% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 27077 0.34% 0.34% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 994 0.01% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.36% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 7551420 96.03% 96.39% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 284170 3.61% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 313802 0.34% 0.34% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 39340328 42.88% 43.22% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 61412 0.07% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 6 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 2 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 3 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.28% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 1696 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.29% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 44630775 48.64% 91.93% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 7405942 8.07% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 313737 0.35% 0.35% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 38536009 42.61% 42.96% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 59463 0.07% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 9 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 3 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 7 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 43.02% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 1448 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 7 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 43.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 44313821 49.00% 92.03% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 7209923 7.97% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 91753969 # Type of FU issued -system.cpu1.iq.rate 0.218398 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 7889583 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.085986 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 313294010 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 87318397 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 55594578 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 14739 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 8070 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 6796 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 99322053 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 7697 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 360033 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 90434427 # Type of FU issued +system.cpu1.iq.rate 0.219930 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 7863661 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.086954 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 306085964 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 85487883 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 54343960 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 14808 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 8052 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 6813 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 97976579 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 7772 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 344186 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 4037305 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 4422 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 18147 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 1519259 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 3955729 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 4256 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 17131 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 1493245 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 31965400 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 1049364 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 31918877 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 1021818 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 3022107 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 25590166 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 410250 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 68573370 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 132853 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 14031046 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 8540774 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 897358 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 85617 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 14991 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 18147 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 245880 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 172266 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 418146 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 88914677 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 43821187 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 2839292 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 2949938 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 24820563 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 368762 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 67089139 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 132396 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 13706939 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 8341114 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 882128 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 65563 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3455 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 17131 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 238596 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 168339 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 406935 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 87595702 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 43496570 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 2838725 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 105590 # number of nop insts executed -system.cpu1.iew.exec_refs 51148287 # number of memory reference insts executed -system.cpu1.iew.exec_branches 7278596 # Number of branches executed -system.cpu1.iew.exec_stores 7327100 # Number of stores executed -system.cpu1.iew.exec_rate 0.211640 # Inst execution rate -system.cpu1.iew.wb_sent 87750200 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 55601374 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 30754041 # num instructions producing a value -system.cpu1.iew.wb_consumers 54503523 # num instructions consuming a value +system.cpu1.iew.exec_nop 105144 # number of nop insts executed +system.cpu1.iew.exec_refs 50630638 # number of memory reference insts executed +system.cpu1.iew.exec_branches 7094868 # Number of branches executed +system.cpu1.iew.exec_stores 7134068 # Number of stores executed +system.cpu1.iew.exec_rate 0.213026 # Inst execution rate +system.cpu1.iew.wb_sent 86451134 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 54350773 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 30183399 # num instructions producing a value +system.cpu1.iew.wb_consumers 53726330 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.132346 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.564258 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.132177 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.561799 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 18816555 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 919914 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 368704 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 118768431 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.415231 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.371949 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 18453809 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 899338 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 357846 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 114304625 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.421644 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.382099 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 101503583 85.46% 85.46% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 8523872 7.18% 92.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 2201888 1.85% 94.49% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 1303888 1.10% 95.59% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 1288434 1.08% 96.68% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 587085 0.49% 97.17% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 997227 0.84% 98.01% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 495127 0.42% 98.43% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1867327 1.57% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 97479553 85.28% 85.28% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 8276936 7.24% 92.52% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 2163829 1.89% 94.41% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1249082 1.09% 95.51% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 1246649 1.09% 96.60% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 573488 0.50% 97.10% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 1001794 0.88% 97.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 527131 0.46% 98.44% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1786163 1.56% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 118768431 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 38949066 # Number of instructions committed -system.cpu1.commit.committedOps 49316340 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 114304625 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 38098697 # Number of instructions committed +system.cpu1.commit.committedOps 48195861 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 17015256 # Number of memory references committed -system.cpu1.commit.loads 9993741 # Number of loads committed -system.cpu1.commit.membars 202364 # Number of memory barriers committed -system.cpu1.commit.branches 6138465 # Number of branches committed +system.cpu1.commit.refs 16599079 # Number of memory references committed +system.cpu1.commit.loads 9751210 # Number of loads committed +system.cpu1.commit.membars 196398 # Number of memory barriers committed +system.cpu1.commit.branches 5978782 # Number of branches committed system.cpu1.commit.fp_insts 6758 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 43706861 # Number of committed integer instructions. -system.cpu1.commit.function_calls 556456 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1867327 # number cycles where commit BW limit reached +system.cpu1.commit.int_insts 42713997 # Number of committed integer instructions. +system.cpu1.commit.function_calls 536442 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1786163 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 183919327 # The number of ROB reads -system.cpu1.rob.rob_writes 139377269 # The number of ROB writes -system.cpu1.timesIdled 1519096 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 298379755 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 4813097636 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 38879427 # Number of Instructions Simulated -system.cpu1.committedOps 49246701 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 38879427 # Number of Instructions Simulated -system.cpu1.cpi 10.805763 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 10.805763 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.092543 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.092543 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 397952991 # number of integer regfile reads -system.cpu1.int_regfile_writes 58412580 # number of integer regfile writes -system.cpu1.fp_regfile_reads 4851 # number of floating regfile reads -system.cpu1.fp_regfile_writes 2298 # number of floating regfile writes -system.cpu1.misc_regfile_reads 91535746 # number of misc regfile reads -system.cpu1.misc_regfile_writes 429838 # number of misc regfile writes -system.cpu1.icache.replacements 621848 # number of replacements -system.cpu1.icache.tagsinuse 498.728003 # Cycle average of tags in use -system.cpu1.icache.total_refs 8507924 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 622360 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 13.670422 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 75775782000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 498.728003 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.974078 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.974078 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 8507924 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 8507924 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 8507924 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 8507924 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 8507924 # number of overall hits -system.cpu1.icache.overall_hits::total 8507924 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 672506 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 672506 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 672506 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 672506 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 672506 # number of overall misses -system.cpu1.icache.overall_misses::total 672506 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10595189995 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 10595189995 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 10595189995 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 10595189995 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 10595189995 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 10595189995 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 9180430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 9180430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 9180430 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 9180430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 9180430 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 9180430 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.073254 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.073254 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.073254 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.073254 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.073254 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.073254 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 15754.788797 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 15754.788797 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 15754.788797 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15754.788797 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 15754.788797 # average overall miss latency -system.cpu1.icache.blocked_cycles::no_mshrs 1171995 # number of cycles access was blocked +system.cpu1.rob.rob_reads 178079063 # The number of ROB reads +system.cpu1.rob.rob_writes 136331127 # The number of ROB writes +system.cpu1.timesIdled 1409981 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 293989270 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 1596154251 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 38029058 # Number of Instructions Simulated +system.cpu1.committedOps 48126222 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 38029058 # Number of Instructions Simulated +system.cpu1.cpi 10.812702 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 10.812702 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.092484 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.092484 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 391789649 # number of integer regfile reads +system.cpu1.int_regfile_writes 57184516 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4895 # number of floating regfile reads +system.cpu1.fp_regfile_writes 2332 # number of floating regfile writes +system.cpu1.misc_regfile_reads 89371872 # number of misc regfile reads +system.cpu1.misc_regfile_writes 414539 # number of misc regfile writes +system.cpu1.icache.replacements 604043 # number of replacements +system.cpu1.icache.tagsinuse 477.396851 # Cycle average of tags in use +system.cpu1.icache.total_refs 8346622 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 604555 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 13.806224 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 74944474500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 477.396851 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.932416 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.932416 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 8346622 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 8346622 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 8346622 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 8346622 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 8346622 # number of overall hits +system.cpu1.icache.overall_hits::total 8346622 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 651698 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 651698 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 651698 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 651698 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 651698 # number of overall misses +system.cpu1.icache.overall_misses::total 651698 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 8706583495 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 8706583495 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 8706583495 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 8706583495 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 8706583495 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 8706583495 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 8998320 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 8998320 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 8998320 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 8998320 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 8998320 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 8998320 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.072424 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.072424 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.072424 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.072424 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.072424 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.072424 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13359.843816 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13359.843816 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13359.843816 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13359.843816 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13359.843816 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 1860 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 180 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 164 # number of cycles access was blocked system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs 6511.083333 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 11.341463 # average number of cycles each access was blocked system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 50115 # number of ReadReq MSHR hits -system.cpu1.icache.ReadReq_mshr_hits::total 50115 # number of ReadReq MSHR hits -system.cpu1.icache.demand_mshr_hits::cpu1.inst 50115 # number of demand (read+write) MSHR hits -system.cpu1.icache.demand_mshr_hits::total 50115 # number of demand (read+write) MSHR hits -system.cpu1.icache.overall_mshr_hits::cpu1.inst 50115 # number of overall MSHR hits -system.cpu1.icache.overall_mshr_hits::total 50115 # number of overall MSHR hits -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 622391 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 622391 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 622391 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 622391 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 622391 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 622391 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8107387995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8107387995 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8107387995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8107387995 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8107387995 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8107387995 # number of overall MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3209000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3209000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.overall_mshr_uncacheable_latency::total 3209000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067795 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.067795 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067795 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.067795 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 13026.197350 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 13026.197350 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 13026.197350 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 13026.197350 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 47118 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 47118 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 47118 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 47118 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 47118 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 47118 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 604580 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 604580 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 604580 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 604580 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 604580 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 604580 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 7117577996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 7117577996 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 7117577996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 7117577996 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 7117577996 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 7117577996 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 3208500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 3208500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 3208500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.overall_mshr_uncacheable_latency::total 3208500 # number of overall MSHR uncacheable cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.067188 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.067188 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.067188 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.067188 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11772.764557 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11772.764557 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11772.764557 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 364389 # number of replacements -system.cpu1.dcache.tagsinuse 487.304887 # Cycle average of tags in use -system.cpu1.dcache.total_refs 13108660 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 364763 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 35.937472 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 71473892000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 487.304887 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.951767 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.951767 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 8608527 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 8608527 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4253626 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4253626 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 105088 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 105088 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 100770 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 100770 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 12862153 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 12862153 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 12862153 # number of overall hits -system.cpu1.dcache.overall_hits::total 12862153 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 413506 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 413506 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 1597634 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 1597634 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14294 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 14294 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10915 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10915 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 2011140 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 2011140 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 2011140 # number of overall misses -system.cpu1.dcache.overall_misses::total 2011140 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8210381000 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 8210381000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 66162469729 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 66162469729 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 166851000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 166851000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 95119500 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 95119500 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 74372850729 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 74372850729 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 74372850729 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 74372850729 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 9022033 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 9022033 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 5851260 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 5851260 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 119382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 119382 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 111685 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 111685 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 14873293 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 14873293 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 14873293 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 14873293 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.045833 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.045833 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.273041 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.273041 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119733 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097730 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097730 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.135218 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.135218 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.135218 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.135218 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19855.530512 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 19855.530512 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 41412.782733 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 41412.782733 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 11672.799776 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 11672.799776 # average LoadLockedReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 8714.567109 # average StoreCondReq miss latency -system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 8714.567109 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 36980.444290 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 36980.444290 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 36980.444290 # average overall miss latency -system.cpu1.dcache.blocked_cycles::no_mshrs 29857004 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 5566500 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 6768 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 168 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs 4411.495863 # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets 33133.928571 # average number of cycles each access was blocked +system.cpu1.dcache.replacements 360631 # number of replacements +system.cpu1.dcache.tagsinuse 472.241123 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12789913 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 361011 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 35.428042 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 71012585000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 472.241123 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.922346 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.922346 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 8401496 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 8401496 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4150430 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4150430 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 102060 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 102060 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 98301 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 98301 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12551926 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12551926 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12551926 # number of overall hits +system.cpu1.dcache.overall_hits::total 12551926 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 394540 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 394540 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 1551061 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 1551061 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 14054 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 14054 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10582 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10582 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 1945601 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 1945601 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 1945601 # number of overall misses +system.cpu1.dcache.overall_misses::total 1945601 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 5828870500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 5828870500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 56343693023 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 56343693023 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 129108000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 129108000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 64979500 # number of StoreCondReq miss cycles +system.cpu1.dcache.StoreCondReq_miss_latency::total 64979500 # number of StoreCondReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 62172563523 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 62172563523 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 62172563523 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 62172563523 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 8796036 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 8796036 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 5701491 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 5701491 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 116114 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 116114 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 108883 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 108883 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 14497527 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 14497527 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 14497527 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 14497527 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.044854 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.044854 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.272045 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.272045 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.121036 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.121036 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.097187 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.097187 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.134202 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.134202 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.134202 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.134202 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14773.839154 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14773.839154 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36325.904025 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 36325.904025 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 9186.566102 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 9186.566102 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 6140.568891 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 6140.568891 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 31955.454136 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31955.454136 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 31955.454136 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 23777 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 10847 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 3216 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 162 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs 7.393346 # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets 66.956790 # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 328923 # number of writebacks -system.cpu1.dcache.writebacks::total 328923 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 180962 # number of ReadReq MSHR hits -system.cpu1.dcache.ReadReq_mshr_hits::total 180962 # number of ReadReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1434656 # number of WriteReq MSHR hits -system.cpu1.dcache.WriteReq_mshr_hits::total 1434656 # number of WriteReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1453 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1453 # number of LoadLockedReq MSHR hits -system.cpu1.dcache.demand_mshr_hits::cpu1.data 1615618 # number of demand (read+write) MSHR hits -system.cpu1.dcache.demand_mshr_hits::total 1615618 # number of demand (read+write) MSHR hits -system.cpu1.dcache.overall_mshr_hits::cpu1.data 1615618 # number of overall MSHR hits -system.cpu1.dcache.overall_mshr_hits::total 1615618 # number of overall MSHR hits -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 232544 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 232544 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 162978 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 162978 # number of WriteReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12841 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12841 # number of LoadLockedReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.StoreCondReq_mshr_misses::total 10909 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 395522 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 395522 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 395522 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 395522 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 3583215887 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 3583215887 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5542320073 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5542320073 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 104521007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 104521007 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 61064509 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 61064509 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 9125535960 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 9125535960 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 9125535960 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 9125535960 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 169307109000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 169307109000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40930247169 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40930247169 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 210237356169 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 210237356169 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025775 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025775 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.027853 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.107562 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.107562 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097677 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097677 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026593 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026593 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026593 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15408.765167 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 15408.765167 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34006.553480 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 34006.553480 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 8139.631415 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 8139.631415 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5597.626639 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5597.626639 # average StoreCondReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 23072.132422 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 23072.132422 # average overall mshr miss latency +system.cpu1.dcache.writebacks::writebacks 325044 # number of writebacks +system.cpu1.dcache.writebacks::total 325044 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 165979 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 165979 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1389692 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1389692 # number of WriteReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 1430 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.LoadLockedReq_mshr_hits::total 1430 # number of LoadLockedReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 1555671 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 1555671 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 1555671 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 1555671 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 228561 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 228561 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 161369 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 161369 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 12624 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 12624 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10579 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10579 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 389930 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 389930 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 389930 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 389930 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 2788566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 2788566500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 5142243728 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 5142243728 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 88146000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 88146000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 43823500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 43823500 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7930810228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7930810228 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7930810228 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7930810228 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168983572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168983572500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 40847570579 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 40847570579 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 209831143079 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 209831143079 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.025985 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.025985 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.028303 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.028303 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.108721 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.108721 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.097159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.097159 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026896 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026896 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026896 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12200.535087 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12200.535087 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31866.366700 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31866.366700 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6982.414449 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6982.414449 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 4142.499291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 4142.499291 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20339.061442 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20339.061442 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1663,18 +1663,18 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1322950372611 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1322950372611 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1322950372611 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479854932995 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 479854932995 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479854932995 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 479854932995 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 43807 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 43104 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 53930 # number of quiesce instructions executed +system.cpu1.kern.inst.quiesce 52217 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |