diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-07-04 10:43:47 -0500 |
| commit | 9954eb74df98c4749651eb78098595f78d642105 (patch) | |
| tree | 74766341f05f999e2ad00626284e09dc6d0a2c58 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr | |
| parent | 67925a833445a8b2ddce0fae4c86677ce0f4298d (diff) | |
| download | gem5-9954eb74df98c4749651eb78098595f78d642105.tar.xz | |
stats: update stale config.ini files, eio and few other stats.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr')
| -rwxr-xr-x | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr index ab972f12d..7a0ceb162 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simerr @@ -8,6 +8,8 @@ warn: Not doing anything for write of miscreg ACTLR warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] +warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented |