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authorAli Saidi <Ali.Saidi@ARM.com>2013-02-15 17:40:14 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2013-02-15 17:40:14 -0500
commitbd31a5dc18def5972967a595d65266d1f9ff05cb (patch)
tree62897fcc906dfb88f50c52d4ba2129be7ccdc114 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
parent8cef39fb6742d834e383f533539ba90f72bbc7d9 (diff)
downloadgem5-bd31a5dc18def5972967a595d65266d1f9ff05cb.tar.xz
stats: update regressions for o3 changes in renaming and translation.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt')
-rw-r--r--tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt1756
1 files changed, 878 insertions, 878 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 406114ee2..5e631440d 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -1,114 +1,126 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 2.533245 # Number of seconds simulated
-sim_ticks 2533245380500 # Number of ticks simulated
-final_tick 2533245380500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 2.533148 # Number of seconds simulated
+sim_ticks 2533147650000 # Number of ticks simulated
+final_tick 2533147650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 67317 # Simulator instruction rate (inst/s)
-host_op_rate 86618 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2827634962 # Simulator tick rate (ticks/s)
-host_mem_usage 409784 # Number of bytes of host memory used
-host_seconds 895.89 # Real time elapsed on the host
-sim_insts 60308251 # Number of instructions simulated
-sim_ops 77599937 # Number of ops (including micro ops) simulated
+host_inst_rate 66149 # Simulator instruction rate (inst/s)
+host_op_rate 85115 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2778505291 # Simulator tick rate (ticks/s)
+host_mem_usage 406592 # Number of bytes of host memory used
+host_seconds 911.69 # Real time elapsed on the host
+sim_insts 60307315 # Number of instructions simulated
+sim_ops 77598799 # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 2944 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 797824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9094032 # Number of bytes read from this memory
-system.physmem.bytes_read::total 129432592 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 797824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 797824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 3784128 # Number of bytes written to this memory
+system.physmem.bytes_read::cpu.inst 795840 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9093648 # Number of bytes read from this memory
+system.physmem.bytes_read::total 129429904 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 795840 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 795840 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 3782016 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
-system.physmem.bytes_written::total 6800200 # Number of bytes written to this memory
+system.physmem.bytes_written::total 6798088 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 46 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12466 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 142128 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 15096850 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 59127 # Number of write requests responded to by this memory
+system.physmem.num_reads::cpu.inst 12435 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 142122 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 15096808 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 59094 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 813145 # Number of write requests responded to by this memory
-system.physmem.bw_read::realview.clcd 47187558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 1162 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_writes::total 813112 # Number of write requests responded to by this memory
+system.physmem.bw_read::realview.clcd 47189379 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 1036 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 314941 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 3589874 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 51093587 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 314941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 314941 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1493787 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu.data 1190596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 2684383 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1493787 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::realview.clcd 47187558 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 1162 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 314170 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 3589861 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 51094497 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 314170 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 314170 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1493010 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu.data 1190642 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 2683652 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1493010 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::realview.clcd 47189379 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 1036 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 314941 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 4780470 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 53777969 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 15096850 # Total number of read requests seen
-system.physmem.writeReqs 813145 # Total number of write requests seen
-system.physmem.cpureqs 218417 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 966198400 # Total number of bytes read from memory
-system.physmem.bytesWritten 52041280 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 129432592 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 6800200 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 331 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed
+system.physmem.bw_total::cpu.inst 314170 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 4780503 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 53778149 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 15096808 # Total number of read requests seen
+system.physmem.writeReqs 813112 # Total number of write requests seen
+system.physmem.cpureqs 218335 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 966195712 # Total number of bytes read from memory
+system.physmem.bytesWritten 52039168 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 129429904 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 6798088 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 295 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 4677 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 943938 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 943448 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 943393 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 943447 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 943391 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 944192 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 943987 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 943149 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 943276 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 943874 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 943803 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 943307 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 943198 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 943602 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 943695 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 943079 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 942979 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 943599 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 50829 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 50415 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 50439 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 51156 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 50914 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 50181 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 50283 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 50861 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 51365 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 50799 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 51184 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 51242 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 50716 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 51227 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::4 943982 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 943143 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 943273 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 943872 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 943781 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 943299 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 943231 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 943609 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 943694 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 943087 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 942964 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 943610 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 50827 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 50416 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 50443 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 51149 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 50907 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 50180 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 50280 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 50862 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 51358 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 50899 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 50801 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 51187 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 51246 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 50710 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 50619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 51228 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 2173038 # Number of times wr buffer was full causing retry
-system.physmem.totGap 2533244279000 # Total gap between requests
+system.physmem.numWrRetry 2236976 # Number of times wr buffer was full causing retry
+system.physmem.totGap 2533146526000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 36 # Categorize read packet sizes
system.physmem.readPktSize::3 14942208 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 154606 # Categorize read packet sizes
+system.physmem.readPktSize::6 154564 # Categorize read packet sizes
system.physmem.readPktSize::7 0 # Categorize read packet sizes
system.physmem.readPktSize::8 0 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # categorize write packet sizes
system.physmem.writePktSize::1 0 # categorize write packet sizes
-system.physmem.writePktSize::2 2927056 # categorize write packet sizes
+system.physmem.writePktSize::2 2990994 # categorize write packet sizes
system.physmem.writePktSize::3 0 # categorize write packet sizes
system.physmem.writePktSize::4 0 # categorize write packet sizes
system.physmem.writePktSize::5 0 # categorize write packet sizes
-system.physmem.writePktSize::6 59127 # categorize write packet sizes
+system.physmem.writePktSize::6 59094 # categorize write packet sizes
system.physmem.writePktSize::7 0 # categorize write packet sizes
system.physmem.writePktSize::8 0 # categorize write packet sizes
system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
@@ -117,29 +129,29 @@ system.physmem.neitherpktsize::2 0 # ca
system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
-system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes
+system.physmem.neitherpktsize::6 4677 # categorize neither packet sizes
system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
-system.physmem.rdQLenPdf::0 1040308 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 981234 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 950339 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 3550137 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 2675999 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 2688015 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 2649233 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 60810 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 59292 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 108760 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 157649 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 108311 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 16828 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 16678 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 21784 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 11013 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 111 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 12 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 1039969 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::1 980923 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::2 950073 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::3 3550359 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::4 2676584 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::5 2688258 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::6 2649649 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::7 60661 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::8 59173 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::9 108720 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::10 157659 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::11 108272 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::12 16731 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::13 16591 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::14 21899 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::15 10876 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::16 104 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::17 5 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 4 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 2 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::19 3 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
@@ -153,110 +165,98 @@ system.physmem.rdQLenPdf::29 0 # Wh
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 2636 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 2726 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 2860 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 3024 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 3149 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 3233 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 3319 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 3428 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 3482 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 35354 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 32719 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 32629 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 32495 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 32330 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 32205 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 32121 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 32035 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 31926 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 31872 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 2580 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 2633 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::2 2680 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::3 2721 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::4 2742 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 2771 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 2796 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 2817 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2832 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::9 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::16 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::17 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::18 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::19 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::20 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::21 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::22 35352 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 32773 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 32720 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::25 32673 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::26 32632 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::27 32611 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::28 32582 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 32557 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 32536 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32521 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.totQLat 393028587393 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 485428123643 # Sum of mem lat for all requests
-system.physmem.totBusLat 75482595000 # Total cycles spent in databus access
-system.physmem.totBankLat 16916941250 # Total cycles spent in bank access
-system.physmem.avgQLat 26034.38 # Average queueing delay per request
-system.physmem.avgBankLat 1120.59 # Average bank access latency per request
+system.physmem.totQLat 393223278963 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 485615648963 # Sum of mem lat for all requests
+system.physmem.totBusLat 75482565000 # Total cycles spent in databus access
+system.physmem.totBankLat 16909805000 # Total cycles spent in bank access
+system.physmem.avgQLat 26047.29 # Average queueing delay per request
+system.physmem.avgBankLat 1120.11 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 32154.97 # Average memory access latency
-system.physmem.avgRdBW 381.41 # Average achieved read bandwidth in MB/s
+system.physmem.avgMemAccLat 32167.41 # Average memory access latency
+system.physmem.avgRdBW 381.42 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 20.54 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 51.09 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.14 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.19 # Average read queue length over time
-system.physmem.avgWrQLen 12.52 # Average write queue length over time
-system.physmem.readRowHits 15020214 # Number of row buffer hits during reads
-system.physmem.writeRowHits 793069 # Number of row buffer hits during writes
+system.physmem.avgWrQLen 11.48 # Average write queue length over time
+system.physmem.readRowHits 15020221 # Number of row buffer hits during reads
+system.physmem.writeRowHits 793131 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.49 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate 97.53 # Row buffer hit rate for writes
-system.physmem.avgGap 159223.45 # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.writeRowHitRate 97.54 # Row buffer hit rate for writes
+system.physmem.avgGap 159218.06 # Average gap between requests
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 14667589 # Number of BP lookups
-system.cpu.branchPred.condPredicted 11748926 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 705805 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 9784798 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 7931964 # Number of BTB hits
+system.cpu.branchPred.lookups 14676489 # Number of BP lookups
+system.cpu.branchPred.condPredicted 11762878 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 704619 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 9800840 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 7950249 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 81.064157 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 1398744 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72667 # Number of incorrect RAS predictions.
+system.cpu.branchPred.BTBHitPct 81.118037 # BTB Hit Percentage
+system.cpu.branchPred.usedRAS 1398960 # Number of times the RAS was used to get a target.
+system.cpu.branchPred.RASInCorrect 72172 # Number of incorrect RAS predictions.
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
-system.cpu.dtb.read_hits 51389080 # DTB read hits
-system.cpu.dtb.read_misses 73326 # DTB read misses
-system.cpu.dtb.write_hits 11702658 # DTB write hits
-system.cpu.dtb.write_misses 17128 # DTB write misses
+system.cpu.dtb.read_hits 51394402 # DTB read hits
+system.cpu.dtb.read_misses 64202 # DTB read misses
+system.cpu.dtb.write_hits 11700782 # DTB write hits
+system.cpu.dtb.write_misses 15842 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.dtb.flush_entries 4257 # Number of entries that have been flushed from TLB
-system.cpu.dtb.align_faults 2506 # Number of TLB faults due to alignment restrictions
-system.cpu.dtb.prefetch_faults 491 # Number of TLB faults due to prefetch
+system.cpu.dtb.flush_entries 3565 # Number of entries that have been flushed from TLB
+system.cpu.dtb.align_faults 2475 # Number of TLB faults due to alignment restrictions
+system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.dtb.perms_faults 1337 # Number of TLB faults due to permissions restrictions
-system.cpu.dtb.read_accesses 51462406 # DTB read accesses
-system.cpu.dtb.write_accesses 11719786 # DTB write accesses
+system.cpu.dtb.perms_faults 1357 # Number of TLB faults due to permissions restrictions
+system.cpu.dtb.read_accesses 51458604 # DTB read accesses
+system.cpu.dtb.write_accesses 11716624 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
-system.cpu.dtb.hits 63091738 # DTB hits
-system.cpu.dtb.misses 90454 # DTB misses
-system.cpu.dtb.accesses 63182192 # DTB accesses
-system.cpu.itb.inst_hits 12277036 # ITB inst hits
-system.cpu.itb.inst_misses 11490 # ITB inst misses
+system.cpu.dtb.hits 63095184 # DTB hits
+system.cpu.dtb.misses 80044 # DTB misses
+system.cpu.dtb.accesses 63175228 # DTB accesses
+system.cpu.itb.inst_hits 12330326 # ITB inst hits
+system.cpu.itb.inst_misses 11351 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
@@ -265,518 +265,518 @@ system.cpu.itb.flush_tlb 2 # Nu
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
-system.cpu.itb.flush_entries 2578 # Number of entries that have been flushed from TLB
+system.cpu.itb.flush_entries 2478 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
-system.cpu.itb.perms_faults 2988 # Number of TLB faults due to permissions restrictions
+system.cpu.itb.perms_faults 2994 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.inst_accesses 12288526 # ITB inst accesses
-system.cpu.itb.hits 12277036 # DTB hits
-system.cpu.itb.misses 11490 # DTB misses
-system.cpu.itb.accesses 12288526 # DTB accesses
-system.cpu.numCycles 472097236 # number of cpu cycles simulated
+system.cpu.itb.inst_accesses 12341677 # ITB inst accesses
+system.cpu.itb.hits 12330326 # DTB hits
+system.cpu.itb.misses 11351 # DTB misses
+system.cpu.itb.accesses 12341677 # DTB accesses
+system.cpu.numCycles 471833351 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 30535145 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 95659606 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 14667589 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 9330708 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 21094710 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 5261516 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 125902 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 95951841 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 2603 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 94532 # Number of stall cycles due to pending traps
-system.cpu.fetch.PendingQuiesceStallCycles 195374 # Number of stall cycles due to pending quiesce instructions
-system.cpu.fetch.IcacheWaitRetryStallCycles 334 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 12273314 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 886277 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 5889 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 151614227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 0.781014 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 2.145237 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 30572359 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 96029601 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 14676489 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 9349209 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 21156129 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 5298120 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 120373 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 95586316 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 2531 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 87050 # Number of stall cycles due to pending traps
+system.cpu.fetch.PendingQuiesceStallCycles 195749 # Number of stall cycles due to pending quiesce instructions
+system.cpu.fetch.IcacheWaitRetryStallCycles 271 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 12326631 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 900507 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 5718 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 151357354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 0.785025 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 2.150266 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 130534830 86.10% 86.10% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1304262 0.86% 86.96% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 1711991 1.13% 88.09% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 2483160 1.64% 89.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 2210564 1.46% 91.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 1108348 0.73% 91.91% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 2746367 1.81% 93.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 744764 0.49% 94.22% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 8769941 5.78% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 130216652 86.03% 86.03% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1302204 0.86% 86.89% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 1711626 1.13% 88.02% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 2495193 1.65% 89.67% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 2215033 1.46% 91.14% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 1107976 0.73% 91.87% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 2757688 1.82% 93.69% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 745754 0.49% 94.18% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 8805228 5.82% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 151614227 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.031069 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.202627 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 32507875 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 95564460 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 19109346 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 988199 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3444347 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1959915 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 171959 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 112281673 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 569222 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3444347 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34437159 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 36947144 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 52554741 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 18109845 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 6120991 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 105853391 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 21725 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 1011282 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4135399 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 28413 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 110224508 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 484220176 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 484129547 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 90629 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 78390630 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31833877 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 830294 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 736801 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 12261174 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 20294238 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 13503315 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1968797 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 2454387 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 97750102 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1983216 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 124244624 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 169680 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 21546848 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 56327140 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 500803 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 151614227 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 0.819479 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 1.532560 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 151357354 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.031105 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.203524 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 32536934 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 95207461 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 19182239 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 963280 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3467440 # Number of cycles decode is squashing
+system.cpu.decode.BranchResolved 1956290 # Number of times decode resolved a branch
+system.cpu.decode.BranchMispred 171623 # Number of times decode detected a branch misprediction
+system.cpu.decode.DecodedInsts 112620131 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 567256 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3467440 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 34479585 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 36699027 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 52520178 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 18147266 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 6043858 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 106106757 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 20523 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 1005521 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4063485 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 592 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 110532069 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 485468581 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 485377824 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 90757 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 78389582 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 32142486 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 830463 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 737014 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 12171984 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 20324763 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 13518088 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1981188 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 2478536 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 97936678 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1983499 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 124321529 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 167156 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 21750573 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 57066044 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 501117 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 151357354 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 0.821378 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 1.534899 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 107320603 70.79% 70.79% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 13614389 8.98% 79.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 7121261 4.70% 84.46% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 5900322 3.89% 88.35% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 12601828 8.31% 96.67% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 2772948 1.83% 98.49% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 1691791 1.12% 99.61% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 464731 0.31% 99.92% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 126354 0.08% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 107117235 70.77% 70.77% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 13550856 8.95% 79.72% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 7067177 4.67% 84.39% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 5940673 3.92% 88.32% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 12604400 8.33% 96.65% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 2784028 1.84% 98.49% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 1701066 1.12% 99.61% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 465188 0.31% 99.92% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 126731 0.08% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 151614227 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 151357354 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 59822 0.68% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 7 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 8365800 94.71% 95.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 407388 4.61% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 61039 0.69% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntMult 3 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShift 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.69% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 8364044 94.63% 95.32% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 413790 4.68% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 58568271 47.14% 47.43% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 93243 0.08% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 19 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 14 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 14 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.51% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 52895196 42.57% 90.08% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 12322086 9.92% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 58631158 47.16% 47.45% # Type of FU issued
+system.cpu.iq.FU_type_0::IntMult 93232 0.07% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMisc 20 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShift 1 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdShiftAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatMultAcc 15 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.53% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 52911235 42.56% 90.09% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 12320074 9.91% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 124244624 # Type of FU issued
-system.cpu.iq.rate 0.263176 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 8833017 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.071094 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 409173362 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 121296699 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 85947126 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 22922 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 12496 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 10285 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 132701824 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 12151 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 625056 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 124321529 # Type of FU issued
+system.cpu.iq.rate 0.263486 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 8838876 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.071097 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 409062941 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 121687155 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 85967434 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 23205 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 12488 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 10289 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 132784424 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 12315 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 622437 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 4639526 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 6246 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 30083 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1771107 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 4670323 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 6258 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 30023 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1786078 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 34107778 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 879356 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 34107730 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 893047 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3444347 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 28046391 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 438374 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 99953895 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 200970 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 20294238 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 13503315 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 1410324 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 116022 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 3795 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 30083 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 349489 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 270440 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 619929 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 121508078 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 52074968 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 2736546 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3467440 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 27945377 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 433355 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 100140842 # Number of instructions dispatched to IQ
+system.cpu.iew.iewDispSquashedInsts 200439 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispLoadInsts 20324763 # Number of dispatched load instructions
+system.cpu.iew.iewDispStoreInsts 13518088 # Number of dispatched store instructions
+system.cpu.iew.iewDispNonSpecInsts 1411116 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewIQFullEvents 112674 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 3579 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 30023 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 350481 # Number of branches that were predicted taken incorrectly
+system.cpu.iew.predictedNotTakenIncorrect 268612 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.branchMispredicts 619093 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 121545908 # Number of executed instructions
+system.cpu.iew.iewExecLoadInsts 52081707 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 2775621 # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp 0 # number of swp insts executed
-system.cpu.iew.exec_nop 220577 # number of nop insts executed
-system.cpu.iew.exec_refs 64289334 # number of memory reference insts executed
-system.cpu.iew.exec_branches 11563754 # Number of branches executed
-system.cpu.iew.exec_stores 12214366 # Number of stores executed
-system.cpu.iew.exec_rate 0.257379 # Inst execution rate
-system.cpu.iew.wb_sent 120366152 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 85957411 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 47207424 # num instructions producing a value
-system.cpu.iew.wb_consumers 88142728 # num instructions consuming a value
+system.cpu.iew.exec_nop 220665 # number of nop insts executed
+system.cpu.iew.exec_refs 64294282 # number of memory reference insts executed
+system.cpu.iew.exec_branches 11561887 # Number of branches executed
+system.cpu.iew.exec_stores 12212575 # Number of stores executed
+system.cpu.iew.exec_rate 0.257603 # Inst execution rate
+system.cpu.iew.wb_sent 120387103 # cumulative count of insts sent to commit
+system.cpu.iew.wb_count 85977723 # cumulative count of insts written-back
+system.cpu.iew.wb_producers 47219839 # num instructions producing a value
+system.cpu.iew.wb_consumers 88163371 # num instructions consuming a value
system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 0.182076 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.535579 # average fanout of values written-back
+system.cpu.iew.wb_rate 0.182221 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.535595 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 21297531 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1482413 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 536366 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 148169880 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.524738 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.515080 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 21484846 # The number of squashed insts skipped by commit
+system.cpu.commit.commitNonSpecStalls 1482382 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.branchMispredicts 535483 # The number of times a branch was mispredicted
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 120738862 81.49% 81.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 13327822 8.99% 90.48% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3883611 2.62% 93.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 2123257 1.43% 94.54% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 1920888 1.30% 95.83% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 968544 0.65% 96.49% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 1598005 1.08% 97.56% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 699927 0.47% 98.04% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 2908964 1.96% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 120439692 81.44% 81.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 13316642 9.00% 90.44% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3906186 2.64% 93.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 2120970 1.43% 94.52% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 1946250 1.32% 95.83% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 970441 0.66% 96.49% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 1598227 1.08% 97.57% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 701359 0.47% 98.05% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 2890147 1.95% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 148169880 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 60458632 # Number of instructions committed
-system.cpu.commit.committedOps 77750318 # Number of ops (including micro ops) committed
+system.cpu.commit.committed_per_cycle::total 147889914 # Number of insts commited each cycle
+system.cpu.commit.committedInsts 60457696 # Number of instructions committed
+system.cpu.commit.committedOps 77749180 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 27386920 # Number of memory references committed
-system.cpu.commit.loads 15654712 # Number of loads committed
-system.cpu.commit.membars 403607 # Number of memory barriers committed
-system.cpu.commit.branches 9961406 # Number of branches committed
+system.cpu.commit.refs 27386450 # Number of memory references committed
+system.cpu.commit.loads 15654440 # Number of loads committed
+system.cpu.commit.membars 403595 # Number of memory barriers committed
+system.cpu.commit.branches 9961299 # Number of branches committed
system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 68855494 # Number of committed integer instructions.
-system.cpu.commit.function_calls 991273 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 2908964 # number cycles where commit BW limit reached
+system.cpu.commit.int_insts 68854449 # Number of committed integer instructions.
+system.cpu.commit.function_calls 991256 # Number of function calls committed.
+system.cpu.commit.bw_lim_events 2890147 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 242460133 # The number of ROB reads
-system.cpu.rob.rob_writes 201635862 # The number of ROB writes
-system.cpu.timesIdled 1769557 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 320483009 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 4594310480 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 60308251 # Number of Instructions Simulated
-system.cpu.committedOps 77599937 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 60308251 # Number of Instructions Simulated
-system.cpu.cpi 7.828070 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 7.828070 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.127745 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.127745 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 550197994 # number of integer regfile reads
-system.cpu.int_regfile_writes 88410647 # number of integer regfile writes
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-system.cpu.misc_regfile_reads 30226423 # number of misc regfile reads
-system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
-system.cpu.icache.replacements 980802 # number of replacements
-system.cpu.icache.tagsinuse 511.577289 # Cycle average of tags in use
-system.cpu.icache.total_refs 11213050 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 981314 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 11.426567 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 6406924000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 511.577289 # Average occupied blocks per requestor
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-system.cpu.icache.occ_percent::total 0.999174 # Average percentage of cache occupancy
-system.cpu.icache.ReadReq_hits::cpu.inst 11213050 # number of ReadReq hits
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-system.cpu.icache.overall_hits::total 11213050 # number of overall hits
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-system.cpu.icache.ReadReq_misses::total 1060138 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1060138 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1060138 # number of overall misses
-system.cpu.icache.overall_misses::total 1060138 # number of overall misses
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-system.cpu.icache.ReadReq_accesses::cpu.inst 12273188 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.ReadReq_avg_miss_latency::total 13206.871178 # average ReadReq miss latency
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-system.cpu.icache.demand_avg_miss_latency::total 13206.871178 # average overall miss latency
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+system.cpu.rob.rob_reads 242385214 # The number of ROB reads
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+system.cpu.idleCycles 320475997 # Total number of cycles that the CPU has spent unscheduled due to idling
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+system.cpu.committedInsts 60307315 # Number of Instructions Simulated
+system.cpu.committedOps 77598799 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 60307315 # Number of Instructions Simulated
+system.cpu.cpi 7.823816 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 7.823816 # CPI: Total CPI of All Threads
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+system.cpu.icache.replacements 979919 # number of replacements
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+system.cpu.icache.warmup_cycle 6426355000 # Cycle when the warmup percentage was hit.
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+system.cpu.icache.ReadReq_avg_miss_latency::total 13207.831523 # average ReadReq miss latency
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+system.cpu.icache.demand_avg_miss_latency::total 13207.831523 # average overall miss latency
+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13207.831523 # average overall miss latency
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+system.cpu.icache.blocked::no_mshrs 292 # number of cycles access was blocked
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-system.cpu.icache.demand_mshr_hits::total 78782 # number of demand (read+write) MSHR hits
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-system.cpu.icache.ReadReq_mshr_misses::total 981356 # number of ReadReq MSHR misses
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-system.cpu.icache.overall_mshr_misses::cpu.inst 981356 # number of overall MSHR misses
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-system.cpu.icache.ReadReq_mshr_miss_latency::total 11396806498 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11396806498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 11396806498 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11396806498 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 11396806498 # number of overall MSHR miss cycles
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system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 7553500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 7553500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 7553500 # number of overall MSHR uncacheable cycles
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-system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11613.325336 # average ReadReq mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11613.325336 # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency::total 11613.325336 # average overall mshr miss latency
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+system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11608.522926 # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11608.522926 # average ReadReq mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11608.522926 # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency::total 11608.522926 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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@@ -785,109 +785,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan
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@@ -897,161 +897,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
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+system.cpu.dcache.WriteReq_mshr_hits::total 2713489 # number of WriteReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1336 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.LoadLockedReq_mshr_hits::total 1336 # number of LoadLockedReq MSHR hits
+system.cpu.dcache.demand_mshr_hits::cpu.data 3065331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_hits::total 3065331 # number of demand (read+write) MSHR hits
+system.cpu.dcache.overall_mshr_hits::cpu.data 3065331 # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_hits::total 3065331 # number of overall MSHR hits
+system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385643 # number of ReadReq MSHR misses
+system.cpu.dcache.ReadReq_mshr_misses::total 385643 # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248984 # number of WriteReq MSHR misses
+system.cpu.dcache.WriteReq_mshr_misses::total 248984 # number of WriteReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12173 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.LoadLockedReq_mshr_misses::total 12173 # number of LoadLockedReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.StoreCondReq_mshr_misses::total 10 # number of StoreCondReq MSHR misses
+system.cpu.dcache.demand_mshr_misses::cpu.data 634627 # number of demand (read+write) MSHR misses
+system.cpu.dcache.demand_mshr_misses::total 634627 # number of demand (read+write) MSHR misses
+system.cpu.dcache.overall_mshr_misses::cpu.data 634627 # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_misses::total 634627 # number of overall MSHR misses
+system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4807486000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_latency::total 4807486000 # number of ReadReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8182883413 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_latency::total 8182883413 # number of WriteReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140770000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140770000 # number of LoadLockedReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 146000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 146000 # number of StoreCondReq MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12990369413 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_latency::total 12990369413 # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12990369413 # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_latency::total 12990369413 # number of overall MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182395639500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182395639500 # number of ReadReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 36729406082 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 36729406082 # number of WriteReq MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 219125045582 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_latency::total 219125045582 # number of overall MSHR uncacheable cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026617 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026617 # mshr miss rate for ReadReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047424 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047424 # mshr miss rate for LoadLockedReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000040 # mshr miss rate for StoreCondReq accesses
+system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses
+system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12466.156523 # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12466.156523 # average ReadReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32865.097408 # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32865.097408 # average WriteReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11564.117309 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11564.117309 # average LoadLockedReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14600 # average StoreCondReq mshr miss latency
+system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14600 # average StoreCondReq mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20469.298364 # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency::total 20469.298364 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
@@ -1073,16 +1073,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan #
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
-system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of ReadReq MSHR uncacheable cycles
-system.iocache.ReadReq_mshr_uncacheable_latency::total 1229394161981 # number of ReadReq MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229394161981 # number of overall MSHR uncacheable cycles
-system.iocache.overall_mshr_uncacheable_latency::total 1229394161981 # number of overall MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of ReadReq MSHR uncacheable cycles
+system.iocache.ReadReq_mshr_uncacheable_latency::total 1229589046447 # number of ReadReq MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1229589046447 # number of overall MSHR uncacheable cycles
+system.iocache.overall_mshr_uncacheable_latency::total 1229589046447 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.kern.inst.arm 0 # number of arm instructions executed
-system.cpu.kern.inst.quiesce 83046 # number of quiesce instructions executed
+system.cpu.kern.inst.quiesce 83042 # number of quiesce instructions executed
---------- End Simulation Statistics ----------