diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3 | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini | 158 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 2747 |
2 files changed, 1533 insertions, 1372 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index f1e51a584..49d73e9a8 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu] @@ -105,6 +113,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -169,6 +179,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -184,6 +195,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -206,18 +218,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[3] @@ -226,15 +241,18 @@ port=system.cpu.toL2Bus.slave[3] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 +eventq_index=0 [system.cpu.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu.fuPool.FUList0.opList [system.cpu.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -243,16 +261,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 [system.cpu.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -261,22 +282,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 [system.cpu.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -285,22 +310,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 [system.cpu.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -309,10 +338,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList4.opList [system.cpu.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -321,124 +352,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 [system.cpu.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -447,10 +499,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu.fuPool.FUList6.opList [system.cpu.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -459,16 +513,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 [system.cpu.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -477,10 +534,12 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu.fuPool.FUList8.opList [system.cpu.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 @@ -491,6 +550,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -513,14 +573,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -539,12 +602,14 @@ midr=890224640 [system.cpu.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[2] @@ -555,6 +620,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -577,12 +643,14 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 [system.cpu.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -592,19 +660,23 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke [system.cpu.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -617,6 +689,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -639,6 +712,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -646,6 +720,7 @@ size=1024 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -657,6 +732,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -683,6 +759,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -694,19 +771,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -716,6 +797,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -725,6 +807,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -753,6 +836,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -762,8 +846,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -775,6 +891,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -790,6 +907,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -804,6 +923,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -813,6 +933,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -834,8 +955,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -844,6 +967,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -854,6 +978,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -864,6 +989,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -874,6 +1000,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -888,6 +1015,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -901,6 +1029,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -918,6 +1047,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -930,6 +1060,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -941,6 +1072,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -951,6 +1083,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -963,6 +1096,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -976,6 +1110,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -986,6 +1121,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -996,6 +1132,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1006,6 +1143,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1018,6 +1156,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1032,6 +1171,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1044,6 +1184,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1058,6 +1199,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1068,6 +1210,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1078,6 +1221,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1088,6 +1232,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1096,6 +1241,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1103,11 +1249,13 @@ port=3456 [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b60e42a06..65955f345 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,101 +1,101 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.525141 # Number of seconds simulated -sim_ticks 2525141046500 # Number of ticks simulated -final_tick 2525141046500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.525132 # Number of seconds simulated +sim_ticks 2525131633500 # Number of ticks simulated +final_tick 2525131633500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 61643 # Simulator instruction rate (inst/s) -host_op_rate 79318 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2581152882 # Simulator tick rate (ticks/s) -host_mem_usage 426780 # Number of bytes of host memory used -host_seconds 978.30 # Real time elapsed on the host -sim_insts 60305756 # Number of instructions simulated -sim_ops 77596741 # Number of ops (including micro ops) simulated +host_inst_rate 49653 # Simulator instruction rate (inst/s) +host_op_rate 63890 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2079077169 # Simulator tick rate (ticks/s) +host_mem_usage 446400 # Number of bytes of host memory used +host_seconds 1214.54 # Real time elapsed on the host +sim_insts 60305678 # Number of instructions simulated +sim_ops 77596684 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 797248 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9094416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.dtb.walker 2688 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 796928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9094736 # Number of bytes read from this memory system.physmem.bytes_read::total 129432144 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 797248 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3784000 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu.inst 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 796928 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3784384 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6800072 # Number of bytes written to this memory +system.physmem.bytes_written::total 6800456 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12457 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142134 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 42 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12452 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142139 # Number of read requests responded to by this memory system.physmem.num_reads::total 15096843 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59125 # Number of write requests responded to by this memory +system.physmem.num_writes::writebacks 59131 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813143 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47339005 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1039 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 315724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3601548 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51257392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315724 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1498530 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1194417 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2692947 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1498530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47339005 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1039 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 315724 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4795965 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53950339 # Total bandwidth to/from this memory (bytes/s) +system.physmem.num_writes::total 813149 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47339181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1064 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 315599 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3601688 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51257583 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 315599 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1498688 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1194422 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2693110 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1498688 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47339181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1064 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 315599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4796110 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53950692 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 15096843 # Number of read requests accepted -system.physmem.writeReqs 813143 # Number of write requests accepted +system.physmem.writeReqs 813149 # Number of write requests accepted system.physmem.readBursts 15096843 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 813143 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.writeBursts 813149 # Number of DRAM write bursts, including those merged in the write queue system.physmem.bytesReadDRAM 963738752 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 2459200 # Total number of bytes read from write queue system.physmem.bytesWritten 6902144 # Total number of bytes written to DRAM system.physmem.bytesReadSys 129432144 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 6800072 # Total written bytes from the system interface side +system.physmem.bytesWrittenSys 6800456 # Total written bytes from the system interface side system.physmem.servicedByWrQ 38425 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 705284 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 4674 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 943582 # Per bank write bursts -system.physmem.perBankRdBursts::1 943145 # Per bank write bursts -system.physmem.perBankRdBursts::2 939291 # Per bank write bursts -system.physmem.perBankRdBursts::3 939307 # Per bank write bursts -system.physmem.perBankRdBursts::4 943115 # Per bank write bursts -system.physmem.perBankRdBursts::5 943141 # Per bank write bursts -system.physmem.perBankRdBursts::6 939138 # Per bank write bursts -system.physmem.perBankRdBursts::7 938546 # Per bank write bursts -system.physmem.perBankRdBursts::8 943996 # Per bank write bursts -system.physmem.perBankRdBursts::9 943390 # Per bank write bursts -system.physmem.perBankRdBursts::10 938426 # Per bank write bursts -system.physmem.perBankRdBursts::11 937974 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 4682 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 943580 # Per bank write bursts +system.physmem.perBankRdBursts::1 943152 # Per bank write bursts +system.physmem.perBankRdBursts::2 939288 # Per bank write bursts +system.physmem.perBankRdBursts::3 939310 # Per bank write bursts +system.physmem.perBankRdBursts::4 943113 # Per bank write bursts +system.physmem.perBankRdBursts::5 943139 # Per bank write bursts +system.physmem.perBankRdBursts::6 939134 # Per bank write bursts +system.physmem.perBankRdBursts::7 938551 # Per bank write bursts +system.physmem.perBankRdBursts::8 944000 # Per bank write bursts +system.physmem.perBankRdBursts::9 943392 # Per bank write bursts +system.physmem.perBankRdBursts::10 938425 # Per bank write bursts +system.physmem.perBankRdBursts::11 937973 # Per bank write bursts system.physmem.perBankRdBursts::12 943928 # Per bank write bursts -system.physmem.perBankRdBursts::13 943533 # Per bank write bursts -system.physmem.perBankRdBursts::14 939234 # Per bank write bursts -system.physmem.perBankRdBursts::15 938672 # Per bank write bursts -system.physmem.perBankWrBursts::0 6704 # Per bank write bursts -system.physmem.perBankWrBursts::1 6457 # Per bank write bursts -system.physmem.perBankWrBursts::2 6598 # Per bank write bursts -system.physmem.perBankWrBursts::3 6635 # Per bank write bursts -system.physmem.perBankWrBursts::4 6561 # Per bank write bursts -system.physmem.perBankWrBursts::5 6794 # Per bank write bursts -system.physmem.perBankWrBursts::6 6789 # Per bank write bursts -system.physmem.perBankWrBursts::7 6723 # Per bank write bursts -system.physmem.perBankWrBursts::8 7136 # Per bank write bursts +system.physmem.perBankRdBursts::13 943534 # Per bank write bursts +system.physmem.perBankRdBursts::14 939230 # Per bank write bursts +system.physmem.perBankRdBursts::15 938669 # Per bank write bursts +system.physmem.perBankWrBursts::0 6703 # Per bank write bursts +system.physmem.perBankWrBursts::1 6464 # Per bank write bursts +system.physmem.perBankWrBursts::2 6595 # Per bank write bursts +system.physmem.perBankWrBursts::3 6634 # Per bank write bursts +system.physmem.perBankWrBursts::4 6559 # Per bank write bursts +system.physmem.perBankWrBursts::5 6792 # Per bank write bursts +system.physmem.perBankWrBursts::6 6793 # Per bank write bursts +system.physmem.perBankWrBursts::7 6730 # Per bank write bursts +system.physmem.perBankWrBursts::8 7130 # Per bank write bursts system.physmem.perBankWrBursts::9 6877 # Per bank write bursts -system.physmem.perBankWrBursts::10 6538 # Per bank write bursts -system.physmem.perBankWrBursts::11 6183 # Per bank write bursts -system.physmem.perBankWrBursts::12 7149 # Per bank write bursts -system.physmem.perBankWrBursts::13 6765 # Per bank write bursts -system.physmem.perBankWrBursts::14 7038 # Per bank write bursts -system.physmem.perBankWrBursts::15 6899 # Per bank write bursts +system.physmem.perBankWrBursts::10 6539 # Per bank write bursts +system.physmem.perBankWrBursts::11 6181 # Per bank write bursts +system.physmem.perBankWrBursts::12 7151 # Per bank write bursts +system.physmem.perBankWrBursts::13 6766 # Per bank write bursts +system.physmem.perBankWrBursts::14 7035 # Per bank write bursts +system.physmem.perBankWrBursts::15 6897 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2525139929000 # Total gap between requests +system.physmem.totGap 2525130505500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 36 # Read request sizes (log2) @@ -109,26 +109,26 @@ system.physmem.writePktSize::2 754018 # Wr system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 59125 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 1163754 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 1108384 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 1064134 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3627605 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2618920 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2606295 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2613037 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 53652 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 58180 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 21151 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 20926 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 20790 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 20516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 20376 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 20256 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 20176 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 255 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59131 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 1173486 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 1117689 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 1073548 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3627714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2609756 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2597217 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2603662 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 53378 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 57682 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 21065 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 20906 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 20772 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 20512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 20369 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 20252 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 20160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 238 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -142,29 +142,29 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 4764 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 5443 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 4887 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 5096 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 5232 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 4854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 4879 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 4886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 4808 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 4805 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 4766 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 5445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 4889 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 5098 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 5233 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4856 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4880 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4887 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4810 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 4807 # What write queue length does an incoming req see system.physmem.wrQLenPdf::10 4811 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 4798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 4799 # What write queue length does an incoming req see system.physmem.wrQLenPdf::12 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 4787 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 4788 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 4792 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 4789 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 4794 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 4797 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 4821 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 4830 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 4800 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 4799 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 5160 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 140 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 4825 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 4820 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 4809 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 4802 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 5139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 138 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 19 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see @@ -174,521 +174,534 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 86114 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 11271.566528 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 1003.490719 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 16771.547354 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 23576 27.38% 27.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 14050 16.32% 43.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 2599 3.02% 46.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 2090 2.43% 49.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 1311 1.52% 50.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 1239 1.44% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 869 1.01% 53.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 1005 1.17% 54.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 571 0.66% 54.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 602 0.70% 55.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 523 0.61% 56.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 509 0.59% 56.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 284 0.33% 57.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 276 0.32% 57.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 154 0.18% 57.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 642 0.75% 58.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 97 0.11% 58.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 141 0.16% 58.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 78 0.09% 58.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 123 0.14% 58.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 49 0.06% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 518 0.60% 59.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 29 0.03% 59.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 316 0.37% 59.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 18 0.02% 60.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 102 0.12% 60.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 18 0.02% 60.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 211 0.25% 60.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 23 0.03% 60.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 55 0.06% 60.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 13 0.02% 60.49% # Bytes accessed per row activation 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98 0.11% 61.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 9 0.01% 61.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 18 0.02% 61.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 8 0.01% 61.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 97 0.11% 62.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 4 0.00% 62.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 12 0.01% 62.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 7 0.01% 62.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 158 0.18% 62.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 9 0.01% 62.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 14 0.02% 62.29% # Bytes accessed per row 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0.01% 63.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 426 0.49% 63.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 63.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 8 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 6 0.01% 63.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 28 0.03% 63.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 11 0.01% 63.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 19 0.02% 63.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.00% 63.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 89 0.10% 63.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 1 0.00% 63.81% # Bytes accessed per row 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8 0.01% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 4 0.00% 64.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 363 0.42% 65.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 3 0.00% 65.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 9 0.01% 65.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 12 0.01% 65.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 84 0.10% 65.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7488-7495 5 0.01% 65.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 10 0.01% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 65.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 98 0.11% 65.54% # Bytes accessed per row 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3 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9664-9671 1 0.00% 66.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 138 0.16% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9792-9799 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9856-9863 1 0.00% 67.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 79 0.09% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10112-10119 6 0.01% 67.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 402 0.47% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10432-10439 1 0.00% 67.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 84 0.10% 67.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10560-10567 1 0.00% 67.81% # Bytes accessed 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+system.physmem.bytesPerActivate::43136-43143 3 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43200-43207 1 0.00% 90.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 14 0.02% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43328-43335 1 0.00% 90.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 127 0.15% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 90.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 80 0.09% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43840-43847 2 0.00% 90.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43904-43911 2 0.00% 90.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 364 0.42% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44096-44103 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44160-44167 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 91.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44288-44295 83 0.10% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44352-44359 1 0.00% 91.15% # Bytes accessed per row activation system.physmem.bytesPerActivate::44416-44423 1 0.00% 91.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 81 0.09% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44672-44679 3 0.00% 91.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 96 0.11% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44864-44871 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 91.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 341 0.40% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 143 0.17% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45440-45447 1 0.00% 91.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 82 0.10% 92.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45696-45703 5 0.01% 92.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 84 0.10% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45888-45895 1 0.00% 92.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 261 0.30% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 73 0.08% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 68 0.08% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 91 0.11% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46976-46983 2 0.00% 92.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 272 0.32% 93.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47168-47175 1 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 142 0.16% 93.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 144 0.17% 93.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47808-47815 1 0.00% 93.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 25 0.03% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47936-47943 2 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 395 0.46% 93.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 16 0.02% 93.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 76 0.09% 93.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48768-48775 71 0.08% 94.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 72 0.08% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 3 0.00% 94.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 5013 5.82% 99.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 73 0.08% 91.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44672-44679 2 0.00% 91.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 144 0.17% 91.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44864-44871 2 0.00% 91.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 337 0.39% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45184-45191 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45248-45255 1 0.00% 91.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 24 0.03% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45440-45447 3 0.00% 91.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 16 0.02% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45696-45703 3 0.00% 91.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 144 0.17% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45888-45895 2 0.00% 92.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 327 0.38% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46144-46151 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46272-46279 1 0.00% 92.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 69 0.08% 92.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46464-46471 1 0.00% 92.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 79 0.09% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46720-46727 2 0.00% 92.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 89 0.10% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46912-46919 1 0.00% 92.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46976-46983 1 0.00% 92.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 334 0.39% 93.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47232-47239 2 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47296-47303 3 0.00% 93.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 78 0.09% 93.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 88 0.10% 93.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47744-47751 4 0.00% 93.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 24 0.03% 93.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47936-47943 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48000-48007 1 0.00% 93.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 398 0.46% 93.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 83 0.10% 93.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 77 0.09% 93.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48768-48775 72 0.08% 94.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 83 0.10% 94.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 3 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 94.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 5012 5.82% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49216-49223 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49408-49415 1 0.00% 99.96% # Bytes accessed per row activation system.physmem.bytesPerActivate::49600-49607 1 0.00% 99.96% # Bytes accessed per row activation @@ -714,15 +727,15 @@ system.physmem.bytesPerActivate::51456-51463 2 0.00% 100.00% system.physmem.bytesPerActivate::51520-51527 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51840-51847 1 0.00% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::51968-51975 2 0.00% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 86114 # Bytes accessed per row activation -system.physmem.totQLat 365610387500 # Total ticks spent queuing -system.physmem.totMemAccLat 458189280000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::total 86134 # Bytes accessed per row activation +system.physmem.totQLat 365453646000 # Total ticks spent queuing +system.physmem.totMemAccLat 458164497250 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 75292090000 # Total ticks spent in databus transfers -system.physmem.totBankLat 17286802500 # Total ticks spent accessing banks -system.physmem.avgQLat 24279.47 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1147.98 # Average bank access latency per DRAM burst +system.physmem.totBankLat 17418761250 # Total ticks spent accessing banks +system.physmem.avgQLat 24269.06 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1156.75 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30427.45 # Average memory access latency per DRAM burst +system.physmem.avgMemAccLat 30425.81 # Average memory access latency per DRAM burst system.physmem.avgRdBW 381.66 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 2.73 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 51.26 # Average system read bandwidth in MiByte/s @@ -732,14 +745,14 @@ system.physmem.busUtil 3.00 # Da system.physmem.busUtilRead 2.98 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.02 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.18 # Average read queue length when enqueuing -system.physmem.avgWrQLen 12.84 # Average write queue length when enqueuing -system.physmem.readRowHits 14986740 # Number of row buffer hits during reads -system.physmem.writeRowHits 93410 # Number of row buffer hits during writes +system.physmem.avgWrQLen 12.83 # Average write queue length when enqueuing +system.physmem.readRowHits 14986798 # Number of row buffer hits during reads +system.physmem.writeRowHits 93332 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.52 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 86.60 # Row buffer hit rate for writes -system.physmem.avgGap 158714.15 # Average gap between requests +system.physmem.writeRowHitRate 86.53 # Row buffer hit rate for writes +system.physmem.avgGap 158713.50 # Average gap between requests system.physmem.pageHitRate 99.43 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 1.73 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.prechargeAllPercent 1.72 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory @@ -752,50 +765,50 @@ system.realview.nvmem.bw_inst_read::cpu.inst 25 system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 54899945 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 16149440 # Transaction distribution -system.membus.trans_dist::ReadResp 16149440 # Transaction distribution +system.membus.throughput 54900302 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 16149434 # Transaction distribution +system.membus.trans_dist::ReadResp 16149434 # Transaction distribution system.membus.trans_dist::WriteReq 763332 # Transaction distribution system.membus.trans_dist::WriteResp 763332 # Transaction distribution -system.membus.trans_dist::Writeback 59125 # Transaction distribution -system.membus.trans_dist::UpgradeReq 4671 # Transaction distribution +system.membus.trans_dist::Writeback 59131 # Transaction distribution +system.membus.trans_dist::UpgradeReq 4679 # Transaction distribution system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4674 # Transaction distribution -system.membus.trans_dist::ReadExReq 131442 # Transaction distribution -system.membus.trans_dist::ReadExResp 131442 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4682 # Transaction distribution +system.membus.trans_dist::ReadExReq 131448 # Transaction distribution +system.membus.trans_dist::ReadExResp 131448 # Transaction distribution system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382942 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 2 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3760 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885779 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272485 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1885801 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4272507 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 29884416 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 29884416 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 34156901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 34156923 # Packet count per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390301 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 64 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7520 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694552 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092441 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16694936 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 19092825 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 119537664 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.iocache.mem_side::total 119537664 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 138630105 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 138630105 # Total data (bytes) +system.membus.tot_pkt_size::total 138630489 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 138630489 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 1486773500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 1486873500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.1 # Layer utilization (%) system.membus.reqLayer1.occupancy 1000 # Layer occupancy (ticks) system.membus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 3686000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 3694000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) system.membus.reqLayer4.occupancy 1500 # Layer occupancy (ticks) system.membus.reqLayer4.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 17363455000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 17363465500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.7 # Layer utilization (%) -system.membus.respLayer1.occupancy 4733701508 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 4733669250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.2 # Layer utilization (%) -system.membus.respLayer2.occupancy 33738367951 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33737503451 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -803,7 +816,7 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.iobus.throughput 48285606 # Throughput (bytes/s) +system.iobus.throughput 48285786 # Throughput (bytes/s) system.iobus.trans_dist::ReadReq 16125522 # Transaction distribution system.iobus.trans_dist::ReadResp 16125522 # Transaction distribution system.iobus.trans_dist::WriteReq 8157 # Transaction distribution @@ -913,40 +926,40 @@ system.iobus.reqLayer25.occupancy 14942208000 # La system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) system.iobus.respLayer0.occupancy 2374785000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.1 # Layer utilization (%) -system.iobus.respLayer1.occupancy 40921194049 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 40921719549 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.6 # Layer utilization (%) -system.cpu.branchPred.lookups 14384905 # Number of BP lookups -system.cpu.branchPred.condPredicted 11471084 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 703956 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 9467627 # Number of BTB lookups -system.cpu.branchPred.BTBHits 7657685 # Number of BTB hits +system.cpu.branchPred.lookups 14384927 # Number of BP lookups +system.cpu.branchPred.condPredicted 11469310 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 704177 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 9471049 # Number of BTB lookups +system.cpu.branchPred.BTBHits 7661571 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 80.882834 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 1397242 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 72494 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 80.894640 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 1398227 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 72610 # Number of incorrect RAS predictions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51179212 # DTB read hits -system.cpu.dtb.read_misses 64531 # DTB read misses -system.cpu.dtb.write_hits 11698539 # DTB write hits -system.cpu.dtb.write_misses 15837 # DTB write misses +system.cpu.dtb.read_hits 51182106 # DTB read hits +system.cpu.dtb.read_misses 64421 # DTB read misses +system.cpu.dtb.write_hits 11699698 # DTB write hits +system.cpu.dtb.write_misses 15824 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3571 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2411 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 405 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 3567 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2374 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 404 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1396 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51243743 # DTB read accesses -system.cpu.dtb.write_accesses 11714376 # DTB write accesses +system.cpu.dtb.perms_faults 1314 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51246527 # DTB read accesses +system.cpu.dtb.write_accesses 11715522 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 62877751 # DTB hits -system.cpu.dtb.misses 80368 # DTB misses -system.cpu.dtb.accesses 62958119 # DTB accesses -system.cpu.itb.inst_hits 11513998 # ITB inst hits -system.cpu.itb.inst_misses 11344 # ITB inst misses +system.cpu.dtb.hits 62881804 # DTB hits +system.cpu.dtb.misses 80245 # DTB misses +system.cpu.dtb.accesses 62962049 # DTB accesses +system.cpu.itb.inst_hits 11522583 # ITB inst hits +system.cpu.itb.inst_misses 11276 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -955,148 +968,148 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2483 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2480 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2968 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 3012 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11525342 # ITB inst accesses -system.cpu.itb.hits 11513998 # DTB hits -system.cpu.itb.misses 11344 # DTB misses -system.cpu.itb.accesses 11525342 # DTB accesses -system.cpu.numCycles 474882944 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11533859 # ITB inst accesses +system.cpu.itb.hits 11522583 # DTB hits +system.cpu.itb.misses 11276 # DTB misses +system.cpu.itb.accesses 11533859 # DTB accesses +system.cpu.numCycles 474898657 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 29745457 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90266235 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14384905 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9054927 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20140969 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4652912 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 123687 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96003967 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2624 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 87891 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 2685420 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 468 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11510536 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 707949 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5425 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 151996950 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.740543 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.094686 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 29752889 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90273347 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14384927 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9059798 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20146705 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4653497 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 122274 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 96010555 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2615 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 88482 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 2690288 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 446 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11519088 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 708911 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5337 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 152021113 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.740504 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.094585 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 131871277 86.76% 86.76% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1302073 0.86% 87.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1710886 1.13% 88.74% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2295409 1.51% 90.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2102442 1.38% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1107607 0.73% 92.36% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2555872 1.68% 94.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 743971 0.49% 94.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8307413 5.47% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 131890125 86.76% 86.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1304050 0.86% 87.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1713045 1.13% 88.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2295968 1.51% 90.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2102742 1.38% 91.64% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1107769 0.73% 92.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2555355 1.68% 94.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744146 0.49% 94.54% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8307913 5.46% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 151996950 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::total 152021113 # Number of instructions fetched each cycle (Total) system.cpu.fetch.branchRate 0.030291 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.190081 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31502209 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 98125273 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18366247 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 966197 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3037024 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1956644 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 171990 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107262918 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 568386 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3037024 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33252800 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 39466554 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 52672825 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17523888 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6043859 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 102275198 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 20557 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1004739 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4063584 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 673 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106014240 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 466907038 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 432047963 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 10635 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78387438 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 27626801 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 830029 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 736499 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12184256 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19715159 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13304037 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1977063 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2478152 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95106473 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 1982467 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 122897190 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 166901 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 18919534 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47250176 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 500160 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 151996950 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.808550 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.527901 # Number of insts issued each cycle +system.cpu.fetch.rate 0.190090 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31508438 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 98138099 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18373215 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 963804 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3037557 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1957081 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171807 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107274658 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567663 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3037557 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33258738 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 39476292 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52673596 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17529662 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6045268 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102285915 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 20597 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1004806 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4066044 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 644 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106018919 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 466959682 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 432092489 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 10446 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387358 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 27631560 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830464 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 736820 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12181979 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19715902 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13307123 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1978281 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2470778 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95109477 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1982753 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 122906700 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 167286 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 18927569 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47237054 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 500451 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 152021113 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.808484 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.527863 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 108284402 71.24% 71.24% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13439431 8.84% 80.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 6944257 4.57% 84.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5857722 3.85% 88.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12372410 8.14% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2808060 1.85% 98.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1695891 1.12% 99.61% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 467423 0.31% 99.92% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 127354 0.08% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 108300469 71.24% 71.24% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13447891 8.85% 80.09% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 6945073 4.57% 84.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5857007 3.85% 88.51% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12370739 8.14% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2808869 1.85% 98.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1695394 1.12% 99.61% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 467391 0.31% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128280 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 151996950 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 152021113 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 62444 0.71% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 7 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.71% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8371933 94.63% 95.34% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 412257 4.66% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 61937 0.70% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 6 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8370529 94.64% 95.34% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 412377 4.66% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57615534 46.88% 47.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93100 0.08% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57620183 46.88% 47.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93128 0.08% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.25% # Type of FU issued @@ -1109,397 +1122,397 @@ system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.25% # Ty system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 33 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 24 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 3 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 6 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2115 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 25 0.00% 47.25% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 20 0.00% 47.25% # Type of FU issued system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52504661 42.72% 89.98% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12318028 10.02% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52507579 42.72% 89.98% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319960 10.02% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 122897190 # Type of FU issued -system.cpu.iq.rate 0.258795 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8846641 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071984 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406861293 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116024937 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85463742 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 23592 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12620 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10347 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131367569 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12596 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623590 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 122906700 # Type of FU issued +system.cpu.iq.rate 0.258806 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8844849 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071964 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 406902990 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116036304 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85470220 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23531 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12536 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10316 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131375312 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12571 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 623425 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4061151 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6344 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30249 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1572309 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4061911 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6363 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30197 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1575391 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107765 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 681284 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34107753 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 681273 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3037024 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30702730 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 434457 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97310809 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 203906 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19715159 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13304037 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1409970 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 113496 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3538 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30249 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 349429 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 269322 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 618751 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 120821579 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51866256 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075611 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3037557 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 30701555 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 434229 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97313991 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 205819 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19715902 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13307123 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1410230 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 113324 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3566 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30197 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 350181 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 268988 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 619169 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120829627 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51869148 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2077073 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221869 # number of nop insts executed -system.cpu.iew.exec_refs 64076774 # number of memory reference insts executed -system.cpu.iew.exec_branches 11475076 # Number of branches executed -system.cpu.iew.exec_stores 12210518 # Number of stores executed -system.cpu.iew.exec_rate 0.254424 # Inst execution rate -system.cpu.iew.wb_sent 119883669 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85474089 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47026181 # num instructions producing a value -system.cpu.iew.wb_consumers 87876552 # num instructions consuming a value +system.cpu.iew.exec_nop 221761 # number of nop insts executed +system.cpu.iew.exec_refs 64080783 # number of memory reference insts executed +system.cpu.iew.exec_branches 11475005 # Number of branches executed +system.cpu.iew.exec_stores 12211635 # Number of stores executed +system.cpu.iew.exec_rate 0.254432 # Inst execution rate +system.cpu.iew.wb_sent 119890224 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85480536 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47031033 # num instructions producing a value +system.cpu.iew.wb_consumers 87879900 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.179990 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535139 # average fanout of values written-back +system.cpu.iew.wb_rate 0.179997 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535174 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18658160 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1482307 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 534513 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 148959926 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.521933 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.510472 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18664214 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482302 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 534875 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 148983556 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.521850 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.510275 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 121529130 81.59% 81.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13302723 8.93% 90.52% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3899356 2.62% 93.13% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2115942 1.42% 94.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1939571 1.30% 95.86% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 978607 0.66% 96.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1596110 1.07% 97.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 718014 0.48% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2880473 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 121547303 81.58% 81.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13306218 8.93% 90.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3902162 2.62% 93.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2119528 1.42% 94.56% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1937783 1.30% 95.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 976082 0.66% 96.51% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1595601 1.07% 97.58% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 718241 0.48% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2880638 1.93% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 148959926 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60456137 # Number of instructions committed -system.cpu.commit.committedOps 77747122 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 148983556 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456059 # Number of instructions committed +system.cpu.commit.committedOps 77747065 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27385736 # Number of memory references committed -system.cpu.commit.loads 15654008 # Number of loads committed -system.cpu.commit.membars 403573 # Number of memory barriers committed -system.cpu.commit.branches 9961077 # Number of branches committed +system.cpu.commit.refs 27385723 # Number of memory references committed +system.cpu.commit.loads 15653991 # Number of loads committed +system.cpu.commit.membars 403571 # Number of memory barriers committed +system.cpu.commit.branches 9961071 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 68852562 # Number of committed integer instructions. -system.cpu.commit.function_calls 991208 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2880473 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68852511 # Number of committed integer instructions. +system.cpu.commit.function_calls 991207 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2880638 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 240636318 # The number of ROB reads -system.cpu.rob.rob_writes 195934369 # The number of ROB writes -system.cpu.timesIdled 1776906 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 322885994 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575316115 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60305756 # Number of Instructions Simulated -system.cpu.committedOps 77596741 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60305756 # Number of Instructions Simulated -system.cpu.cpi 7.874587 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.874587 # CPI: Total CPI of All Threads -system.cpu.ipc 0.126991 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.126991 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 547208469 # number of integer regfile reads -system.cpu.int_regfile_writes 87526188 # number of integer regfile writes -system.cpu.fp_regfile_reads 8624 # number of floating regfile reads -system.cpu.fp_regfile_writes 3008 # number of floating regfile writes -system.cpu.misc_regfile_reads 30165107 # number of misc regfile reads +system.cpu.rob.rob_reads 240665808 # The number of ROB reads +system.cpu.rob.rob_writes 195946920 # The number of ROB writes +system.cpu.timesIdled 1776652 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 322877544 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4575281578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60305678 # Number of Instructions Simulated +system.cpu.committedOps 77596684 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60305678 # Number of Instructions Simulated +system.cpu.cpi 7.874858 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.874858 # CPI: Total CPI of All Threads +system.cpu.ipc 0.126986 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.126986 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547244882 # number of integer regfile reads +system.cpu.int_regfile_writes 87532645 # number of integer regfile writes +system.cpu.fp_regfile_reads 8511 # number of floating regfile reads +system.cpu.fp_regfile_writes 2972 # number of floating regfile writes +system.cpu.misc_regfile_reads 30145050 # number of misc regfile reads system.cpu.misc_regfile_writes 831837 # number of misc regfile writes -system.cpu.toL2Bus.throughput 58889875 # Throughput (bytes/s) -system.cpu.toL2Bus.trans_dist::ReadReq 2658094 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadResp 2658093 # Transaction distribution +system.cpu.toL2Bus.throughput 58898886 # Throughput (bytes/s) +system.cpu.toL2Bus.trans_dist::ReadReq 2658060 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadResp 2658059 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteReq 763332 # Transaction distribution system.cpu.toL2Bus.trans_dist::WriteResp 763332 # Transaction distribution -system.cpu.toL2Bus.trans_dist::Writeback 607699 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeReq 2955 # Transaction distribution -system.cpu.toL2Bus.trans_dist::SCUpgradeReq 12 # Transaction distribution -system.cpu.toL2Bus.trans_dist::UpgradeResp 2967 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExReq 246142 # Transaction distribution -system.cpu.toL2Bus.trans_dist::ReadExResp 246142 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961671 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796233 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 31091 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 128199 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 7917194 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 62737088 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 85515993 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 43120 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 214584 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.tot_pkt_size::total 148510785 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.data_through_bus 148510785 # Total data (bytes) -system.cpu.toL2Bus.snoop_data_through_bus 194456 # Total snoop data (bytes) -system.cpu.toL2Bus.reqLayer0.occupancy 3128799181 # Layer occupancy (ticks) +system.cpu.toL2Bus.trans_dist::Writeback 607897 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeReq 2956 # Transaction distribution +system.cpu.toL2Bus.trans_dist::SCUpgradeReq 13 # Transaction distribution +system.cpu.toL2Bus.trans_dist::UpgradeResp 2969 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExReq 246128 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadExResp 246128 # Transaction distribution +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1961789 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5796637 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma::system.cpu.l2cache.cpu_side 30578 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma::system.cpu.l2cache.cpu_side 127052 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 7916056 # Packet count per connected master and slave (bytes) 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(read+write) misses -system.cpu.icache.demand_misses::total 1060761 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1060761 # number of overall misses -system.cpu.icache.overall_misses::total 1060761 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14273214680 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14273214680 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14273214680 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14273214680 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14273214680 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11510410 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11510410 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11510410 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11510410 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11510410 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092157 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092157 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092157 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092157 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092157 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13455.636736 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13455.636736 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13455.636736 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13455.636736 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 6677 # number of cycles access was blocked +system.cpu.icache.ReadReq_hits::cpu.inst 10457750 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10457750 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10457750 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10457750 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10457750 # number of overall hits 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+system.cpu.icache.overall_miss_latency::cpu.inst 14272429649 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 14272429649 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11518964 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11518964 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11518964 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11518964 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11518964 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.092128 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.092128 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.092128 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.092128 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.092128 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13449.153186 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13449.153186 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13449.153186 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13449.153186 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5990 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 323 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 322 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 20.671827 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 18.602484 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79476 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 79476 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 79476 # number of demand (read+write) MSHR hits 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-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11587356987 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11587356987 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11587356987 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79868 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79868 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79868 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79868 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79868 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981346 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 981346 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 981346 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 981346 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 981346 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 981346 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11584683024 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11584683024 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11584683024 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11584683024 # number of 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-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.085252 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11808.350262 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11808.350262 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11808.350262 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085194 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085194 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085194 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11804.891469 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11804.891469 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11804.891469 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 64371 # number of replacements -system.cpu.l2cache.tags.tagsinuse 51366.694603 # Cycle average of tags in use -system.cpu.l2cache.tags.total_refs 1888244 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 129769 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 14.550810 # Average number of references to valid blocks. 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Average number of references to valid blocks. +system.cpu.l2cache.tags.warmup_cycle 2489982729000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.tags.occ_blocks::writebacks 36926.272860 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 27.936805 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.000373 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 8173.687928 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 6235.066458 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::writebacks 0.563450 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000426 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.124750 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.095177 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.783794 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 53605 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10777 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 967799 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387031 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1419212 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607699 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607699 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 40 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 40 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 9 # number of SCUpgradeReq hits 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mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65333.333333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 60827.437394 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63391.586712 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62029.298060 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 184377712817 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 184383900066 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000192 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012583 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026780 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015983 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986130 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.230769 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541231 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000799 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 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system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.tags.replacements 643382 # number of replacements +system.cpu.dcache.tags.replacements 643483 # number of replacements system.cpu.dcache.tags.tagsinuse 511.993331 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 21503755 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 643894 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 33.396421 # Average number of references to valid blocks. +system.cpu.dcache.tags.total_refs 21507621 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 643995 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 33.397186 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 42430250 # Cycle when the warmup percentage was hit. system.cpu.dcache.tags.occ_blocks::cpu.data 511.993331 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.999987 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.999987 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13751955 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13751955 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7258296 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7258296 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 242828 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 242828 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247595 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247595 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21010251 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21010251 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21010251 # number of overall hits -system.cpu.dcache.overall_hits::total 21010251 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 737736 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 737736 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2963735 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2963735 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13555 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13555 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 12 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 12 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3701471 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3701471 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3701471 # number of overall misses -system.cpu.dcache.overall_misses::total 3701471 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 10012711310 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 141368125836 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 185715250 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 193503 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 151380837146 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 151380837146 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 151380837146 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14489691 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10222031 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 256383 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247607 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24711722 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24711722 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24711722 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24711722 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050915 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.289936 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052870 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000048 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.149786 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.149786 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.149786 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.149786 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13572.214600 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13572.214600 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47699.313817 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47699.313817 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13700.866839 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 40897.480257 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 40897.480257 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 33174 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 27500 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2643 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 285 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.551646 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 96.491228 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13755484 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13755484 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7258628 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7258628 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 242811 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 242811 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247593 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247593 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21014112 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21014112 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21014112 # number of overall hits +system.cpu.dcache.overall_hits::total 21014112 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 737297 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 737297 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2963410 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2963410 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13576 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13576 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 13 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 13 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3700707 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3700707 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3700707 # number of overall misses +system.cpu.dcache.overall_misses::total 3700707 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10005137822 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 141347559382 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 185728250 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 206503 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 151352697204 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 151352697204 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 151352697204 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14492781 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222038 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256387 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247606 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24714819 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24714819 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24714819 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24714819 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050873 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289904 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052951 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000053 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149736 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149736 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149736 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149736 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13570.023779 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13570.023779 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47697.604915 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47697.604915 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13680.631261 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15884.846154 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 40898.319484 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 40898.319484 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 32831 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 27415 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2635 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 279 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.459583 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 98.261649 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607699 # number of writebacks -system.cpu.dcache.writebacks::total 607699 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 352116 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 352116 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2714717 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1344 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3066833 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3066833 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3066833 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385620 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385620 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249018 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249018 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12211 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 12 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634638 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634638 # number 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-system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000048 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.writebacks::writebacks 607897 # number of writebacks +system.cpu.dcache.writebacks::total 607897 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 351582 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 351582 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2714405 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1345 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3065987 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3065987 # number of demand (read+write) MSHR hits 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+system.cpu.dcache.demand_mshr_misses::total 634720 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634720 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634720 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4972029375 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 11600619783 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 146011500 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 180497 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16572649158 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16572649158 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182328280000 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26841536765 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 209169816765 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026614 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024360 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047705 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000053 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000053 # mshr miss rate for StoreCondReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.025682 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025682 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.025682 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12889.163238 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46590.465500 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11957.333552 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26112.813393 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 26112.813393 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12890.422657 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46587.898970 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11937.821928 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13884.384615 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26110.173239 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 26110.173239 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1796,16 +1809,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1499087755049 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499087755049 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1499087755049 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1499067779549 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1499067779549 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1499067779549 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 83035 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83033 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |