diff options
| author | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
|---|---|---|
| committer | Ali Saidi <saidi@eecs.umich.edu> | 2013-01-08 08:54:16 -0500 |
| commit | fbeced6135151cc70f83b95603589bcca53f3efc (patch) | |
| tree | cb8a877be1970b24d2eca0851fa5bfe5f5bca340 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3 | |
| parent | 25efbb5bdcc037826aac4ee2c9604dabb70e0ee5 (diff) | |
| download | gem5-fbeced6135151cc70f83b95603589bcca53f3efc.tar.xz | |
stats: update stats for previous six changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt | 1738 |
1 files changed, 869 insertions, 869 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index b454be827..e98399cb1 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -1,114 +1,126 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.523518 # Number of seconds simulated -sim_ticks 2523517846500 # Number of ticks simulated -final_tick 2523517846500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.523205 # Number of seconds simulated +sim_ticks 2523204701000 # Number of ticks simulated +final_tick 2523204701000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24932 # Simulator instruction rate (inst/s) -host_op_rate 32070 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1038273503 # Simulator tick rate (ticks/s) -host_mem_usage 403456 # Number of bytes of host memory used -host_seconds 2430.49 # Real time elapsed on the host -sim_insts 60597240 # Number of instructions simulated -sim_ops 77945362 # Number of ops (including micro ops) simulated +host_inst_rate 64094 # Simulator instruction rate (inst/s) +host_op_rate 82471 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2681679652 # Simulator tick rate (ticks/s) +host_mem_usage 409992 # Number of bytes of host memory used +host_seconds 940.90 # Real time elapsed on the host +sim_insts 60306320 # Number of instructions simulated +sim_ops 77597310 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 119537664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.dtb.walker 2624 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 798272 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9093392 # Number of bytes read from this memory -system.physmem.bytes_read::total 129432080 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 798272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 798272 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3783104 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.dtb.walker 3264 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 797888 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9093968 # Number of bytes read from this memory +system.physmem.bytes_read::total 129432976 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 797888 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3783680 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6799176 # Number of bytes written to this memory +system.physmem.bytes_written::total 6799752 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14942208 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.dtb.walker 41 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 12473 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 142118 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15096842 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59111 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.dtb.walker 51 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 12467 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 142127 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15096856 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59120 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813129 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47369455 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.dtb.walker 1040 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.itb.walker 51 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 316333 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3603459 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51290337 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 316333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 316333 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1499139 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1195186 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2694325 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1499139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47369455 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.dtb.walker 1040 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.itb.walker 51 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 316333 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4798644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53984661 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15096842 # Total number of read requests seen -system.physmem.writeReqs 813129 # Total number of write requests seen -system.physmem.cpureqs 218393 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 966197888 # Total number of bytes read from memory -system.physmem.bytesWritten 52040256 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 129432080 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6799176 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 355 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4684 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 943616 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 943949 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 943429 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 943465 # Track reads on a per bank basis +system.physmem.num_writes::total 813138 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47375333 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.dtb.walker 1294 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.itb.walker 76 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 316220 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3604134 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51297057 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 316220 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 316220 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1499553 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1195334 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2694887 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1499553 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47375333 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.dtb.walker 1294 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.itb.walker 76 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 316220 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4799468 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53991944 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15096856 # Total number of read requests seen +system.physmem.writeReqs 813138 # Total number of write requests seen +system.physmem.cpureqs 218433 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 966198784 # Total number of bytes read from memory +system.physmem.bytesWritten 52040832 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 129432976 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6799752 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 308 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 4701 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 943619 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 943957 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 943426 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 943469 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 943373 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 943244 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 943101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 943294 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 943771 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 943633 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 943702 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 943683 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 943743 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 943617 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 943644 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 943223 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50104 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50365 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 49969 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50029 # Track writes on a per bank basis +system.physmem.perBankRdReqs::5 943243 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 943117 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 943291 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 943773 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 943640 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 943701 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 943687 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 943747 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 943605 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 943661 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 943239 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50100 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50374 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 49971 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50036 # Track writes on a per bank basis system.physmem.perBankWrReqs::4 50909 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50818 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50662 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51139 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51219 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51125 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50668 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50825 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51146 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51221 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51118 # Track writes on a per bank basis system.physmem.perBankWrReqs::11 51111 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51357 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51177 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51291 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51356 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51168 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51290 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51027 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 1183132 # Number of times wr buffer was full causing retry -system.physmem.totGap 2523516727500 # Total gap between requests +system.physmem.numWrRetry 1189836 # Number of times wr buffer was full causing retry +system.physmem.totGap 2523203522000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 36 # Categorize read packet sizes system.physmem.readPktSize::3 14942208 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154598 # Categorize read packet sizes +system.physmem.readPktSize::6 154612 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes system.physmem.writePktSize::1 0 # categorize write packet sizes -system.physmem.writePktSize::2 1937150 # categorize write packet sizes +system.physmem.writePktSize::2 1943854 # categorize write packet sizes system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 59111 # categorize write packet sizes +system.physmem.writePktSize::6 59120 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -117,28 +129,28 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 4684 # categorize neither packet sizes +system.physmem.neitherpktsize::6 4701 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 1042834 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 981659 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 938516 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 972890 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2730387 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2738053 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 5375105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 45255 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 30596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 30326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 30339 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 57584 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 37998 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 64788 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17179 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 2831 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 20 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1043197 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 981510 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 938251 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 972710 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2730334 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2737857 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5375310 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45160 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 30623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 30406 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 30384 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 57649 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 38036 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 64911 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2864 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 121 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 18 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 6 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -153,72 +165,60 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2802 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 3008 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3102 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3240 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3424 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3580 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3721 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3875 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2796 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2911 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3093 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3215 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3380 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3546 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3837 # What write queue length does an incoming req see system.physmem.wrQLenPdf::9 35354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35353 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35354 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35353 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 32552 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32442 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 32252 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 32114 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 31930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 31774 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 31633 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 31479 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 32558 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32443 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 32261 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 32139 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 31974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 31808 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 31658 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 31517 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 328143428340 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 404872878340 # Sum of mem lat for all requests -system.physmem.totBusLat 60385948000 # Total cycles spent in databus access -system.physmem.totBankLat 16343502000 # Total cycles spent in bank access -system.physmem.avgQLat 21736.41 # Average queueing delay per request -system.physmem.avgBankLat 1082.60 # Average bank access latency per request +system.physmem.totQLat 328245753609 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 404988565609 # Sum of mem lat for all requests +system.physmem.totBusLat 60386192000 # Total cycles spent in databus access +system.physmem.totBankLat 16356620000 # Total cycles spent in bank access +system.physmem.avgQLat 21743.10 # Average queueing delay per request +system.physmem.avgBankLat 1083.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26819.01 # Average memory access latency -system.physmem.avgRdBW 382.88 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26826.57 # Average memory access latency +system.physmem.avgRdBW 382.93 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 51.29 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 51.30 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.69 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.52 # Data bus utilization in percentage system.physmem.avgRdQLen 0.16 # Average read queue length over time -system.physmem.avgWrQLen 11.85 # Average write queue length over time -system.physmem.readRowHits 15052691 # Number of row buffer hits during reads -system.physmem.writeRowHits 784814 # Number of row buffer hits during writes +system.physmem.avgWrQLen 10.68 # Average write queue length over time +system.physmem.readRowHits 15052450 # Number of row buffer hits during reads +system.physmem.writeRowHits 784654 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.52 # Row buffer hit rate for writes -system.physmem.avgGap 158612.28 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 64 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 64 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 64 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 1 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 1 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 25 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 25 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 25 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 25 # Total bandwidth to/from this memory (bytes/s) +system.physmem.writeRowHitRate 96.50 # Row buffer hit rate for writes +system.physmem.avgGap 158592.36 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -227,27 +227,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 51295505 # DTB read hits -system.cpu.dtb.read_misses 73548 # DTB read misses -system.cpu.dtb.write_hits 11769416 # DTB write hits -system.cpu.dtb.write_misses 17308 # DTB write misses +system.cpu.dtb.read_hits 51212683 # DTB read hits +system.cpu.dtb.read_misses 73387 # DTB read misses +system.cpu.dtb.write_hits 11701466 # DTB write hits +system.cpu.dtb.write_misses 17011 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 4227 # Number of entries that have been flushed from TLB -system.cpu.dtb.align_faults 2384 # Number of TLB faults due to alignment restrictions -system.cpu.dtb.prefetch_faults 485 # Number of TLB faults due to prefetch +system.cpu.dtb.flush_entries 4259 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 2457 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 493 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.dtb.perms_faults 1341 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 51369053 # DTB read accesses -system.cpu.dtb.write_accesses 11786724 # DTB write accesses +system.cpu.dtb.perms_faults 1316 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 51286070 # DTB read accesses +system.cpu.dtb.write_accesses 11718477 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 63064921 # DTB hits -system.cpu.dtb.misses 90856 # DTB misses -system.cpu.dtb.accesses 63155777 # DTB accesses -system.cpu.itb.inst_hits 11599470 # ITB inst hits -system.cpu.itb.inst_misses 11387 # ITB inst misses +system.cpu.dtb.hits 62914149 # DTB hits +system.cpu.dtb.misses 90398 # DTB misses +system.cpu.dtb.accesses 63004547 # DTB accesses +system.cpu.itb.inst_hits 11530598 # ITB inst hits +system.cpu.itb.inst_misses 11503 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.write_hits 0 # DTB write hits @@ -256,122 +256,122 @@ system.cpu.itb.flush_tlb 2 # Nu system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.itb.flush_entries 2571 # Number of entries that have been flushed from TLB +system.cpu.itb.flush_entries 2585 # Number of entries that have been flushed from TLB system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu.itb.perms_faults 2925 # Number of TLB faults due to permissions restrictions +system.cpu.itb.perms_faults 2992 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 11610857 # ITB inst accesses -system.cpu.itb.hits 11599470 # DTB hits -system.cpu.itb.misses 11387 # DTB misses -system.cpu.itb.accesses 11610857 # DTB accesses -system.cpu.numCycles 470965317 # number of cpu cycles simulated +system.cpu.itb.inst_accesses 11542101 # ITB inst accesses +system.cpu.itb.hits 11530598 # DTB hits +system.cpu.itb.misses 11503 # DTB misses +system.cpu.itb.accesses 11542101 # DTB accesses +system.cpu.numCycles 469830472 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 14487364 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 11552940 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 711872 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 9478925 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 7718754 # Number of BTB hits +system.cpu.BPredUnit.lookups 14400111 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 11483411 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 706790 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 9536193 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 7670918 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 1413170 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 72913 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 29863213 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 90950612 # Number of instructions fetch has processed -system.cpu.fetch.Branches 14487364 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 9131924 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 20302505 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 4756883 # Number of cycles fetch has spent squashing -system.cpu.fetch.TlbCycles 122119 # Number of cycles fetch has spent waiting for tlb -system.cpu.fetch.BlockedCycles 96718680 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 2503 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 94285 # Number of stall cycles due to pending traps -system.cpu.fetch.PendingQuiesceStallCycles 205383 # Number of stall cycles due to pending quiesce instructions -system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 11595815 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 694954 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.ItlbSquashes 5716 # Number of outstanding ITLB misses that were squashed -system.cpu.fetch.rateDist::samples 150585846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.753226 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.110122 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 1400062 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72720 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 29776209 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 90590417 # Number of instructions fetch has processed +system.cpu.fetch.Branches 14400111 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 9070980 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 20202933 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 4722920 # Number of cycles fetch has spent squashing +system.cpu.fetch.TlbCycles 125032 # Number of cycles fetch has spent waiting for tlb +system.cpu.fetch.BlockedCycles 95829394 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2555 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 95206 # Number of stall cycles due to pending traps +system.cpu.fetch.PendingQuiesceStallCycles 195647 # Number of stall cycles due to pending quiesce instructions +system.cpu.fetch.IcacheWaitRetryStallCycles 358 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 11526864 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 692679 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.ItlbSquashes 5866 # Number of outstanding ITLB misses that were squashed +system.cpu.fetch.rateDist::samples 149483349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.755286 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.112756 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 130298669 86.53% 86.53% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1345087 0.89% 87.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 1687300 1.12% 88.54% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 2309882 1.53% 90.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 2120076 1.41% 91.48% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 1117365 0.74% 92.23% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 2592055 1.72% 93.95% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 766865 0.51% 94.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 8348547 5.54% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 129295948 86.50% 86.50% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1305590 0.87% 87.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 1714120 1.15% 88.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 2303032 1.54% 90.06% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 2113838 1.41% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 1113268 0.74% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 2558966 1.71% 93.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 744431 0.50% 94.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 8334156 5.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 150585846 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.030761 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.193115 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 31645642 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 96356331 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 18440866 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 1036174 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 3106833 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 1972079 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 172496 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 107972230 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 569848 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 3106833 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 33398103 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 36860235 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 53381295 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 17668341 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 6171039 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 103073979 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 21323 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 1016179 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 4134721 # Number of times rename has blocked due to LSQ full -system.cpu.rename.FullRegisterEvents 29043 # Number of times there has been no free registers -system.cpu.rename.RenamedOperands 106845782 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 470577676 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 470486821 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 90855 # Number of floating rename lookups -system.cpu.rename.CommittedMaps 78731209 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 28114572 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 880520 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 786795 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 12341610 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 19847152 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 13390380 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 1964070 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 2407797 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 95636460 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 2047932 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 123412976 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 169796 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 19147761 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 47762380 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 503425 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 150585846 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.819552 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.531798 # Number of insts issued each cycle +system.cpu.fetch.rateDist::total 149483349 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.030650 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.192815 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 31568829 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 95441634 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 18423468 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 962668 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 3086750 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 1958757 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 171759 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 107509453 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 567408 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 3086750 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 33316275 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 36833231 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 52536283 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 17586527 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 6124283 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 102642292 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 21405 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1017740 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 4132022 # Number of times rename has blocked due to LSQ full +system.cpu.rename.FullRegisterEvents 26613 # Number of times there has been no free registers +system.cpu.rename.RenamedOperands 106442929 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 468643722 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 468552758 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 90964 # Number of floating rename lookups +system.cpu.rename.CommittedMaps 78387937 # Number of HB maps that are committed +system.cpu.rename.UndoneMaps 28054991 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 830730 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 737238 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 12262816 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 19748975 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 13319169 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 1971812 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 2437048 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 95275123 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 1983935 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 123023978 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 168737 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 19077764 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 47550140 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 501597 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 149483349 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.822995 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.535359 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 106411056 70.66% 70.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 13811108 9.17% 79.84% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 7031286 4.67% 84.51% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 5838601 3.88% 88.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 12442775 8.26% 96.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 2756258 1.83% 98.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 1722165 1.14% 99.62% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 442663 0.29% 99.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 129934 0.09% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 105584615 70.63% 70.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 13583539 9.09% 79.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 7010052 4.69% 84.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 5841080 3.91% 88.32% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 12416825 8.31% 96.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 2753053 1.84% 98.47% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 1723438 1.15% 99.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 442074 0.30% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 128673 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 150585846 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 149483349 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 60097 0.68% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 3 0.00% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 60184 0.68% 0.68% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 2 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::IntDiv 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatAdd 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::FloatCmp 0 0.00% 0.68% # attempts to use FU when none available @@ -399,383 +399,383 @@ system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 0.68% # at system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.68% # attempts to use FU when none available system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 0.68% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 8367175 94.63% 95.31% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 414340 4.69% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 8365721 94.70% 95.38% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 408464 4.62% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 363666 0.29% 0.29% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 57952199 46.96% 47.25% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 93294 0.08% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 21 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 2 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 2114 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 16 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.33% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 52612072 42.63% 89.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 12389576 10.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 363666 0.30% 0.30% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 57715634 46.91% 47.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 93245 0.08% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 22 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 17 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 2113 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 17 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.29% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 52529463 42.70% 89.99% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 12319801 10.01% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 123412976 # Type of FU issued -system.cpu.iq.rate 0.262043 # Inst issue rate -system.cpu.iq.fu_busy_cnt 8841615 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.071643 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 406490722 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 116848589 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 85936823 # Number of integer instruction queue wakeup accesses -system.cpu.iq.fp_inst_queue_reads 22982 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 12524 # Number of floating instruction queue writes -system.cpu.iq.fp_inst_queue_wakeup_accesses 10288 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 131878765 # Number of integer alu accesses -system.cpu.iq.fp_alu_accesses 12160 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 623393 # Number of loads that had data forwarded from stores +system.cpu.iq.FU_type_0::total 123023978 # Type of FU issued +system.cpu.iq.rate 0.261848 # Inst issue rate +system.cpu.iq.fu_busy_cnt 8834371 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.071810 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 404601083 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 116353341 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 85576668 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fp_inst_queue_reads 23374 # Number of floating instruction queue reads +system.cpu.iq.fp_inst_queue_writes 12534 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_wakeup_accesses 10291 # Number of floating instruction queue wakeup accesses +system.cpu.iq.int_alu_accesses 131482242 # Number of integer alu accesses +system.cpu.iq.fp_alu_accesses 12441 # Number of floating point alu accesses +system.cpu.iew.lsq.thread0.forwLoads 624673 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 4131120 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 6284 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 30077 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1591861 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 4094892 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 6341 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 30170 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 1587360 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 34107803 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 700236 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 34109626 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 700754 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 3106833 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 27952249 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 439003 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 97906020 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 205363 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 19847152 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 13390380 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 1460347 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 117327 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 3551 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 30077 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 353051 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 272581 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 625632 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 121337067 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 51981447 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 2075909 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 3086750 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 27929596 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 435687 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 97480096 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 201338 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 19748975 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 13319169 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 1411062 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 114312 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3640 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 30170 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 351854 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 269334 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 621188 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 120956829 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 51898553 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 2067149 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 221628 # number of nop insts executed -system.cpu.iew.exec_refs 64262784 # number of memory reference insts executed -system.cpu.iew.exec_branches 11537560 # Number of branches executed -system.cpu.iew.exec_stores 12281337 # Number of stores executed -system.cpu.iew.exec_rate 0.257635 # Inst execution rate -system.cpu.iew.wb_sent 120375089 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 85947111 # cumulative count of insts written-back -system.cpu.iew.wb_producers 47183541 # num instructions producing a value -system.cpu.iew.wb_consumers 88082196 # num instructions consuming a value +system.cpu.iew.exec_nop 221038 # number of nop insts executed +system.cpu.iew.exec_refs 64111605 # number of memory reference insts executed +system.cpu.iew.exec_branches 11477980 # Number of branches executed +system.cpu.iew.exec_stores 12213052 # Number of stores executed +system.cpu.iew.exec_rate 0.257448 # Inst execution rate +system.cpu.iew.wb_sent 119998029 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 85586959 # cumulative count of insts written-back +system.cpu.iew.wb_producers 47051195 # num instructions producing a value +system.cpu.iew.wb_consumers 87903517 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.182491 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.535676 # average fanout of values written-back +system.cpu.iew.wb_rate 0.182166 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.535260 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 18905107 # The number of squashed insts skipped by commit -system.cpu.commit.commitNonSpecStalls 1544507 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 541940 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 147479013 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.529538 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.516870 # Number of insts commited each cycle +system.cpu.commit.commitSquashedInsts 18827380 # The number of squashed insts skipped by commit +system.cpu.commit.commitNonSpecStalls 1482338 # The number of times commit has been forced to stall to communicate backwards +system.cpu.commit.branchMispredicts 537525 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 146396599 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.531076 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.520958 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 119767946 81.21% 81.21% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 13521242 9.17% 90.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 3932347 2.67% 93.04% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 2139837 1.45% 94.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 1947041 1.32% 95.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 981141 0.67% 96.48% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 1580635 1.07% 97.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 757975 0.51% 98.07% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 2850849 1.93% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 118947239 81.25% 81.25% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 13290993 9.08% 90.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 3927955 2.68% 93.01% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 2128242 1.45% 94.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 1935809 1.32% 95.79% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 981559 0.67% 96.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 1577858 1.08% 97.54% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 757669 0.52% 98.05% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 2849275 1.95% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 147479013 # Number of insts commited each cycle -system.cpu.commit.committedInsts 60747621 # Number of instructions committed -system.cpu.commit.committedOps 78095743 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 146396599 # Number of insts commited each cycle +system.cpu.commit.committedInsts 60456701 # Number of instructions committed +system.cpu.commit.committedOps 77747691 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu.commit.refs 27514551 # Number of memory references committed -system.cpu.commit.loads 15716032 # Number of loads committed -system.cpu.commit.membars 413105 # Number of memory barriers committed -system.cpu.commit.branches 10023101 # Number of branches committed +system.cpu.commit.refs 27385892 # Number of memory references committed +system.cpu.commit.loads 15654083 # Number of loads committed +system.cpu.commit.membars 403583 # Number of memory barriers committed +system.cpu.commit.branches 9961154 # Number of branches committed system.cpu.commit.fp_insts 10212 # Number of committed floating point instructions. -system.cpu.commit.int_insts 69134175 # Number of committed integer instructions. -system.cpu.commit.function_calls 995982 # Number of function calls committed. -system.cpu.commit.bw_lim_events 2850849 # number cycles where commit BW limit reached +system.cpu.commit.int_insts 68853054 # Number of committed integer instructions. +system.cpu.commit.function_calls 991222 # Number of function calls committed. +system.cpu.commit.bw_lim_events 2849275 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 239713879 # The number of ROB reads -system.cpu.rob.rob_writes 197204165 # The number of ROB writes -system.cpu.timesIdled 1775890 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 320379471 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.quiesceCycles 4575982354 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu.committedInsts 60597240 # Number of Instructions Simulated -system.cpu.committedOps 77945362 # Number of Ops (including micro ops) Simulated -system.cpu.committedInsts_total 60597240 # Number of Instructions Simulated -system.cpu.cpi 7.772059 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.772059 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128666 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128666 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 549724990 # number of integer regfile reads -system.cpu.int_regfile_writes 88045459 # number of integer regfile writes -system.cpu.fp_regfile_reads 8276 # number of floating regfile reads -system.cpu.fp_regfile_writes 2926 # number of floating regfile writes -system.cpu.misc_regfile_reads 30431218 # number of misc regfile reads -system.cpu.misc_regfile_writes 912900 # number of misc regfile writes -system.cpu.icache.replacements 981280 # number of replacements -system.cpu.icache.tagsinuse 511.007424 # Cycle average of tags in use -system.cpu.icache.total_refs 10533801 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 981792 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 10.729157 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 6666221000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.007424 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.998061 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.998061 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 10533801 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 10533801 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 10533801 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 10533801 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 10533801 # number of overall hits -system.cpu.icache.overall_hits::total 10533801 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 1061888 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 1061888 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 1061888 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 1061888 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 1061888 # number of overall misses -system.cpu.icache.overall_misses::total 1061888 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13967491489 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13967491489 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13967491489 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13967491489 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13967491489 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13967491489 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 11595689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 11595689 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 11595689 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 11595689 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 11595689 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 11595689 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091576 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.091576 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.091576 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.091576 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.091576 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.091576 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13153.450730 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13153.450730 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13153.450730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13153.450730 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13153.450730 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 5396 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 1220 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 303 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 17.808581 # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 610 # average number of cycles each access was blocked +system.cpu.rob.rob_reads 238273902 # The number of ROB reads +system.cpu.rob.rob_writes 196332947 # The number of ROB writes +system.cpu.timesIdled 1769968 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 320347123 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.quiesceCycles 4576495890 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu.committedInsts 60306320 # Number of Instructions Simulated +system.cpu.committedOps 77597310 # Number of Ops (including micro ops) Simulated +system.cpu.committedInsts_total 60306320 # Number of Instructions Simulated +system.cpu.cpi 7.790734 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.790734 # CPI: Total CPI of All Threads +system.cpu.ipc 0.128358 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.128358 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 547824485 # number of integer regfile reads +system.cpu.int_regfile_writes 87698031 # number of integer regfile writes +system.cpu.fp_regfile_reads 8340 # number of floating regfile reads +system.cpu.fp_regfile_writes 2902 # number of floating regfile writes +system.cpu.misc_regfile_reads 30214457 # number of misc regfile reads +system.cpu.misc_regfile_writes 831851 # number of misc regfile writes +system.cpu.icache.replacements 979772 # number of replacements +system.cpu.icache.tagsinuse 511.620578 # Cycle average of tags in use +system.cpu.icache.total_refs 10466836 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 980284 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 10.677351 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 6363732000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.620578 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.999259 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.999259 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 10466836 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 10466836 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 10466836 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 10466836 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 10466836 # number of overall hits +system.cpu.icache.overall_hits::total 10466836 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1059904 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1059904 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1059904 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1059904 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1059904 # number of overall misses +system.cpu.icache.overall_misses::total 1059904 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13935365493 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13935365493 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13935365493 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13935365493 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13935365493 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13935365493 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 11526740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 11526740 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 11526740 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 11526740 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 11526740 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 11526740 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.091952 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.091952 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.091952 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.091952 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.091952 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.091952 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13147.761961 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13147.761961 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13147.761961 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13147.761961 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13147.761961 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5103 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 436 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 297 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 17.181818 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets 436 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 80057 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 80057 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 80057 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 80057 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 80057 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 80057 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 981831 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 981831 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 981831 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 981831 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 981831 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 981831 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11353310491 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11353310491 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11353310491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11353310491 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11353310491 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11353310491 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 79583 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 79583 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 79583 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 79583 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 79583 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 79583 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 980321 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 980321 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 980321 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 980321 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 980321 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 980321 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11335281493 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11335281493 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11335281493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11335281493 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11335281493 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11335281493 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 6803000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 6803000 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 6803000 # number of overall MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::total 6803000 # number of overall MSHR uncacheable cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.084672 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.084672 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.084672 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.084672 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11563.406015 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11563.406015 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11563.406015 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11563.406015 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.085048 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.085048 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.085048 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.085048 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11562.826353 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11562.826353 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11562.826353 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11562.826353 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.l2cache.replacements 64370 # number of replacements -system.cpu.l2cache.tagsinuse 51358.666800 # Cycle average of tags in use -system.cpu.l2cache.total_refs 1910788 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 129761 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 14.725441 # Average number of references to valid blocks. -system.cpu.l2cache.warmup_cycle 2488452468500 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::writebacks 36927.008868 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.dtb.walker 28.274765 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000348 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.inst 8177.411143 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 6225.971675 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::writebacks 0.563461 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000431 # Average percentage of cache occupancy +system.cpu.l2cache.replacements 64384 # number of replacements +system.cpu.l2cache.tagsinuse 51365.557849 # Cycle average of tags in use +system.cpu.l2cache.total_refs 1909698 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 129778 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 14.715114 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 2488155004000 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::writebacks 36926.744718 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.dtb.walker 36.464010 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.003926 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 8168.761699 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 6233.583496 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::writebacks 0.563457 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000556 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.inst 0.124777 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.095001 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.783671 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78622 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10599 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.inst 968211 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 387222 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 1444654 # number of ReadReq hits -system.cpu.l2cache.Writeback_hits::writebacks 607832 # number of Writeback hits -system.cpu.l2cache.Writeback_hits::total 607832 # number of Writeback hits -system.cpu.l2cache.UpgradeReq_hits::cpu.data 41 # number of UpgradeReq hits -system.cpu.l2cache.UpgradeReq_hits::total 41 # number of UpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 13 # number of SCUpgradeReq hits -system.cpu.l2cache.SCUpgradeReq_hits::total 13 # number of SCUpgradeReq hits -system.cpu.l2cache.ReadExReq_hits::cpu.data 112968 # number of ReadExReq hits -system.cpu.l2cache.ReadExReq_hits::total 112968 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.dtb.walker 78622 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.itb.walker 10599 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.inst 968211 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 500190 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 1557622 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.dtb.walker 78622 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.itb.walker 10599 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.inst 968211 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 500190 # number of overall hits -system.cpu.l2cache.overall_hits::total 1557622 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 41 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.inst 12367 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 10717 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 23127 # number of ReadReq misses -system.cpu.l2cache.UpgradeReq_misses::cpu.data 2921 # number of UpgradeReq misses -system.cpu.l2cache.UpgradeReq_misses::total 2921 # number of UpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 3 # number of SCUpgradeReq misses -system.cpu.l2cache.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses -system.cpu.l2cache.ReadExReq_misses::cpu.data 133186 # number of ReadExReq misses -system.cpu.l2cache.ReadExReq_misses::total 133186 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.dtb.walker 41 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.inst 12367 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 143903 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 156313 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.dtb.walker 41 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.inst 12367 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 143903 # number of overall misses -system.cpu.l2cache.overall_misses::total 156313 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 2982500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 118000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653684500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 590050498 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 1246835498 # number of ReadReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 431500 # number of UpgradeReq miss cycles -system.cpu.l2cache.UpgradeReq_miss_latency::total 431500 # number of UpgradeReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6675201498 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6675201498 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 2982500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 118000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 653684500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7265251996 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 7922036996 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 2982500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 118000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 653684500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7265251996 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 7922036996 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78663 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10601 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.inst 980578 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 397939 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 1467781 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::writebacks 607832 # number of Writeback accesses(hits+misses) -system.cpu.l2cache.Writeback_accesses::total 607832 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.occ_percent::cpu.inst 0.124645 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.095117 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.783776 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 78725 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 10899 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 966625 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 387064 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 1443313 # number of ReadReq hits +system.cpu.l2cache.Writeback_hits::writebacks 607596 # number of Writeback hits +system.cpu.l2cache.Writeback_hits::total 607596 # number of Writeback hits +system.cpu.l2cache.UpgradeReq_hits::cpu.data 39 # number of UpgradeReq hits +system.cpu.l2cache.UpgradeReq_hits::total 39 # number of UpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::cpu.data 10 # number of SCUpgradeReq hits +system.cpu.l2cache.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits +system.cpu.l2cache.ReadExReq_hits::cpu.data 112907 # number of ReadExReq hits +system.cpu.l2cache.ReadExReq_hits::total 112907 # number of ReadExReq hits +system.cpu.l2cache.demand_hits::cpu.dtb.walker 78725 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.itb.walker 10899 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 966625 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 499971 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 1556220 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.dtb.walker 78725 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.itb.walker 10899 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 966625 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 499971 # number of overall hits +system.cpu.l2cache.overall_hits::total 1556220 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 51 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 12362 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 10723 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 23139 # number of ReadReq misses +system.cpu.l2cache.UpgradeReq_misses::cpu.data 2923 # number of UpgradeReq misses +system.cpu.l2cache.UpgradeReq_misses::total 2923 # number of UpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::cpu.data 4 # number of SCUpgradeReq misses +system.cpu.l2cache.SCUpgradeReq_misses::total 4 # number of SCUpgradeReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 133204 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 133204 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.dtb.walker 51 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 12362 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 143927 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 156343 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.dtb.walker 51 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.itb.walker 3 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 12362 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 143927 # number of overall misses +system.cpu.l2cache.overall_misses::total 156343 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 3708000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 187000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 653051500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 588973999 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 1245920499 # number of ReadReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 478500 # number of UpgradeReq miss cycles +system.cpu.l2cache.UpgradeReq_miss_latency::total 478500 # number of UpgradeReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6665784498 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 6665784498 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 3708000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 187000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 653051500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7254758497 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 7911704997 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 3708000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 187000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 653051500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7254758497 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 7911704997 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 78776 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 10902 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.inst 978987 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 397787 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 1466452 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::writebacks 607596 # number of Writeback accesses(hits+misses) +system.cpu.l2cache.Writeback_accesses::total 607596 # number of Writeback accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2962 # number of UpgradeReq accesses(hits+misses) system.cpu.l2cache.UpgradeReq_accesses::total 2962 # number of UpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 16 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.SCUpgradeReq_accesses::total 16 # number of SCUpgradeReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 246154 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 246154 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78663 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.itb.walker 10601 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.inst 980578 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 644093 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 1713935 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78663 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.itb.walker 10601 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 980578 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 644093 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 1713935 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000521 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000189 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012612 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026931 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.015756 # miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986158 # miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986158 # miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.187500 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.187500 # miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541068 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 0.541068 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000521 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000189 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012612 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.223420 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.091201 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000521 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000189 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012612 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.223420 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.091201 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72743.902439 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 59000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52857.160184 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55057.431931 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 53912.548017 # average ReadReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 147.723382 # average UpgradeReq miss latency -system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 147.723382 # average UpgradeReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50119.393164 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50119.393164 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50680.602356 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72743.902439 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 59000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52857.160184 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50487.147565 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50680.602356 # average overall miss latency +system.cpu.l2cache.SCUpgradeReq_accesses::cpu.data 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.SCUpgradeReq_accesses::total 14 # number of SCUpgradeReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 246111 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 246111 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.dtb.walker 78776 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.itb.walker 10902 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 978987 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 643898 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 1712563 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.dtb.walker 78776 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.itb.walker 10902 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 978987 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 643898 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 1712563 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000647 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000275 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012627 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.026957 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.015779 # miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.986833 # miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_miss_rate::total 0.986833 # miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::cpu.data 0.285714 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_miss_rate::total 0.285714 # miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541235 # miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_miss_rate::total 0.541235 # miss rate for ReadExReq accesses +system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000647 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000275 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012627 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.223525 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.091292 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000647 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000275 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012627 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.223525 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.091292 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 72705.882353 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 62333.333333 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52827.333765 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54926.233237 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 53845.045119 # average ReadReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 163.701676 # average UpgradeReq miss latency +system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 163.701676 # average UpgradeReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50041.924402 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50041.924402 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 72705.882353 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52827.333765 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50405.820291 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50604.792009 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 72705.882353 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 62333.333333 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52827.333765 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50405.820291 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50604.792009 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -784,109 +784,109 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.writebacks::writebacks 59111 # number of writebacks -system.cpu.l2cache.writebacks::total 59111 # number of writebacks -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 12 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 12 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 61 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 12 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 61 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 73 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 41 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12355 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10656 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 23054 # number of ReadReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2921 # number of UpgradeReq MSHR misses -system.cpu.l2cache.UpgradeReq_mshr_misses::total 2921 # number of UpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 3 # number of SCUpgradeReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133186 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 133186 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 41 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 12355 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 143842 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 156240 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 41 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 12355 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 143842 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 156240 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 2461077 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 93002 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 497040130 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 451732824 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 951327033 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29212921 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29212921 # number of UpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 30003 # number of SCUpgradeReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5024401862 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5024401862 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 2461077 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 93002 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 497040130 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5476134686 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 5975728895 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 2461077 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 93002 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 497040130 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5476134686 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 5975728895 # number of overall MSHR miss cycles +system.cpu.l2cache.writebacks::writebacks 59120 # number of writebacks +system.cpu.l2cache.writebacks::total 59120 # number of writebacks +system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 13 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.inst 13 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::cpu.data 62 # number of demand (read+write) MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.inst 13 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::cpu.data 62 # number of overall MSHR hits +system.cpu.l2cache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 51 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 3 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12349 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 10661 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 23064 # number of ReadReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2923 # number of UpgradeReq MSHR misses +system.cpu.l2cache.UpgradeReq_mshr_misses::total 2923 # number of UpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::cpu.data 4 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.SCUpgradeReq_mshr_misses::total 4 # number of SCUpgradeReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133204 # number of ReadExReq MSHR misses +system.cpu.l2cache.ReadExReq_mshr_misses::total 133204 # number of ReadExReq MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 51 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 3 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 12349 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 143865 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 156268 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 51 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 3 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 12349 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 143865 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 156268 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 3058596 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 149004 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 496430614 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 450664827 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 950303041 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 29232923 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 29232923 # number of UpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::cpu.data 40004 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.SCUpgradeReq_mshr_miss_latency::total 40004 # number of SCUpgradeReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5014619823 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5014619823 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 3058596 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 149004 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 496430614 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5465284650 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 5964922864 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 3058596 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 149004 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 496430614 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5465284650 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 5964922864 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 4345155 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167008598530 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167012943685 # number of ReadReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18318853408 # number of WriteReq MSHR uncacheable cycles -system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18318853408 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 167009478530 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 167013823685 # number of ReadReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 18374986550 # number of WriteReq MSHR uncacheable cycles +system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 18374986550 # number of WriteReq MSHR uncacheable cycles system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 4345155 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185327451938 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185331797093 # number of overall MSHR uncacheable cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026778 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015707 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986158 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986158 # mshr miss rate for UpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.187500 # mshr miss rate for SCUpgradeReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541068 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541068 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.091159 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000521 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000189 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012600 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223325 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.091159 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 46501 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40229.876973 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42392.344595 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41265.161490 # average ReadReq mshr miss latency +system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 185384465080 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.overall_mshr_uncacheable_latency::total 185388810235 # number of overall MSHR uncacheable cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.026801 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.015728 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.986833 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.986833 # mshr miss rate for UpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::cpu.data 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.SCUpgradeReq_mshr_miss_rate::total 0.285714 # mshr miss rate for SCUpgradeReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541235 # mshr miss rate for ReadExReq accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.091248 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000647 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000275 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012614 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.223428 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.091248 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 49668 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40200.065916 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42272.284682 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 41202.872052 # average ReadReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average SCUpgradeReq mshr miss latency system.cpu.l2cache.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37724.699758 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37724.699758 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 60026.268293 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 46501 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40229.876973 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38070.484879 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38247.112743 # average overall mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37646.165453 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37646.165453 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 59972.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 49668 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40200.065916 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37988.980294 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38171.109018 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -896,161 +896,161 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 643581 # number of replacements -system.cpu.dcache.tagsinuse 511.994224 # Cycle average of tags in use -system.cpu.dcache.total_refs 21676734 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 644093 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 33.654665 # Average number of references to valid blocks. +system.cpu.dcache.replacements 643386 # number of replacements +system.cpu.dcache.tagsinuse 511.994223 # Cycle average of tags in use +system.cpu.dcache.total_refs 21524162 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 643898 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 33.427906 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 35006000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.994224 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.994223 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999989 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999989 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13816029 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13816029 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 7289413 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 7289413 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 282441 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 282441 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 285740 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 285740 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 21105442 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 21105442 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 21105442 # number of overall hits -system.cpu.dcache.overall_hits::total 21105442 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 731834 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 731834 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 2961255 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 2961255 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 13603 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 13603 # number of LoadLockedReq misses -system.cpu.dcache.StoreCondReq_misses::cpu.data 16 # number of StoreCondReq misses -system.cpu.dcache.StoreCondReq_misses::total 16 # number of StoreCondReq misses -system.cpu.dcache.demand_misses::cpu.data 3693089 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 3693089 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 3693089 # number of overall misses -system.cpu.dcache.overall_misses::total 3693089 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9564740000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9564740000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 104026861731 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 104026861731 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180604500 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 180604500 # number of LoadLockedReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 244000 # number of StoreCondReq miss cycles -system.cpu.dcache.StoreCondReq_miss_latency::total 244000 # number of StoreCondReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 113591601731 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 113591601731 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 113591601731 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 113591601731 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 14547863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 14547863 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10250668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10250668 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 296044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 296044 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 285756 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 285756 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 24798531 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 24798531 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 24798531 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 24798531 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050305 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.050305 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.288884 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.288884 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045949 # miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_miss_rate::total 0.000056 # miss rate for StoreCondReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.148924 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.148924 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.148924 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.148924 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13069.548559 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13069.548559 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35129.315689 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35129.315689 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13276.813938 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13276.813938 # average LoadLockedReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 15250 # average StoreCondReq miss latency -system.cpu.dcache.StoreCondReq_avg_miss_latency::total 15250 # average StoreCondReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30757.883639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30757.883639 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30757.883639 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 32046 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 14482 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 2589 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 251 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.377752 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 57.697211 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_hits::cpu.data 13769851 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13769851 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 7260574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 7260574 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 243031 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 243031 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247598 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247598 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 21030425 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 21030425 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 21030425 # number of overall hits +system.cpu.dcache.overall_hits::total 21030425 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 731035 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 731035 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 2961528 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 2961528 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 13553 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 13553 # number of LoadLockedReq misses +system.cpu.dcache.StoreCondReq_misses::cpu.data 14 # number of StoreCondReq misses +system.cpu.dcache.StoreCondReq_misses::total 14 # number of StoreCondReq misses +system.cpu.dcache.demand_misses::cpu.data 3692563 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 3692563 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 3692563 # number of overall misses +system.cpu.dcache.overall_misses::total 3692563 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9558145500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9558145500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 103975545233 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 103975545233 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 180615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 180615500 # number of LoadLockedReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::cpu.data 229500 # number of StoreCondReq miss cycles +system.cpu.dcache.StoreCondReq_miss_latency::total 229500 # number of StoreCondReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 113533690733 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 113533690733 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 113533690733 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 113533690733 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 14500886 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 14500886 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222102 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222102 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 256584 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 256584 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247612 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247612 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 24722988 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 24722988 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 24722988 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 24722988 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.050413 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.050413 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.289718 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.289718 # miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.052821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.052821 # miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::cpu.data 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_miss_rate::total 0.000057 # miss rate for StoreCondReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.149357 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.149357 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.149357 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.149357 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13074.812423 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13074.812423 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35108.749684 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 35108.749684 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13326.606655 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13326.606655 # average LoadLockedReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::cpu.data 16392.857143 # average StoreCondReq miss latency +system.cpu.dcache.StoreCondReq_avg_miss_latency::total 16392.857143 # average StoreCondReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 30746.581909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 30746.581909 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 30746.581909 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 31725 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 15165 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2547 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 253 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.455830 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets 59.940711 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 607832 # number of writebacks -system.cpu.dcache.writebacks::total 607832 # number of writebacks -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345983 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 345983 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712226 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 2712226 # number of WriteReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1428 # number of LoadLockedReq MSHR hits -system.cpu.dcache.LoadLockedReq_mshr_hits::total 1428 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 3058209 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 3058209 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 3058209 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 3058209 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385851 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 385851 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 249029 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 249029 # number of WriteReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.LoadLockedReq_mshr_misses::total 12175 # number of LoadLockedReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.StoreCondReq_mshr_misses::total 16 # number of StoreCondReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 634880 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 634880 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 634880 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 634880 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4768256000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4768256000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8126256417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8126256417 # number of WriteReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 140756500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 140756500 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 212000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 212000 # number of StoreCondReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12894512417 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12894512417 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12894512417 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12894512417 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182401837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182401837500 # number of ReadReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28201633550 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28201633550 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210603471050 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 210603471050 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026523 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026523 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024294 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.041126 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.041126 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000056 # mshr miss rate for StoreCondReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.025602 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025602 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.025602 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12357.765044 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12357.765044 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32631.767453 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32631.767453 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11561.108830 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11561.108830 # average LoadLockedReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 13250 # average StoreCondReq mshr miss latency -system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 13250 # average StoreCondReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20310.156907 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 20310.156907 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 607596 # number of writebacks +system.cpu.dcache.writebacks::total 607596 # number of writebacks +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 345371 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 345371 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2712545 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 2712545 # number of WriteReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 1340 # number of LoadLockedReq MSHR hits +system.cpu.dcache.LoadLockedReq_mshr_hits::total 1340 # number of LoadLockedReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 3057916 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 3057916 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 3057916 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 3057916 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 385664 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 385664 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 248983 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 248983 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 12213 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 12213 # number of LoadLockedReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::cpu.data 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.StoreCondReq_mshr_misses::total 14 # number of StoreCondReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 634647 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 634647 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 634647 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 634647 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4764852000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4764852000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8115946915 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8115946915 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 141227000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 141227000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::cpu.data 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.StoreCondReq_mshr_miss_latency::total 201500 # number of StoreCondReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12880798915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12880798915 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12880798915 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12880798915 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182402678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182402678500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 28257534484 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 28257534484 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 210660212984 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 210660212984 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.026596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.026596 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024357 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.047598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.047598 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::cpu.data 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.StoreCondReq_mshr_miss_rate::total 0.000057 # mshr miss rate for StoreCondReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.025670 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.025670 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.025670 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12354.930717 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12354.930717 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 32596.389774 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 32596.389774 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11563.661672 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11563.661672 # average LoadLockedReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::cpu.data 14392.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.StoreCondReq_avg_mshr_miss_latency::total 14392.857143 # average StoreCondReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 20296.005362 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 20296.005362 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -1072,16 +1072,16 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1148123553642 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148123553642 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1148123553642 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1148250225785 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1148250225785 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1148250225785 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.quiesce 88023 # number of quiesce instructions executed +system.cpu.kern.inst.quiesce 83041 # number of quiesce instructions executed ---------- End Simulation Statistics ---------- |