diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 14:14:36 +0100 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-06-02 14:14:36 +0100 |
commit | 1d933447fc62de67db938970a8308ac47189fd96 (patch) | |
tree | df7f389eeae7916c3a58082644d6929bf0e94280 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3 | |
parent | 660fbd543f7c84dec81cd17bdb4ff08f954aec77 (diff) | |
download | gem5-1d933447fc62de67db938970a8308ac47189fd96.tar.xz |
stats: Update to match ARM ISA changes
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3')
3 files changed, 33 insertions, 11 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini index dead082fc..cf234591c 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini @@ -24,7 +24,7 @@ exit_on_work_items=false flags_addr=469827632 gic_cpu_addr=738205696 have_large_asid_64=false -have_lpae=false +have_lpae=true have_security=false have_virtualization=false highest_el_is_64=false @@ -47,6 +47,8 @@ phys_addr_range_64=40 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= +thermal_components= +thermal_model=Null work_begin_ckpt_count=0 work_begin_cpu_id_exit=-1 work_begin_exit_count=0 @@ -199,8 +201,15 @@ choicePredictorSize=8192 eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 +indirectHashGHR=true +indirectHashTargets=true +indirectPathLength=3 +indirectSets=256 +indirectTagSize=16 +indirectWays=2 instShiftAmt=2 numThreads=1 +useIndirect=true [system.cpu.dcache] type=Cache @@ -1029,6 +1038,7 @@ pio=system.iobus.master[5] type=SubSystem children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys eventq_index=0 +thermal_domain=Null [system.realview.dcc.osc_cpu] type=RealViewOsc @@ -1221,6 +1231,7 @@ cpu_pio_delay=10000 dist_addr=738201600 dist_pio_delay=10000 eventq_index=0 +gem5_extensions=true int_latency=10000 it_lines=128 platform=system.realview @@ -1416,8 +1427,9 @@ pio=system.membus.master[4] [system.realview.mcc] type=SubSystem -children=osc_clcd osc_mcc osc_peripheral osc_system_bus +children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl eventq_index=0 +thermal_domain=Null [system.realview.mcc.osc_clcd] type=RealViewOsc @@ -1463,6 +1475,16 @@ position=0 site=0 voltage_domain=system.voltage_domain +[system.realview.mcc.temp_crtl] +type=RealViewTemperatureSensor +dcc=0 +device=0 +eventq_index=0 +parent=system.realview.realview_io +position=0 +site=0 +system=system + [system.realview.mmc_fake] type=AmbaFake amba_id=0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout index c85683f6b..76b741f0a 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout @@ -29,4 +29,4 @@ info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 -Exiting @ tick 2832922792000 because m5_exit instruction encountered +Exiting @ tick 2832862976500 because m5_exit instruction encountered diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt index a08043e3c..690dc124e 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt @@ -4,11 +4,11 @@ sim_seconds 2.832863 # Nu sim_ticks 2832862976500 # Number of ticks simulated final_tick 2832862976500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70501 # Simulator instruction rate (inst/s) -host_op_rate 85511 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1765850548 # Simulator tick rate (ticks/s) -host_mem_usage 578080 # Number of bytes of host memory used -host_seconds 1604.25 # Real time elapsed on the host +host_inst_rate 159961 # Simulator instruction rate (inst/s) +host_op_rate 194019 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4006592882 # Simulator tick rate (ticks/s) +host_mem_usage 625056 # Number of bytes of host memory used +host_seconds 707.05 # Real time elapsed on the host sim_insts 113100501 # Number of instructions simulated sim_ops 137180951 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -601,7 +601,7 @@ system.cpu.rename.IQFullEvents 65507 # Nu system.cpu.rename.LQFullEvents 18530 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 30752508 # Number of times rename has blocked due to SQ full system.cpu.rename.RenamedOperands 150221263 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 676972712 # Number of register rename lookups that rename has made +system.cpu.rename.RenameLookups 676943612 # Number of register rename lookups that rename has made system.cpu.rename.int_rename_lookups 163957736 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 10899 # Number of floating rename lookups system.cpu.rename.CommittedMaps 141737618 # Number of HB maps that are committed @@ -618,7 +618,7 @@ system.cpu.iq.iqNonSpecInstsAdded 2117732 # Nu system.cpu.iq.iqInstsIssued 143038678 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 260968 # Number of squashed instructions issued system.cpu.iq.iqSquashedInstsExamined 8155598 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14296072 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedOperandsExamined 14294324 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 121861 # Number of squashed non-spec instructions that were removed system.cpu.iq.issued_per_cycle::samples 270560621 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::mean 0.528675 # Number of insts issued each cycle @@ -840,7 +840,7 @@ system.cpu.fp_regfile_reads 9529 # nu system.cpu.fp_regfile_writes 2716 # number of floating regfile writes system.cpu.cc_regfile_reads 502156061 # number of cc regfile reads system.cpu.cc_regfile_writes 53129749 # number of cc regfile writes -system.cpu.misc_regfile_reads 347863701 # number of misc regfile reads +system.cpu.misc_regfile_reads 347855567 # number of misc regfile reads system.cpu.misc_regfile_writes 1521708 # number of misc regfile writes system.cpu.dcache.tags.replacements 838747 # number of replacements system.cpu.dcache.tags.tagsinuse 511.925928 # Cycle average of tags in use |