stats: Update to match ARM ISA changes

3 files changed, 78 insertions, 37 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index 4d37af833..9d9d131ca 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -24,7 +24,7 @@ exit_on_work_items=false
 flags_addr=469827632
 gic_cpu_addr=738205696
 have_large_asid_64=false
-have_lpae=false
+have_lpae=true
 have_security=false
 have_virtualization=false
 highest_el_is_64=false
@@ -47,6 +47,8 @@ phys_addr_range_64=40
 readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh
 reset_addr_64=0
 symbolfile=
+thermal_components=
+thermal_model=Null
 work_begin_ckpt_count=0
 work_begin_cpu_id_exit=-1
 work_begin_exit_count=0
@@ -552,11 +554,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu2.dstage2_mmu]
 type=ArmStage2MMU
@@ -1155,11 +1164,18 @@ choicePredictorSize=8192
 eventq_index=0
 globalCtrBits=2
 globalPredictorSize=8192
+indirectHashGHR=true
+indirectHashTargets=true
+indirectPathLength=3
+indirectSets=256
+indirectTagSize=16
+indirectWays=2
 instShiftAmt=2
 localCtrBits=2
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
+useIndirect=true
 
 [system.cpu3.dstage2_mmu]
 type=ArmStage2MMU
@@ -1690,14 +1706,14 @@ size=4194304
 
 [system.membus]
 type=CoherentXBar
-children=badaddr_responder
+children=badaddr_responder snoop_filter
 clk_domain=system.clk_domain
 eventq_index=0
 forward_latency=4
 frontend_latency=3
 point_of_coherency=true
 response_latency=2
-snoop_filter=Null
+snoop_filter=system.membus.snoop_filter
 snoop_response_latency=4
 system=system
 use_default_range=false
@@ -1724,6 +1740,13 @@ update_data=false
 warn_access=warn
 pio=system.membus.default
 
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=1
+max_capacity=8388608
+system=system
+
 [system.physmem]
 type=DRAMCtrl
 IDD0=0.075000
@@ -1928,6 +1951,7 @@ pio=system.iobus.master[5]
 type=SubSystem
 children=osc_cpu osc_ddr osc_hsbm osc_pxl osc_smb osc_sys
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.dcc.osc_cpu]
 type=RealViewOsc
@@ -2120,6 +2144,7 @@ cpu_pio_delay=10000
 dist_addr=738201600
 dist_pio_delay=10000
 eventq_index=0
+gem5_extensions=true
 int_latency=10000
 it_lines=128
 platform=system.realview
@@ -2315,8 +2340,9 @@ pio=system.membus.master[4]
 
 [system.realview.mcc]
 type=SubSystem
-children=osc_clcd osc_mcc osc_peripheral osc_system_bus
+children=osc_clcd osc_mcc osc_peripheral osc_system_bus temp_crtl
 eventq_index=0
+thermal_domain=Null
 
 [system.realview.mcc.osc_clcd]
 type=RealViewOsc
@@ -2362,6 +2388,16 @@ position=0
 site=0
 voltage_domain=system.voltage_domain
 
+[system.realview.mcc.temp_crtl]
+type=RealViewTemperatureSensor
+dcc=0
+device=0
+eventq_index=0
+parent=system.realview.realview_io
+position=0
+site=0
+system=system
+
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
index 9318c5011..e34805b0d 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr
@@ -12,8 +12,6 @@ warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
 warn: 	instruction 'mcr icialluis' unimplemented
-WARNING: One or more banks are active! REF requires all banks to be precharged.
-Command: 4, Timestamp: 12458, Bank: 0
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: Tried to read RealView I/O at offset 0x60 that doesn't exist
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -33,6 +31,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4]
 warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4]
@@ -40,21 +40,20 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0]
 warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10462, Bank: 2
+warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 8288, Bank: 0
-WARNING: Bank is already active!
-Command: 0, Timestamp: 6918, Bank: 3
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11135, Bank: 1
-WARNING: Bank is already active!
-Command: 0, Timestamp: 11139, Bank: 6
-warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[0]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: Bank is already active!
+Command: 0, Timestamp: 10621, Bank: 7
+WARNING: Bank is already active!
+Command: 0, Timestamp: 11318, Bank: 7
 warn: Returning zero for read from miscreg pmcr
 warn: Ignoring write to miscreg pmcntenclr
 warn: Ignoring write to miscreg pmintenclr
@@ -64,11 +63,12 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[10], opc1[0], crm[4], opc2[3]
 warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2]
-warn: CP14 unimplemented crn[7], opc1[0], crm[12], opc2[1]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
@@ -79,14 +79,17 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: 	instruction 'mcr bpiall' unimplemented
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: 	instruction 'mcr dcisw' unimplemented
+warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5]
+warn: CP14 unimplemented crn[6], opc1[5], crm[0], opc2[3]
+warn: CP14 unimplemented crn[6], opc1[5], crm[4], opc2[3]
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2]
+warn: 	instruction 'mcr bpiall' unimplemented
+warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0]
+warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7]
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
@@ -99,6 +102,8 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+WARNING: One or more banks are active! REF requires all banks to be precharged.
+Command: 4, Timestamp: 12458, Bank: 0
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
@@ -107,14 +112,14 @@ WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
-warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
 WARNING: One or more banks are active! REF requires all banks to be precharged.
 Command: 4, Timestamp: 12458, Bank: 0
 WARNING: One or more banks are active! REF requires all banks to be precharged.
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
index 42b6a0fb0..c8a56e9dc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.823729                       # Nu
 sim_ticks                                2823728611500                       # Number of ticks simulated
 final_tick                               2823728611500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 192143                       # Simulator instruction rate (inst/s)
-host_op_rate                                   233071                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4415299854                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 584992                       # Number of bytes of host memory used
-host_seconds                                   639.53                       # Real time elapsed on the host
+host_inst_rate                                 406612                       # Simulator instruction rate (inst/s)
+host_op_rate                                   493225                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             9343639540                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 632204                       # Number of bytes of host memory used
+host_seconds                                   302.21                       # Real time elapsed on the host
 sim_insts                                   122881667                       # Number of instructions simulated
 sim_ops                                     149056790                       # Number of ops (including micro ops) simulated
 system.voltage_domain.voltage                       1                       # Voltage in Volts
@@ -534,7 +534,7 @@ system.cpu0.num_func_calls                    5787158                       # nu
 system.cpu0.num_conditional_control_insts      7357632                       # number of instructions that are conditional controls
 system.cpu0.num_int_insts                    58995481                       # number of integer instructions
 system.cpu0.num_fp_insts                         4380                       # number of float instructions
-system.cpu0.num_int_register_reads          108779991                       # number of times the integer registers were read
+system.cpu0.num_int_register_reads          108769217                       # number of times the integer registers were read
 system.cpu0.num_int_register_writes          41129875                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                3339                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes               1042                       # number of times the floating registers were written
@@ -1292,7 +1292,7 @@ system.cpu1.num_func_calls                    1992181                       # nu
 system.cpu1.num_conditional_control_insts      2177842                       # number of instructions that are conditional controls
 system.cpu1.num_int_insts                    18584422                       # number of integer instructions
 system.cpu1.num_fp_insts                         1582                       # number of float instructions
-system.cpu1.num_int_register_reads           34435383                       # number of times the integer registers were read
+system.cpu1.num_int_register_reads           34431709                       # number of times the integer registers were read
 system.cpu1.num_int_register_writes          13029372                       # number of times the integer registers were written
 system.cpu1.num_fp_register_reads                1129                       # number of times the floating registers were read
 system.cpu1.num_fp_register_writes                454                       # number of times the floating registers were written
@@ -1852,7 +1852,7 @@ system.cpu3.rename.IQFullEvents               1185922                       # Nu
 system.cpu3.rename.LQFullEvents                108960                       # Number of times rename has blocked due to LQ full
 system.cpu3.rename.SQFullEvents               3941702                       # Number of times rename has blocked due to SQ full
 system.cpu3.rename.RenamedOperands           46859897                       # Number of destination operands rename has renamed
-system.cpu3.rename.RenameLookups            206328923                       # Number of register rename lookups that rename has made
+system.cpu3.rename.RenameLookups            206319121                       # Number of register rename lookups that rename has made
 system.cpu3.rename.int_rename_lookups        50493322                       # Number of integer rename lookups
 system.cpu3.rename.fp_rename_lookups             4028                       # Number of floating rename lookups
 system.cpu3.rename.CommittedMaps             39227152                       # Number of HB maps that are committed
@@ -1869,7 +1869,7 @@ system.cpu3.iq.iqNonSpecInstsAdded             518690                       # Nu
 system.cpu3.iq.iqInstsIssued                 41211343                       # Number of instructions issued
 system.cpu3.iq.iqSquashedInstsIssued            55539                       # Number of squashed instructions issued
 system.cpu3.iq.iqSquashedInstsExamined        6082671                       # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu3.iq.iqSquashedOperandsExamined     14073441                       # Number of squashed operands that are examined and possibly removed from graph
+system.cpu3.iq.iqSquashedOperandsExamined     14072351                       # Number of squashed operands that are examined and possibly removed from graph
 system.cpu3.iq.iqSquashedNonSpecRemoved         54569                       # Number of squashed non-spec instructions that were removed
 system.cpu3.iq.issued_per_cycle::samples     54325621                       # Number of insts issued each cycle
 system.cpu3.iq.issued_per_cycle::mean        0.758599                       # Number of insts issued each cycle
@@ -2091,7 +2091,7 @@ system.cpu3.fp_regfile_reads                    14550                       # nu
 system.cpu3.fp_regfile_writes                   12084                       # number of floating regfile writes
 system.cpu3.cc_regfile_reads                144202792                       # number of cc regfile reads
 system.cpu3.cc_regfile_writes                15932581                       # number of cc regfile writes
-system.cpu3.misc_regfile_reads               74870960                       # number of misc regfile reads
+system.cpu3.misc_regfile_reads               74868210                       # number of misc regfile reads
 system.cpu3.misc_regfile_writes                343753                       # number of misc regfile writes
 system.iobus.trans_dist::ReadReq                30152                       # Transaction distribution
 system.iobus.trans_dist::ReadResp               30152                       # Transaction distribution