diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-03-26 14:46:49 -0400 |
| commit | 08f7a8bc005507117ffda41f283adecf7e4d24f2 (patch) | |
| tree | d3588f01b572538601360998b89e23607549934c /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | 93a8423dea8f8194d83df85a5b3043f9beaf0a1e (diff) | |
| download | gem5-08f7a8bc005507117ffda41f283adecf7e4d24f2.tar.xz | |
stats: Update stats to reflect bus retry changes
This patch updates the stats after splitting the bus retry into
waiting for the bus and waiting for the peer.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 2406 |
1 files changed, 1203 insertions, 1203 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index d1147fb64..7a69bab79 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401153 # Number of seconds simulated -sim_ticks 2401153455000 # Number of ticks simulated -final_tick 2401153455000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.401336 # Number of seconds simulated +sim_ticks 2401336466000 # Number of ticks simulated +final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 200255 # Simulator instruction rate (inst/s) -host_op_rate 257182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7970039029 # Simulator tick rate (ticks/s) -host_mem_usage 397936 # Number of bytes of host memory used -host_seconds 301.27 # Real time elapsed on the host -sim_insts 60331276 # Number of instructions simulated -sim_ops 77481997 # Number of ops (including micro ops) simulated +host_inst_rate 184517 # Simulator instruction rate (inst/s) +host_op_rate 236966 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7343776984 # Simulator tick rate (ticks/s) +host_mem_usage 427572 # Number of bytes of host memory used +host_seconds 326.99 # Real time elapsed on the host +sim_insts 60334938 # Number of instructions simulated +sim_ops 77485485 # Number of ops (including micro ops) simulated system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -26,149 +26,149 @@ system.realview.nvmem.bw_total::total 8 # To system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 502176 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7085840 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 85312 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678208 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 177920 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1312828 # Number of bytes read from this memory -system.physmem.bytes_read::total 124662252 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 502176 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 85312 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 177920 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 765408 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746944 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490908 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325456 # Number of bytes written to this memory -system.physmem.bytes_written::total 6762760 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14049 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110750 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1333 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10597 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2780 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20527 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512434 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58546 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372727 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331364 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812500 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47818298 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 209139 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2951015 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35530 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282451 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 267 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 546749 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51917653 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 209139 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35530 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74098 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318767 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560477 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620913 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83065 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 552008 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2816463 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560477 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47818298 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 209139 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3571928 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35530 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 365516 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 267 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1098757 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54734116 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12597264 # Total number of read requests seen -system.physmem.writeReqs 398689 # Total number of write requests seen -system.physmem.cpureqs 55044 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 806224896 # Total number of bytes read from memory -system.physmem.bytesWritten 25516096 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102751100 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2642476 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12617991 # Total number of read requests seen +system.physmem.writeReqs 398645 # Total number of write requests seen +system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807551424 # Total number of bytes read from memory +system.physmem.bytesWritten 25513280 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 787593 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 787339 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 787599 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 787924 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 787752 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 787476 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 787626 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 787678 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 787361 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 786762 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 786761 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 787020 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 787004 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 786857 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 787043 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 787469 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24827 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24768 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24837 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24655 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 24743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25297 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25167 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24838 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24777 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24716 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24963 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24891 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 780903 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400118241500 # Total gap between requests +system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400301266000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12562016 # Categorize read packet sizes +system.physmem.readPktSize::3 12582912 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35233 # Categorize read packet sizes +system.physmem.readPktSize::6 35064 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381227 # Categorize write packet sizes +system.physmem.writePktSize::2 381229 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17462 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 814730 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 790825 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 796437 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2993221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2257059 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2257380 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2245823 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49187 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49109 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91199 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133310 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91200 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6958 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6947 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6939 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6938 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17416 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792038 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 797714 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2998166 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2260876 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2261203 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2249594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 49322 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 91361 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 133530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 91345 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6960 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6956 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6952 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see @@ -185,326 +185,326 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2982 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2977 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2995 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3016 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3014 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3011 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 3005 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2990 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3015 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3013 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17335 # What write queue length does an incoming req see system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17327 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17323 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17319 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17312 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17306 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17303 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17299 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17293 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17289 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14405 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17307 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17304 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17291 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17286 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14404 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14382 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14357 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14355 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14353 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14349 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14347 # What write queue length does an incoming req see -system.physmem.totQLat 276742406750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 352442416750 # Sum of mem lat for all requests -system.physmem.totBusLat 62986320000 # Total cycles spent in databus access -system.physmem.totBankLat 12713690000 # Total cycles spent in bank access -system.physmem.avgQLat 21968.45 # Average queueing delay per request -system.physmem.avgBankLat 1009.24 # Average bank access latency per request +system.physmem.wrQLenPdf::25 14384 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14356 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14354 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14352 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14350 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see +system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests +system.physmem.totBusLat 63089955000 # Total cycles spent in databus access +system.physmem.totBankLat 12731042500 # Total cycles spent in bank access +system.physmem.avgQLat 21968.79 # Average queueing delay per request +system.physmem.avgBankLat 1008.96 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27977.70 # Average memory access latency -system.physmem.avgRdBW 335.77 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.79 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 27977.75 # Average memory access latency +system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.71 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # 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Average occupied blocks per requestor +system.physmem.avgGap 184402.58 # Average gap between requests +system.l2c.replacements 63266 # number of replacements +system.l2c.tagsinuse 50361.629322 # Cycle average of tags in use +system.l2c.total_refs 1749187 # Total number of references to valid blocks. +system.l2c.sampled_refs 128660 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.595422 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374413040000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36831.903030 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5142.534834 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3774.448687 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 5145.178956 # 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mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 59716089 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 365170781 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 621263 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 144123701 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 864492415 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1434180500 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25160642000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26578724012 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51739366012 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647954364 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9829694360 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10477648724 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25808596364 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36408418372 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62217014736 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018073 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018363 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006033 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991984 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505285 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.334894 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.354442 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.113401 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023036 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023036 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45130.683597 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 47562.460485 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47550.582794 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10083.144814 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45296.247934 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 46994.995323 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47975.113272 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10077.717172 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.266667 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32440.935981 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40491.915620 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37733.022718 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.624157 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32386.759992 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40372.476772 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37640.243422 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44347.024006 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33842.995492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 75951 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 50015.898921 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41348.301568 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39876.474832 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -656,436 +656,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8076292 # DTB read hits -system.cpu0.dtb.read_misses 6232 # DTB read misses -system.cpu0.dtb.write_hits 6627548 # DTB write hits -system.cpu0.dtb.write_misses 2039 # DTB write misses +system.cpu0.dtb.read_hits 8079595 # DTB read hits +system.cpu0.dtb.read_misses 6254 # DTB read misses +system.cpu0.dtb.write_hits 6630051 # DTB write hits +system.cpu0.dtb.write_misses 2055 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5689 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5732 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 126 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 128 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8082524 # DTB read accesses -system.cpu0.dtb.write_accesses 6629587 # DTB write accesses +system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8085849 # DTB read accesses +system.cpu0.dtb.write_accesses 6632106 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14703840 # DTB hits -system.cpu0.dtb.misses 8271 # DTB misses -system.cpu0.dtb.accesses 14712111 # DTB accesses -system.cpu0.itb.inst_hits 32739442 # ITB inst hits -system.cpu0.itb.inst_misses 3479 # ITB inst misses +system.cpu0.dtb.hits 14709646 # DTB hits +system.cpu0.dtb.misses 8309 # DTB misses +system.cpu0.dtb.accesses 14717955 # DTB accesses +system.cpu0.itb.inst_hits 32707746 # ITB inst hits +system.cpu0.itb.inst_misses 3496 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 695 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32742921 # ITB inst accesses -system.cpu0.itb.hits 32739442 # DTB hits -system.cpu0.itb.misses 3479 # DTB misses -system.cpu0.itb.accesses 32742921 # DTB accesses -system.cpu0.numCycles 113988971 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32711242 # ITB inst accesses +system.cpu0.itb.hits 32707746 # DTB hits +system.cpu0.itb.misses 3496 # DTB misses +system.cpu0.itb.accesses 32711242 # DTB accesses +system.cpu0.numCycles 113988289 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32238592 # Number of instructions committed -system.cpu0.committedOps 42426848 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37569901 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses -system.cpu0.num_func_calls 1188707 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4243711 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37569901 # number of integer instructions -system.cpu0.num_fp_insts 5136 # number of float instructions -system.cpu0.num_int_register_reads 191405612 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39677066 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written -system.cpu0.num_mem_refs 15367259 # number of memory refs -system.cpu0.num_load_insts 8443691 # Number of load instructions -system.cpu0.num_store_insts 6923568 # Number of store instructions -system.cpu0.num_idle_cycles 13415307720.919615 # Number of idle cycles -system.cpu0.num_busy_cycles -13301318749.919615 # Number of busy cycles -system.cpu0.not_idle_fraction -116.689524 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.689524 # Percentage of idle cycles +system.cpu0.committedInsts 32205724 # Number of instructions committed +system.cpu0.committedOps 42407604 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37554027 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5120 # Number of float alu accesses +system.cpu0.num_func_calls 1187729 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4239348 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37554027 # number of integer instructions +system.cpu0.num_fp_insts 5120 # number of float instructions +system.cpu0.num_int_register_reads 191333530 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39644160 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3702 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1420 # number of times the floating registers were written +system.cpu0.num_mem_refs 15372618 # number of memory refs +system.cpu0.num_load_insts 8447076 # Number of load instructions +system.cpu0.num_store_insts 6925542 # Number of store instructions +system.cpu0.num_idle_cycles 13415449988.373053 # Number of idle cycles +system.cpu0.num_busy_cycles -13301461699.373053 # Number of busy cycles +system.cpu0.not_idle_fraction -116.691476 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.691476 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed -system.cpu0.icache.replacements 892272 # number of replacements -system.cpu0.icache.tagsinuse 511.604135 # Cycle average of tags in use -system.cpu0.icache.total_refs 44302234 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 892784 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.622567 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed +system.cpu0.icache.replacements 892496 # number of replacements +system.cpu0.icache.tagsinuse 511.604237 # Cycle average of tags in use +system.cpu0.icache.total_refs 44360992 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 893008 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.675918 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 477.646185 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.780881 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 16.177069 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.932903 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.034728 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.031596 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 478.427369 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.974038 # 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average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23929.632359 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.909091 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13484.903226 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6233.772735 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18408.282364 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17259.292333 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25566.004984 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18408.282364 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9007 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1035 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1102 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 47 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.173321 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 22.021277 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18289.988271 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18289.988271 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 9551 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1090 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.762385 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 37.434783 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597677 # number of writebacks -system.cpu0.dcache.writebacks::total 597677 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145837 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 145837 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 545226 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 545226 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 406 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 406 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 691063 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691063 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 691063 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691063 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65419 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 137122 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 202541 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29767 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52891 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82658 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1720 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3471 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5191 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 3 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 95186 # 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number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19076000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40648000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59724000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1452471000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3210213490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4662684490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1452471000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3210213490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4662684490 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27580693500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009829000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56590522500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281089000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14115638625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15396727625 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28861782500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43125467625 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71987250125 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033441 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028925 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014651 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021578 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019445 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008091 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047810 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045268 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020747 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000041 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011863 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028535 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025469 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011863 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11940.330791 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.656802 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12643.963444 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22553.381261 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27044.619879 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25427.224104 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.697674 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11710.746183 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11505.297631 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597590 # number of writebacks +system.cpu0.dcache.writebacks::total 597590 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145454 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 145454 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546284 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 546284 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 421 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 691738 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 691738 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 691738 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 691738 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65235 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 136322 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 201557 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29114 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52948 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1716 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3454 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5170 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94349 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 189270 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 283619 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94349 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 189270 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 283619 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779717500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1769361500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2549079000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 660454500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1423557990 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2084012490 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19032000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40419500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59451500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440172000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3192919490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4633091490 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440172000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3192919490 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4633091490 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27487398000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29017842000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56505240000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281263000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147361293 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15428624293 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28768661000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43165203293 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71933864293 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15259.292333 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16894.704520 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16348.880922 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,218 +1098,218 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2171794 # DTB read hits -system.cpu1.dtb.read_misses 2101 # DTB read misses -system.cpu1.dtb.write_hits 1466259 # DTB write hits -system.cpu1.dtb.write_misses 389 # DTB write misses +system.cpu1.dtb.read_hits 2185339 # DTB read hits +system.cpu1.dtb.read_misses 2099 # DTB read misses +system.cpu1.dtb.write_hits 1465312 # DTB write hits +system.cpu1.dtb.write_misses 382 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1716 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 80 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2173895 # DTB read accesses -system.cpu1.dtb.write_accesses 1466648 # DTB write accesses +system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2187438 # DTB read accesses +system.cpu1.dtb.write_accesses 1465694 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3638053 # DTB hits -system.cpu1.dtb.misses 2490 # DTB misses -system.cpu1.dtb.accesses 3640543 # DTB accesses -system.cpu1.itb.inst_hits 8419414 # ITB inst hits -system.cpu1.itb.inst_misses 1129 # ITB inst misses +system.cpu1.dtb.hits 3650651 # DTB hits +system.cpu1.dtb.misses 2481 # DTB misses +system.cpu1.dtb.accesses 3653132 # DTB accesses +system.cpu1.itb.inst_hits 8513719 # ITB inst hits +system.cpu1.itb.inst_misses 1131 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8420543 # ITB inst accesses -system.cpu1.itb.hits 8419414 # DTB hits -system.cpu1.itb.misses 1129 # DTB misses -system.cpu1.itb.accesses 8420543 # DTB accesses -system.cpu1.numCycles 574251142 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses +system.cpu1.itb.hits 8513719 # DTB hits +system.cpu1.itb.misses 1131 # DTB misses +system.cpu1.itb.accesses 8514850 # DTB accesses +system.cpu1.numCycles 574637078 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8213191 # Number of instructions committed -system.cpu1.committedOps 10466435 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9372254 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses -system.cpu1.num_func_calls 317964 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1146067 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9372254 # number of integer instructions -system.cpu1.num_fp_insts 2062 # number of float instructions -system.cpu1.num_int_register_reads 54024867 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10146423 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written -system.cpu1.num_mem_refs 3811897 # number of memory refs -system.cpu1.num_load_insts 2267853 # Number of load instructions -system.cpu1.num_store_insts 1544044 # Number of store instructions -system.cpu1.num_idle_cycles 537580210.089888 # Number of idle cycles -system.cpu1.num_busy_cycles 36670931.910112 # Number of busy cycles -system.cpu1.not_idle_fraction 0.063859 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.936141 # Percentage of idle cycles +system.cpu1.committedInsts 8294211 # Number of instructions committed +system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses +system.cpu1.num_func_calls 319530 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9421872 # number of integer instructions +system.cpu1.num_fp_insts 2078 # number of float instructions +system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written +system.cpu1.num_mem_refs 3824850 # number of memory refs +system.cpu1.num_load_insts 2281405 # Number of load instructions +system.cpu1.num_store_insts 1543445 # Number of store instructions +system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles +system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles +system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4709991 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3829375 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 221875 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3139297 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527298 # Number of BTB hits +system.cpu2.branchPred.lookups 4687055 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.505221 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 410694 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21534 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10865348 # DTB read hits -system.cpu2.dtb.read_misses 22611 # DTB read misses -system.cpu2.dtb.write_hits 3267482 # DTB write hits -system.cpu2.dtb.write_misses 5780 # DTB write misses +system.cpu2.dtb.read_hits 10844149 # DTB read hits +system.cpu2.dtb.read_misses 22603 # DTB read misses +system.cpu2.dtb.write_hits 3263914 # DTB write hits +system.cpu2.dtb.write_misses 5857 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 877 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 154 # Number of TLB faults due to prefetch +system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 449 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10887959 # DTB read accesses -system.cpu2.dtb.write_accesses 3273262 # DTB write accesses +system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10866752 # DTB read accesses +system.cpu2.dtb.write_accesses 3269771 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14132830 # DTB hits -system.cpu2.dtb.misses 28391 # DTB misses -system.cpu2.dtb.accesses 14161221 # DTB accesses -system.cpu2.itb.inst_hits 4058794 # ITB inst hits -system.cpu2.itb.inst_misses 4496 # ITB inst misses +system.cpu2.dtb.hits 14108063 # DTB hits +system.cpu2.dtb.misses 28460 # DTB misses +system.cpu2.dtb.accesses 14136523 # DTB accesses +system.cpu2.itb.inst_hits 4055013 # ITB inst hits +system.cpu2.itb.inst_misses 4560 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 504 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1567 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1061 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4063290 # ITB inst accesses -system.cpu2.itb.hits 4058794 # DTB hits -system.cpu2.itb.misses 4496 # DTB misses -system.cpu2.itb.accesses 4063290 # DTB accesses -system.cpu2.numCycles 88265633 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses +system.cpu2.itb.hits 4055013 # DTB hits +system.cpu2.itb.misses 4560 # DTB misses +system.cpu2.itb.accesses 4059573 # DTB accesses +system.cpu2.numCycles 88254759 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9438008 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32342862 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4709991 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2937992 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6815885 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1813158 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 52200 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19319240 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 204 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 990 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33528 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57014 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 272 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4057414 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309972 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1938 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36961797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.050032 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.436638 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30150982 81.57% 81.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 382433 1.03% 82.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 508858 1.38% 83.98% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812110 2.20% 86.18% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 648973 1.76% 87.94% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 344473 0.93% 88.87% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1008779 2.73% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 237853 0.64% 92.24% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2867336 7.76% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36961797 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053362 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.366426 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10050266 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19257143 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6169060 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 292369 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1191852 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 610072 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53860 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36648451 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 182697 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1191852 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10623039 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6559507 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11162234 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5869128 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1554979 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34406679 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2425 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 416595 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 876326 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 106 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36902595 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 157291448 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 157264010 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27438 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25708511 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11194083 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 230845 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207258 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3329183 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6509687 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3839458 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 526321 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 767723 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31666176 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 511259 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34215654 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53951 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7402351 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19875920 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 155450 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36961797 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.925703 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.580463 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24411546 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3907285 10.57% 76.62% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2341872 6.34% 82.95% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974558 5.34% 88.29% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782177 7.53% 95.82% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 896473 2.43% 98.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 480042 1.30% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 133126 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34718 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36961797 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16658 1.09% 1.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available @@ -1338,148 +1338,148 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407260 91.71% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110601 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61295 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19329502 56.49% 56.67% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25951 0.08% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 9 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 8 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 376 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 8 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.75% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11364260 33.21% 89.96% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3434245 10.04% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34215654 # Type of FU issued -system.cpu2.iq.rate 0.387644 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534519 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044848 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 107003021 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39584963 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27346219 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6827 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3771 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3100 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35685269 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3609 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 207108 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued +system.cpu2.iq.rate 0.386887 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1576105 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1884 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9268 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 580803 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5370889 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352686 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1191852 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4868557 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 91379 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32255245 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 59750 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6509687 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3839458 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 369212 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 31393 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2360 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9268 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105822 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 88057 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 193879 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33230591 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11076582 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 985063 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 77810 # number of nop insts executed -system.cpu2.iew.exec_refs 14478078 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3688656 # Number of branches executed -system.cpu2.iew.exec_stores 3401496 # Number of stores executed -system.cpu2.iew.exec_rate 0.376484 # Inst execution rate -system.cpu2.iew.wb_sent 32812407 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27349319 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15625261 # num instructions producing a value -system.cpu2.iew.wb_consumers 28412503 # num instructions consuming a value +system.cpu2.iew.exec_nop 72670 # number of nop insts executed +system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3670278 # Number of branches executed +system.cpu2.iew.exec_stores 3398105 # Number of stores executed +system.cpu2.iew.exec_rate 0.375646 # Inst execution rate +system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15591378 # num instructions producing a value +system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309852 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549943 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7344146 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 355809 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 168786 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35769820 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.688862 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.716544 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147085 75.89% 75.89% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4176329 11.68% 87.57% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1256730 3.51% 91.08% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 649005 1.81% 92.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 570906 1.60% 94.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 316592 0.89% 95.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 399111 1.12% 96.49% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 290067 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 963995 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35769820 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19931262 # Number of instructions committed -system.cpu2.commit.committedOps 24640483 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 19883492 # Number of instructions committed +system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8192237 # Number of memory references committed -system.cpu2.commit.loads 4933582 # Number of loads committed -system.cpu2.commit.membars 94126 # Number of memory barriers committed -system.cpu2.commit.branches 3155533 # Number of branches committed +system.cpu2.commit.refs 8174125 # Number of memory references committed +system.cpu2.commit.loads 4916766 # Number of loads committed +system.cpu2.commit.membars 94500 # Number of memory barriers committed +system.cpu2.commit.branches 3146107 # Number of branches committed system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21875712 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294009 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 963995 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions. +system.cpu2.commit.function_calls 293773 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66266303 # The number of ROB reads -system.cpu2.rob.rob_writes 65202475 # The number of ROB writes -system.cpu2.timesIdled 360564 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51303836 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567277023 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19879493 # Number of Instructions Simulated -system.cpu2.committedOps 24588714 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19879493 # Number of Instructions Simulated -system.cpu2.cpi 4.440034 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.440034 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.225223 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.225223 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153509449 # number of integer regfile reads -system.cpu2.int_regfile_writes 29174173 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22340 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20840 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9001304 # number of misc regfile reads -system.cpu2.misc_regfile_writes 240409 # number of misc regfile writes +system.cpu2.rob.rob_reads 66150526 # The number of ROB reads +system.cpu2.rob.rob_writes 64978873 # The number of ROB writes +system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19835003 # Number of Instructions Simulated +system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated +system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads +system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes +system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads +system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1494,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 979501914046 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 979501914046 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 979501914046 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 979501914046 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |