diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2015-09-15 08:14:09 -0500 |
| commit | 0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e (patch) | |
| tree | 45d559d0511bdca749a08a2f42eeafdcf25739cf /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | 3de9def6c1ad38d6a5068b07512cbefffafcb758 (diff) | |
| download | gem5-0d6a6dfd7b500aff7e91a22c9bb7211e1807b90e.tar.xz | |
stats: updates due to recent changesets including d0934b57735a
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
4 files changed, 2203 insertions, 2225 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index fa71746e2..5e44bb6ce 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,11 +12,11 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain dvfs_handler intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=134217728 -boot_loader=/work/gem5/dist/binaries/boot_emm.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot_emm.arm boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=256MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=/work/gem5/dist/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb +dtb_filename=/scratch/nilay/GEM5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb early_kernel_symbols=false enable_context_switch_stats_dump=false eventq_index=0 @@ -28,7 +28,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/work/gem5/dist/binaries/vmlinux.aarch32.ll_20131205.0-gem5 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 kernel_addr_check=true load_addr_mask=268435455 load_offset=2147483648 @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=/work/gem5/outgoing/gem5/tests/halt.sh +readfile=/scratch/nilay/GEM5/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/work/gem5/dist/disks/linux-aarch32-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-aarch32-ael.img read_only=true [system.clk_domain] @@ -136,7 +136,7 @@ dcache_port=system.cpu0.dcache.cpu_side icache_port=system.cpu0.icache.cpu_side [system.cpu0.dcache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=4 @@ -212,7 +212,7 @@ sys=system port=system.toL2Bus.slave[3] [system.cpu0.icache] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=1 @@ -1610,7 +1610,7 @@ master=system.realview.uart.pio system.realview.realview_io.pio system.realview. slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma system.realview.ide.dma system.realview.ethernet.dma [system.iocache] -type=BaseCache +type=Cache children=tags addr_ranges=2147483648:2415919103 assoc=8 @@ -1645,7 +1645,7 @@ sequential_access=false size=1024 [system.l2c] -type=BaseCache +type=Cache children=tags addr_ranges=0:18446744073709551615 assoc=8 @@ -2060,9 +2060,12 @@ gic=system.realview.gic int_num=117 pio_addr=721420288 pio_latency=10000 -pixel_clock=7299 +pixel_buffer_size=2048 +pixel_chunk=32 +pxl_clk=system.realview.realview_io.osc_pxl system=system vnc=system.vncserver +workaround_dma_line_count=true workaround_swap_rb=true dma=system.membus.slave[0] pio=system.iobus.master[5] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 392d7b9c9..9e05ec404 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -40,21 +40,19 @@ warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 9104, Bank: 0 +WARNING: Bank is already active! +Command: 0, Timestamp: 11912, Bank: 1 warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] +WARNING: Bank is already active! +Command: 0, Timestamp: 9339, Bank: 5 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -WARNING: Bank is not active! -Command: 1, Timestamp: 3178, Bank: 4 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 WARNING: Bank is already active! -Command: 0, Timestamp: 7386, Bank: 2 -WARNING: One or more banks are active! REF requires all banks to be precharged. -Command: 4, Timestamp: 12458, Bank: 0 +Command: 0, Timestamp: 8168, Bank: 2 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 warn: Returning zero for read from miscreg pmcr @@ -66,28 +64,27 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: CP14 unimplemented crn[0], opc1[4], crm[0], opc2[2] WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: CP14 unimplemented crn[2], opc1[2], crm[0], opc2[2] -warn: instruction 'mcr bpiall' unimplemented WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +warn: instruction 'mcr bpiall' unimplemented WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. @@ -106,6 +103,10 @@ WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 WARNING: One or more banks are active! REF requires all banks to be precharged. Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 +WARNING: One or more banks are active! REF requires all banks to be precharged. +Command: 4, Timestamp: 12458, Bank: 0 warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 5454319fd..8581849c1 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,9 +1,11 @@ +Redirecting stdout to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simout +Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Aug 7 2015 10:13:08 -gem5 started Aug 7 2015 10:47:25 -gem5 executing on e104799-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /work/gem5/outgoing/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Sep 14 2015 23:29:19 +gem5 started Sep 15 2015 01:34:12 +gem5 executing on ribera.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /scratch/nilay/GEM5/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 19db0f3e8..b0310bea3 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,164 +1,160 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.823474 # Number of seconds simulated -sim_ticks 2823473696000 # Number of ticks simulated -final_tick 2823473696000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.823417 # Number of seconds simulated +sim_ticks 2823417216000 # Number of ticks simulated +final_tick 2823417216000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 253388 # Simulator instruction rate (inst/s) -host_op_rate 307362 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 5820051646 # Simulator tick rate (ticks/s) -host_mem_usage 579664 # Number of bytes of host memory used -host_seconds 485.13 # Real time elapsed on the host -sim_insts 122925898 # Number of instructions simulated -sim_ops 149109939 # Number of ops (including micro ops) simulated +host_inst_rate 190092 # Simulator instruction rate (inst/s) +host_op_rate 230584 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4366555088 # Simulator tick rate (ticks/s) +host_mem_usage 623124 # Number of bytes of host memory used +host_seconds 646.60 # Real time elapsed on the host +sim_insts 122913537 # Number of instructions simulated +sim_ops 149095594 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu0.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 537380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 3052900 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 121024 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 891264 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 1984 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 373952 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 2012736 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.dtb.walker 4224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 356480 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 3623360 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 532260 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 3026788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 122112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 894784 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 379328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 2028160 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.dtb.walker 4800 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.inst 356352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3.data 3635968 # Number of bytes read from this memory system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory -system.physmem.bytes_read::total 10976712 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 537380 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 121024 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 373952 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 356480 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 1388836 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 8247936 # Number of bytes written to this memory +system.physmem.bytes_read::total 10983560 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 532260 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 122112 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 379328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu3.inst 356352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 1390052 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 8264064 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17524 # Number of bytes written to this memory -system.physmem.bytes_written::total 8265460 # Number of bytes written to this memory +system.physmem.bytes_written::total 8281588 # Number of bytes written to this memory system.physmem.num_reads::cpu0.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 16850 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 48221 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1891 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 13926 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 31 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 5843 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 31449 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.dtb.walker 66 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 5570 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 56615 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 16770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 47813 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1908 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 13981 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 26 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 5927 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 31690 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.dtb.walker 75 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.inst 5568 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3.data 56812 # Number of read requests responded to by this memory system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory -system.physmem.num_reads::total 180484 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 128874 # Number of write requests responded to by this memory +system.physmem.num_reads::total 180591 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 129126 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4381 # Number of write requests responded to by this memory -system.physmem.num_writes::total 133255 # Number of write requests responded to by this memory +system.physmem.num_writes::total 133507 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.dtb.walker 113 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 190326 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1081257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 42864 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 315662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 703 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 23 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 132444 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 712858 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.dtb.walker 1496 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 126256 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 1283299 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 188516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1072030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 43250 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 316915 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 134351 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 718335 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.dtb.walker 1700 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 126213 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 1287790 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::realview.ide 340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3887662 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 190326 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 42864 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 132444 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 126256 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 491889 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 2921202 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3890165 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 188516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 43250 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 134351 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 126213 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 492330 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 2926972 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 6207 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2927408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 2921202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2933179 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 2926972 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 113 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 190326 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 1087463 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 42864 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 315662 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 703 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 23 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 132444 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 712858 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.dtb.walker 1496 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 126256 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 1283299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 188516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 1078237 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 43250 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 316915 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 589 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 134351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 718335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.dtb.walker 1700 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 126213 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 1287790 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::realview.ide 340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 6815070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 115392 # Number of read requests accepted -system.physmem.writeReqs 70006 # Number of write requests accepted -system.physmem.readBursts 115392 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 70006 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 7377600 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 7488 # Total number of bytes read from write queue -system.physmem.bytesWritten 4479552 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 7385088 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 4480384 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 117 # Number of DRAM read bursts serviced by the write queue +system.physmem.bw_total::total 6823344 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 115987 # Number of read requests accepted +system.physmem.writeReqs 70622 # Number of write requests accepted +system.physmem.readBursts 115987 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 70622 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 7416384 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 6784 # Total number of bytes read from write queue +system.physmem.bytesWritten 4519488 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 7423168 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 4519808 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 106 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 16729 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 7736 # Per bank write bursts -system.physmem.perBankRdBursts::1 7063 # Per bank write bursts -system.physmem.perBankRdBursts::2 7688 # Per bank write bursts -system.physmem.perBankRdBursts::3 7632 # Per bank write bursts -system.physmem.perBankRdBursts::4 7697 # Per bank write bursts -system.physmem.perBankRdBursts::5 7461 # Per bank write bursts -system.physmem.perBankRdBursts::6 7652 # Per bank write bursts -system.physmem.perBankRdBursts::7 7853 # Per bank write bursts -system.physmem.perBankRdBursts::8 7016 # Per bank write bursts -system.physmem.perBankRdBursts::9 7651 # Per bank write bursts -system.physmem.perBankRdBursts::10 6943 # Per bank write bursts -system.physmem.perBankRdBursts::11 6411 # Per bank write bursts -system.physmem.perBankRdBursts::12 6488 # Per bank write bursts -system.physmem.perBankRdBursts::13 7344 # Per bank write bursts -system.physmem.perBankRdBursts::14 6713 # Per bank write bursts -system.physmem.perBankRdBursts::15 5927 # Per bank write bursts -system.physmem.perBankWrBursts::0 4604 # Per bank write bursts -system.physmem.perBankWrBursts::1 4172 # Per bank write bursts -system.physmem.perBankWrBursts::2 4724 # Per bank write bursts -system.physmem.perBankWrBursts::3 4597 # Per bank write bursts -system.physmem.perBankWrBursts::4 4526 # Per bank write bursts -system.physmem.perBankWrBursts::5 4564 # Per bank write bursts -system.physmem.perBankWrBursts::6 4573 # Per bank write bursts -system.physmem.perBankWrBursts::7 4592 # Per bank write bursts -system.physmem.perBankWrBursts::8 4263 # Per bank write bursts -system.physmem.perBankWrBursts::9 4993 # Per bank write bursts -system.physmem.perBankWrBursts::10 4344 # Per bank write bursts -system.physmem.perBankWrBursts::11 3939 # Per bank write bursts -system.physmem.perBankWrBursts::12 3901 # Per bank write bursts -system.physmem.perBankWrBursts::13 4724 # Per bank write bursts -system.physmem.perBankWrBursts::14 4019 # Per bank write bursts -system.physmem.perBankWrBursts::15 3458 # Per bank write bursts +system.physmem.neitherReadNorWriteReqs 16716 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 7738 # Per bank write bursts +system.physmem.perBankRdBursts::1 7157 # Per bank write bursts +system.physmem.perBankRdBursts::2 7568 # Per bank write bursts +system.physmem.perBankRdBursts::3 7635 # Per bank write bursts +system.physmem.perBankRdBursts::4 7727 # Per bank write bursts +system.physmem.perBankRdBursts::5 7298 # Per bank write bursts +system.physmem.perBankRdBursts::6 7875 # Per bank write bursts +system.physmem.perBankRdBursts::7 7810 # Per bank write bursts +system.physmem.perBankRdBursts::8 7237 # Per bank write bursts +system.physmem.perBankRdBursts::9 7597 # Per bank write bursts +system.physmem.perBankRdBursts::10 7159 # Per bank write bursts +system.physmem.perBankRdBursts::11 6221 # Per bank write bursts +system.physmem.perBankRdBursts::12 6467 # Per bank write bursts +system.physmem.perBankRdBursts::13 7007 # Per bank write bursts +system.physmem.perBankRdBursts::14 6960 # Per bank write bursts +system.physmem.perBankRdBursts::15 6425 # Per bank write bursts +system.physmem.perBankWrBursts::0 4628 # Per bank write bursts +system.physmem.perBankWrBursts::1 4274 # Per bank write bursts +system.physmem.perBankWrBursts::2 4625 # Per bank write bursts +system.physmem.perBankWrBursts::3 4563 # Per bank write bursts +system.physmem.perBankWrBursts::4 4564 # Per bank write bursts +system.physmem.perBankWrBursts::5 4431 # Per bank write bursts +system.physmem.perBankWrBursts::6 4784 # Per bank write bursts +system.physmem.perBankWrBursts::7 4577 # Per bank write bursts +system.physmem.perBankWrBursts::8 4485 # Per bank write bursts +system.physmem.perBankWrBursts::9 4954 # Per bank write bursts +system.physmem.perBankWrBursts::10 4488 # Per bank write bursts +system.physmem.perBankWrBursts::11 3709 # Per bank write bursts +system.physmem.perBankWrBursts::12 3882 # Per bank write bursts +system.physmem.perBankWrBursts::13 4478 # Per bank write bursts +system.physmem.perBankWrBursts::14 4241 # Per bank write bursts +system.physmem.perBankWrBursts::15 3934 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry -system.physmem.numWrRetry 2 # Number of times write queue was full causing retry -system.physmem.totGap 2821902889500 # Total gap between requests +system.physmem.numWrRetry 3 # Number of times write queue was full causing retry +system.physmem.totGap 2821846409500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 115392 # Read request sizes (log2) +system.physmem.readPktSize::6 115987 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 70006 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 87082 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 25035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 2573 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 583 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 70622 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 87604 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 25234 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 2505 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 534 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -186,173 +182,173 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 70 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 71 # What write queue length does an incoming req see system.physmem.wrQLenPdf::1 66 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 65 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::3 64 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 63 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 62 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 61 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 61 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 62 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 63 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 60 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 59 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 59 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 59 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1142 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1373 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 3178 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 3727 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 3775 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 3833 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 3936 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 4298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 4359 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 4769 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 4543 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 4412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 4145 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 4333 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 4426 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 3858 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 3891 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 3738 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 101 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 82 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 86 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::36 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::37 60 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::38 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::39 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::40 75 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::41 49 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::42 50 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::43 38 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::44 40 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::45 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::46 58 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::47 71 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::48 55 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::49 47 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::50 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::51 64 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::52 46 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::53 27 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::54 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::55 24 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::56 17 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::57 19 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::58 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::59 6 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::60 13 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::61 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::62 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::63 4 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 39680 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 298.819355 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 174.296873 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 326.728623 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 15567 39.23% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 9452 23.82% 63.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 3895 9.82% 72.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 2106 5.31% 78.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 1684 4.24% 82.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 926 2.33% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 731 1.84% 86.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 606 1.53% 88.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 4713 11.88% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 39680 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 3702 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 31.134792 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 625.115005 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-2047 3701 99.97% 99.97% # Reads before turning the bus around for writes +system.physmem.wrQLenPdf::15 1185 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1388 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 3260 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 3803 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 3852 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 3935 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 3916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 4293 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 4379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4868 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 4555 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 4480 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 4133 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 4375 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 4462 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 3904 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 3897 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 3769 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 90 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 73 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 42 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 48 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 52 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 54 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 38 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 29 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 41 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 37 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 36 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 35 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 50 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 39 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 25 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 32 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 14 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 9 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 9 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 40043 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 298.076368 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 174.108717 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 325.784807 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 15715 39.25% 39.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 9618 24.02% 63.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 3841 9.59% 72.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 2194 5.48% 78.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 1638 4.09% 82.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 995 2.48% 84.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 706 1.76% 86.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 639 1.60% 88.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 4697 11.73% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 40043 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 3750 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 30.898667 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 620.943727 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-2047 3749 99.97% 99.97% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::36864-38911 1 0.03% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 3702 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 3702 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.906807 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 17.729572 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 10.893119 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::0-3 6 0.16% 0.16% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4-7 2 0.05% 0.22% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::8-11 2 0.05% 0.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12-15 7 0.19% 0.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16-19 3319 89.65% 90.11% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20-23 56 1.51% 91.63% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24-27 61 1.65% 93.27% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28-31 52 1.40% 94.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::32-35 33 0.89% 95.57% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::36-39 54 1.46% 97.03% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::40-43 14 0.38% 97.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::44-47 4 0.11% 97.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::48-51 10 0.27% 97.78% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::52-55 2 0.05% 97.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::56-59 1 0.03% 97.87% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::60-63 1 0.03% 97.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::64-67 54 1.46% 99.35% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::68-71 3 0.08% 99.43% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::72-75 3 0.08% 99.51% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::84-87 1 0.03% 99.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::88-91 2 0.05% 99.59% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::92-95 1 0.03% 99.62% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::100-103 1 0.03% 99.65% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::124-127 1 0.03% 99.68% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::128-131 5 0.14% 99.81% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::132-135 1 0.03% 99.84% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::140-143 1 0.03% 99.86% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::152-155 1 0.03% 99.89% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::164-167 4 0.11% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 3702 # Writes before turning the bus around for reads -system.physmem.totQLat 1386684000 # Total ticks spent queuing -system.physmem.totMemAccLat 3548090250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 576375000 # Total ticks spent in databus transfers -system.physmem.avgQLat 12029.36 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 3750 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 3750 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.831200 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 17.732451 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 9.879160 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::0-3 7 0.19% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4-7 3 0.08% 0.27% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::8-11 2 0.05% 0.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12-15 3 0.08% 0.40% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16-19 3363 89.68% 90.08% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20-23 40 1.07% 91.15% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24-27 85 2.27% 93.41% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28-31 44 1.17% 94.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32-35 28 0.75% 95.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::36-39 63 1.68% 97.01% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40-43 19 0.51% 97.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44-47 1 0.03% 97.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48-51 9 0.24% 97.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::52-55 1 0.03% 97.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::56-59 5 0.13% 97.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::60-63 2 0.05% 98.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::64-67 56 1.49% 99.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::68-71 2 0.05% 99.55% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::72-75 3 0.08% 99.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::76-79 1 0.03% 99.65% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::80-83 1 0.03% 99.68% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::92-95 1 0.03% 99.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::100-103 1 0.03% 99.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::112-115 1 0.03% 99.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::120-123 1 0.03% 99.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::124-127 1 0.03% 99.81% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::128-131 5 0.13% 99.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 3750 # Writes before turning the bus around for reads +system.physmem.totQLat 1369225250 # Total ticks spent queuing +system.physmem.totMemAccLat 3541994000 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 579405000 # Total ticks spent in databus transfers +system.physmem.avgQLat 11815.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30779.36 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 2.61 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.59 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 2.62 # Average system read bandwidth in MiByte/s -system.physmem.avgWrBWSys 1.59 # Average system write bandwidth in MiByte/s +system.physmem.avgMemAccLat 30565.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 2.63 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.60 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 2.63 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.60 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 0.03 # Data bus utilization in percentage system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing -system.physmem.avgWrQLen 19.44 # Average write queue length when enqueuing -system.physmem.readRowHits 95329 # Number of row buffer hits during reads -system.physmem.writeRowHits 50259 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.70 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 71.79 # Row buffer hit rate for writes -system.physmem.avgGap 15220783.88 # Average gap between requests -system.physmem.pageHitRate 78.58 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 160733160 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 87536625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 474099600 # Energy for read commands per rank (pJ) -system.physmem_0.writeEnergy 235560960 # Energy for write commands per rank (pJ) -system.physmem_0.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 72207385965 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 1621122462750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 1873980335220 # Total energy per rank (pJ) -system.physmem_0.averagePower 667.505718 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 2640566607500 # Time in different power states -system.physmem_0.memoryStateTime::REF 91867360000 # Time in different power states +system.physmem.avgWrQLen 16.05 # Average write queue length when enqueuing +system.physmem.readRowHits 95975 # Number of row buffer hits during reads +system.physmem.writeRowHits 50480 # Number of row buffer hits during writes +system.physmem.readRowHitRate 82.82 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 71.48 # Row buffer hit rate for writes +system.physmem.avgGap 15121705.86 # Average gap between requests +system.physmem.pageHitRate 78.53 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 160793640 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 87577875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 474302400 # Energy for read commands per rank (pJ) +system.physmem_0.writeEnergy 236170080 # Energy for write commands per rank (pJ) +system.physmem_0.refreshEnergy 179688996240 # Energy for refresh commands per rank (pJ) +system.physmem_0.actBackEnergy 72061472520 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 1621212124500 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 1873921437255 # Total energy per rank (pJ) +system.physmem_0.averagePower 667.499929 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 2640719336250 # Time in different power states +system.physmem_0.memoryStateTime::REF 91865540000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 18778047250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 18574630750 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 139247640 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 75805125 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 425045400 # Energy for read commands per rank (pJ) -system.physmem_1.writeEnergy 217993680 # Energy for write commands per rank (pJ) -system.physmem_1.refreshEnergy 179692556160 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 71111774430 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 1616695526250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 1868357948685 # Total energy per rank (pJ) -system.physmem_1.averagePower 667.638582 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2642185763250 # Time in different power states -system.physmem_1.memoryStateTime::REF 91867360000 # Time in different power states +system.physmem_1.actEnergy 141931440 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 77281875 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 429569400 # Energy for read commands per rank (pJ) +system.physmem_1.writeEnergy 221428080 # Energy for write commands per rank (pJ) +system.physmem_1.refreshEnergy 179688996240 # Energy for refresh commands per rank (pJ) +system.physmem_1.actBackEnergy 71292253815 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 1621879121250 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 1873730582100 # Total energy per rank (pJ) +system.physmem_1.averagePower 667.435019 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 2641834859500 # Time in different power states +system.physmem_1.memoryStateTime::REF 91865540000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 17159721000 # Time in different power states +system.physmem_1.memoryStateTime::ACT 17456789000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -402,47 +398,47 @@ system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.dtb.walker.walks 5013 # Table walker walks requested -system.cpu0.dtb.walker.walksShort 5013 # Table walker walks initiated with short descriptors -system.cpu0.dtb.walker.walkWaitTime::samples 5013 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::0 5013 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walkWaitTime::total 5013 # Table walker wait (enqueue to first request) latency -system.cpu0.dtb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::mean 1.269102 # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::0 -15265500874 -26.91% -26.91% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::1 71993143250 126.91% 100.00% # Table walker pending requests distribution -system.cpu0.dtb.walker.walksPending::total 56727642376 # Table walker pending requests distribution -system.cpu0.dtb.walker.walkPageSizes::4K 2853 68.40% 68.40% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::1M 1318 31.60% 100.00% # Table walker page sizes translated -system.cpu0.dtb.walker.walkPageSizes::total 4171 # Table walker page sizes translated -system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5013 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walks 5058 # Table walker walks requested +system.cpu0.dtb.walker.walksShort 5058 # Table walker walks initiated with short descriptors +system.cpu0.dtb.walker.walkWaitTime::samples 5058 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::0 5058 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walkWaitTime::total 5058 # Table walker wait (enqueue to first request) latency +system.cpu0.dtb.walker.walksPending::samples 56709099876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::mean 1.269517 # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::0 -15284046374 -26.95% -26.95% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::1 71993146250 126.95% 100.00% # Table walker pending requests distribution +system.cpu0.dtb.walker.walksPending::total 56709099876 # Table walker pending requests distribution +system.cpu0.dtb.walker.walkPageSizes::4K 2875 68.18% 68.18% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::1M 1342 31.82% 100.00% # Table walker page sizes translated +system.cpu0.dtb.walker.walkPageSizes::total 4217 # Table walker page sizes translated +system.cpu0.dtb.walker.walkRequestOrigin_Requested::Data 5058 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5013 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4171 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Requested::total 5058 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::Data 4217 # Table walker requests started/completed, data/inst system.cpu0.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4171 # Table walker requests started/completed, data/inst -system.cpu0.dtb.walker.walkRequestOrigin::total 9184 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin_Completed::total 4217 # Table walker requests started/completed, data/inst +system.cpu0.dtb.walker.walkRequestOrigin::total 9275 # Table walker requests started/completed, data/inst system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 12054005 # DTB read hits -system.cpu0.dtb.read_misses 4307 # DTB read misses -system.cpu0.dtb.write_hits 9056572 # DTB write hits -system.cpu0.dtb.write_misses 706 # DTB write misses +system.cpu0.dtb.read_hits 12051362 # DTB read hits +system.cpu0.dtb.read_misses 4340 # DTB read misses +system.cpu0.dtb.write_hits 9035813 # DTB write hits +system.cpu0.dtb.write_misses 718 # DTB write misses system.cpu0.dtb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.dtb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva 378 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2897 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2913 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 829 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 825 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 179 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 12058312 # DTB read accesses -system.cpu0.dtb.write_accesses 9057278 # DTB write accesses +system.cpu0.dtb.perms_faults 186 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 12055702 # DTB read accesses +system.cpu0.dtb.write_accesses 9036531 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 21110577 # DTB hits -system.cpu0.dtb.misses 5013 # DTB misses -system.cpu0.dtb.accesses 21115590 # DTB accesses +system.cpu0.dtb.hits 21087175 # DTB hits +system.cpu0.dtb.misses 5058 # DTB misses +system.cpu0.dtb.accesses 21092233 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu0.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -472,648 +468,648 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.walker.walks 2456 # Table walker walks requested -system.cpu0.itb.walker.walksShort 2456 # Table walker walks initiated with short descriptors -system.cpu0.itb.walker.walkWaitTime::samples 2456 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::0 2456 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walkWaitTime::total 2456 # Table walker wait (enqueue to first request) latency -system.cpu0.itb.walker.walksPending::samples 56727642376 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::mean 1.269104 # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::0 -15265627374 -26.91% -26.91% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::1 71993269750 126.91% 100.00% # Table walker pending requests distribution -system.cpu0.itb.walker.walksPending::total 56727642376 # Table walker pending requests distribution -system.cpu0.itb.walker.walkPageSizes::4K 1347 75.13% 75.13% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::1M 446 24.87% 100.00% # Table walker page sizes translated -system.cpu0.itb.walker.walkPageSizes::total 1793 # Table walker page sizes translated +system.cpu0.itb.walker.walks 2491 # Table walker walks requested +system.cpu0.itb.walker.walksShort 2491 # Table walker walks initiated with short descriptors +system.cpu0.itb.walker.walkWaitTime::samples 2491 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::0 2491 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walkWaitTime::total 2491 # Table walker wait (enqueue to first request) latency +system.cpu0.itb.walker.walksPending::samples 56709099876 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::mean 1.269519 # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::0 -15284164374 -26.95% -26.95% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::1 71993264250 126.95% 100.00% # Table walker pending requests distribution +system.cpu0.itb.walker.walksPending::total 56709099876 # Table walker pending requests distribution +system.cpu0.itb.walker.walkPageSizes::4K 1355 75.15% 75.15% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::1M 448 24.85% 100.00% # Table walker page sizes translated +system.cpu0.itb.walker.walkPageSizes::total 1803 # Table walker page sizes translated system.cpu0.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2456 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2456 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::Inst 2491 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Requested::total 2491 # Table walker requests started/completed, data/inst system.cpu0.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1793 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1793 # Table walker requests started/completed, data/inst -system.cpu0.itb.walker.walkRequestOrigin::total 4249 # Table walker requests started/completed, data/inst -system.cpu0.itb.inst_hits 56651895 # ITB inst hits -system.cpu0.itb.inst_misses 2456 # ITB inst misses +system.cpu0.itb.walker.walkRequestOrigin_Completed::Inst 1803 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin_Completed::total 1803 # Table walker requests started/completed, data/inst +system.cpu0.itb.walker.walkRequestOrigin::total 4294 # Table walker requests started/completed, data/inst +system.cpu0.itb.inst_hits 56612424 # ITB inst hits +system.cpu0.itb.inst_misses 2491 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 172 # Number of times complete TLB was flushed -system.cpu0.itb.flush_tlb_mva 358 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva 378 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1793 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1798 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 56654351 # ITB inst accesses -system.cpu0.itb.hits 56651895 # DTB hits -system.cpu0.itb.misses 2456 # DTB misses -system.cpu0.itb.accesses 56654351 # DTB accesses -system.cpu0.numCycles 68396174 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 56614915 # ITB inst accesses +system.cpu0.itb.hits 56612424 # DTB hits +system.cpu0.itb.misses 2491 # DTB misses +system.cpu0.itb.accesses 56614915 # DTB accesses +system.cpu0.numCycles 68338048 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 55195315 # Number of instructions committed -system.cpu0.committedOps 66856964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 58675450 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4621 # Number of float alu accesses -system.cpu0.num_func_calls 5764530 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 7314757 # number of instructions that are conditional controls -system.cpu0.num_int_insts 58675450 # number of integer instructions -system.cpu0.num_fp_insts 4621 # number of float instructions -system.cpu0.num_int_register_reads 108161484 # number of times the integer registers were read -system.cpu0.num_int_register_writes 40950551 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3516 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1106 # number of times the floating registers were written -system.cpu0.num_cc_register_reads 203464939 # number of times the CC registers were read -system.cpu0.num_cc_register_writes 24566154 # number of times the CC registers were written -system.cpu0.num_mem_refs 21694661 # number of memory refs -system.cpu0.num_load_insts 12202966 # Number of load instructions -system.cpu0.num_store_insts 9491695 # Number of store instructions -system.cpu0.num_idle_cycles 64604771.704346 # Number of idle cycles -system.cpu0.num_busy_cycles 3791402.295654 # Number of busy cycles -system.cpu0.not_idle_fraction 0.055433 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.944567 # Percentage of idle cycles -system.cpu0.Branches 13394190 # Number of branches fetched -system.cpu0.op_class::No_OpClass 2179 0.00% 0.00% # Class of executed instruction -system.cpu0.op_class::IntAlu 46192822 67.99% 67.99% # Class of executed instruction -system.cpu0.op_class::IntMult 50582 0.07% 68.06% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.06% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 3903 0.01% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.07% # Class of executed instruction -system.cpu0.op_class::MemRead 12202966 17.96% 86.03% # Class of executed instruction -system.cpu0.op_class::MemWrite 9491695 13.97% 100.00% # Class of executed instruction +system.cpu0.committedInsts 55154455 # Number of instructions committed +system.cpu0.committedOps 66797328 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 58626360 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4657 # Number of float alu accesses +system.cpu0.num_func_calls 5768343 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 7305007 # number of instructions that are conditional controls +system.cpu0.num_int_insts 58626360 # number of integer instructions +system.cpu0.num_fp_insts 4657 # number of float instructions +system.cpu0.num_int_register_reads 108074182 # number of times the integer registers were read +system.cpu0.num_int_register_writes 40930233 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3548 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1110 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 203289315 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 24533313 # number of times the CC registers were written +system.cpu0.num_mem_refs 21670788 # number of memory refs +system.cpu0.num_load_insts 12200183 # Number of load instructions +system.cpu0.num_store_insts 9470605 # Number of store instructions +system.cpu0.num_idle_cycles 64551377.953400 # Number of idle cycles +system.cpu0.num_busy_cycles 3786670.046600 # Number of busy cycles +system.cpu0.not_idle_fraction 0.055411 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.944589 # Percentage of idle cycles +system.cpu0.Branches 13387911 # Number of branches fetched +system.cpu0.op_class::No_OpClass 2178 0.00% 0.00% # Class of executed instruction +system.cpu0.op_class::IntAlu 46158472 67.99% 68.00% # Class of executed instruction +system.cpu0.op_class::IntMult 50521 0.07% 68.07% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.07% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 3911 0.01% 68.08% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 68.08% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.08% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.08% # Class of executed instruction +system.cpu0.op_class::MemRead 12200183 17.97% 86.05% # Class of executed instruction +system.cpu0.op_class::MemWrite 9470605 13.95% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 67944147 # Class of executed instruction +system.cpu0.op_class::total 67885870 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 3087 # number of quiesce instructions executed -system.cpu0.dcache.tags.replacements 833490 # number of replacements -system.cpu0.dcache.tags.tagsinuse 511.996671 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 45958483 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 834002 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 55.105963 # Average number of references to valid blocks. +system.cpu0.dcache.tags.replacements 832545 # number of replacements +system.cpu0.dcache.tags.tagsinuse 511.996677 # Cycle average of tags in use +system.cpu0.dcache.tags.total_refs 45907523 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 833057 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 55.107301 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 483.294893 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.112781 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.133577 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu3.data 11.455419 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.943935 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021705 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.011980 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu3.data 0.022374 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::total 0.999993 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 480.190626 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 11.229209 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 5.101691 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu3.data 15.475151 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.937872 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.021932 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.009964 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu3.data 0.030225 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 363 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::2 87 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 61 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 362 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::2 89 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 193340724 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 193340724 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 11422910 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 3593204 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4066922 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu3.data 6785601 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 25868637 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 8719261 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 2659250 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 3172966 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu3.data 4237084 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 18788561 # number of WriteReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu0.data 177218 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu1.data 53891 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu2.data 68030 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::cpu3.data 87717 # number of SoftPFReq hits -system.cpu0.dcache.SoftPFReq_hits::total 386856 # number of SoftPFReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 215939 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 74279 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 70102 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu3.data 90632 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 450952 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 216972 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 75904 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 72697 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu3.data 95027 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 460600 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 20142171 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 6252454 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 7239888 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu3.data 11022685 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 44657198 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 20319389 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 6306345 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 7307918 # number of overall hits -system.cpu0.dcache.overall_hits::cpu3.data 11110402 # number of overall hits -system.cpu0.dcache.overall_hits::total 45044054 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 171223 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 51523 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 83889 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu3.data 223011 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 529646 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 111924 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 33653 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 105580 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu3.data 1235287 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 1486444 # number of WriteReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu0.data 54469 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu1.data 16872 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu2.data 18830 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::cpu3.data 46816 # number of SoftPFReq misses -system.cpu0.dcache.SoftPFReq_misses::total 136987 # number of SoftPFReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 3702 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 2319 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3513 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu3.data 8435 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 17969 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu3.data 21 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 21 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 283147 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 85176 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 189469 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu3.data 1458298 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 2016090 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 337616 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 102048 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 208299 # number of overall misses -system.cpu0.dcache.overall_misses::cpu3.data 1505114 # number of overall misses -system.cpu0.dcache.overall_misses::total 2153077 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 825879500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 1199033500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu3.data 3362095000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 5387008000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1242542000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 5087689996 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu3.data 62077343955 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 68407575951 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 28207500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 45088000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu3.data 123538000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 196833500 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu3.data 598500 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 598500 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 2068421500 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 6286723496 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu3.data 65439438955 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 73794583951 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 2068421500 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 6286723496 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu3.data 65439438955 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 73794583951 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 11594133 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 3644727 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4150811 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu3.data 7008612 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 26398283 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 8831185 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 2692903 # 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miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.235020 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.238006 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.215337 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::cpu3.data 0.350022 # miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_miss_rate::total 0.262048 # miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.016952 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.029799 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048041 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu3.data 0.084551 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.038279 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu3.data 0.000283 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000059 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013821 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.013425 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.025414 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu3.data 0.117670 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.043422 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.016302 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.015882 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.027611 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu3.data 0.120182 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.045855 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 16030.252822 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14357.108547 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu3.data 15041.476535 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 10179.915275 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 37022.163493 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 48282.452374 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu3.data 50166.952205 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 46007.972962 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 12212.577502 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 12681.715893 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu3.data 14597.134705 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10890.226234 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu3.data 21981.481481 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 21981.481481 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 24292.627572 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 33345.133962 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu3.data 44806.708534 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 36639.067092 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20309.836049 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30335.893174 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu3.data 43396.224669 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 34309.228449 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 331201 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 49900 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 13718 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 839 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 24.143534 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 59.475566 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 692577 # number of writebacks -system.cpu0.dcache.writebacks::total 692577 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 93 # 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number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu3.data 1248972 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 1306269 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu1.data 93 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 57204 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu3.data 1248972 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 1306269 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51430 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75379 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112432 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 239241 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33653 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 56886 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu3.data 96894 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 187433 # number of WriteReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 16552 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 15262 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::cpu3.data 32143 # number of SoftPFReq MSHR misses -system.cpu0.dcache.SoftPFReq_mshr_misses::total 63957 # number of SoftPFReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 700 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 1096 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu3.data 3082 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4878 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 21 # 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number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7555 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18412 # number of ReadReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3203 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5165 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 5997 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14365 # number of WriteReq MSHR uncacheable -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 7301 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 11924 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13552 # number of overall MSHR uncacheable misses -system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32777 # number of overall MSHR uncacheable misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 773027500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1007573000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1610752500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3391353000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1208889000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2669627000 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4928516402 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8807032402 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 214952000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 207552500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 496800000 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 919304500 # number of SoftPFReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8874500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 16213500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 51414500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76502500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 577500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 577500 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1981916500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3677200000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6539268902 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 12198385402 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2196868500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3884752500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7036068902 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13117689902 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 706453000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1317087500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1529047000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3552587500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 543393000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 982352000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1199505482 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2725250482 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1249846000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2299439500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2728552482 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6277837982 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014111 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018160 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016042 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009063 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012497 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017351 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017706 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009245 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233908 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.175708 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238923 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.122092 # mshr miss rate for SoftPFReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.009139 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.014888 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031110 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010403 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000221 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000046 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013425 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017803 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016772 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.009142 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015860 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019628 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019141 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.010395 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15030.672759 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13366.759973 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14326.459549 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14175.467416 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 35922.176329 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 46929.420244 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50865.031911 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46987.629724 # average WriteReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12986.466892 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13599.298912 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15455.931307 # average SoftPFReq mshr miss latency -system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14373.790203 # average SoftPFReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12677.857143 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14793.339416 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16682.186892 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15683.169332 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 27500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 27500 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23293.918879 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27801.761615 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31239.640092 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28589.474404 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21615.275250 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26332.484901 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29138.601237 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26736.365827 # average overall mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 172389.702294 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194864.255067 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202388.749173 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 192949.570932 # average ReadReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 169651.264440 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 190193.998064 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 200017.589128 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189714.617612 # average WriteReq mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 171188.330366 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 192841.286481 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 201339.468861 # average overall mshr uncacheable latency -system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191531.805290 # average overall mshr uncacheable latency +system.cpu0.dcache.writebacks::writebacks 690898 # number of writebacks +system.cpu0.dcache.writebacks::total 690898 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 95 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 8080 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::cpu3.data 111730 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 119905 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 48720 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu3.data 1147356 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1196076 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1581 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 2443 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu3.data 5244 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 9268 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu1.data 95 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 56800 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu3.data 1259086 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 1315981 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu1.data 95 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 56800 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu3.data 1259086 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 1315981 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 51206 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 75193 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu3.data 112457 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 238856 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33298 # 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number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu3.data 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 27 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 84504 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 132328 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu3.data 210003 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 426835 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 100767 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 147513 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu3.data 242551 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 490831 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu1.data 4191 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu2.data 6644 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::cpu3.data 7640 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.ReadReq_mshr_uncacheable::total 18475 # number of ReadReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu1.data 3264 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu2.data 5115 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::cpu3.data 6049 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.WriteReq_mshr_uncacheable::total 14428 # number of WriteReq MSHR uncacheable +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu1.data 7455 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu2.data 11759 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::cpu3.data 13689 # number of overall MSHR uncacheable misses +system.cpu0.dcache.overall_mshr_uncacheable_misses::total 32903 # number of overall MSHR uncacheable misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 769942000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1010315000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu3.data 1623285000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 3403542000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1199466000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 2687448500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu3.data 4925947438 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8812861938 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 208330500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 207010000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu3.data 504057000 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 919397500 # number of SoftPFReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 8657000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 16053500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu3.data 52056000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 76766500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu3.data 566500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 566500 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1969408000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3697763500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu3.data 6549232438 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 12216403938 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2177738500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3904773500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu3.data 7053289438 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13135801438 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 729067500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1290773000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu3.data 1548554500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 3568395000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 558890500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 964426500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu3.data 1217476000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2740793000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1287958000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 2255199500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu3.data 2766030500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 6309188000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.014099 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018100 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.016112 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.009062 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.012473 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017379 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.017719 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.009272 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.233315 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.174292 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu3.data 0.238592 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121965 # mshr miss rate for SoftPFReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.008934 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.015027 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu3.data 0.031836 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.010571 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu3.data 0.000283 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000059 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.013410 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.017781 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu3.data 0.016821 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.009154 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.015816 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.019592 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu3.data 0.019218 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.010409 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 15036.167637 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13436.290612 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 14434.717270 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 14249.346887 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36022.163493 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 47036.816312 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 50498.712792 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 46882.162039 # average WriteReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12810.090389 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 13632.532104 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu3.data 15486.573676 # average SoftPFReq mshr miss latency +system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14366.483843 # average SoftPFReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12787.296898 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 14436.600719 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu3.data 16437.006631 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 15489.608555 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu3.data 20981.481481 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 20981.481481 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 23305.500331 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 27943.923433 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu3.data 31186.375614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 28620.904888 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 21611.623845 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 26470.707666 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu3.data 29079.613929 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 26762.371240 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 173960.272011 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 194276.490066 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 202690.379581 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total 193147.225981 # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 171228.707108 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 188548.680352 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 201268.970078 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total 189963.473801 # average WriteReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data 172764.319249 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data 191784.973212 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu3.data 202062.276280 # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total 191751.147312 # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.icache.tags.replacements 1976565 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.476096 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 92948208 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 1977077 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 47.012943 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 12310006500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 437.069776 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 12.930889 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 27.368710 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu3.inst 34.106720 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.853652 # 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average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12781.025821 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12641.969806 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12873.409573 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.797074 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12781.025821 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu3.inst 41700 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 41700 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu3.inst 41700 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 41700 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu3.inst 41700 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 41700 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 208894 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 479974 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu3.inst 542295 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 1231163 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 208894 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 479974 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu3.inst 542295 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 1231163 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 208894 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 479974 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu3.inst 542295 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 1231163 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2642350000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 6179717500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu3.inst 6915980993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 15738048493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2642350000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 6179717500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu3.inst 6915980993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 15738048493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2642350000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 6179717500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu3.inst 6915980993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 15738048493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.012984 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.012984 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011795 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.045434 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu3.inst 0.054581 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.012984 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 12649.238370 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12875.108860 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12783.074616 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 12649.238370 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12875.108860 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12783.074616 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 12649.238370 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12875.108860 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu3.inst 12753.171232 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12783.074616 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -1144,58 +1140,58 @@ system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.dtb.walker.walks 1944 # Table walker walks requested -system.cpu1.dtb.walker.walksShort 1944 # Table walker walks initiated with short descriptors -system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 547 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1397 # Level at which table walker walks with short descriptors terminate -system.cpu1.dtb.walker.walkWaitTime::samples 1944 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::0 1944 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkWaitTime::total 1944 # Table walker wait (enqueue to first request) latency -system.cpu1.dtb.walker.walkCompletionTime::samples 1569 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::mean 12632.887189 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::gmean 11014.350507 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::stdev 6231.121643 # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 0.96% 0.96% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::4096-6143 406 25.88% 26.83% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::10240-12287 522 33.27% 60.10% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::12288-14335 230 14.66% 74.76% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::14336-16383 77 4.91% 79.67% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::22528-24575 319 20.33% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.dtb.walker.walkCompletionTime::total 1569 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walks 1838 # Table walker walks requested +system.cpu1.dtb.walker.walksShort 1838 # Table walker walks initiated with short descriptors +system.cpu1.dtb.walker.walksShortTerminationLevel::Level1 545 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walksShortTerminationLevel::Level2 1293 # Level at which table walker walks with short descriptors terminate +system.cpu1.dtb.walker.walkWaitTime::samples 1838 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::0 1838 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkWaitTime::total 1838 # Table walker wait (enqueue to first request) latency +system.cpu1.dtb.walker.walkCompletionTime::samples 1481 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::mean 10921.336935 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::gmean 9355.199997 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::stdev 6102.562917 # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::2048-4095 15 1.01% 1.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::4096-6143 577 38.96% 39.97% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::10240-12287 520 35.11% 75.08% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::12288-14335 129 8.71% 83.79% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::14336-16383 18 1.22% 85.01% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::22528-24575 222 14.99% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.dtb.walker.walkCompletionTime::total 1481 # Table walker service (enqueue to completion) latency system.cpu1.dtb.walker.walksPending::samples 1000016000 # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::0 1000016000 100.00% 100.00% # Table walker pending requests distribution system.cpu1.dtb.walker.walksPending::total 1000016000 # Table walker pending requests distribution -system.cpu1.dtb.walker.walkPageSizes::4K 1032 65.77% 65.77% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::1M 537 34.23% 100.00% # Table walker page sizes translated -system.cpu1.dtb.walker.walkPageSizes::total 1569 # Table walker page sizes translated -system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1944 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkPageSizes::4K 946 63.88% 63.88% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::1M 535 36.12% 100.00% # Table walker page sizes translated +system.cpu1.dtb.walker.walkPageSizes::total 1481 # Table walker page sizes translated +system.cpu1.dtb.walker.walkRequestOrigin_Requested::Data 1838 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1944 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1569 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Requested::total 1838 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::Data 1481 # Table walker requests started/completed, data/inst system.cpu1.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1569 # Table walker requests started/completed, data/inst -system.cpu1.dtb.walker.walkRequestOrigin::total 3513 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin_Completed::total 1481 # Table walker requests started/completed, data/inst +system.cpu1.dtb.walker.walkRequestOrigin::total 3319 # Table walker requests started/completed, data/inst system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 3796186 # DTB read hits -system.cpu1.dtb.read_misses 1676 # DTB read misses -system.cpu1.dtb.write_hits 2772085 # DTB write hits -system.cpu1.dtb.write_misses 268 # DTB write misses +system.cpu1.dtb.read_hits 3781599 # DTB read hits +system.cpu1.dtb.read_misses 1598 # DTB read misses +system.cpu1.dtb.write_hits 2748070 # DTB write hits +system.cpu1.dtb.write_misses 240 # DTB write misses system.cpu1.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.dtb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1249 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1169 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 236 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 241 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 75 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 3797862 # DTB read accesses -system.cpu1.dtb.write_accesses 2772353 # DTB write accesses +system.cpu1.dtb.perms_faults 67 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 3783197 # DTB read accesses +system.cpu1.dtb.write_accesses 2748310 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 6568271 # DTB hits -system.cpu1.dtb.misses 1944 # DTB misses -system.cpu1.dtb.accesses 6570215 # DTB accesses +system.cpu1.dtb.hits 6529669 # DTB hits +system.cpu1.dtb.misses 1838 # DTB misses +system.cpu1.dtb.accesses 6531507 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu1.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1225,128 +1221,128 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.walker.walks 1001 # Table walker walks requested -system.cpu1.itb.walker.walksShort 1001 # Table walker walks initiated with short descriptors +system.cpu1.itb.walker.walks 906 # Table walker walks requested +system.cpu1.itb.walker.walksShort 906 # Table walker walks initiated with short descriptors system.cpu1.itb.walker.walksShortTerminationLevel::Level1 197 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walksShortTerminationLevel::Level2 804 # Level at which table walker walks with short descriptors terminate -system.cpu1.itb.walker.walkWaitTime::samples 1001 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::0 1001 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkWaitTime::total 1001 # Table walker wait (enqueue to first request) latency -system.cpu1.itb.walker.walkCompletionTime::samples 723 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::mean 12766.251729 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::gmean 11015.623409 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::stdev 6540.201330 # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::4096-6143 211 29.18% 29.18% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 26.97% 56.15% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::12288-14335 151 20.89% 77.04% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::14336-16383 4 0.55% 77.59% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::22528-24575 162 22.41% 100.00% # Table walker service (enqueue to completion) latency -system.cpu1.itb.walker.walkCompletionTime::total 723 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walksShortTerminationLevel::Level2 709 # Level at which table walker walks with short descriptors terminate +system.cpu1.itb.walker.walkWaitTime::samples 906 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::0 906 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkWaitTime::total 906 # Table walker wait (enqueue to first request) latency +system.cpu1.itb.walker.walkCompletionTime::samples 660 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::mean 11564.393939 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::gmean 9819.657022 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::stdev 6526.531967 # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::4096-6143 251 38.03% 38.03% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::10240-12287 195 29.55% 67.58% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::12288-14335 88 13.33% 80.91% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::14336-16383 3 0.45% 81.36% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::22528-24575 123 18.64% 100.00% # Table walker service (enqueue to completion) latency +system.cpu1.itb.walker.walkCompletionTime::total 660 # Table walker service (enqueue to completion) latency system.cpu1.itb.walker.walksPending::samples 1000000500 # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::0 1000000500 100.00% 100.00% # Table walker pending requests distribution system.cpu1.itb.walker.walksPending::total 1000000500 # Table walker pending requests distribution -system.cpu1.itb.walker.walkPageSizes::4K 526 72.75% 72.75% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::1M 197 27.25% 100.00% # Table walker page sizes translated -system.cpu1.itb.walker.walkPageSizes::total 723 # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::4K 463 70.15% 70.15% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::1M 197 29.85% 100.00% # Table walker page sizes translated +system.cpu1.itb.walker.walkPageSizes::total 660 # Table walker page sizes translated system.cpu1.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 1001 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Requested::total 1001 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::Inst 906 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Requested::total 906 # Table walker requests started/completed, data/inst system.cpu1.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 723 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin_Completed::total 723 # Table walker requests started/completed, data/inst -system.cpu1.itb.walker.walkRequestOrigin::total 1724 # Table walker requests started/completed, data/inst -system.cpu1.itb.inst_hits 17742437 # ITB inst hits -system.cpu1.itb.inst_misses 1001 # ITB inst misses +system.cpu1.itb.walker.walkRequestOrigin_Completed::Inst 660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin_Completed::total 660 # Table walker requests started/completed, data/inst +system.cpu1.itb.walker.walkRequestOrigin::total 1566 # Table walker requests started/completed, data/inst +system.cpu1.itb.inst_hits 17710907 # ITB inst hits +system.cpu1.itb.inst_misses 906 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu1.itb.flush_tlb_mva 168 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva 142 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 750 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 687 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 17743438 # ITB inst accesses -system.cpu1.itb.hits 17742437 # DTB hits -system.cpu1.itb.misses 1001 # DTB misses -system.cpu1.itb.accesses 17743438 # DTB accesses -system.cpu1.numCycles 143583360 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 17711813 # ITB inst accesses +system.cpu1.itb.hits 17710907 # DTB hits +system.cpu1.itb.misses 906 # DTB misses +system.cpu1.itb.accesses 17711813 # DTB accesses +system.cpu1.numCycles 143508927 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 17142475 # Number of instructions committed -system.cpu1.committedOps 20690900 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 18446976 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1261 # Number of float alu accesses -system.cpu1.num_func_calls 2007420 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 2180791 # number of instructions that are conditional controls -system.cpu1.num_int_insts 18446976 # number of integer instructions -system.cpu1.num_fp_insts 1261 # number of float instructions -system.cpu1.num_int_register_reads 34256544 # number of times the integer registers were read -system.cpu1.num_int_register_writes 12938178 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 872 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 390 # number of times the floating registers were written -system.cpu1.num_cc_register_reads 75360742 # number of times the CC registers were read -system.cpu1.num_cc_register_writes 7365753 # number of times the CC registers were written -system.cpu1.num_mem_refs 6767228 # number of memory refs -system.cpu1.num_load_insts 3839902 # Number of load instructions -system.cpu1.num_store_insts 2927326 # Number of store instructions -system.cpu1.num_idle_cycles 136602426.841061 # Number of idle cycles -system.cpu1.num_busy_cycles 6980933.158939 # Number of busy cycles -system.cpu1.not_idle_fraction 0.048619 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.951381 # Percentage of idle cycles -system.cpu1.Branches 4294582 # Number of branches fetched +system.cpu1.committedInsts 17104818 # Number of instructions committed +system.cpu1.committedOps 20623291 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 18381943 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1289 # Number of float alu accesses +system.cpu1.num_func_calls 1997851 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 2177891 # number of instructions that are conditional controls +system.cpu1.num_int_insts 18381943 # number of integer instructions +system.cpu1.num_fp_insts 1289 # number of float instructions +system.cpu1.num_int_register_reads 34111926 # number of times the integer registers were read +system.cpu1.num_int_register_writes 12889581 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 904 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 386 # number of times the floating registers were written +system.cpu1.num_cc_register_reads 75094286 # number of times the CC registers were read +system.cpu1.num_cc_register_writes 7377149 # number of times the CC registers were written +system.cpu1.num_mem_refs 6727087 # number of memory refs +system.cpu1.num_load_insts 3824966 # Number of load instructions +system.cpu1.num_store_insts 2902121 # Number of store instructions +system.cpu1.num_idle_cycles 136535289.121910 # Number of idle cycles +system.cpu1.num_busy_cycles 6973637.878090 # Number of busy cycles +system.cpu1.not_idle_fraction 0.048594 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.951406 # Percentage of idle cycles +system.cpu1.Branches 4285863 # Number of branches fetched system.cpu1.op_class::No_OpClass 47 0.00% 0.00% # Class of executed instruction -system.cpu1.op_class::IntAlu 14519635 68.15% 68.15% # Class of executed instruction -system.cpu1.op_class::IntMult 16307 0.08% 68.23% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.23% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 962 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.24% # Class of executed instruction -system.cpu1.op_class::MemRead 3839902 18.02% 86.26% # Class of executed instruction -system.cpu1.op_class::MemWrite 2927326 13.74% 100.00% # Class of executed instruction +system.cpu1.op_class::IntAlu 14489486 68.24% 68.24% # Class of executed instruction +system.cpu1.op_class::IntMult 16051 0.08% 68.31% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.31% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 956 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.32% # Class of executed instruction +system.cpu1.op_class::MemRead 3824966 18.01% 86.33% # Class of executed instruction +system.cpu1.op_class::MemWrite 2902121 13.67% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 21304179 # Class of executed instruction +system.cpu1.op_class::total 21233627 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 5611894 # Number of BP lookups -system.cpu2.branchPred.condPredicted 2863788 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 506095 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3300567 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2344817 # Number of BTB hits +system.cpu2.branchPred.lookups 5616381 # Number of BP lookups +system.cpu2.branchPred.condPredicted 2865516 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 500930 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3264186 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2338379 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 71.042854 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 1575596 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 331093 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 71.637431 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 1579826 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 329229 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1376,56 +1372,56 @@ system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.dtb.walker.walks 12465 # Table walker walks requested -system.cpu2.dtb.walker.walksShort 12465 # Table walker walks initiated with short descriptors -system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7792 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4673 # Level at which table walker walks with short descriptors terminate -system.cpu2.dtb.walker.walkWaitTime::samples 12465 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::0 12465 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkWaitTime::total 12465 # Table walker wait (enqueue to first request) latency -system.cpu2.dtb.walker.walkCompletionTime::samples 2089 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::mean 13064.145524 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::gmean 11307.663622 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::stdev 6855.441685 # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::0-8191 538 25.75% 25.75% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1043 49.93% 75.68% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::16384-24575 506 24.22% 99.90% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.10% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.dtb.walker.walkCompletionTime::total 2089 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walks 12496 # Table walker walks requested +system.cpu2.dtb.walker.walksShort 12496 # Table walker walks initiated with short descriptors +system.cpu2.dtb.walker.walksShortTerminationLevel::Level1 7848 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walksShortTerminationLevel::Level2 4648 # Level at which table walker walks with short descriptors terminate +system.cpu2.dtb.walker.walkWaitTime::samples 12496 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::0 12496 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkWaitTime::total 12496 # Table walker wait (enqueue to first request) latency +system.cpu2.dtb.walker.walkCompletionTime::samples 2107 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::mean 12567.631704 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::gmean 10798.757465 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::stdev 6853.701577 # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::0-8191 615 29.19% 29.19% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::8192-16383 1022 48.50% 77.69% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::16384-24575 468 22.21% 99.91% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::81920-90111 2 0.09% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.dtb.walker.walkCompletionTime::total 2107 # Table walker service (enqueue to completion) latency system.cpu2.dtb.walker.walksPending::samples 2000070000 # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::0 2000070000 100.00% 100.00% # Table walker pending requests distribution system.cpu2.dtb.walker.walksPending::total 2000070000 # Table walker pending requests distribution -system.cpu2.dtb.walker.walkPageSizes::4K 1323 63.33% 63.33% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::1M 766 36.67% 100.00% # Table walker page sizes translated -system.cpu2.dtb.walker.walkPageSizes::total 2089 # Table walker page sizes translated -system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12465 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkPageSizes::4K 1329 63.08% 63.08% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::1M 778 36.92% 100.00% # Table walker page sizes translated +system.cpu2.dtb.walker.walkPageSizes::total 2107 # Table walker page sizes translated +system.cpu2.dtb.walker.walkRequestOrigin_Requested::Data 12496 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12465 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2089 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Requested::total 12496 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::Data 2107 # Table walker requests started/completed, data/inst system.cpu2.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2089 # Table walker requests started/completed, data/inst -system.cpu2.dtb.walker.walkRequestOrigin::total 14554 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin_Completed::total 2107 # Table walker requests started/completed, data/inst +system.cpu2.dtb.walker.walkRequestOrigin::total 14603 # Table walker requests started/completed, data/inst system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 4354485 # DTB read hits -system.cpu2.dtb.read_misses 11147 # DTB read misses -system.cpu2.dtb.write_hits 3379229 # DTB write hits -system.cpu2.dtb.write_misses 1318 # DTB write misses +system.cpu2.dtb.read_hits 4358544 # DTB read hits +system.cpu2.dtb.read_misses 11242 # DTB read misses +system.cpu2.dtb.write_hits 3388369 # DTB write hits +system.cpu2.dtb.write_misses 1254 # DTB write misses system.cpu2.dtb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.dtb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 1531 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 193 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 1540 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 194 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 307 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 117 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 4365632 # DTB read accesses -system.cpu2.dtb.write_accesses 3380547 # DTB write accesses +system.cpu2.dtb.perms_faults 126 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 4369786 # DTB read accesses +system.cpu2.dtb.write_accesses 3389623 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 7733714 # DTB hits -system.cpu2.dtb.misses 12465 # DTB misses -system.cpu2.dtb.accesses 7746179 # DTB accesses +system.cpu2.dtb.hits 7746913 # DTB hits +system.cpu2.dtb.misses 12496 # DTB misses +system.cpu2.dtb.accesses 7759409 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu2.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1455,80 +1451,80 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.walker.walks 1328 # Table walker walks requested -system.cpu2.itb.walker.walksShort 1328 # Table walker walks initiated with short descriptors +system.cpu2.itb.walker.walks 1368 # Table walker walks requested +system.cpu2.itb.walker.walksShort 1368 # Table walker walks initiated with short descriptors system.cpu2.itb.walker.walksShortTerminationLevel::Level1 246 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1082 # Level at which table walker walks with short descriptors terminate -system.cpu2.itb.walker.walkWaitTime::samples 1328 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::0 1328 100.00% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkWaitTime::total 1328 # Table walker wait (enqueue to first request) latency -system.cpu2.itb.walker.walkCompletionTime::samples 881 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::mean 12986.379115 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::gmean 11270.183591 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::stdev 6464.618437 # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::4096-6143 240 27.24% 27.24% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::10240-12287 238 27.01% 54.26% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::12288-14335 191 21.68% 75.94% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::14336-16383 6 0.68% 76.62% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::22528-24575 206 23.38% 100.00% # Table walker service (enqueue to completion) latency -system.cpu2.itb.walker.walkCompletionTime::total 881 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walksShortTerminationLevel::Level2 1122 # Level at which table walker walks with short descriptors terminate +system.cpu2.itb.walker.walkWaitTime::samples 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::0 1368 100.00% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkWaitTime::total 1368 # Table walker wait (enqueue to first request) latency +system.cpu2.itb.walker.walkCompletionTime::samples 900 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::mean 12559.444444 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::gmean 10783.610995 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::stdev 6567.445052 # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::4096-6143 280 31.11% 31.11% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::10240-12287 242 26.89% 58.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::12288-14335 171 19.00% 77.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::14336-16383 5 0.56% 77.56% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::22528-24575 202 22.44% 100.00% # Table walker service (enqueue to completion) latency +system.cpu2.itb.walker.walkCompletionTime::total 900 # Table walker service (enqueue to completion) latency system.cpu2.itb.walker.walksPending::samples 2000055500 # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::0 2000055500 100.00% 100.00% # Table walker pending requests distribution system.cpu2.itb.walker.walksPending::total 2000055500 # Table walker pending requests distribution -system.cpu2.itb.walker.walkPageSizes::4K 640 72.64% 72.64% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::1M 241 27.36% 100.00% # Table walker page sizes translated -system.cpu2.itb.walker.walkPageSizes::total 881 # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::4K 655 72.78% 72.78% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::1M 245 27.22% 100.00% # Table walker page sizes translated +system.cpu2.itb.walker.walkPageSizes::total 900 # Table walker page sizes translated system.cpu2.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1328 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1328 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::Inst 1368 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Requested::total 1368 # Table walker requests started/completed, data/inst system.cpu2.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 881 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin_Completed::total 881 # Table walker requests started/completed, data/inst -system.cpu2.itb.walker.walkRequestOrigin::total 2209 # Table walker requests started/completed, data/inst -system.cpu2.itb.inst_hits 10575904 # ITB inst hits -system.cpu2.itb.inst_misses 1328 # ITB inst misses +system.cpu2.itb.walker.walkRequestOrigin_Completed::Inst 900 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin_Completed::total 900 # Table walker requests started/completed, data/inst +system.cpu2.itb.walker.walkRequestOrigin::total 2268 # Table walker requests started/completed, data/inst +system.cpu2.itb.inst_hits 10566039 # ITB inst hits +system.cpu2.itb.inst_misses 1368 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 152 # Number of times complete TLB was flushed -system.cpu2.itb.flush_tlb_mva 167 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva 166 # Number of times TLB was flushed by MVA system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 923 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 943 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1777 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1761 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 10577232 # ITB inst accesses -system.cpu2.itb.hits 10575904 # DTB hits -system.cpu2.itb.misses 1328 # DTB misses -system.cpu2.itb.accesses 10577232 # DTB accesses -system.cpu2.numCycles 1381990575 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 10567407 # ITB inst accesses +system.cpu2.itb.hits 10566039 # DTB hits +system.cpu2.itb.misses 1368 # DTB misses +system.cpu2.itb.accesses 10567407 # DTB accesses +system.cpu2.numCycles 1381994110 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 19415856 # Number of instructions committed -system.cpu2.committedOps 23538274 # Number of ops (including micro ops) committed -system.cpu2.discardedOps 1407481 # Number of ops (including micro ops) which were discarded before commit -system.cpu2.numFetchSuspends 550 # Number of times Execute suspended instruction fetching -system.cpu2.quiesceCycles 4259391923 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.cpi 71.178452 # CPI: cycles per instruction -system.cpu2.ipc 0.014049 # IPC: instructions per cycle +system.cpu2.committedInsts 19454188 # Number of instructions committed +system.cpu2.committedOps 23590012 # Number of ops (including micro ops) committed +system.cpu2.discardedOps 1394518 # Number of ops (including micro ops) which were discarded before commit +system.cpu2.numFetchSuspends 553 # Number of times Execute suspended instruction fetching +system.cpu2.quiesceCycles 4259350283 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.cpi 71.038386 # CPI: cycles per instruction +system.cpu2.ipc 0.014077 # IPC: instructions per cycle system.cpu2.kern.inst.arm 0 # number of arm instructions executed system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.tickCycles 41337448 # Number of cycles that the object actually ticked -system.cpu2.idleCycles 1340653127 # Total number of cycles that the object has spent stopped -system.cpu3.branchPred.lookups 13659827 # Number of BP lookups -system.cpu3.branchPred.condPredicted 7557018 # Number of conditional branches predicted -system.cpu3.branchPred.condIncorrect 321485 # Number of conditional branches incorrect -system.cpu3.branchPred.BTBLookups 8617850 # Number of BTB lookups -system.cpu3.branchPred.BTBHits 6480530 # Number of BTB hits +system.cpu2.tickCycles 41318295 # Number of cycles that the object actually ticked +system.cpu2.idleCycles 1340675815 # Total number of cycles that the object has spent stopped +system.cpu3.branchPred.lookups 13596196 # Number of BP lookups +system.cpu3.branchPred.condPredicted 7509425 # Number of conditional branches predicted +system.cpu3.branchPred.condIncorrect 305533 # Number of conditional branches incorrect +system.cpu3.branchPred.BTBLookups 8486163 # Number of BTB lookups +system.cpu3.branchPred.BTBHits 6439399 # Number of BTB hits system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu3.branchPred.BTBHitPct 75.198919 # BTB Hit Percentage -system.cpu3.branchPred.usedRAS 3094736 # Number of times the RAS was used to get a target. -system.cpu3.branchPred.RASInCorrect 16291 # Number of incorrect RAS predictions. +system.cpu3.branchPred.BTBHitPct 75.881161 # BTB Hit Percentage +system.cpu3.branchPred.usedRAS 3090908 # Number of times the RAS was used to get a target. +system.cpu3.branchPred.RASInCorrect 15400 # Number of incorrect RAS predictions. system.cpu3.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1558,88 +1554,90 @@ system.cpu3.dstage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.dstage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.dstage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.dtb.walker.walks 35471 # Table walker walks requested -system.cpu3.dtb.walker.walksShort 35471 # Table walker walks initiated with short descriptors -system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11945 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7769 # Level at which table walker walks with short descriptors terminate -system.cpu3.dtb.walker.walksSquashedBefore 15757 # Table walks squashed before starting -system.cpu3.dtb.walker.walkWaitTime::samples 19714 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::mean 617.099523 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::stdev 4045.428418 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::0-16383 19501 98.92% 98.92% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::16384-32767 152 0.77% 99.69% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::32768-49151 42 0.21% 99.90% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walks 33126 # Table walker walks requested +system.cpu3.dtb.walker.walksShort 33126 # Table walker walks initiated with short descriptors +system.cpu3.dtb.walker.walksShortTerminationLevel::Level1 11032 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksShortTerminationLevel::Level2 7972 # Level at which table walker walks with short descriptors terminate +system.cpu3.dtb.walker.walksSquashedBefore 14122 # Table walks squashed before starting +system.cpu3.dtb.walker.walkWaitTime::samples 19004 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::mean 831.246053 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::stdev 4468.197044 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::0-16383 18648 98.13% 98.13% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::16384-32767 304 1.60% 99.73% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::32768-49151 32 0.17% 99.89% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::49152-65535 8 0.04% 99.94% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::65536-81919 7 0.04% 99.98% # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkWaitTime::65536-81919 8 0.04% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::81920-98303 1 0.01% 99.98% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::98304-114687 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::114688-131071 1 0.01% 99.99% # Table walker wait (enqueue to first request) latency system.cpu3.dtb.walker.walkWaitTime::131072-147455 1 0.01% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkWaitTime::total 19714 # Table walker wait (enqueue to first request) latency -system.cpu3.dtb.walker.walkCompletionTime::samples 6425 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::mean 12552.451362 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::gmean 10392.470797 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::stdev 7297.231216 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::0-8191 1902 29.60% 29.60% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::8192-16383 3093 48.14% 77.74% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1290 20.08% 97.82% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::24576-32767 56 0.87% 98.69% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::32768-40959 42 0.65% 99.35% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::40960-49151 37 0.58% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::49152-57343 1 0.02% 99.94% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.98% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 100.00% # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walkCompletionTime::total 6425 # Table walker service (enqueue to completion) latency -system.cpu3.dtb.walker.walksPending::samples -8701578064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::mean 1.155310 # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::0-1 -8749138564 100.55% 100.55% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::2-3 32608500 -0.37% 100.17% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::4-5 7394500 -0.08% 100.09% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::6-7 2262500 -0.03% 100.06% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::8-9 1618000 -0.02% 100.04% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::10-11 1153500 -0.01% 100.03% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::12-13 459000 -0.01% 100.02% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::14-15 1335500 -0.02% 100.01% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::16-17 300000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::18-19 181000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::20-21 108000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::22-23 25500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::24-25 53500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::26-27 12000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::28-29 19000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::30-31 30000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.dtb.walker.walksPending::total -8701578064 # Table walker pending requests distribution -system.cpu3.dtb.walker.walkPageSizes::4K 1781 71.41% 71.41% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::1M 713 28.59% 100.00% # Table walker page sizes translated -system.cpu3.dtb.walker.walkPageSizes::total 2494 # Table walker page sizes translated -system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 35471 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkWaitTime::total 19004 # Table walker wait (enqueue to first request) latency +system.cpu3.dtb.walker.walkCompletionTime::samples 6133 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::mean 11867.275395 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::gmean 9714.087610 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::stdev 7406.609922 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::0-8191 2110 34.40% 34.40% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::8192-16383 2847 46.42% 80.83% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::16384-24575 1040 16.96% 97.78% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::24576-32767 49 0.80% 98.58% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::32768-40959 40 0.65% 99.23% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::40960-49151 39 0.64% 99.87% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::49152-57343 3 0.05% 99.92% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::57344-65535 3 0.05% 99.97% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::81920-90111 1 0.02% 99.98% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::90112-98303 1 0.02% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walkCompletionTime::total 6133 # Table walker service (enqueue to completion) latency +system.cpu3.dtb.walker.walksPending::samples -8716832064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::mean 0.261873 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::stdev 0.297258 # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::0-1 -8763394564 100.53% 100.53% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::2-3 31995000 -0.37% 100.17% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::4-5 7342000 -0.08% 100.08% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::6-7 3254000 -0.04% 100.05% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::8-9 1291000 -0.01% 100.03% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::10-11 970500 -0.01% 100.02% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::12-13 493000 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::14-15 640500 -0.01% 100.01% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::16-17 281000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::18-19 70500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::20-21 112500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::22-23 18500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::24-25 49000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::26-27 6500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::28-29 10500 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::30-31 28000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.dtb.walker.walksPending::total -8716832064 # Table walker pending requests distribution +system.cpu3.dtb.walker.walkPageSizes::4K 1783 70.92% 70.92% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::1M 731 29.08% 100.00% # Table walker page sizes translated +system.cpu3.dtb.walker.walkPageSizes::total 2514 # Table walker page sizes translated +system.cpu3.dtb.walker.walkRequestOrigin_Requested::Data 33126 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 35471 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2494 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Requested::total 33126 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::Data 2514 # Table walker requests started/completed, data/inst system.cpu3.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2494 # Table walker requests started/completed, data/inst -system.cpu3.dtb.walker.walkRequestOrigin::total 37965 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin_Completed::total 2514 # Table walker requests started/completed, data/inst +system.cpu3.dtb.walker.walkRequestOrigin::total 35640 # Table walker requests started/completed, data/inst system.cpu3.dtb.inst_hits 0 # ITB inst hits system.cpu3.dtb.inst_misses 0 # ITB inst misses -system.cpu3.dtb.read_hits 7577935 # DTB read hits -system.cpu3.dtb.read_misses 29413 # DTB read misses -system.cpu3.dtb.write_hits 5839655 # DTB write hits -system.cpu3.dtb.write_misses 6058 # DTB write misses +system.cpu3.dtb.read_hits 7551044 # DTB read hits +system.cpu3.dtb.read_misses 27915 # DTB read misses +system.cpu3.dtb.write_hits 5856516 # DTB write hits +system.cpu3.dtb.write_misses 5211 # DTB write misses system.cpu3.dtb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.dtb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA +system.cpu3.dtb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB -system.cpu3.dtb.align_faults 415 # Number of TLB faults due to alignment restrictions -system.cpu3.dtb.prefetch_faults 739 # Number of TLB faults due to prefetch +system.cpu3.dtb.flush_entries 1721 # Number of entries that have been flushed from TLB +system.cpu3.dtb.align_faults 394 # Number of TLB faults due to alignment restrictions +system.cpu3.dtb.prefetch_faults 742 # Number of TLB faults due to prefetch system.cpu3.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.dtb.perms_faults 327 # Number of TLB faults due to permissions restrictions -system.cpu3.dtb.read_accesses 7607348 # DTB read accesses -system.cpu3.dtb.write_accesses 5845713 # DTB write accesses +system.cpu3.dtb.perms_faults 328 # Number of TLB faults due to permissions restrictions +system.cpu3.dtb.read_accesses 7578959 # DTB read accesses +system.cpu3.dtb.write_accesses 5861727 # DTB write accesses system.cpu3.dtb.inst_accesses 0 # ITB inst accesses -system.cpu3.dtb.hits 13417590 # DTB hits -system.cpu3.dtb.misses 35471 # DTB misses -system.cpu3.dtb.accesses 13453061 # DTB accesses +system.cpu3.dtb.hits 13407560 # DTB hits +system.cpu3.dtb.misses 33126 # DTB misses +system.cpu3.dtb.accesses 13440686 # DTB accesses system.cpu3.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst system.cpu3.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst @@ -1669,385 +1667,385 @@ system.cpu3.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu3.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu3.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu3.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu3.itb.walker.walks 4217 # Table walker walks requested -system.cpu3.itb.walker.walksShort 4217 # Table walker walks initiated with short descriptors -system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1465 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2667 # Level at which table walker walks with short descriptors terminate -system.cpu3.itb.walker.walksSquashedBefore 85 # Table walks squashed before starting -system.cpu3.itb.walker.walkWaitTime::samples 4132 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::mean 1732.090997 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::stdev 7203.300582 # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::0-16383 3973 96.15% 96.15% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::16384-32767 122 2.95% 99.10% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::32768-49151 16 0.39% 99.49% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::49152-65535 12 0.29% 99.78% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::65536-81919 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::81920-98303 2 0.05% 99.93% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::98304-114687 1 0.02% 99.95% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::114688-131071 1 0.02% 99.98% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::131072-147455 1 0.02% 100.00% # Table walker wait (enqueue to first request) latency -system.cpu3.itb.walker.walkWaitTime::total 4132 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walks 4167 # Table walker walks requested +system.cpu3.itb.walker.walksShort 4167 # Table walker walks initiated with short descriptors +system.cpu3.itb.walker.walksShortTerminationLevel::Level1 1453 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksShortTerminationLevel::Level2 2641 # Level at which table walker walks with short descriptors terminate +system.cpu3.itb.walker.walksSquashedBefore 73 # Table walks squashed before starting +system.cpu3.itb.walker.walkWaitTime::samples 4094 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::mean 1495.114802 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::stdev 5985.882126 # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::0-8191 3827 93.48% 93.48% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::8192-16383 124 3.03% 96.51% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::16384-24575 85 2.08% 98.58% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::24576-32767 26 0.64% 99.22% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::32768-40959 12 0.29% 99.51% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::40960-49151 6 0.15% 99.66% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::49152-57343 5 0.12% 99.78% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::57344-65535 4 0.10% 99.88% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::65536-73727 3 0.07% 99.95% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::73728-81919 2 0.05% 100.00% # Table walker wait (enqueue to first request) latency +system.cpu3.itb.walker.walkWaitTime::total 4094 # Table walker wait (enqueue to first request) latency system.cpu3.itb.walker.walkCompletionTime::samples 1265 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::mean 13666.007905 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::gmean 11737.085754 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::stdev 7328.478477 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::0-4095 21 1.66% 1.66% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::4096-8191 283 22.37% 24.03% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::8192-12287 342 27.04% 51.07% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::12288-16383 308 24.35% 75.42% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::16384-20479 17 1.34% 76.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 97.39% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::24576-28671 6 0.47% 97.87% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::28672-32767 7 0.55% 98.42% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::32768-36863 1 0.08% 98.50% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::36864-40959 7 0.55% 99.05% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.76% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::45056-49151 2 0.16% 99.92% # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walkCompletionTime::57344-61439 1 0.08% 100.00% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::mean 13262.450593 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::gmean 11104.068636 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::stdev 7912.964367 # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::0-4095 17 1.34% 1.34% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::4096-8191 362 28.62% 29.96% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::8192-12287 345 27.27% 57.23% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::12288-16383 231 18.26% 75.49% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::16384-20479 10 0.79% 76.28% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::20480-24575 261 20.63% 96.92% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::24576-28671 10 0.79% 97.71% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::28672-32767 6 0.47% 98.18% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::32768-36863 2 0.16% 98.34% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::36864-40959 5 0.40% 98.74% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::40960-45055 9 0.71% 99.45% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::45056-49151 4 0.32% 99.76% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::53248-57343 1 0.08% 99.84% # Table walker service (enqueue to completion) latency +system.cpu3.itb.walker.walkCompletionTime::57344-61439 2 0.16% 100.00% # Table walker service (enqueue to completion) latency system.cpu3.itb.walker.walkCompletionTime::total 1265 # Table walker service (enqueue to completion) latency -system.cpu3.itb.walker.walksPending::samples -8974548064 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::mean 0.863052 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::stdev 0.342327 # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::0 -1226005296 13.66% 13.66% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::1 -7750612268 86.36% 100.02% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::2 1421000 -0.02% 100.01% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::3 452500 -0.01% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::4 116500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::5 31500 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::6 48000 -0.00% 100.00% # Table walker pending requests distribution -system.cpu3.itb.walker.walksPending::total -8974548064 # Table walker pending requests distribution -system.cpu3.itb.walker.walkPageSizes::4K 850 72.03% 72.03% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::1M 330 27.97% 100.00% # Table walker page sizes translated -system.cpu3.itb.walker.walkPageSizes::total 1180 # Table walker page sizes translated +system.cpu3.itb.walker.walksPending::samples -4725503768 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::mean 0.775529 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::stdev 0.415678 # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::0 -1058328796 22.40% 22.40% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::1 -3669011472 77.64% 100.04% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::2 1338500 -0.03% 100.01% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::3 422000 -0.01% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::4 76000 -0.00% 100.00% # Table walker pending requests distribution +system.cpu3.itb.walker.walksPending::total -4725503768 # Table walker pending requests distribution +system.cpu3.itb.walker.walkPageSizes::4K 861 72.23% 72.23% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::1M 331 27.77% 100.00% # Table walker page sizes translated +system.cpu3.itb.walker.walkPageSizes::total 1192 # Table walker page sizes translated system.cpu3.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4217 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4217 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::Inst 4167 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Requested::total 4167 # Table walker requests started/completed, data/inst system.cpu3.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1180 # Table walker requests started/completed, data/inst -system.cpu3.itb.walker.walkRequestOrigin::total 5397 # Table walker requests started/completed, data/inst -system.cpu3.itb.inst_hits 9998093 # ITB inst hits -system.cpu3.itb.inst_misses 4217 # ITB inst misses +system.cpu3.itb.walker.walkRequestOrigin_Completed::Inst 1192 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin_Completed::total 1192 # Table walker requests started/completed, data/inst +system.cpu3.itb.walker.walkRequestOrigin::total 5359 # Table walker requests started/completed, data/inst +system.cpu3.itb.inst_hits 9936571 # ITB inst hits +system.cpu3.itb.inst_misses 4167 # ITB inst misses system.cpu3.itb.read_hits 0 # DTB read hits system.cpu3.itb.read_misses 0 # DTB read misses system.cpu3.itb.write_hits 0 # DTB write hits system.cpu3.itb.write_misses 0 # DTB write misses system.cpu3.itb.flush_tlb 158 # Number of times complete TLB was flushed -system.cpu3.itb.flush_tlb_mva 224 # Number of times TLB was flushed by MVA +system.cpu3.itb.flush_tlb_mva 231 # Number of times TLB was flushed by MVA system.cpu3.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID system.cpu3.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID -system.cpu3.itb.flush_entries 1209 # Number of entries that have been flushed from TLB +system.cpu3.itb.flush_entries 1221 # Number of entries that have been flushed from TLB system.cpu3.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu3.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu3.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu3.itb.perms_faults 709 # Number of TLB faults due to permissions restrictions +system.cpu3.itb.perms_faults 718 # Number of TLB faults due to permissions restrictions system.cpu3.itb.read_accesses 0 # DTB read accesses system.cpu3.itb.write_accesses 0 # DTB write accesses -system.cpu3.itb.inst_accesses 10002310 # ITB inst accesses -system.cpu3.itb.hits 9998093 # DTB hits -system.cpu3.itb.misses 4217 # DTB misses -system.cpu3.itb.accesses 10002310 # DTB accesses -system.cpu3.numCycles 55588609 # number of cpu cycles simulated +system.cpu3.itb.inst_accesses 9940738 # ITB inst accesses +system.cpu3.itb.hits 9936571 # DTB hits +system.cpu3.itb.misses 4167 # DTB misses +system.cpu3.itb.accesses 9940738 # DTB accesses +system.cpu3.numCycles 55573485 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.fetch.icacheStallCycles 20911805 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 54608834 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 13659827 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 9575266 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 32188027 # Number of cycles fetch has run and was not squashing or blocked -system.cpu3.fetch.SquashCycles 1609304 # Number of cycles fetch has spent squashing -system.cpu3.fetch.TlbCycles 73500 # Number of cycles fetch has spent waiting for tlb -system.cpu3.fetch.MiscStallCycles 636 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.PendingDrainCycles 188 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu3.fetch.PendingTrapStallCycles 174621 # Number of stall cycles due to pending traps -system.cpu3.fetch.PendingQuiesceStallCycles 79934 # Number of stall cycles due to pending quiesce instructions -system.cpu3.fetch.IcacheWaitRetryStallCycles 246 # Number of stall cycles due to full MSHR -system.cpu3.fetch.CacheLines 9997086 # Number of cache lines fetched -system.cpu3.fetch.IcacheSquashes 214812 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.ItlbSquashes 2061 # Number of outstanding ITLB misses that were squashed -system.cpu3.fetch.rateDist::samples 54233591 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.215961 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.348203 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.icacheStallCycles 20863261 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 54294907 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 13596196 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 9530307 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 32292568 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 1579965 # Number of cycles fetch has spent squashing +system.cpu3.fetch.TlbCycles 69120 # Number of cycles fetch has spent waiting for tlb +system.cpu3.fetch.MiscStallCycles 1162 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingDrainCycles 268 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu3.fetch.PendingTrapStallCycles 137847 # Number of stall cycles due to pending traps +system.cpu3.fetch.PendingQuiesceStallCycles 66642 # Number of stall cycles due to pending quiesce instructions +system.cpu3.fetch.IcacheWaitRetryStallCycles 261 # Number of stall cycles due to full MSHR +system.cpu3.fetch.CacheLines 9935560 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 207453 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.ItlbSquashes 2022 # Number of outstanding ITLB misses that were squashed +system.cpu3.fetch.rateDist::samples 54221093 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.209618 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.343030 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 39592641 73.00% 73.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 1866738 3.44% 76.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::2 1209172 2.23% 78.68% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::3 3694476 6.81% 85.49% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::4 961111 1.77% 87.26% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 647261 1.19% 88.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::6 2977203 5.49% 93.94% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::7 646450 1.19% 95.13% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::8 2638539 4.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 39652063 73.13% 73.13% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 1860834 3.43% 76.56% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 1199577 2.21% 78.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 3689809 6.81% 85.58% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 944481 1.74% 87.32% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 637799 1.18% 88.50% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 2980778 5.50% 94.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 640190 1.18% 95.18% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2615562 4.82% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 54233591 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.245731 # Number of branch fetches per cycle -system.cpu3.fetch.rate 0.982375 # Number of inst fetches per cycle -system.cpu3.decode.IdleCycles 14602129 # Number of cycles decode is idle -system.cpu3.decode.BlockedCycles 29778773 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 8106369 # Number of cycles decode is running -system.cpu3.decode.UnblockCycles 1026636 # Number of cycles decode is unblocking -system.cpu3.decode.SquashCycles 719503 # Number of cycles decode is squashing -system.cpu3.decode.BranchResolved 1079419 # Number of times decode resolved a branch -system.cpu3.decode.BranchMispred 86358 # Number of times decode detected a branch misprediction -system.cpu3.decode.DecodedInsts 47749839 # Number of instructions handled by decode -system.cpu3.decode.SquashedInsts 276699 # Number of squashed instructions handled by decode -system.cpu3.rename.SquashCycles 719503 # Number of cycles rename is squashing -system.cpu3.rename.IdleCycles 15137242 # Number of cycles rename is idle -system.cpu3.rename.BlockCycles 3025598 # Number of cycles rename is blocking -system.cpu3.rename.serializeStallCycles 21153466 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 8589840 # Number of cycles rename is running -system.cpu3.rename.UnblockCycles 5607720 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 45799280 # Number of instructions processed by rename -system.cpu3.rename.ROBFullEvents 610 # Number of times rename has blocked due to ROB full -system.cpu3.rename.IQFullEvents 1145187 # Number of times rename has blocked due to IQ full -system.cpu3.rename.LQFullEvents 113658 # Number of times rename has blocked due to LQ full -system.cpu3.rename.SQFullEvents 3954911 # Number of times rename has blocked due to SQ full -system.cpu3.rename.RenamedOperands 47609045 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 210470711 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 51575848 # Number of integer rename lookups -system.cpu3.rename.fp_rename_lookups 3589 # Number of floating rename lookups -system.cpu3.rename.CommittedMaps 39452126 # Number of HB maps that are committed -system.cpu3.rename.UndoneMaps 8156919 # Number of HB maps that are undone due to squashing -system.cpu3.rename.serializingInsts 730493 # count of serializing insts renamed -system.cpu3.rename.tempSerializingInsts 676284 # count of temporary serializing insts renamed -system.cpu3.rename.skidInsts 5731608 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 8102362 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 6460033 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 1172202 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 1643889 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 44018542 # Number of instructions added to the IQ (excludes non-spec) -system.cpu3.iq.iqNonSpecInstsAdded 534103 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 41806723 # Number of instructions issued -system.cpu3.iq.iqSquashedInstsIssued 56092 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 6528844 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 14989618 # Number of squashed operands that are examined and possibly removed from graph -system.cpu3.iq.iqSquashedNonSpecRemoved 58298 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 54233591 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 0.770864 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.468112 # Number of insts issued each cycle +system.cpu3.fetch.rateDist::total 54221093 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.244653 # Number of branch fetches per cycle +system.cpu3.fetch.rate 0.976993 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 14541124 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 29923428 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 8020267 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 1031030 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 705051 # Number of cycles decode is squashing +system.cpu3.decode.BranchResolved 1065595 # Number of times decode resolved a branch +system.cpu3.decode.BranchMispred 86058 # Number of times decode detected a branch misprediction +system.cpu3.decode.DecodedInsts 47410230 # Number of instructions handled by decode +system.cpu3.decode.SquashedInsts 276975 # Number of squashed instructions handled by decode +system.cpu3.rename.SquashCycles 705051 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 15074857 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 2997482 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 21287118 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 8510425 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 5645953 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 45500627 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 766 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 1126128 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LQFullEvents 117998 # Number of times rename has blocked due to LQ full +system.cpu3.rename.SQFullEvents 4001017 # Number of times rename has blocked due to SQ full +system.cpu3.rename.RenamedOperands 47247848 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 209204758 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 51266498 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 3571 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 39476281 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 7771567 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 731786 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 677453 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 5778610 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 8053628 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 6456539 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1175060 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1664059 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 43783527 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 535809 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 41699371 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 53091 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 6234373 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 14300280 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 56558 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 54221093 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 0.769062 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.467188 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 37808852 69.71% 69.71% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::1 5406123 9.97% 79.68% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 4124283 7.60% 87.29% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 3378417 6.23% 93.52% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::4 1383474 2.55% 96.07% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::5 844457 1.56% 97.63% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::6 890959 1.64% 99.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::7 261360 0.48% 99.75% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::8 135666 0.25% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 37844395 69.80% 69.80% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 5386682 9.93% 79.73% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 4110296 7.58% 87.31% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 3372256 6.22% 93.53% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 1382084 2.55% 96.08% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 838917 1.55% 97.63% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 889664 1.64% 99.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 259968 0.48% 99.75% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 136831 0.25% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 54233591 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 54221093 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntAlu 64650 10.11% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::IntDiv 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatAdd 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCmp 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatCvt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatDiv 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAdd 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdAlu 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCmp 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdCvt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMisc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShift 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 10.11% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemRead 286710 44.85% 54.96% # attempts to use FU when none available -system.cpu3.iq.fu_full::MemWrite 287936 45.04% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 63437 9.96% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 9.96% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 290906 45.69% 55.65% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 282359 44.35% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu3.iq.FU_type_0::No_OpClass 64 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 27827699 66.56% 66.56% # Type of FU issued -system.cpu3.iq.FU_type_0::IntMult 30281 0.07% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMisc 2306 0.01% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.64% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 7806443 18.67% 85.31% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 6139930 14.69% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::No_OpClass 65 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 27741162 66.53% 66.53% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 30355 0.07% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.60% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 2311 0.01% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.61% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 7771642 18.64% 85.24% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 6153835 14.76% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 41806723 # Type of FU issued -system.cpu3.iq.rate 0.752074 # Inst issue rate -system.cpu3.iq.fu_busy_cnt 639296 # FU busy when requested -system.cpu3.iq.fu_busy_rate 0.015292 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 138534759 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 51105205 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 40599791 # Number of integer instruction queue wakeup accesses -system.cpu3.iq.fp_inst_queue_reads 7666 # Number of floating instruction queue reads -system.cpu3.iq.fp_inst_queue_writes 4221 # Number of floating instruction queue writes -system.cpu3.iq.fp_inst_queue_wakeup_accesses 3348 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 42441848 # Number of integer alu accesses -system.cpu3.iq.fp_alu_accesses 4107 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 178912 # Number of loads that had data forwarded from stores +system.cpu3.iq.FU_type_0::total 41699371 # Type of FU issued +system.cpu3.iq.rate 0.750347 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 636702 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.015269 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 138301991 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 50577353 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 40524265 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 7637 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 4163 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 3346 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 42331916 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 4092 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 178799 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu3.iew.lsq.thread0.squashedLoads 1280236 # Number of loads squashed -system.cpu3.iew.lsq.thread0.ignoredResponses 1538 # Number of memory responses ignored because the instruction is squashed -system.cpu3.iew.lsq.thread0.memOrderViolation 28536 # Number of memory ordering violations -system.cpu3.iew.lsq.thread0.squashedStores 657537 # Number of stores squashed +system.cpu3.iew.lsq.thread0.squashedLoads 1221804 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 1431 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 28394 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 619889 # Number of stores squashed system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu3.iew.lsq.thread0.rescheduledLoads 107166 # Number of loads that were rescheduled -system.cpu3.iew.lsq.thread0.cacheBlocked 47571 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.lsq.thread0.rescheduledLoads 105799 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 48648 # Number of times an access to memory failed due to the cache being blocked system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu3.iew.iewSquashCycles 719503 # Number of cycles IEW is squashing -system.cpu3.iew.iewBlockCycles 2584673 # Number of cycles IEW is blocking -system.cpu3.iew.iewUnblockCycles 329572 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 44617850 # Number of instructions dispatched to IQ -system.cpu3.iew.iewDispSquashedInsts 80448 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 8102362 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 6460033 # Number of dispatched store instructions -system.cpu3.iew.iewDispNonSpecInsts 277261 # Number of dispatched non-speculative instructions -system.cpu3.iew.iewIQFullEvents 23890 # Number of times the IQ has become full, causing a stall -system.cpu3.iew.iewLSQFullEvents 299738 # Number of times the LSQ has become full, causing a stall -system.cpu3.iew.memOrderViolationEvents 28536 # Number of memory order violations -system.cpu3.iew.predictedTakenIncorrect 153085 # Number of branches that were predicted taken incorrectly -system.cpu3.iew.predictedNotTakenIncorrect 129623 # Number of branches that were predicted not taken incorrectly -system.cpu3.iew.branchMispredicts 282708 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 41453550 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 7664420 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 317790 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewSquashCycles 705051 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 2546149 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 337754 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 44384176 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 73225 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 8053628 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 6456539 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 278302 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 24620 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 307122 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 28394 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 141723 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 123945 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 265668 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 41365560 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 7637563 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 300776 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 65205 # number of nop insts executed -system.cpu3.iew.exec_refs 13740951 # number of memory reference insts executed -system.cpu3.iew.exec_branches 7582733 # Number of branches executed -system.cpu3.iew.exec_stores 6076531 # Number of stores executed -system.cpu3.iew.exec_rate 0.745720 # Inst execution rate -system.cpu3.iew.wb_sent 41141473 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 40603139 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 21356385 # num instructions producing a value -system.cpu3.iew.wb_consumers 37848912 # num instructions consuming a value +system.cpu3.iew.exec_nop 64840 # number of nop insts executed +system.cpu3.iew.exec_refs 13731746 # number of memory reference insts executed +system.cpu3.iew.exec_branches 7566030 # Number of branches executed +system.cpu3.iew.exec_stores 6094183 # Number of stores executed +system.cpu3.iew.exec_rate 0.744340 # Inst execution rate +system.cpu3.iew.wb_sent 41063512 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 40527611 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 21306307 # num instructions producing a value +system.cpu3.iew.wb_consumers 37726918 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 0.730422 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.564254 # average fanout of values written-back +system.cpu3.iew.wb_rate 0.729262 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.564751 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu3.commit.commitSquashedInsts 6551591 # The number of squashed insts skipped by commit -system.cpu3.commit.commitNonSpecStalls 475805 # The number of times commit has been forced to stall to communicate backwards -system.cpu3.commit.branchMispredicts 236318 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 52873966 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 0.719843 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 1.617254 # Number of insts commited each cycle +system.cpu3.commit.commitSquashedInsts 6255806 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 479251 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 220583 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 52905057 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 0.720581 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.620547 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 38351228 72.53% 72.53% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 6390419 12.09% 84.62% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::2 3217103 6.08% 90.70% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::3 1425073 2.70% 93.40% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::4 785450 1.49% 94.88% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 547204 1.03% 95.92% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::6 964459 1.82% 97.74% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::7 247730 0.47% 98.21% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::8 945300 1.79% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 38385903 72.56% 72.56% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 6395220 12.09% 84.64% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 3197776 6.04% 90.69% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 1426680 2.70% 93.39% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 782047 1.48% 94.86% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 543081 1.03% 95.89% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 967847 1.83% 97.72% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 251119 0.47% 98.19% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 955384 1.81% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 52873966 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 31209379 # Number of instructions committed -system.cpu3.commit.committedOps 38060928 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 52905057 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 31237505 # Number of instructions committed +system.cpu3.commit.committedOps 38122392 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 12624622 # Number of memory references committed -system.cpu3.commit.loads 6822126 # Number of loads committed -system.cpu3.commit.membars 184951 # Number of memory barriers committed -system.cpu3.commit.branches 7133186 # Number of branches committed +system.cpu3.commit.refs 12668474 # Number of memory references committed +system.cpu3.commit.loads 6831824 # Number of loads committed +system.cpu3.commit.membars 186001 # Number of memory barriers committed +system.cpu3.commit.branches 7139918 # Number of branches committed system.cpu3.commit.fp_insts 3315 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 33210326 # Number of committed integer instructions. -system.cpu3.commit.function_calls 1242319 # Number of function calls committed. +system.cpu3.commit.int_insts 33267854 # Number of committed integer instructions. +system.cpu3.commit.function_calls 1244626 # Number of function calls committed. system.cpu3.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu3.commit.op_class_0::IntAlu 25404774 66.75% 66.75% # Class of committed instruction -system.cpu3.commit.op_class_0::IntMult 29228 0.08% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.82% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMisc 2304 0.01% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.83% # Class of committed instruction -system.cpu3.commit.op_class_0::MemRead 6822126 17.92% 84.75% # Class of committed instruction -system.cpu3.commit.op_class_0::MemWrite 5802496 15.25% 100.00% # Class of committed instruction +system.cpu3.commit.op_class_0::IntAlu 25422255 66.69% 66.69% # Class of committed instruction +system.cpu3.commit.op_class_0::IntMult 29353 0.08% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMisc 2310 0.01% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction +system.cpu3.commit.op_class_0::MemRead 6831824 17.92% 84.69% # Class of committed instruction +system.cpu3.commit.op_class_0::MemWrite 5836650 15.31% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu3.commit.op_class_0::total 38060928 # Class of committed instruction -system.cpu3.commit.bw_lim_events 945300 # number cycles where commit BW limit reached -system.cpu3.rob.rob_reads 90970787 # The number of ROB reads -system.cpu3.rob.rob_writes 90587481 # The number of ROB writes -system.cpu3.timesIdled 219785 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1355018 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 5161755203 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 31172252 # Number of Instructions Simulated -system.cpu3.committedOps 38023801 # Number of Ops (including micro ops) Simulated -system.cpu3.cpi 1.783272 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 1.783272 # CPI: Total CPI of All Threads -system.cpu3.ipc 0.560767 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 0.560767 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 45496208 # number of integer regfile reads -system.cpu3.int_regfile_writes 25431004 # number of integer regfile writes -system.cpu3.fp_regfile_reads 14216 # number of floating regfile reads -system.cpu3.fp_regfile_writes 12004 # number of floating regfile writes -system.cpu3.cc_regfile_reads 146184815 # number of cc regfile reads -system.cpu3.cc_regfile_writes 16067235 # number of cc regfile writes -system.cpu3.misc_regfile_reads 75058867 # number of misc regfile reads -system.cpu3.misc_regfile_writes 353976 # number of misc regfile writes +system.cpu3.commit.op_class_0::total 38122392 # Class of committed instruction +system.cpu3.commit.bw_lim_events 955384 # number cycles where commit BW limit reached +system.cpu3.rob.rob_reads 90746167 # The number of ROB reads +system.cpu3.rob.rob_writes 90074886 # The number of ROB writes +system.cpu3.timesIdled 219461 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 1352392 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 5161729815 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 31200076 # Number of Instructions Simulated +system.cpu3.committedOps 38084963 # Number of Ops (including micro ops) Simulated +system.cpu3.cpi 1.781197 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 1.781197 # CPI: Total CPI of All Threads +system.cpu3.ipc 0.561420 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 0.561420 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 45423777 # number of integer regfile reads +system.cpu3.int_regfile_writes 25365434 # number of integer regfile writes +system.cpu3.fp_regfile_reads 14212 # number of floating regfile reads +system.cpu3.fp_regfile_writes 12005 # number of floating regfile writes +system.cpu3.cc_regfile_reads 145868338 # number of cc regfile reads +system.cpu3.cc_regfile_writes 16008509 # number of cc regfile writes +system.cpu3.misc_regfile_reads 75068874 # number of misc regfile reads +system.cpu3.misc_regfile_writes 356547 # number of misc regfile writes system.iobus.trans_dist::ReadReq 30152 # Transaction distribution system.iobus.trans_dist::ReadResp 30152 # Transaction distribution system.iobus.trans_dist::WriteReq 59010 # Transaction distribution @@ -2102,7 +2100,7 @@ system.iobus.pkt_size_system.bridge.master::total 159093 system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size_system.realview.ide.dma::total 2320992 # Cumulative packet size per connected master and slave (bytes) system.iobus.pkt_size::total 2480085 # Cumulative packet size per connected master and slave (bytes) -system.iobus.reqLayer0.occupancy 23971000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 24223000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer1.occupancy 85000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) @@ -2118,31 +2116,31 @@ system.iobus.reqLayer19.occupancy 2000 # La system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer23.occupancy 3350000 # Layer occupancy (ticks) +system.iobus.reqLayer23.occupancy 3354000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer24.occupancy 85000 # Layer occupancy (ticks) +system.iobus.reqLayer24.occupancy 88000 # Layer occupancy (ticks) system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 18885000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 18813000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer26.occupancy 75000 # Layer occupancy (ticks) system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer27.occupancy 72461073 # Layer occupancy (ticks) +system.iobus.reqLayer27.occupancy 72446830 # Layer occupancy (ticks) system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer28.occupancy 30000 # Layer occupancy (ticks) system.iobus.reqLayer28.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer0.occupancy 50561000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 50749000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) system.iobus.respLayer3.occupancy 14254000 # Layer occupancy (ticks) system.iobus.respLayer3.utilization 0.0 # Layer utilization (%) system.iocache.tags.replacements 36410 # number of replacements -system.iocache.tags.tagsinuse 1.001949 # Cycle average of tags in use +system.iocache.tags.tagsinuse 1.001763 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. system.iocache.tags.sampled_refs 36426 # Sample count of references to valid blocks. system.iocache.tags.avg_refs 0 # Average number of references to valid blocks. -system.iocache.tags.warmup_cycle 248566131009 # Cycle when the warmup percentage was hit. -system.iocache.tags.occ_blocks::realview.ide 1.001949 # Average occupied blocks per requestor -system.iocache.tags.occ_percent::realview.ide 0.062622 # Average percentage of cache occupancy -system.iocache.tags.occ_percent::total 0.062622 # Average percentage of cache occupancy +system.iocache.tags.warmup_cycle 248545825009 # Cycle when the warmup percentage was hit. +system.iocache.tags.occ_blocks::realview.ide 1.001763 # Average occupied blocks per requestor +system.iocache.tags.occ_percent::realview.ide 0.062610 # Average percentage of cache occupancy +system.iocache.tags.occ_percent::total 0.062610 # Average percentage of cache occupancy system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id @@ -2158,8 +2156,8 @@ system.iocache.overall_misses::realview.ide 220 # system.iocache.overall_misses::total 220 # number of overall misses system.iocache.ReadReq_miss_latency::realview.ide 16046914 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 16046914 # number of ReadReq miss cycles -system.iocache.WriteLineReq_miss_latency::realview.ide 1649931159 # number of WriteLineReq miss cycles -system.iocache.WriteLineReq_miss_latency::total 1649931159 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::realview.ide 1650232916 # number of WriteLineReq miss cycles +system.iocache.WriteLineReq_miss_latency::total 1650232916 # number of WriteLineReq miss cycles system.iocache.demand_miss_latency::realview.ide 16046914 # number of demand (read+write) miss cycles system.iocache.demand_miss_latency::total 16046914 # number of demand (read+write) miss cycles system.iocache.overall_miss_latency::realview.ide 16046914 # number of overall miss cycles @@ -2182,8 +2180,8 @@ system.iocache.overall_miss_rate::realview.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::realview.ide 72940.518182 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 72940.518182 # average ReadReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45548.011236 # average WriteLineReq miss latency -system.iocache.WriteLineReq_avg_miss_latency::total 45548.011236 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::realview.ide 45556.341542 # average WriteLineReq miss latency +system.iocache.WriteLineReq_avg_miss_latency::total 45556.341542 # average WriteLineReq miss latency system.iocache.demand_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency system.iocache.demand_avg_miss_latency::total 72940.518182 # average overall miss latency system.iocache.overall_avg_miss_latency::realview.ide 72940.518182 # average overall miss latency @@ -2208,8 +2206,8 @@ system.iocache.overall_mshr_misses::realview.ide 135 system.iocache.overall_mshr_misses::total 135 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::realview.ide 9296914 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 9296914 # number of ReadReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 950731159 # number of WriteLineReq MSHR miss cycles -system.iocache.WriteLineReq_mshr_miss_latency::total 950731159 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::realview.ide 951032916 # number of WriteLineReq MSHR miss cycles +system.iocache.WriteLineReq_mshr_miss_latency::total 951032916 # number of WriteLineReq MSHR miss cycles system.iocache.demand_mshr_miss_latency::realview.ide 9296914 # number of demand (read+write) MSHR miss cycles system.iocache.demand_mshr_miss_latency::total 9296914 # number of demand (read+write) MSHR miss cycles system.iocache.overall_mshr_miss_latency::realview.ide 9296914 # number of overall MSHR miss cycles @@ -2224,390 +2222,376 @@ system.iocache.overall_mshr_miss_rate::realview.ide 0.613636 system.iocache.overall_mshr_miss_rate::total 0.613636 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 68866.029630 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 68866.029630 # average ReadReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 67987.068006 # average WriteLineReq mshr miss latency -system.iocache.WriteLineReq_avg_mshr_miss_latency::total 67987.068006 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::realview.ide 68008.646739 # average WriteLineReq mshr miss latency +system.iocache.WriteLineReq_avg_mshr_miss_latency::total 68008.646739 # average WriteLineReq mshr miss latency system.iocache.demand_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency system.iocache.demand_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::realview.ide 68866.029630 # average overall mshr miss latency system.iocache.overall_avg_mshr_miss_latency::total 68866.029630 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.tags.replacements 101236 # number of replacements -system.l2c.tags.tagsinuse 65107.326464 # Cycle average of tags in use -system.l2c.tags.total_refs 5169585 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 166405 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 31.066284 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 79214835000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 49083.542399 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902823 # Average occupied blocks per requestor +system.l2c.tags.replacements 101351 # number of replacements +system.l2c.tags.tagsinuse 65107.437503 # Cycle average of tags in use +system.l2c.tags.total_refs 5159062 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 166512 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 30.983124 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 79184308500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 48838.010407 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.dtb.walker 2.902867 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 4686.027695 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 1888.757570 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 762.533127 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 823.027459 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 21.612176 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.006778 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 2605.585835 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 671.628280 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.dtb.walker 48.673794 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.inst 2617.148912 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu3.data 1895.879520 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.748955 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 4685.718264 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 1889.035593 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 795.990767 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 850.885557 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 18.207428 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 2675.377352 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 739.764762 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.dtb.walker 57.652959 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.inst 2556.556001 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu3.data 1997.335453 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.745209 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000044 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.071503 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.028820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.011635 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.012558 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000330 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.039758 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.010248 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000743 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.inst 0.039935 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu3.data 0.028929 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.993459 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 52 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65117 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 52 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 13 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 27 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2279 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 8100 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 54698 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000793 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.993607 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 45651328 # Number of tag accesses -system.l2c.tags.data_accesses 45651328 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 4883 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 2386 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 1737 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 894 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 13247 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 1208 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.dtb.walker 21839 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.itb.walker 4721 # number of ReadReq hits -system.l2c.ReadReq_hits::total 50915 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 692577 # number of Writeback hits -system.l2c.Writeback_hits::total 692577 # number of Writeback hits +system.l2c.tags.occ_percent::cpu0.inst 0.071498 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.028824 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.inst 0.012146 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.012983 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000278 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.040823 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.011288 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.dtb.walker 0.000880 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.inst 0.039010 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu3.data 0.030477 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.993461 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 60 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65101 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 60 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 15 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 25 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2291 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 8090 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 54680 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000916 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.993362 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 45578118 # Number of tag accesses +system.l2c.tags.data_accesses 45578118 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 4244 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 2185 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 1248 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 674 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 13130 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 1192 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.dtb.walker 20158 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.itb.walker 4312 # number of ReadReq hits +system.l2c.ReadReq_hits::total 47143 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 690898 # number of Writeback hits +system.l2c.Writeback_hits::total 690898 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 11 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 6 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu2.data 7 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3.data 25 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 49 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu3.data 10 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 10 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 67466 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 21347 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 26309 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3.data 43752 # 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number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3.data 1453053500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3337454000 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 521354500 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 905601000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3.data 1147910000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 2574865500 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1198034500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2113321500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3.data 2600963500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5912319500 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.001976 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.dtb.walker 0.003707 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.002138 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.987069 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.985477 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 0.964844 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.597004 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu3.data 0.259259 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.259259 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.361120 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.534755 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 0.541443 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.318964 # mshr miss rate for ReadExReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.009134 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.012355 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.010269 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadCleanReq_mshr_miss_rate::total 0.006786 # mshr miss rate for ReadCleanReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.035468 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.019554 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.033537 # mshr miss rate for ReadSharedReq accesses +system.l2c.ReadSharedReq_mshr_miss_rate::total 0.017097 # mshr miss rate for ReadSharedReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009134 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.141355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.001976 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.012355 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.216581 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.dtb.walker 0.003707 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.010269 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.234219 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.041054 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009134 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.141355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.001976 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.012355 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.216581 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.dtb.walker 0.003707 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.010269 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.234219 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.041054 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 81000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 20762.008734 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 20768.421053 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 20749.662618 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 20758.363202 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu3.data 35142.857143 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 35142.857143 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 67178.417812 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 66199.184711 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 71748.945671 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 69397.658530 # average ReadExReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 71178.721174 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 70999.831366 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 72168.283046 # average ReadCleanReq mshr miss latency +system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 71510.592272 # average ReadCleanReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 70474.348366 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 72615.986585 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 76724.894345 # average ReadSharedReq mshr miss latency +system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 74277.111717 # average ReadSharedReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 71178.721174 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 67736.513941 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 70999.831366 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 66556.973664 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 72168.283046 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 72179.913547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 70031.128985 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 71178.721174 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 67736.513941 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 80211.538462 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 70999.831366 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 66556.973664 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.dtb.walker 81273.333333 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 72168.283046 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 72179.913547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 70031.128985 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data 161460.272011 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data 181776.113787 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu3.data 190190.248691 # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total 180647.036536 # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data 159728.707108 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data 177048.093842 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3.data 189768.556786 # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total 178463.092598 # average WriteReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data 160702.146211 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data 179719.491453 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu3.data 190003.908247 # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total 179689.374829 # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.membus.trans_dist::ReadReq 40114 # Transaction distribution -system.membus.trans_dist::ReadResp 75602 # Transaction distribution +system.membus.trans_dist::ReadResp 75713 # Transaction distribution system.membus.trans_dist::WriteReq 27565 # Transaction distribution system.membus.trans_dist::WriteResp 27565 # Transaction distribution -system.membus.trans_dist::Writeback 128874 # Transaction distribution -system.membus.trans_dist::CleanEvict 8637 # Transaction distribution +system.membus.trans_dist::Writeback 129126 # Transaction distribution +system.membus.trans_dist::CleanEvict 8500 # Transaction distribution system.membus.trans_dist::UpgradeReq 4529 # Transaction distribution -system.membus.trans_dist::SCUpgradeReq 11 # Transaction distribution -system.membus.trans_dist::UpgradeResp 4540 # Transaction distribution -system.membus.trans_dist::ReadExReq 135912 # Transaction distribution -system.membus.trans_dist::ReadExResp 135912 # Transaction distribution -system.membus.trans_dist::ReadSharedReq 35488 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 7 # Transaction distribution +system.membus.trans_dist::UpgradeResp 4536 # Transaction distribution +system.membus.trans_dist::ReadExReq 135907 # Transaction distribution +system.membus.trans_dist::ReadExResp 135907 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 35599 # Transaction distribution system.membus.trans_dist::InvalidateReq 36224 # Transaction distribution system.membus.trans_dist::InvalidateResp 36224 # Transaction distribution system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105436 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 2006 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480381 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 587833 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 480701 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 588153 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 109028 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.iocache.mem_side::total 109028 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 696861 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 697181 # Packet count per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159093 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 4012 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16930428 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size_system.l2c.mem_side::total 17093553 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16953404 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2c.mem_side::total 17116529 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2321600 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.iocache.mem_side::total 2321600 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 19415153 # Cumulative packet size per connected master and slave (bytes) -system.membus.snoops 336 # Total snoops (count) -system.membus.snoop_fanout::samples 417491 # Request fanout histogram +system.membus.pkt_size::total 19438129 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 335 # Total snoops (count) +system.membus.snoop_fanout::samples 417709 # Request fanout histogram system.membus.snoop_fanout::mean 1 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::1 417491 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 417709 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 1 # Request fanout histogram system.membus.snoop_fanout::max_value 1 # Request fanout histogram -system.membus.snoop_fanout::total 417491 # Request fanout histogram -system.membus.reqLayer0.occupancy 56695500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 417709 # Request fanout histogram +system.membus.reqLayer0.occupancy 57005500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 701000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 697500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer5.occupancy 501323202 # Layer occupancy (ticks) +system.membus.reqLayer5.occupancy 504943941 # Layer occupancy (ticks) system.membus.reqLayer5.utilization 0.0 # Layer utilization (%) -system.membus.respLayer2.occupancy 664397755 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 667734518 # Layer occupancy (ticks) system.membus.respLayer2.utilization 0.0 # Layer utilization (%) -system.membus.respLayer3.occupancy 25144064 # Layer occupancy (ticks) +system.membus.respLayer3.occupancy 25122086 # Layer occupancy (ticks) system.membus.respLayer3.utilization 0.0 # Layer utilization (%) system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -2922,63 +2894,63 @@ system.realview.ethernet.totalRxOrn 0 # to system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.realview.ethernet.postedInterrupts 0 # number of posts to CPU system.realview.ethernet.droppedPackets 0 # number of packets dropped +system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_clcd.clock 42105 # Clock period in ticks system.realview.realview_io.osc_cpu.clock 16667 # Clock period in ticks system.realview.realview_io.osc_ddr.clock 25000 # Clock period in ticks system.realview.realview_io.osc_hsbm.clock 25000 # Clock period in ticks system.realview.realview_io.osc_mcc.clock 20000 # Clock period in ticks system.realview.realview_io.osc_peripheral.clock 41667 # Clock period in ticks -system.realview.realview_io.osc_pxl.clock 42105 # Clock period in ticks system.realview.realview_io.osc_smb.clock 20000 # Clock period in ticks system.realview.realview_io.osc_sys.clock 16667 # Clock period in ticks system.realview.realview_io.osc_system_bus.clock 41667 # Clock period in ticks -system.toL2Bus.trans_dist::ReadReq 112246 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 2626935 # Transaction distribution +system.toL2Bus.trans_dist::ReadReq 111495 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 2623751 # Transaction distribution system.toL2Bus.trans_dist::WriteReq 27565 # Transaction distribution system.toL2Bus.trans_dist::WriteResp 27565 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 762585 # Transaction distribution -system.toL2Bus.trans_dist::CleanEvict 2095941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 2795 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 21 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 2816 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 296569 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 296569 # Transaction distribution -system.toL2Bus.trans_dist::ReadCleanReq 1977107 # Transaction distribution -system.toL2Bus.trans_dist::ReadSharedReq 537598 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 761523 # Transaction distribution +system.toL2Bus.trans_dist::CleanEvict 2094648 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 2804 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 27 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 2831 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 296447 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 296447 # Transaction distribution +system.toL2Bus.trans_dist::ReadCleanReq 1975500 # Transaction distribution +system.toL2Bus.trans_dist::ReadSharedReq 536772 # Transaction distribution system.toL2Bus.trans_dist::InvalidateReq 13984 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5926014 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2620361 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26770 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 102262 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 8675407 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126565496 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97893497 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 45160 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 182440 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.pkt_size::total 224686593 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.snoops 127382 # Total snoops (count) -system.toL2Bus.snoop_fanout::samples 5875721 # Request fanout histogram -system.toL2Bus.snoop_fanout::mean 1.031320 # Request fanout histogram -system.toL2Bus.snoop_fanout::stdev 0.174182 # Request fanout histogram +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 5920920 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2617534 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 26086 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 99400 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 8663940 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 126461880 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97725369 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 42848 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 173572 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.pkt_size::total 224403669 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.snoops 129912 # Total snoops (count) +system.toL2Bus.snoop_fanout::samples 5870347 # Request fanout histogram +system.toL2Bus.snoop_fanout::mean 1.031302 # Request fanout histogram +system.toL2Bus.snoop_fanout::stdev 0.174132 # Request fanout histogram system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram -system.toL2Bus.snoop_fanout::1 5691691 96.87% 96.87% # Request fanout histogram -system.toL2Bus.snoop_fanout::2 184030 3.13% 100.00% # Request fanout histogram +system.toL2Bus.snoop_fanout::1 5686595 96.87% 96.87% # Request fanout histogram +system.toL2Bus.snoop_fanout::2 183752 3.13% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram system.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram -system.toL2Bus.snoop_fanout::total 5875721 # Request fanout histogram -system.toL2Bus.reqLayer0.occupancy 2190361997 # Layer occupancy (ticks) +system.toL2Bus.snoop_fanout::total 5870347 # Request fanout histogram +system.toL2Bus.reqLayer0.occupancy 2188688500 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) system.toL2Bus.snoopLayer0.occupancy 178500 # Layer occupancy (ticks) system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1848817301 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1847107273 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 767245312 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 767774788 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 11020987 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10846487 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 48078267 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 47373752 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) system.cpu3.kern.inst.arm 0 # number of arm instructions executed system.cpu3.kern.inst.quiesce 0 # number of quiesce instructions executed |