diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-11-26 17:05:25 -0600 |
| commit | 2823982a3cbd60a1b21db1a73b78440468df158a (patch) | |
| tree | b955647023da451506138be5a325dfaa2bfd8ee5 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | 9fb93e5cd226ca928ef9cd45bcefcbd94649f4ea (diff) | |
| download | gem5-2823982a3cbd60a1b21db1a73b78440468df158a.tar.xz | |
stats: updates due to changes to ticksToCycles()
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini | 172 | ||||
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 3004 |
2 files changed, 1681 insertions, 1495 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index c314ac71a..745161c28 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -1,7 +1,9 @@ [root] type=Root children=system +eventq_index=0 full_system=true +sim_quantum=0 time_sync_enable=false time_sync_period=100000000000 time_sync_spin_threshold=100000000 @@ -10,17 +12,18 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 cache_line_size=64 clk_domain=system.clk_domain -dtb_filename=False +dtb_filename= early_kernel_symbols=false enable_context_switch_stats_dump=false +eventq_index=0 flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic @@ -45,6 +48,7 @@ system_port=system.membus.slave[0] type=Bridge clk_domain=system.clk_domain delay=50000 +eventq_index=0 ranges=268435456:520093695 1073741824:1610612735 req_size=16 resp_size=16 @@ -56,24 +60,28 @@ type=IdeDisk children=image delay=1000000 driveID=master +eventq_index=0 image=system.cf0.image [system.cf0.image] type=CowDiskImage children=child child=system.cf0.image.child +eventq_index=0 image_file= read_only=false table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +eventq_index=0 +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.clk_domain] type=SrcClockDomain clock=1000 +eventq_index=0 voltage_domain=system.voltage_domain [system.cpu0] @@ -86,6 +94,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu0.dtb +eventq_index=0 fastmem=false function_trace=false function_trace_start=0 @@ -119,6 +128,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=4 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -141,18 +151,21 @@ type=LRU assoc=4 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -163,6 +176,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=1 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=2 is_top_level=true @@ -185,14 +199,17 @@ type=LRU assoc=1 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=2 size=32768 [system.cpu0.interrupts] type=ArmInterrupts +eventq_index=0 [system.cpu0.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -211,18 +228,21 @@ midr=890224640 [system.cpu0.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] [system.cpu0.tracer] type=ExeTracer +eventq_index=0 [system.cpu1] type=TimingSimpleCPU @@ -234,6 +254,7 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu1.dtb +eventq_index=0 function_trace=false function_trace_start=0 interrupts=Null @@ -255,17 +276,20 @@ workload= [system.cpu1.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -284,17 +308,20 @@ midr=890224640 [system.cpu1.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu1.tracer] type=ExeTracer +eventq_index=0 [system.cpu2] type=DerivO3CPU @@ -325,6 +352,8 @@ do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true dtb=system.cpu2.dtb +eventq_index=0 +fetchBufferSize=64 fetchToDecodeDelay=1 fetchTrapLatency=1 fetchWidth=8 @@ -387,6 +416,7 @@ BTBTagSize=16 RASSize=16 choiceCtrBits=2 choicePredictorSize=8192 +eventq_index=0 globalCtrBits=2 globalPredictorSize=8192 instShiftAmt=2 @@ -399,12 +429,14 @@ predType=tournament [system.cpu2.dtb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.dtb.walker [system.cpu2.dtb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system @@ -412,15 +444,18 @@ sys=system type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 +eventq_index=0 [system.cpu2.fuPool.FUList0] type=FUDesc children=opList count=6 +eventq_index=0 opList=system.cpu2.fuPool.FUList0.opList [system.cpu2.fuPool.FUList0.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntAlu opLat=1 @@ -429,16 +464,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 [system.cpu2.fuPool.FUList1.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=IntMult opLat=3 [system.cpu2.fuPool.FUList1.opList1] type=OpDesc +eventq_index=0 issueLat=19 opClass=IntDiv opLat=20 @@ -447,22 +485,26 @@ opLat=20 type=FUDesc children=opList0 opList1 opList2 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 [system.cpu2.fuPool.FUList2.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatAdd opLat=2 [system.cpu2.fuPool.FUList2.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCmp opLat=2 [system.cpu2.fuPool.FUList2.opList2] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatCvt opLat=2 @@ -471,22 +513,26 @@ opLat=2 type=FUDesc children=opList0 opList1 opList2 count=2 +eventq_index=0 opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 [system.cpu2.fuPool.FUList3.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=FloatMult opLat=4 [system.cpu2.fuPool.FUList3.opList1] type=OpDesc +eventq_index=0 issueLat=12 opClass=FloatDiv opLat=12 [system.cpu2.fuPool.FUList3.opList2] type=OpDesc +eventq_index=0 issueLat=24 opClass=FloatSqrt opLat=24 @@ -495,10 +541,12 @@ opLat=24 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList4.opList [system.cpu2.fuPool.FUList4.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 @@ -507,124 +555,145 @@ opLat=1 type=FUDesc children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 [system.cpu2.fuPool.FUList5.opList00] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAdd opLat=1 [system.cpu2.fuPool.FUList5.opList01] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAddAcc opLat=1 [system.cpu2.fuPool.FUList5.opList02] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdAlu opLat=1 [system.cpu2.fuPool.FUList5.opList03] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCmp opLat=1 [system.cpu2.fuPool.FUList5.opList04] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdCvt opLat=1 [system.cpu2.fuPool.FUList5.opList05] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMisc opLat=1 [system.cpu2.fuPool.FUList5.opList06] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMult opLat=1 [system.cpu2.fuPool.FUList5.opList07] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList08] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShift opLat=1 [system.cpu2.fuPool.FUList5.opList09] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdShiftAcc opLat=1 [system.cpu2.fuPool.FUList5.opList10] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdSqrt opLat=1 [system.cpu2.fuPool.FUList5.opList11] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAdd opLat=1 [system.cpu2.fuPool.FUList5.opList12] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatAlu opLat=1 [system.cpu2.fuPool.FUList5.opList13] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCmp opLat=1 [system.cpu2.fuPool.FUList5.opList14] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatCvt opLat=1 [system.cpu2.fuPool.FUList5.opList15] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatDiv opLat=1 [system.cpu2.fuPool.FUList5.opList16] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMisc opLat=1 [system.cpu2.fuPool.FUList5.opList17] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMult opLat=1 [system.cpu2.fuPool.FUList5.opList18] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatMultAcc opLat=1 [system.cpu2.fuPool.FUList5.opList19] type=OpDesc +eventq_index=0 issueLat=1 opClass=SimdFloatSqrt opLat=1 @@ -633,10 +702,12 @@ opLat=1 type=FUDesc children=opList count=0 +eventq_index=0 opList=system.cpu2.fuPool.FUList6.opList [system.cpu2.fuPool.FUList6.opList] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -645,16 +716,19 @@ opLat=1 type=FUDesc children=opList0 opList1 count=4 +eventq_index=0 opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 [system.cpu2.fuPool.FUList7.opList0] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemRead opLat=1 [system.cpu2.fuPool.FUList7.opList1] type=OpDesc +eventq_index=0 issueLat=1 opClass=MemWrite opLat=1 @@ -663,16 +737,19 @@ opLat=1 type=FUDesc children=opList count=1 +eventq_index=0 opList=system.cpu2.fuPool.FUList8.opList [system.cpu2.fuPool.FUList8.opList] type=OpDesc +eventq_index=0 issueLat=3 opClass=IprAccess opLat=3 [system.cpu2.isa] type=ArmISA +eventq_index=0 fpsid=1090793632 id_isar0=34607377 id_isar1=34677009 @@ -691,30 +768,36 @@ midr=890224640 [system.cpu2.itb] type=ArmTLB children=walker +eventq_index=0 size=64 walker=system.cpu2.itb.walker [system.cpu2.itb.walker] type=ArmTableWalker clk_domain=system.cpu_clk_domain +eventq_index=0 num_squash_per_cycle=2 sys=system [system.cpu2.tracer] type=ExeTracer +eventq_index=0 [system.cpu_clk_domain] type=SrcClockDomain clock=500 +eventq_index=0 voltage_domain=system.voltage_domain [system.intrctrl] type=IntrControl +eventq_index=0 sys=system [system.iobus] type=NoncoherentBus clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 use_default_range=false width=8 @@ -727,6 +810,7 @@ children=tags addr_ranges=0:134217727 assoc=8 clk_domain=system.clk_domain +eventq_index=0 forward_snoops=false hit_latency=50 is_top_level=true @@ -749,6 +833,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.clk_domain +eventq_index=0 hit_latency=50 size=1024 @@ -758,6 +843,7 @@ children=tags addr_ranges=0:18446744073709551615 assoc=8 clk_domain=system.cpu_clk_domain +eventq_index=0 forward_snoops=true hit_latency=20 is_top_level=false @@ -780,6 +866,7 @@ type=LRU assoc=8 block_size=64 clk_domain=system.cpu_clk_domain +eventq_index=0 hit_latency=20 size=4194304 @@ -787,6 +874,7 @@ size=4194304 type=CoherentBus children=badaddr_responder clk_domain=system.clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -798,6 +886,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=0 pio_latency=100000 @@ -824,6 +913,7 @@ conf_table_reported=true device_bus_width=8 device_rowbuffer_size=1024 devices_per_rank=8 +eventq_index=0 in_addr_map=true mem_sched_policy=frfcfs null=false @@ -835,19 +925,23 @@ static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 tCL=13750 +tRAS=35000 tRCD=13750 tREFI=7800000 tRFC=300000 tRP=13750 +tRRD=6250 tWTR=7500 tXAW=40000 write_buffer_size=32 -write_thresh_perc=70 +write_high_thresh_perc=70 +write_low_thresh_perc=0 port=system.membus.master[6] [system.realview] type=RealView children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +eventq_index=0 intrctrl=system.intrctrl max_mem_size=268435456 mem_start_addr=0 @@ -857,6 +951,7 @@ system=system [system.realview.a9scu] type=A9SCU clk_domain=system.clk_domain +eventq_index=0 pio_addr=520093696 pio_latency=100000 system=system @@ -866,6 +961,7 @@ pio=system.membus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -894,6 +990,7 @@ BAR5LegacyIO=false BAR5Size=0 BIST=0 CacheLineSize=0 +CapabilityPtr=0 CardbusCIS=0 ClassCode=1 Command=1 @@ -903,8 +1000,40 @@ HeaderType=0 InterruptLine=31 InterruptPin=1 LatencyTimer=0 +MSICAPBaseOffset=0 +MSICAPCapId=0 +MSICAPMaskBits=0 +MSICAPMsgAddr=0 +MSICAPMsgCtrl=0 +MSICAPMsgData=0 +MSICAPMsgUpperAddr=0 +MSICAPNextCapability=0 +MSICAPPendingBits=0 +MSIXCAPBaseOffset=0 +MSIXCAPCapId=0 +MSIXCAPNextCapability=0 +MSIXMsgCtrl=0 +MSIXPbaOffset=0 +MSIXTableOffset=0 MaximumLatency=0 MinimumGrant=0 +PMCAPBaseOffset=0 +PMCAPCapId=0 +PMCAPCapabilities=0 +PMCAPCtrlStatus=0 +PMCAPNextCapability=0 +PXCAPBaseOffset=0 +PXCAPCapId=0 +PXCAPCapabilities=0 +PXCAPDevCap2=0 +PXCAPDevCapabilities=0 +PXCAPDevCtrl=0 +PXCAPDevCtrl2=0 +PXCAPDevStatus=0 +PXCAPLinkCap=0 +PXCAPLinkCtrl=0 +PXCAPLinkStatus=0 +PXCAPNextCapability=0 ProgIF=133 Revision=0 Status=640 @@ -916,6 +1045,7 @@ clk_domain=system.clk_domain config_latency=20000 ctrl_offset=2 disks=system.cf0 +eventq_index=0 io_shift=1 pci_bus=2 pci_dev=7 @@ -931,6 +1061,8 @@ pio=system.iobus.master[7] type=Pl111 amba_id=1315089 clk_domain=system.clk_domain +enable_capture=true +eventq_index=0 gic=system.realview.gic int_num=55 pio_addr=268566528 @@ -945,6 +1077,7 @@ pio=system.iobus.master[4] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -954,6 +1087,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -975,8 +1109,10 @@ cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 dist_pio_delay=10000 +eventq_index=0 int_latency=10000 it_lines=128 +msix_addr=0 platform=system.realview system=system pio=system.membus.master[2] @@ -985,6 +1121,7 @@ pio=system.membus.master[2] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -995,6 +1132,7 @@ pio=system.iobus.master[16] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -1005,6 +1143,7 @@ pio=system.iobus.master[17] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -1015,6 +1154,7 @@ pio=system.iobus.master[18] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -1029,6 +1169,7 @@ pio=system.iobus.master[5] type=Pl050 amba_id=1314896 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -1042,6 +1183,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake clk_domain=system.clk_domain +eventq_index=0 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -1059,6 +1201,7 @@ pio=system.membus.master[3] [system.realview.local_cpu_timer] type=CpuLocalTimer clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_num_timer=29 int_num_watchdog=30 @@ -1071,6 +1214,7 @@ pio=system.membus.master[5] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -1082,6 +1226,7 @@ type=SimpleMemory bandwidth=73.000000 clk_domain=system.clk_domain conf_table_reported=false +eventq_index=0 in_addr_map=true latency=30000 latency_var=0 @@ -1092,6 +1237,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl clk_domain=system.clk_domain +eventq_index=0 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -1104,6 +1250,7 @@ pio=system.iobus.master[1] type=PL031 amba_id=3412017 clk_domain=system.clk_domain +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=42 @@ -1117,6 +1264,7 @@ pio=system.iobus.master[23] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -1127,6 +1275,7 @@ pio=system.iobus.master[20] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -1137,6 +1286,7 @@ pio=system.iobus.master[13] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -1147,6 +1297,7 @@ pio=system.iobus.master[14] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -1159,6 +1310,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=36 int_num1=36 @@ -1173,6 +1325,7 @@ amba_id=1316868 clk_domain=system.clk_domain clock0=1000000 clock1=1000000 +eventq_index=0 gic=system.realview.gic int_num0=37 int_num1=37 @@ -1185,6 +1338,7 @@ pio=system.iobus.master[3] type=Pl011 clk_domain=system.clk_domain end_on_eot=false +eventq_index=0 gic=system.realview.gic int_delay=100000 int_num=44 @@ -1199,6 +1353,7 @@ pio=system.iobus.master[0] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -1209,6 +1364,7 @@ pio=system.iobus.master[10] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -1219,6 +1375,7 @@ pio=system.iobus.master[11] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -1229,6 +1386,7 @@ pio=system.iobus.master[12] type=AmbaFake amba_id=0 clk_domain=system.clk_domain +eventq_index=0 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -1237,6 +1395,7 @@ pio=system.iobus.master[15] [system.terminal] type=Terminal +eventq_index=0 intr_control=system.intrctrl number=0 output=true @@ -1245,6 +1404,7 @@ port=3456 [system.toL2Bus] type=CoherentBus clk_domain=system.cpu_clk_domain +eventq_index=0 header_cycles=1 system=system use_default_range=false @@ -1254,11 +1414,13 @@ slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.wa [system.vncserver] type=VncServer +eventq_index=0 frame_capture=false number=0 port=5900 [system.voltage_domain] type=VoltageDomain +eventq_index=0 voltage=1.000000 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 506582551..3eab7d5a6 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,166 +1,182 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403658 # Number of seconds simulated -sim_ticks 2403657545000 # Number of ticks simulated -final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403659 # Number of seconds simulated +sim_ticks 2403658742000 # Number of ticks simulated +final_tick 2403658742000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 183148 # Simulator instruction rate (inst/s) -host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7297160965 # Simulator tick rate (ticks/s) -host_mem_usage 427808 # Number of bytes of host memory used -host_seconds 329.40 # Real time elapsed on the host -sim_insts 60328152 # Number of instructions simulated -sim_ops 77483430 # Number of ops (including micro ops) simulated +host_inst_rate 141358 # Simulator instruction rate (inst/s) +host_op_rate 181555 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 5632122143 # Simulator tick rate (ticks/s) +host_mem_usage 447420 # Number of bytes of host memory used +host_seconds 426.78 # Real time elapsed on the host +sim_insts 60328128 # Number of instructions simulated +sim_ops 77483556 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512480 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7049296 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 674944 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353888 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661072 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512480 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_inst_read::cpu2.inst 186496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 763104 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743872 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298256 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory -system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558256 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14210 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110179 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 10546 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2914 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21162 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512409 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58498 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324564 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::cpu2.data 389564 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812452 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768458 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213208 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77588 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563261 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213208 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77588 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317476 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557572 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540117 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648285 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812249 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557572 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768458 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213208 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472852 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13467317 # Number of read requests accepted -system.physmem.writeReqs 446508 # Number of write requests accepted -system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.data 347074 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77588 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211546 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675299 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13477345 # Number of read requests accepted +system.physmem.writeReqs 446482 # Number of write requests accepted +system.physmem.readBursts 13477345 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446482 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 862550080 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.bytesWritten 2865536 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109813728 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2811448 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837719 # Per bank write bursts -system.physmem.perBankRdBursts::1 837389 # Per bank write bursts -system.physmem.perBankRdBursts::2 837556 # Per bank write bursts -system.physmem.perBankRdBursts::3 837999 # Per bank write bursts -system.physmem.perBankRdBursts::4 838842 # Per bank write bursts -system.physmem.perBankRdBursts::5 838880 # Per bank write bursts -system.physmem.perBankRdBursts::6 838796 # Per bank write bursts -system.physmem.perBankRdBursts::7 839742 # Per bank write bursts -system.physmem.perBankRdBursts::8 840911 # Per bank write bursts -system.physmem.perBankRdBursts::9 843323 # Per bank write bursts -system.physmem.perBankRdBursts::10 844015 # Per bank write bursts -system.physmem.perBankRdBursts::11 845500 # Per bank write bursts -system.physmem.perBankRdBursts::12 847242 # Per bank write bursts -system.physmem.perBankRdBursts::13 846993 # Per bank write bursts -system.physmem.perBankRdBursts::14 845867 # Per bank write bursts -system.physmem.perBankRdBursts::15 846543 # Per bank write bursts -system.physmem.perBankWrBursts::0 2729 # Per bank write bursts -system.physmem.perBankWrBursts::1 2587 # Per bank write bursts -system.physmem.perBankWrBursts::2 2574 # Per bank write bursts -system.physmem.perBankWrBursts::3 3045 # Per bank write bursts -system.physmem.perBankWrBursts::4 3468 # Per bank write bursts -system.physmem.perBankWrBursts::5 3206 # Per bank write bursts -system.physmem.perBankWrBursts::6 2544 # Per bank write bursts -system.physmem.perBankWrBursts::7 2321 # Per bank write bursts -system.physmem.perBankWrBursts::8 2236 # Per bank write bursts -system.physmem.perBankWrBursts::9 2427 # Per bank write bursts -system.physmem.perBankWrBursts::10 2367 # Per bank write bursts -system.physmem.perBankWrBursts::11 2798 # Per bank write bursts -system.physmem.perBankWrBursts::12 3813 # Per bank write bursts -system.physmem.perBankWrBursts::13 3444 # Per bank write bursts -system.physmem.perBankWrBursts::14 2680 # Per bank write bursts -system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.mergedWrBursts 401707 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2370 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837716 # Per bank write bursts +system.physmem.perBankRdBursts::1 837382 # Per bank write bursts +system.physmem.perBankRdBursts::2 837561 # Per bank write bursts +system.physmem.perBankRdBursts::3 838016 # Per bank write bursts +system.physmem.perBankRdBursts::4 839132 # Per bank write bursts +system.physmem.perBankRdBursts::5 839847 # Per bank write bursts +system.physmem.perBankRdBursts::6 839973 # Per bank write bursts +system.physmem.perBankRdBursts::7 841200 # Per bank write bursts +system.physmem.perBankRdBursts::8 842679 # Per bank write bursts +system.physmem.perBankRdBursts::9 845377 # Per bank write bursts +system.physmem.perBankRdBursts::10 845421 # Per bank write bursts +system.physmem.perBankRdBursts::11 845910 # Per bank write bursts +system.physmem.perBankRdBursts::12 847235 # Per bank write bursts +system.physmem.perBankRdBursts::13 846991 # Per bank write bursts +system.physmem.perBankRdBursts::14 846262 # Per bank write bursts +system.physmem.perBankRdBursts::15 846643 # Per bank write bursts +system.physmem.perBankWrBursts::0 2727 # Per bank write bursts +system.physmem.perBankWrBursts::1 2580 # Per bank write bursts +system.physmem.perBankWrBursts::2 2569 # Per bank write bursts +system.physmem.perBankWrBursts::3 3046 # Per bank write bursts +system.physmem.perBankWrBursts::4 3472 # Per bank write bursts +system.physmem.perBankWrBursts::5 3199 # Per bank write bursts +system.physmem.perBankWrBursts::6 2543 # Per bank write bursts +system.physmem.perBankWrBursts::7 2318 # Per bank write bursts +system.physmem.perBankWrBursts::8 2233 # Per bank write bursts +system.physmem.perBankWrBursts::9 2426 # Per bank write bursts +system.physmem.perBankWrBursts::10 2368 # Per bank write bursts +system.physmem.perBankWrBursts::11 2824 # Per bank write bursts +system.physmem.perBankWrBursts::12 3814 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2652 # Per bank write bursts +system.physmem.perBankWrBursts::15 2556 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.totGap 2402623562000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::3 13441712 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.readPktSize::6 35625 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::2 429390 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17102 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17092 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 971418 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 948778 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 943230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3279616 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2365953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2365403 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2381873 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 45829 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 51923 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17632 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17623 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17610 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17603 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17598 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17596 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 27 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -176,30 +192,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2024 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2445 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2034 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2193 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2289 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2015 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2045 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1984 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1977 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1972 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1965 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1955 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 64 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -208,304 +224,298 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation -system.physmem.totQLat 326245474250 # Total ticks spent queuing -system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers -system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks -system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.bytesPerActivate::samples 48550 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17825.239135 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3190.498487 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18342.849091 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8610 17.73% 17.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4856 10.00% 27.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 981 2.02% 29.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 733 1.51% 31.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 427 0.88% 32.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 370 0.76% 32.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 272 0.56% 33.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 308 0.63% 34.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 164 0.34% 34.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 164 0.34% 34.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 166 0.34% 35.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 231 0.48% 35.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 82 0.17% 35.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 88 0.18% 35.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 37 0.08% 36.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 306 0.63% 36.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 22 0.05% 36.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 33 0.07% 36.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 21 0.04% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 99 0.20% 37.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 20 0.04% 37.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 170 0.35% 37.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 13 0.03% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 137 0.28% 37.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 12 0.02% 37.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 29 0.06% 37.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 10 0.02% 37.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 139 0.29% 38.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 7 0.01% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 378 0.78% 38.94% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 6 0.01% 38.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 7 0.01% 38.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 7 0.01% 38.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 70 0.14% 39.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 3 0.01% 39.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 71 0.15% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 4 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 4 0.01% 39.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 9 0.02% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 7 0.01% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 7 0.01% 39.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 5 0.01% 39.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 411 0.85% 40.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 4 0.01% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 1 0.00% 40.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 132 0.27% 40.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.54% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 7 0.01% 40.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 5 0.01% 40.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 3 0.01% 40.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 73 0.15% 40.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.88% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.89% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 384 0.79% 41.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 7 0.01% 41.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 3 0.01% 41.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 131 0.27% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 8 0.02% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 2 0.00% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 2 0.00% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 2 0.00% 42.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 42.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 42.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 34 0.07% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 2 0.00% 42.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 6 0.01% 42.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 4 0.01% 42.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 263 0.54% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 3 0.01% 42.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 5 0.01% 42.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 131 0.27% 43.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 4 0.01% 43.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 9 0.02% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 43.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 70 0.14% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 3 0.01% 43.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 4 0.01% 43.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 5 0.01% 43.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 103 0.21% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 1 0.00% 43.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 4 0.01% 43.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 9 0.02% 43.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 323 0.67% 44.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 3 0.01% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 4 0.01% 44.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 7 0.01% 44.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 82 0.17% 44.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6720-6727 1 0.00% 44.40% # Bytes accessed per row activation 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65 0.13% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8064-8071 1 0.00% 45.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 415 0.85% 46.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 128 0.26% 46.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 291 0.60% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 1 0.00% 47.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 81 0.17% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 3 0.01% 47.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 320 0.66% 48.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 64 0.13% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 64 0.13% 48.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 128 0.26% 48.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 256 0.53% 49.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 32 0.07% 49.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 64 0.13% 49.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.69% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 375 0.77% 50.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 68 0.14% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12608-12615 1 0.00% 50.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 65 0.13% 50.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 125 0.26% 50.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13120-13127 1 0.00% 51.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 408 0.84% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13568-13575 1 0.00% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13824-13831 64 0.13% 51.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 364 0.75% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14400-14407 1 0.00% 52.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 98 0.20% 53.32% # Bytes accessed per row activation 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+system.physmem.bytesPerActivate::46080-46087 406 0.84% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46528-46535 1 0.00% 87.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46592-46599 64 0.13% 88.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 364 0.75% 88.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 96 0.20% 89.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 69 0.14% 89.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 258 0.53% 90.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 71 0.15% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48960-48967 1 0.00% 90.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 2 0.00% 90.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4686 9.65% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48550 # Bytes accessed per row activation +system.physmem.totQLat 326412969750 # Total ticks spent queuing +system.physmem.totMemAccLat 407861489750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67386725000 # Total ticks spent in databus transfers +system.physmem.totBankLat 14061795000 # Total ticks spent accessing banks +system.physmem.avgQLat 24219.38 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1043.37 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 30262.75 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.85 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage @@ -513,328 +523,330 @@ system.physmem.busUtilRead 2.80 # Da system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13424164 # Number of row buffer hits during reads -system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHits 13434104 # Number of row buffer hits during reads +system.physmem.writeRowHits 39465 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes -system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes +system.physmem.avgGap 172554.83 # Average gap between requests system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55673060 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13803640 # Transaction distribution -system.membus.trans_dist::ReadResp 13803640 # Transaction distribution -system.membus.trans_dist::WriteReq 432247 # Transaction distribution -system.membus.trans_dist::WriteResp 432247 # Transaction distribution -system.membus.trans_dist::Writeback 17102 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution -system.membus.trans_dist::ReadExReq 28053 # Transaction distribution -system.membus.trans_dist::ReadExResp 28053 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.physmem.prechargeAllPercent 0.75 # Percentage of time for which DRAM has all the banks in precharge state +system.membus.throughput 55672581 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13813538 # Transaction distribution +system.membus.trans_dist::ReadResp 13813538 # Transaction distribution +system.membus.trans_dist::WriteReq 432230 # Transaction distribution +system.membus.trans_dist::WriteResp 432230 # Transaction distribution +system.membus.trans_dist::Writeback 17092 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2370 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2370 # Transaction distribution +system.membus.trans_dist::ReadExReq 28046 # Transaction distribution +system.membus.trans_dist::ReadExResp 28046 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 733938 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951878 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686036 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26883424 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28569460 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 737821 # Cumulative packet size per connected master and slave (bytes) system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133818970 # Total data (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5091480 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5829741 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113363437 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133817886 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 418359500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 204500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14607428500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1598779620 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30355600750 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63262 # number of replacements -system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use -system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor +system.l2c.tags.replacements 63253 # number of replacements +system.l2c.tags.tagsinuse 50392.264505 # Cycle average of tags in use +system.l2c.tags.total_refs 1749443 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128649 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.598574 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375574111000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36861.205107 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5227.235315 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3840.097341 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 502.876093 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 689.542033 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.851035 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974650 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1682.063126 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1580.426346 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562457 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079761 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058595 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467622 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 176862 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2604 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 130139 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64269 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18599 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4205 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281217 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 132179 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290754 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597747 # number of Writeback hits -system.l2c.Writeback_hits::total 597747 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007673 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010522 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000105 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025666 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024115 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768925 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8706 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3165 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176725 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2609 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130025 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64311 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18749 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4292 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281381 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 132168 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291173 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597611 # number of Writeback hits +system.l2c.Writeback_hits::total 597611 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61947 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18483 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33173 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113603 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8708 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3160 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 467622 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 238809 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2604 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 130139 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 82752 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18599 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4205 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 281217 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 165352 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404357 # number of demand (read+write) hits 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demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 281381 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 165387 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404794 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8706 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3165 # number of overall hits +system.l2c.overall_hits::cpu0.inst 467858 # number of overall hits +system.l2c.overall_hits::cpu0.data 238674 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2609 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits +system.l2c.overall_hits::cpu1.inst 130025 # number of overall hits +system.l2c.overall_hits::cpu1.data 82764 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18749 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4292 # number of overall hits +system.l2c.overall_hits::cpu2.inst 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60853546260 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017132 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018803 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005773 # mshr miss rate for ReadReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991507 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986564 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987512 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::total 0.508676 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344249 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366927 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.117133 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023420 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000384 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007641 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.115680 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000591 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010305 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116263 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023420 # mshr miss rate for overall accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.344476 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.366569 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117092 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023400 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007647 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115599 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000373 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000233 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010250 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116251 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023400 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63510.695187 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64946.202532 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 62947.444679 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64624.219447 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 66537.011054 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 64252.770682 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.070664 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001.486381 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.668896 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62525.097599 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 63351.490352 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 63074.321708 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.334448 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62561.980200 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62753.451571 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 62689.252619 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58759.980040 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62627.253764 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62440.744536 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63536.800965 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 63047.947183 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 60039.171657 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 62775.676835 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64464.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63573.867536 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 63193.942271 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 63013.907507 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -987,52 +1011,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58815755 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.throughput 58816500 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021450 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021449 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432230 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432230 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265546 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1512 # Transaction distribution system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141271334 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80593 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80593 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831311 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423002 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15637 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52276 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322226 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26580608 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37417965 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85464 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64105945 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141275262 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 99532 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179112263 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872836168 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848885181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10174967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31036489 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762849 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution -system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution -system.iobus.trans_dist::WriteReq 2775 # Transaction distribution -system.iobus.trans_dist::WriteResp 2775 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762826 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13805907 # Transaction distribution +system.iobus.trans_dist::ReadResp 13805907 # Transaction distribution +system.iobus.trans_dist::WriteReq 2774 # Transaction distribution +system.iobus.trans_dist::WriteResp 2774 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 718942 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1048,18 +1072,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 733938 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26883424 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27617362 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715269 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1075,14 +1099,14 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 737821 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107533696 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108271517 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209194 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) @@ -1094,7 +1118,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359973000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1126,35 +1150,35 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13441712000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731164000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36852557250 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7991455 # DTB read hits -system.cpu0.dtb.read_misses 6184 # DTB read misses -system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.read_hits 7990938 # DTB read hits +system.cpu0.dtb.read_misses 6181 # DTB read misses +system.cpu0.dtb.write_hits 6591681 # DTB write hits system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5665 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 119 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7997639 # DTB read accesses -system.cpu0.dtb.write_accesses 6593530 # DTB write accesses +system.cpu0.dtb.read_accesses 7997119 # DTB read accesses +system.cpu0.dtb.write_accesses 6593670 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14582996 # DTB hits -system.cpu0.dtb.misses 8173 # DTB misses -system.cpu0.dtb.accesses 14591169 # DTB accesses -system.cpu0.itb.inst_hits 32325256 # ITB inst hits -system.cpu0.itb.inst_misses 3454 # ITB inst misses +system.cpu0.dtb.hits 14582619 # DTB hits +system.cpu0.dtb.misses 8170 # DTB misses +system.cpu0.dtb.accesses 14590789 # DTB accesses +system.cpu0.itb.inst_hits 32323173 # ITB inst hits +system.cpu0.itb.inst_misses 3455 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -1170,400 +1194,400 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses -system.cpu0.itb.hits 32325256 # DTB hits -system.cpu0.itb.misses 3454 # DTB misses -system.cpu0.itb.accesses 32328710 # DTB accesses -system.cpu0.numCycles 113673861 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32326628 # ITB inst accesses +system.cpu0.itb.hits 32323173 # DTB hits +system.cpu0.itb.misses 3455 # DTB misses +system.cpu0.itb.accesses 32326628 # DTB accesses +system.cpu0.numCycles 113706934 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31847112 # Number of instructions committed -system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses -system.cpu0.num_func_calls 1198427 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37152656 # number of integer instructions -system.cpu0.num_fp_insts 5018 # number of float instructions -system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written -system.cpu0.num_mem_refs 15250074 # number of memory refs -system.cpu0.num_load_insts 8359762 # Number of load instructions -system.cpu0.num_store_insts 6890312 # Number of store instructions -system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles -system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles +system.cpu0.committedInsts 31845607 # Number of instructions committed +system.cpu0.committedOps 42007795 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37151613 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses +system.cpu0.num_func_calls 1198507 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245528 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37151613 # number of integer instructions +system.cpu0.num_fp_insts 4937 # number of float instructions +system.cpu0.num_int_register_reads 189362798 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39261274 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written +system.cpu0.num_mem_refs 15249830 # number of memory refs +system.cpu0.num_load_insts 8359344 # Number of load instructions +system.cpu0.num_store_insts 6890486 # Number of store instructions +system.cpu0.num_idle_cycles 110900908.371908 # Number of idle cycles +system.cpu0.num_busy_cycles 2806025.628092 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024678 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975322 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891412 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602619 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43641790 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891924 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.929942 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8178595250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 492.265032 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.623785 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 11.713802 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.961455 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014890 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.022879 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 31851952 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8051251 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3738587 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43641790 # number of ReadReq hits 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average of tags in use +system.cpu0.icache.tags.total_refs 43642559 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 892173 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.917148 # Average number of references to valid blocks. +system.cpu0.icache.tags.warmup_cycle 8180434250 # Cycle when the warmup percentage was hit. +system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.710568 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.685506 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.207759 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964278 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.015011 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.019937 # Average percentage of cache occupancy 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(read+write) accesses +system.cpu0.icache.overall_accesses::total 44558733 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014731 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016046 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076204 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020561 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014731 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016046 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076204 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020561 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014731 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016046 # miss rate for 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cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3596884562 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5328134323 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27375287500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28782575500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1733546761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3590440812 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5323987573 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1733546761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3590440812 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5323987573 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27356277500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28781091750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56137369250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442174490 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339751582 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14781926072 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28798451990 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42120843332 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70919295322 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033820 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026749 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014103 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021316 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019469 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049859 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043028 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020218 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011525 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028616 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024139 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011525 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12245.686678 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12959.606210 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.544437 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33315.433109 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35310.030029 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34614.428054 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.665513 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11526.466466 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11387.033208 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18777.789632 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19421.330614 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19206.997269 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1576,27 +1600,27 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096740 # DTB read hits -system.cpu1.dtb.read_misses 2075 # DTB read misses -system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.read_hits 2096419 # DTB read hits +system.cpu1.dtb.read_misses 2083 # DTB read misses +system.cpu1.dtb.write_hits 1418166 # DTB write hits system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1734 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098815 # DTB read accesses -system.cpu1.dtb.write_accesses 1419688 # DTB write accesses +system.cpu1.dtb.read_accesses 2098502 # DTB read accesses +system.cpu1.dtb.write_accesses 1418539 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3516055 # DTB hits -system.cpu1.dtb.misses 2448 # DTB misses -system.cpu1.dtb.accesses 3518503 # DTB accesses -system.cpu1.itb.inst_hits 8182654 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.dtb.hits 3514585 # DTB hits +system.cpu1.dtb.misses 2456 # DTB misses +system.cpu1.dtb.accesses 3517041 # DTB accesses +system.cpu1.itb.inst_hits 8182058 # ITB inst hits +system.cpu1.itb.inst_misses 1201 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1605,73 +1629,73 @@ system.cpu1.itb.flush_tlb 277 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 889 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses -system.cpu1.itb.hits 8182654 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8183854 # DTB accesses -system.cpu1.numCycles 581318737 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183259 # ITB inst accesses +system.cpu1.itb.hits 8182058 # DTB hits +system.cpu1.itb.misses 1201 # DTB misses +system.cpu1.itb.accesses 8183259 # DTB accesses +system.cpu1.numCycles 581387993 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7974693 # Number of instructions committed -system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses -system.cpu1.num_func_calls 304877 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9058549 # number of integer instructions -system.cpu1.num_fp_insts 1938 # number of float instructions -system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written -system.cpu1.num_mem_refs 3684398 # number of memory refs -system.cpu1.num_load_insts 2190368 # Number of load instructions -system.cpu1.num_store_insts 1494030 # Number of store instructions -system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles -system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles -system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles +system.cpu1.committedInsts 7973391 # Number of instructions committed +system.cpu1.committedOps 10123180 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9055145 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses +system.cpu1.num_func_calls 304839 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1113920 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9055145 # number of integer instructions +system.cpu1.num_fp_insts 2019 # number of float instructions +system.cpu1.num_int_register_reads 52196104 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9841677 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written +system.cpu1.num_mem_refs 3682729 # number of memory refs +system.cpu1.num_load_insts 2189938 # Number of load instructions +system.cpu1.num_store_insts 1492791 # Number of store instructions +system.cpu1.num_idle_cycles 546287151.729317 # Number of idle cycles +system.cpu1.num_busy_cycles 35100841.270683 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060374 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939626 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4723221 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits +system.cpu2.branchPred.lookups 4728615 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3846891 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223365 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3153803 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2531568 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 80.270328 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413323 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21760 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10969613 # DTB read hits -system.cpu2.dtb.read_misses 23045 # DTB read misses -system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.read_hits 10972958 # DTB read hits +system.cpu2.dtb.read_misses 22884 # DTB read misses +system.cpu2.dtb.write_hits 3353841 # DTB write hits system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2329 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 684 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 147 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10992658 # DTB read accesses -system.cpu2.dtb.write_accesses 3358770 # DTB write accesses +system.cpu2.dtb.perms_faults 471 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10995842 # DTB read accesses +system.cpu2.dtb.write_accesses 3360281 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14321943 # DTB hits -system.cpu2.dtb.misses 29485 # DTB misses -system.cpu2.dtb.accesses 14351428 # DTB accesses -system.cpu2.itb.inst_hits 4048520 # ITB inst hits -system.cpu2.itb.inst_misses 4581 # ITB inst misses +system.cpu2.dtb.hits 14326799 # DTB hits +system.cpu2.dtb.misses 29324 # DTB misses +system.cpu2.dtb.accesses 14356123 # DTB accesses +system.cpu2.itb.inst_hits 4052293 # ITB inst hits +system.cpu2.itb.inst_misses 4591 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits @@ -1684,110 +1708,110 @@ system.cpu2.itb.flush_entries 1671 # Nu system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses -system.cpu2.itb.hits 4048520 # DTB hits -system.cpu2.itb.misses 4581 # DTB misses -system.cpu2.itb.accesses 4053101 # DTB accesses -system.cpu2.numCycles 88363580 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4056884 # ITB inst accesses +system.cpu2.itb.hits 4052293 # DTB hits +system.cpu2.itb.misses 4591 # DTB misses +system.cpu2.itb.accesses 4056884 # DTB accesses +system.cpu2.numCycles 88364936 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9352566 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32517206 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4728615 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2944891 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6861610 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1759869 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50868 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18844594 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 335 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 866 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 32744 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721068 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 448 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4050852 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289827 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1989 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.054164 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440934 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30218075 81.51% 81.51% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 386681 1.04% 82.55% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516163 1.39% 83.94% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819367 2.21% 86.15% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628808 1.70% 87.85% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344228 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1045241 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229591 0.62% 92.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2886315 7.79% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37074469 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053512 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367988 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9932859 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19459354 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6244628 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279238 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1157490 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 609849 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53110 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36985250 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179754 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1157490 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10483306 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6921288 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11074515 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5953553 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483425 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34895792 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2444 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 326661 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 892066 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 111 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37386016 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159700078 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148525933 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3408 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26513636 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10872379 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232480 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 208815 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3253838 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628841 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3905916 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 536820 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 771052 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32212739 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505163 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34823222 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55040 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7182108 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19097970 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148083 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37074469 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939278 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598547 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24463826 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833492 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2324654 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2008652 5.42% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2796278 7.54% 95.56% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971248 2.62% 98.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496274 1.34% 99.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144890 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35155 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37074469 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19545 1.28% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available @@ -1816,13 +1840,13 @@ system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # at system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1401661 91.55% 92.82% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109897 7.18% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61115 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19755783 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28013 0.08% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued @@ -1838,7 +1862,7 @@ system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued @@ -1850,114 +1874,114 @@ system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Ty system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11456328 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3521577 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued -system.cpu2.iq.rate 0.393931 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34823222 # Type of FU issued +system.cpu2.iq.rate 0.394084 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1531104 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043968 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108328678 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39905127 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28084625 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7572 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 4019 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3368 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36289170 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4041 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 206363 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533130 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2013 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9465 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562980 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5327720 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344503 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1157490 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5247900 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88519 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32800222 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60619 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628841 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3905916 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362644 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29757 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2395 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9465 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107959 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89408 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 197367 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33908136 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11185478 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 915086 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82965 # number of nop insts executed -system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3706634 # Number of branches executed -system.cpu2.iew.exec_stores 3486681 # Number of stores executed -system.cpu2.iew.exec_rate 0.383584 # Inst execution rate -system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16115456 # num instructions producing a value -system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value +system.cpu2.iew.exec_nop 82320 # number of nop insts executed +system.cpu2.iew.exec_refs 14673656 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3709694 # Number of branches executed +system.cpu2.iew.exec_stores 3488178 # Number of stores executed +system.cpu2.iew.exec_rate 0.383728 # Inst execution rate +system.cpu2.iew.wb_sent 33508440 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28087993 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16121354 # num instructions producing a value +system.cpu2.iew.wb_consumers 29172590 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317864 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552620 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7137877 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357080 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171034 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35916785 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707415 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751354 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27161260 75.62% 75.62% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4227698 11.77% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1252285 3.49% 90.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 635084 1.77% 92.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 561790 1.56% 94.21% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 319405 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418201 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311340 0.87% 97.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1029722 2.87% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20561870 # Number of instructions committed -system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35916785 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20564616 # Number of instructions committed +system.cpu2.commit.committedOps 25408067 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8436727 # Number of memory references committed -system.cpu2.commit.loads 5094860 # Number of loads committed -system.cpu2.commit.membars 94449 # Number of memory barriers committed -system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.refs 8438647 # Number of memory references committed +system.cpu2.commit.loads 5095711 # Number of loads committed +system.cpu2.commit.membars 94423 # Number of memory barriers committed +system.cpu2.commit.branches 3185422 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295605 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22610745 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295586 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1029722 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66885510 # The number of ROB reads -system.cpu2.rob.rob_writes 66259648 # The number of ROB writes -system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20506347 # Number of Instructions Simulated -system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated -system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads -system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads -system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes +system.cpu2.rob.rob_reads 66910934 # The number of ROB reads +system.cpu2.rob.rob_writes 66293514 # The number of ROB writes +system.cpu2.timesIdled 359960 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51290467 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553935024 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20509130 # Number of Instructions Simulated +system.cpu2.committedOps 25352581 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20509130 # Number of Instructions Simulated +system.cpu2.cpi 4.308566 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.308566 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232096 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232096 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157121826 # number of integer regfile reads +system.cpu2.int_regfile_writes 29906145 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22616 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20826 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9261107 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242774 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1972,10 +1996,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1347589582250 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347589582250 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1347589582250 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |