diff options
| author | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
|---|---|---|
| committer | Nilay Vaish <nilay@cs.wisc.edu> | 2013-03-27 18:36:21 -0500 |
| commit | 4646369afd408b486fd3515c35d6c6bbe8960839 (patch) | |
| tree | 0649a2372083956dc573d4b0d56d60c1c15a344c /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | 4920f0d7e5a4c29ada074bf3a73f36510e138016 (diff) | |
| download | gem5-4646369afd408b486fd3515c35d6c6bbe8960839.tar.xz | |
regressions: update due to cache latency fix
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
4 files changed, 2888 insertions, 2891 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index 22443d9d9..3a9f6f104 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -10,7 +10,7 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/dist/m5/system/binaries/boot.arm +boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 clock=1000 dtb_filename=False @@ -19,12 +19,12 @@ enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic mem_ranges=0:134217727 -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -65,7 +65,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-arm-ael.img +image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img read_only=true [system.cpu0] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr index 151c69fa7..b4a6065b7 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -1,6 +1,7 @@ warn: Sockets disabled, not accepting vnc client connections warn: Sockets disabled, not accepting terminal connections warn: Sockets disabled, not accepting gdb connections +warn: DTB file specified, but no device tree support in kernel warn: The clidr register always reports 0 caches. warn: clidr LoUIS field of 0b001 to match current ARM implementations. warn: The csselr register isn't implemented. @@ -22,5 +23,7 @@ warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR warn: User mode does not have SPSR -gem5.opt: build/ARM/cpu/o3/fetch_impl.hh:432: void DefaultFetch<Impl>::drainSanityCheck() const [with Impl = O3CPUImpl]: Assertion `!memReq[i]' failed. -Program aborted at cycle 2395768530500 +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 527d0013c..1c8a8dfdd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -3,8 +3,8 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2013 19:43:25 -gem5 started Jan 23 2013 22:03:06 +gem5 compiled Mar 26 2013 15:15:23 +gem5 started Mar 27 2013 02:07:42 gem5 executing on ribera.cs.wisc.edu command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second @@ -33,4104 +33,4056 @@ Switching CPUs... Next CPU: DerivO3CPU info: Entering event queue @ 5000004000. Starting simulation... switching cpus -info: Entering event queue @ 5000004500. Starting simulation... +info: Entering event queue @ 5000005000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 6000004500. Starting simulation... +info: Entering event queue @ 6000005000. Starting simulation... switching cpus -info: Entering event queue @ 6000011000. Starting simulation... +info: Entering event queue @ 6000010500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 7000011000. Starting simulation... +info: Entering event queue @ 7000010500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 8000011000. Starting simulation... +info: Entering event queue @ 8000010500. Starting simulation... switching cpus -info: Entering event queue @ 8000065000. Starting simulation... +info: Entering event queue @ 8000121000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 9000065000. Starting simulation... -info: Entering event queue @ 9000075500. Starting simulation... +info: Entering event queue @ 9000121000. Starting simulation... switching cpus -info: Entering event queue @ 9000080000. Starting simulation... +info: Entering event queue @ 9000131500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 10000080000. Starting simulation... switching cpus -info: Entering event queue @ 10000082500. Starting simulation... +info: Entering event queue @ 10000131500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 11000082500. Starting simulation... +info: Entering event queue @ 11000131500. Starting simulation... switching cpus -info: Entering event queue @ 11000084500. Starting simulation... +info: Entering event queue @ 11000132500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 12000084500. Starting simulation... +info: Entering event queue @ 12000132500. Starting simulation... switching cpus -info: Entering event queue @ 12000089500. Starting simulation... +info: Entering event queue @ 12000140500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 13000140500. Starting simulation... switching cpus -info: Entering event queue @ 13000089500. Starting simulation... +info: Entering event queue @ 13000141500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 14000089500. Starting simulation... +info: Entering event queue @ 14000141500. Starting simulation... switching cpus -info: Entering event queue @ 14000090500. Starting simulation... +info: Entering event queue @ 14000161500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 15000090500. Starting simulation... +info: Entering event queue @ 15000161500. Starting simulation... switching cpus -info: Entering event queue @ 15000095000. Starting simulation... +info: Entering event queue @ 15000173500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 16000095000. Starting simulation... +info: Entering event queue @ 16000173500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 17000095000. Starting simulation... +info: Entering event queue @ 17000173500. Starting simulation... switching cpus -info: Entering event queue @ 17000096000. Starting simulation... +info: Entering event queue @ 17000181000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 18000096000. Starting simulation... -info: Entering event queue @ 26044720500. Starting simulation... -info: Entering event queue @ 26044727000. Starting simulation... +info: Entering event queue @ 18000181000. Starting simulation... +info: Entering event queue @ 26044694500. Starting simulation... +info: Entering event queue @ 26044701500. Starting simulation... switching cpus -info: Entering event queue @ 26044727500. Starting simulation... +info: Entering event queue @ 26044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 27044727500. Starting simulation... +info: Entering event queue @ 27044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 28044727500. Starting simulation... +info: Entering event queue @ 28044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 29044727500. Starting simulation... -info: Entering event queue @ 36044720500. Starting simulation... -info: Entering event queue @ 36044727000. Starting simulation... +info: Entering event queue @ 29044706000. Starting simulation... +info: Entering event queue @ 36044694500. Starting simulation... +info: Entering event queue @ 36044701500. Starting simulation... switching cpus -info: Entering event queue @ 36044727500. Starting simulation... +info: Entering event queue @ 36044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 37044727500. Starting simulation... +info: Entering event queue @ 37044706000. Starting simulation... switching cpus -info: Entering event queue @ 37044728000. Starting simulation... +info: Entering event queue @ 37044706500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 38044728000. Starting simulation... -info: Entering event queue @ 38044743500. Starting simulation... +info: Entering event queue @ 38044706500. Starting simulation... +info: Entering event queue @ 38044722500. Starting simulation... switching cpus -info: Entering event queue @ 38044784500. Starting simulation... +info: Entering event queue @ 38044806000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 39044784500. Starting simulation... +info: Entering event queue @ 39044806000. Starting simulation... switching cpus -info: Entering event queue @ 39044856000. Starting simulation... +info: Entering event queue @ 39044813500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 40044856000. Starting simulation... +info: Entering event queue @ 40044813500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 41044856000. Starting simulation... +info: Entering event queue @ 41044813500. Starting simulation... switching cpus -info: Entering event queue @ 41044857500. Starting simulation... +info: Entering event queue @ 41044821000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 42044857500. Starting simulation... +info: Entering event queue @ 42044821000. Starting simulation... switching cpus -info: Entering event queue @ 42045164500. Starting simulation... +info: Entering event queue @ 42045002500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU -info: Entering event queue @ 43045164500. Starting simulation... switching cpus -info: Entering event queue @ 43045165500. Starting simulation... +info: Entering event queue @ 43045002500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 44045165500. Starting simulation... +info: Entering event queue @ 44045002500. Starting simulation... switching cpus -info: Entering event queue @ 44045166000. Starting simulation... +info: Entering event queue @ 44045003500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 45045166000. Starting simulation... +info: Entering event queue @ 45045003500. Starting simulation... switching cpus -info: Entering event queue @ 45045171000. Starting simulation... +info: Entering event queue @ 45045006000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 46045171000. Starting simulation... +info: Entering event queue @ 46045006000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 47045171000. Starting simulation... +info: Entering event queue @ 47045006000. Starting simulation... switching cpus -info: Entering event queue @ 47045181500. Starting simulation... +info: Entering event queue @ 47045010000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 48045181500. Starting simulation... +info: Entering event queue @ 48045010000. Starting simulation... switching cpus -info: Entering event queue @ 48045187000. Starting simulation... +info: Entering event queue @ 48045031000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 49045187000. Starting simulation... +info: Entering event queue @ 49045031000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU +info: Entering event queue @ 50045031000. Starting simulation... switching cpus -info: Entering event queue @ 50045187000. Starting simulation... +info: Entering event queue @ 50045038500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 51045187000. Starting simulation... -info: Entering event queue @ 56044720500. Starting simulation... -info: Entering event queue @ 56044727000. Starting simulation... +info: Entering event queue @ 51045038500. Starting simulation... +info: Entering event queue @ 56044694500. Starting simulation... +info: Entering event queue @ 56044701500. Starting simulation... switching cpus -info: Entering event queue @ 56044727500. Starting simulation... +info: Entering event queue @ 56044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 57044727500. Starting simulation... +info: Entering event queue @ 57044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 58044727500. Starting simulation... +info: Entering event queue @ 58044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 59044727500. Starting simulation... -info: Entering event queue @ 66044720500. Starting simulation... -info: Entering event queue @ 66044727000. Starting simulation... +info: Entering event queue @ 59044706000. Starting simulation... +info: Entering event queue @ 66044694500. Starting simulation... +info: Entering event queue @ 66044701500. Starting simulation... switching cpus -info: Entering event queue @ 66044727500. Starting simulation... +info: Entering event queue @ 66044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 67044727500. Starting simulation... +info: Entering event queue @ 67044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 68044727500. Starting simulation... +info: Entering event queue @ 68044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 69044727500. Starting simulation... -info: Entering event queue @ 76044720500. Starting simulation... -info: Entering event queue @ 76044727000. Starting simulation... +info: Entering event queue @ 69044706000. Starting simulation... +info: Entering event queue @ 76044694500. Starting simulation... +info: Entering event queue @ 76044701500. Starting simulation... switching cpus -info: Entering event queue @ 76044727500. Starting simulation... +info: Entering event queue @ 76044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 77044727500. Starting simulation... +info: Entering event queue @ 77044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 78044727500. Starting simulation... +info: Entering event queue @ 78044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 79044727500. Starting simulation... -info: Entering event queue @ 86044720500. Starting simulation... -info: Entering event queue @ 86044727000. Starting simulation... +info: Entering event queue @ 79044706000. Starting simulation... +info: Entering event queue @ 86044694500. Starting simulation... +info: Entering event queue @ 86044701000. Starting simulation... switching cpus -info: Entering event queue @ 86044727500. Starting simulation... +info: Entering event queue @ 86044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 87044727500. Starting simulation... +info: Entering event queue @ 87044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 88044727500. Starting simulation... +info: Entering event queue @ 88044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 89044727500. Starting simulation... -info: Entering event queue @ 96044720500. Starting simulation... -info: Entering event queue @ 96044727000. Starting simulation... +info: Entering event queue @ 89044701500. Starting simulation... +info: Entering event queue @ 96044694500. Starting simulation... +info: Entering event queue @ 96044701500. Starting simulation... switching cpus -info: Entering event queue @ 96044727500. Starting simulation... +info: Entering event queue @ 96044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 97044727500. Starting simulation... +info: Entering event queue @ 97044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 98044727500. Starting simulation... +info: Entering event queue @ 98044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 99044727500. Starting simulation... -info: Entering event queue @ 106044720500. Starting simulation... -info: Entering event queue @ 106044727000. Starting simulation... +info: Entering event queue @ 99044706000. Starting simulation... +info: Entering event queue @ 106044694500. Starting simulation... +info: Entering event queue @ 106044701500. Starting simulation... switching cpus -info: Entering event queue @ 106044727500. Starting simulation... +info: Entering event queue @ 106044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 107044727500. Starting simulation... +info: Entering event queue @ 107044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 108044727500. Starting simulation... +info: Entering event queue @ 108044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 109044727500. Starting simulation... -info: Entering event queue @ 116044720500. Starting simulation... -info: Entering event queue @ 116044727000. Starting simulation... +info: Entering event queue @ 109044706000. Starting simulation... +info: Entering event queue @ 116044694500. Starting simulation... +info: Entering event queue @ 116044701500. Starting simulation... switching cpus -info: Entering event queue @ 116044727500. Starting simulation... +info: Entering event queue @ 116044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 117044727500. Starting simulation... +info: Entering event queue @ 117044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 118044727500. Starting simulation... +info: Entering event queue @ 118044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 119044727500. Starting simulation... -info: Entering event queue @ 126044720500. Starting simulation... -info: Entering event queue @ 126044727000. Starting simulation... +info: Entering event queue @ 119044706000. Starting simulation... +info: Entering event queue @ 126044695500. Starting simulation... +info: Entering event queue @ 126044702000. Starting simulation... switching cpus -info: Entering event queue @ 126044727500. Starting simulation... +info: Entering event queue @ 126044702500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 127044727500. Starting simulation... +info: Entering event queue @ 127044702500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 128044727500. Starting simulation... +info: Entering event queue @ 128044702500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 129044727500. Starting simulation... -info: Entering event queue @ 136044720500. Starting simulation... -info: Entering event queue @ 136044727000. Starting simulation... +info: Entering event queue @ 129044702500. Starting simulation... +info: Entering event queue @ 136044694500. Starting simulation... +info: Entering event queue @ 136044701000. Starting simulation... switching cpus -info: Entering event queue @ 136044727500. Starting simulation... +info: Entering event queue @ 136044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 137044727500. Starting simulation... +info: Entering event queue @ 137044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 138044727500. Starting simulation... +info: Entering event queue @ 138044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 139044727500. Starting simulation... -info: Entering event queue @ 146044720500. Starting simulation... -info: Entering event queue @ 146044727000. Starting simulation... +info: Entering event queue @ 139044701500. Starting simulation... +info: Entering event queue @ 146044694500. Starting simulation... +info: Entering event queue @ 146044701500. Starting simulation... switching cpus -info: Entering event queue @ 146044727500. Starting simulation... +info: Entering event queue @ 146044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 147044727500. Starting simulation... +info: Entering event queue @ 147044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 148044727500. Starting simulation... +info: Entering event queue @ 148044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 149044727500. Starting simulation... -info: Entering event queue @ 156044720500. Starting simulation... -info: Entering event queue @ 156044727000. Starting simulation... +info: Entering event queue @ 149044706000. Starting simulation... +info: Entering event queue @ 156044694500. Starting simulation... +info: Entering event queue @ 156044701500. Starting simulation... switching cpus -info: Entering event queue @ 156044727500. Starting simulation... +info: Entering event queue @ 156044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 157044727500. Starting simulation... +info: Entering event queue @ 157044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 158044727500. Starting simulation... +info: Entering event queue @ 158044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 159044727500. Starting simulation... -info: Entering event queue @ 166044720500. Starting simulation... -info: Entering event queue @ 166044727000. Starting simulation... +info: Entering event queue @ 159044706000. Starting simulation... +info: Entering event queue @ 166044694500. Starting simulation... +info: Entering event queue @ 166044701500. Starting simulation... switching cpus -info: Entering event queue @ 166044727500. Starting simulation... +info: Entering event queue @ 166044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 167044727500. Starting simulation... +info: Entering event queue @ 167044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 168044727500. Starting simulation... +info: Entering event queue @ 168044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 169044727500. Starting simulation... -info: Entering event queue @ 176044720500. Starting simulation... -info: Entering event queue @ 176044727000. Starting simulation... +info: Entering event queue @ 169044706000. Starting simulation... +info: Entering event queue @ 176044694500. Starting simulation... +info: Entering event queue @ 176044701500. Starting simulation... switching cpus -info: Entering event queue @ 176044727500. Starting simulation... +info: Entering event queue @ 176044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 177044727500. Starting simulation... +info: Entering event queue @ 177044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 178044727500. Starting simulation... +info: Entering event queue @ 178044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 179044727500. Starting simulation... -info: Entering event queue @ 186044720500. Starting simulation... -info: Entering event queue @ 186044727000. Starting simulation... +info: Entering event queue @ 179044706000. Starting simulation... +info: Entering event queue @ 186044694500. Starting simulation... +info: Entering event queue @ 186044701500. Starting simulation... switching cpus -info: Entering event queue @ 186044727500. Starting simulation... +info: Entering event queue @ 186044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 187044727500. Starting simulation... +info: Entering event queue @ 187044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 188044727500. Starting simulation... +info: Entering event queue @ 188044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 189044727500. Starting simulation... -info: Entering event queue @ 196044720500. Starting simulation... -info: Entering event queue @ 196044727000. Starting simulation... +info: Entering event queue @ 189044706000. Starting simulation... +info: Entering event queue @ 196044695500. Starting simulation... +info: Entering event queue @ 196044702500. Starting simulation... switching cpus -info: Entering event queue @ 196044727500. Starting simulation... +info: Entering event queue @ 196044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 197044727500. Starting simulation... +info: Entering event queue @ 197044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 198044727500. Starting simulation... +info: Entering event queue @ 198044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 199044727500. Starting simulation... -info: Entering event queue @ 206044720500. Starting simulation... -info: Entering event queue @ 206044727000. Starting simulation... +info: Entering event queue @ 199044707000. Starting simulation... +info: Entering event queue @ 206044695500. Starting simulation... +info: Entering event queue @ 206044702500. Starting simulation... switching cpus -info: Entering event queue @ 206044727500. Starting simulation... +info: Entering event queue @ 206044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 207044727500. Starting simulation... +info: Entering event queue @ 207044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 208044727500. Starting simulation... +info: Entering event queue @ 208044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 209044727500. Starting simulation... -info: Entering event queue @ 216044720500. Starting simulation... -info: Entering event queue @ 216044727000. Starting simulation... +info: Entering event queue @ 209044707000. Starting simulation... +info: Entering event queue @ 216044694500. Starting simulation... +info: Entering event queue @ 216044701500. Starting simulation... switching cpus -info: Entering event queue @ 216044727500. Starting simulation... +info: Entering event queue @ 216044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 217044727500. Starting simulation... +info: Entering event queue @ 217044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 218044727500. Starting simulation... +info: Entering event queue @ 218044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 219044727500. Starting simulation... -info: Entering event queue @ 226044720500. Starting simulation... -info: Entering event queue @ 226044727000. Starting simulation... +info: Entering event queue @ 219044706000. Starting simulation... +info: Entering event queue @ 226044694500. Starting simulation... +info: Entering event queue @ 226044701500. Starting simulation... switching cpus -info: Entering event queue @ 226044727500. Starting simulation... +info: Entering event queue @ 226044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 227044727500. Starting simulation... +info: Entering event queue @ 227044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 228044727500. Starting simulation... +info: Entering event queue @ 228044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 229044727500. Starting simulation... -info: Entering event queue @ 236044720500. Starting simulation... -info: Entering event queue @ 236044727000. Starting simulation... +info: Entering event queue @ 229044706000. Starting simulation... +info: Entering event queue @ 236044694500. Starting simulation... +info: Entering event queue @ 236044701500. Starting simulation... switching cpus -info: Entering event queue @ 236044727500. Starting simulation... +info: Entering event queue @ 236044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 237044727500. Starting simulation... +info: Entering event queue @ 237044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 238044727500. Starting simulation... +info: Entering event queue @ 238044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 239044727500. Starting simulation... -info: Entering event queue @ 246044720500. Starting simulation... -info: Entering event queue @ 246044727000. Starting simulation... +info: Entering event queue @ 239044706000. Starting simulation... +info: Entering event queue @ 246044694500. Starting simulation... +info: Entering event queue @ 246044701000. Starting simulation... switching cpus -info: Entering event queue @ 246044727500. Starting simulation... +info: Entering event queue @ 246044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 247044727500. Starting simulation... +info: Entering event queue @ 247044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 248044727500. Starting simulation... +info: Entering event queue @ 248044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 249044727500. Starting simulation... -info: Entering event queue @ 256044720500. Starting simulation... -info: Entering event queue @ 256044727000. Starting simulation... +info: Entering event queue @ 249044701500. Starting simulation... +info: Entering event queue @ 256044694500. Starting simulation... +info: Entering event queue @ 256044701500. Starting simulation... switching cpus -info: Entering event queue @ 256044727500. Starting simulation... +info: Entering event queue @ 256044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 257044727500. Starting simulation... +info: Entering event queue @ 257044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 258044727500. Starting simulation... +info: Entering event queue @ 258044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 259044727500. Starting simulation... -info: Entering event queue @ 266044720500. Starting simulation... -info: Entering event queue @ 266847937000. Starting simulation... +info: Entering event queue @ 259044706000. Starting simulation... +info: Entering event queue @ 266044694500. Starting simulation... +info: Entering event queue @ 266911751000. Starting simulation... switching cpus -info: Entering event queue @ 266847939000. Starting simulation... +info: Entering event queue @ 266911753000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 267847939000. Starting simulation... +info: Entering event queue @ 267911753000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 268847939000. Starting simulation... +info: Entering event queue @ 268911753000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 269847939000. Starting simulation... -info: Entering event queue @ 276044720500. Starting simulation... -info: Entering event queue @ 276044727000. Starting simulation... +info: Entering event queue @ 269911753000. Starting simulation... +info: Entering event queue @ 276044694500. Starting simulation... +info: Entering event queue @ 276044701500. Starting simulation... switching cpus -info: Entering event queue @ 276044727500. Starting simulation... +info: Entering event queue @ 276044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 277044727500. Starting simulation... +info: Entering event queue @ 277044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 278044727500. Starting simulation... +info: Entering event queue @ 278044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 279044727500. Starting simulation... -info: Entering event queue @ 286044720500. Starting simulation... -info: Entering event queue @ 286044727000. Starting simulation... +info: Entering event queue @ 279044706000. Starting simulation... +info: Entering event queue @ 286044695500. Starting simulation... +info: Entering event queue @ 286044702500. Starting simulation... switching cpus -info: Entering event queue @ 286044727500. Starting simulation... +info: Entering event queue @ 286044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 287044727500. Starting simulation... +info: Entering event queue @ 287044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 288044727500. Starting simulation... +info: Entering event queue @ 288044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 289044727500. Starting simulation... -info: Entering event queue @ 296044720500. Starting simulation... -info: Entering event queue @ 296044727000. Starting simulation... +info: Entering event queue @ 289044707000. Starting simulation... +info: Entering event queue @ 296044694500. Starting simulation... +info: Entering event queue @ 296044701000. Starting simulation... switching cpus -info: Entering event queue @ 296044727500. Starting simulation... +info: Entering event queue @ 296044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 297044727500. Starting simulation... +info: Entering event queue @ 297044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 298044727500. Starting simulation... -info: Entering event queue @ 299584231000. Starting simulation... +info: Entering event queue @ 298044701500. Starting simulation... +info: Entering event queue @ 299648351000. Starting simulation... switching cpus -info: Entering event queue @ 299584233000. Starting simulation... +info: Entering event queue @ 299648353000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 300584233000. Starting simulation... -info: Entering event queue @ 306044720500. Starting simulation... -info: Entering event queue @ 306044727000. Starting simulation... +info: Entering event queue @ 300648353000. Starting simulation... +info: Entering event queue @ 306044694500. Starting simulation... +info: Entering event queue @ 306044701500. Starting simulation... switching cpus -info: Entering event queue @ 306044727500. Starting simulation... +info: Entering event queue @ 306044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 307044727500. Starting simulation... +info: Entering event queue @ 307044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 308044727500. Starting simulation... +info: Entering event queue @ 308044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 309044727500. Starting simulation... -info: Entering event queue @ 316044720500. Starting simulation... -info: Entering event queue @ 316044727000. Starting simulation... +info: Entering event queue @ 309044706000. Starting simulation... +info: Entering event queue @ 316044694500. Starting simulation... +info: Entering event queue @ 316044701500. Starting simulation... switching cpus -info: Entering event queue @ 316044727500. Starting simulation... +info: Entering event queue @ 316044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 317044727500. Starting simulation... +info: Entering event queue @ 317044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 318044727500. Starting simulation... +info: Entering event queue @ 318044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 319044727500. Starting simulation... -info: Entering event queue @ 326044720500. Starting simulation... -info: Entering event queue @ 326044727000. Starting simulation... +info: Entering event queue @ 319044706000. Starting simulation... +info: Entering event queue @ 326044694500. Starting simulation... +info: Entering event queue @ 326044701500. Starting simulation... switching cpus -info: Entering event queue @ 326044727500. Starting simulation... +info: Entering event queue @ 326044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 327044727500. Starting simulation... +info: Entering event queue @ 327044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 328044727500. Starting simulation... +info: Entering event queue @ 328044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 329044727500. Starting simulation... -info: Entering event queue @ 336044720500. Starting simulation... -info: Entering event queue @ 336044727000. Starting simulation... +info: Entering event queue @ 329044706000. Starting simulation... +info: Entering event queue @ 336044694500. Starting simulation... +info: Entering event queue @ 336044701500. Starting simulation... switching cpus -info: Entering event queue @ 336044727500. Starting simulation... +info: Entering event queue @ 336044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 337044727500. Starting simulation... +info: Entering event queue @ 337044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 338044727500. Starting simulation... +info: Entering event queue @ 338044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 339044727500. Starting simulation... -info: Entering event queue @ 346044720500. Starting simulation... -info: Entering event queue @ 346044727000. Starting simulation... +info: Entering event queue @ 339044706000. Starting simulation... +info: Entering event queue @ 346044694500. Starting simulation... +info: Entering event queue @ 346044701500. Starting simulation... switching cpus -info: Entering event queue @ 346044727500. Starting simulation... +info: Entering event queue @ 346044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 347044727500. Starting simulation... +info: Entering event queue @ 347044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 348044727500. Starting simulation... +info: Entering event queue @ 348044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 349044727500. Starting simulation... -info: Entering event queue @ 356044720500. Starting simulation... -info: Entering event queue @ 356044727000. Starting simulation... +info: Entering event queue @ 349044706000. Starting simulation... +info: Entering event queue @ 356044695500. Starting simulation... +info: Entering event queue @ 356044702500. Starting simulation... switching cpus -info: Entering event queue @ 356044727500. Starting simulation... +info: Entering event queue @ 356044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 357044727500. Starting simulation... +info: Entering event queue @ 357044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 358044727500. Starting simulation... +info: Entering event queue @ 358044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 359044727500. Starting simulation... -info: Entering event queue @ 366044720500. Starting simulation... -info: Entering event queue @ 366044727000. Starting simulation... +info: Entering event queue @ 359044707000. Starting simulation... +info: Entering event queue @ 366044695500. Starting simulation... +info: Entering event queue @ 366044702500. Starting simulation... switching cpus -info: Entering event queue @ 366044727500. Starting simulation... +info: Entering event queue @ 366044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 367044727500. Starting simulation... +info: Entering event queue @ 367044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 368044727500. Starting simulation... +info: Entering event queue @ 368044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 369044727500. Starting simulation... -info: Entering event queue @ 376044720500. Starting simulation... -info: Entering event queue @ 376044727000. Starting simulation... +info: Entering event queue @ 369044707000. Starting simulation... +info: Entering event queue @ 376044695500. Starting simulation... +info: Entering event queue @ 376044703500. Starting simulation... switching cpus -info: Entering event queue @ 376044727500. Starting simulation... +info: Entering event queue @ 376044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 377044727500. Starting simulation... +info: Entering event queue @ 377044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 378044727500. Starting simulation... +info: Entering event queue @ 378044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 379044727500. Starting simulation... -info: Entering event queue @ 386044720500. Starting simulation... -info: Entering event queue @ 386044727000. Starting simulation... +info: Entering event queue @ 379044708000. Starting simulation... +info: Entering event queue @ 386044695500. Starting simulation... +info: Entering event queue @ 386044703500. Starting simulation... switching cpus -info: Entering event queue @ 386044727500. Starting simulation... +info: Entering event queue @ 386044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 387044727500. Starting simulation... +info: Entering event queue @ 387044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 388044727500. Starting simulation... +info: Entering event queue @ 388044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 389044727500. Starting simulation... -info: Entering event queue @ 396044720500. Starting simulation... -info: Entering event queue @ 396044727000. Starting simulation... +info: Entering event queue @ 389044704000. Starting simulation... +info: Entering event queue @ 396044695500. Starting simulation... +info: Entering event queue @ 396044703500. Starting simulation... switching cpus -info: Entering event queue @ 396044727500. Starting simulation... +info: Entering event queue @ 396044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 397044727500. Starting simulation... +info: Entering event queue @ 397044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 398044727500. Starting simulation... +info: Entering event queue @ 398044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 399044727500. Starting simulation... -info: Entering event queue @ 406044720500. Starting simulation... -info: Entering event queue @ 406044727000. Starting simulation... +info: Entering event queue @ 399044708000. Starting simulation... +info: Entering event queue @ 406044694500. Starting simulation... +info: Entering event queue @ 406044701000. Starting simulation... switching cpus -info: Entering event queue @ 406044727500. Starting simulation... +info: Entering event queue @ 406044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 407044727500. Starting simulation... +info: Entering event queue @ 407044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 408044727500. Starting simulation... +info: Entering event queue @ 408044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 409044727500. Starting simulation... -info: Entering event queue @ 416044720500. Starting simulation... -info: Entering event queue @ 416044727000. Starting simulation... +info: Entering event queue @ 409044701500. Starting simulation... +info: Entering event queue @ 416044694500. Starting simulation... +info: Entering event queue @ 416044701500. Starting simulation... switching cpus -info: Entering event queue @ 416044727500. Starting simulation... +info: Entering event queue @ 416044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 417044727500. Starting simulation... +info: Entering event queue @ 417044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 418044727500. Starting simulation... +info: Entering event queue @ 418044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 419044727500. Starting simulation... -info: Entering event queue @ 426044720500. Starting simulation... -info: Entering event queue @ 426044727000. Starting simulation... +info: Entering event queue @ 419044706000. Starting simulation... +info: Entering event queue @ 426044695500. Starting simulation... +info: Entering event queue @ 426044703500. Starting simulation... switching cpus -info: Entering event queue @ 426044727500. Starting simulation... +info: Entering event queue @ 426044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 427044727500. Starting simulation... +info: Entering event queue @ 427044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 428044727500. Starting simulation... +info: Entering event queue @ 428044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 429044727500. Starting simulation... -info: Entering event queue @ 436044720500. Starting simulation... -info: Entering event queue @ 436044727000. Starting simulation... +info: Entering event queue @ 429044708000. Starting simulation... +info: Entering event queue @ 436044694500. Starting simulation... +info: Entering event queue @ 436044701500. Starting simulation... switching cpus -info: Entering event queue @ 436044727500. Starting simulation... +info: Entering event queue @ 436044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 437044727500. Starting simulation... +info: Entering event queue @ 437044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 438044727500. Starting simulation... +info: Entering event queue @ 438044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 439044727500. Starting simulation... -info: Entering event queue @ 446044720500. Starting simulation... -info: Entering event queue @ 446044727000. Starting simulation... +info: Entering event queue @ 439044706000. Starting simulation... +info: Entering event queue @ 446044695500. Starting simulation... +info: Entering event queue @ 446044702500. Starting simulation... switching cpus -info: Entering event queue @ 446044727500. Starting simulation... +info: Entering event queue @ 446044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 447044727500. Starting simulation... +info: Entering event queue @ 447044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 448044727500. Starting simulation... +info: Entering event queue @ 448044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 449044727500. Starting simulation... -info: Entering event queue @ 456044720500. Starting simulation... -info: Entering event queue @ 456044727000. Starting simulation... +info: Entering event queue @ 449044707000. Starting simulation... +info: Entering event queue @ 456044694500. Starting simulation... +info: Entering event queue @ 456044701000. Starting simulation... switching cpus -info: Entering event queue @ 456044727500. Starting simulation... +info: Entering event queue @ 456044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 457044727500. Starting simulation... +info: Entering event queue @ 457044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 458044727500. Starting simulation... +info: Entering event queue @ 458044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 459044727500. Starting simulation... -info: Entering event queue @ 466044720500. Starting simulation... -info: Entering event queue @ 466044727000. Starting simulation... +info: Entering event queue @ 459044701500. Starting simulation... +info: Entering event queue @ 466044694500. Starting simulation... +info: Entering event queue @ 466044701500. Starting simulation... switching cpus -info: Entering event queue @ 466044727500. Starting simulation... +info: Entering event queue @ 466044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 467044727500. Starting simulation... +info: Entering event queue @ 467044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 468044727500. Starting simulation... +info: Entering event queue @ 468044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 469044727500. Starting simulation... -info: Entering event queue @ 476044720500. Starting simulation... -info: Entering event queue @ 476044727000. Starting simulation... +info: Entering event queue @ 469044706000. Starting simulation... +info: Entering event queue @ 476044694500. Starting simulation... +info: Entering event queue @ 476044701500. Starting simulation... switching cpus -info: Entering event queue @ 476044727500. Starting simulation... +info: Entering event queue @ 476044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 477044727500. Starting simulation... +info: Entering event queue @ 477044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 478044727500. Starting simulation... +info: Entering event queue @ 478044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 479044727500. Starting simulation... -info: Entering event queue @ 486044720500. Starting simulation... -info: Entering event queue @ 486044727000. Starting simulation... +info: Entering event queue @ 479044706000. Starting simulation... +info: Entering event queue @ 486044694500. Starting simulation... +info: Entering event queue @ 486044701500. Starting simulation... switching cpus -info: Entering event queue @ 486044727500. Starting simulation... +info: Entering event queue @ 486044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 487044727500. Starting simulation... +info: Entering event queue @ 487044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 488044727500. Starting simulation... +info: Entering event queue @ 488044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 489044727500. Starting simulation... -info: Entering event queue @ 496044720500. Starting simulation... -info: Entering event queue @ 496044727000. Starting simulation... +info: Entering event queue @ 489044706000. Starting simulation... +info: Entering event queue @ 496044694500. Starting simulation... +info: Entering event queue @ 496065726000. Starting simulation... switching cpus -info: Entering event queue @ 496044727500. Starting simulation... +info: Entering event queue @ 496065728000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 497044727500. Starting simulation... +info: Entering event queue @ 497065728000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 498044727500. Starting simulation... +info: Entering event queue @ 498065728000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 499044727500. Starting simulation... -info: Entering event queue @ 506044720500. Starting simulation... -info: Entering event queue @ 506044727000. Starting simulation... +info: Entering event queue @ 499065728000. Starting simulation... +info: Entering event queue @ 506044695500. Starting simulation... +info: Entering event queue @ 506044703500. Starting simulation... switching cpus -info: Entering event queue @ 506044727500. Starting simulation... +info: Entering event queue @ 506044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 507044727500. Starting simulation... +info: Entering event queue @ 507044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 508044727500. Starting simulation... +info: Entering event queue @ 508044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 509044727500. Starting simulation... -info: Entering event queue @ 516044720500. Starting simulation... -info: Entering event queue @ 516044727000. Starting simulation... +info: Entering event queue @ 509044708000. Starting simulation... +info: Entering event queue @ 516044695500. Starting simulation... +info: Entering event queue @ 516044703000. Starting simulation... switching cpus -info: Entering event queue @ 516044727500. Starting simulation... +info: Entering event queue @ 516044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 517044727500. Starting simulation... +info: Entering event queue @ 517044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 518044727500. Starting simulation... +info: Entering event queue @ 518044703500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 519044727500. Starting simulation... -info: Entering event queue @ 526044720500. Starting simulation... -info: Entering event queue @ 526044727000. Starting simulation... +info: Entering event queue @ 519044703500. Starting simulation... switching cpus -info: Entering event queue @ 526044727500. Starting simulation... +info: Entering event queue @ 526044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 527044727500. Starting simulation... +info: Entering event queue @ 527044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 528044727500. Starting simulation... -info: Entering event queue @ 528737989000. Starting simulation... +info: Entering event queue @ 528044695500. Starting simulation... +info: Entering event queue @ 528802326000. Starting simulation... switching cpus -info: Entering event queue @ 528737991000. Starting simulation... +info: Entering event queue @ 528802328000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 529737991000. Starting simulation... -info: Entering event queue @ 536044720500. Starting simulation... -info: Entering event queue @ 536044727000. Starting simulation... +info: Entering event queue @ 529802328000. Starting simulation... switching cpus -info: Entering event queue @ 536044727500. Starting simulation... +info: Entering event queue @ 536044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 537044727500. Starting simulation... +info: Entering event queue @ 537044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 538044727500. Starting simulation... +info: Entering event queue @ 538044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 539044727500. Starting simulation... -info: Entering event queue @ 546044720500. Starting simulation... -info: Entering event queue @ 546044727000. Starting simulation... +info: Entering event queue @ 539044695500. Starting simulation... +info: Entering event queue @ 546044694500. Starting simulation... +info: Entering event queue @ 546044701500. Starting simulation... switching cpus -info: Entering event queue @ 546044727500. Starting simulation... +info: Entering event queue @ 546044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 547044727500. Starting simulation... +info: Entering event queue @ 547044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 548044727500. Starting simulation... +info: Entering event queue @ 548044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 549044727500. Starting simulation... -info: Entering event queue @ 556044720500. Starting simulation... -info: Entering event queue @ 556044727000. Starting simulation... +info: Entering event queue @ 549044706000. Starting simulation... +info: Entering event queue @ 556044695500. Starting simulation... +info: Entering event queue @ 556044703500. Starting simulation... switching cpus -info: Entering event queue @ 556044727500. Starting simulation... +info: Entering event queue @ 556044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 557044727500. Starting simulation... +info: Entering event queue @ 557044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 558044727500. Starting simulation... +info: Entering event queue @ 558044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 559044727500. Starting simulation... -info: Entering event queue @ 566044720500. Starting simulation... -info: Entering event queue @ 566044727000. Starting simulation... +info: Entering event queue @ 559044708000. Starting simulation... +info: Entering event queue @ 566044694500. Starting simulation... +info: Entering event queue @ 566044701000. Starting simulation... switching cpus -info: Entering event queue @ 566044727500. Starting simulation... +info: Entering event queue @ 566044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 567044727500. Starting simulation... +info: Entering event queue @ 567044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 568044727500. Starting simulation... +info: Entering event queue @ 568044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 569044727500. Starting simulation... -info: Entering event queue @ 576044720500. Starting simulation... -info: Entering event queue @ 576044727000. Starting simulation... +info: Entering event queue @ 569044701500. Starting simulation... +info: Entering event queue @ 576044694500. Starting simulation... +info: Entering event queue @ 576044701500. Starting simulation... switching cpus -info: Entering event queue @ 576044727500. Starting simulation... +info: Entering event queue @ 576044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 577044727500. Starting simulation... +info: Entering event queue @ 577044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 578044727500. Starting simulation... +info: Entering event queue @ 578044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 579044727500. Starting simulation... -info: Entering event queue @ 586044720500. Starting simulation... -info: Entering event queue @ 586044727000. Starting simulation... +info: Entering event queue @ 579044706000. Starting simulation... switching cpus -info: Entering event queue @ 586044727500. Starting simulation... +info: Entering event queue @ 586044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 587044727500. Starting simulation... +info: Entering event queue @ 587044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 588044727500. Starting simulation... +info: Entering event queue @ 588044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 589044727500. Starting simulation... -info: Entering event queue @ 596044720500. Starting simulation... -info: Entering event queue @ 596044727000. Starting simulation... +info: Entering event queue @ 589044695500. Starting simulation... switching cpus -info: Entering event queue @ 596044727500. Starting simulation... +info: Entering event queue @ 596044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 597044727500. Starting simulation... +info: Entering event queue @ 597044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 598044727500. Starting simulation... +info: Entering event queue @ 598044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 599044727500. Starting simulation... -info: Entering event queue @ 606044720500. Starting simulation... -info: Entering event queue @ 606044727000. Starting simulation... +info: Entering event queue @ 599044695500. Starting simulation... +info: Entering event queue @ 606044695500. Starting simulation... +info: Entering event queue @ 606044702500. Starting simulation... switching cpus -info: Entering event queue @ 606044727500. Starting simulation... +info: Entering event queue @ 606044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 607044727500. Starting simulation... +info: Entering event queue @ 607044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 608044727500. Starting simulation... +info: Entering event queue @ 608044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 609044727500. Starting simulation... -info: Entering event queue @ 616044720500. Starting simulation... -info: Entering event queue @ 616044727000. Starting simulation... +info: Entering event queue @ 609044707000. Starting simulation... +info: Entering event queue @ 616044694500. Starting simulation... +info: Entering event queue @ 616044701500. Starting simulation... switching cpus -info: Entering event queue @ 616044727500. Starting simulation... +info: Entering event queue @ 616044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 617044727500. Starting simulation... +info: Entering event queue @ 617044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 618044727500. Starting simulation... +info: Entering event queue @ 618044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 619044727500. Starting simulation... -info: Entering event queue @ 626044720500. Starting simulation... -info: Entering event queue @ 626946715000. Starting simulation... +info: Entering event queue @ 619044706000. Starting simulation... +info: Entering event queue @ 626044694500. Starting simulation... +info: Entering event queue @ 627010955000. Starting simulation... switching cpus -info: Entering event queue @ 626946717000. Starting simulation... +info: Entering event queue @ 627010957000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 627946717000. Starting simulation... +info: Entering event queue @ 628010957000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 628946717000. Starting simulation... +info: Entering event queue @ 629010957000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 629946717000. Starting simulation... -info: Entering event queue @ 636044720500. Starting simulation... -info: Entering event queue @ 636044727000. Starting simulation... +info: Entering event queue @ 630010957000. Starting simulation... +info: Entering event queue @ 636044694500. Starting simulation... +info: Entering event queue @ 636044701500. Starting simulation... switching cpus -info: Entering event queue @ 636044727500. Starting simulation... +info: Entering event queue @ 636044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 637044727500. Starting simulation... +info: Entering event queue @ 637044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 638044727500. Starting simulation... +info: Entering event queue @ 638044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 639044727500. Starting simulation... -info: Entering event queue @ 646044720500. Starting simulation... -info: Entering event queue @ 646044727000. Starting simulation... +info: Entering event queue @ 639044706000. Starting simulation... +info: Entering event queue @ 646044694500. Starting simulation... +info: Entering event queue @ 646044701500. Starting simulation... switching cpus -info: Entering event queue @ 646044727500. Starting simulation... +info: Entering event queue @ 646044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 647044727500. Starting simulation... +info: Entering event queue @ 647044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 648044727500. Starting simulation... +info: Entering event queue @ 648044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 649044727500. Starting simulation... -info: Entering event queue @ 656044720500. Starting simulation... -info: Entering event queue @ 656044727000. Starting simulation... +info: Entering event queue @ 649044706000. Starting simulation... +info: Entering event queue @ 656044695500. Starting simulation... +info: Entering event queue @ 656044702500. Starting simulation... switching cpus -info: Entering event queue @ 656044727500. Starting simulation... +info: Entering event queue @ 656044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 657044727500. Starting simulation... +info: Entering event queue @ 657044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 658044727500. Starting simulation... -info: Entering event queue @ 659682856000. Starting simulation... +info: Entering event queue @ 658044707000. Starting simulation... +info: Entering event queue @ 659746543000. Starting simulation... switching cpus -info: Entering event queue @ 659682858000. Starting simulation... +info: Entering event queue @ 659746545000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 660682858000. Starting simulation... -info: Entering event queue @ 666044720500. Starting simulation... -info: Entering event queue @ 666044727000. Starting simulation... +info: Entering event queue @ 660746545000. Starting simulation... +info: Entering event queue @ 666044694500. Starting simulation... +info: Entering event queue @ 666044701500. Starting simulation... switching cpus -info: Entering event queue @ 666044727500. Starting simulation... +info: Entering event queue @ 666044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 667044727500. Starting simulation... +info: Entering event queue @ 667044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 668044727500. Starting simulation... +info: Entering event queue @ 668044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 669044727500. Starting simulation... -info: Entering event queue @ 676044720500. Starting simulation... -info: Entering event queue @ 676044727000. Starting simulation... +info: Entering event queue @ 669044706000. Starting simulation... +info: Entering event queue @ 676044694500. Starting simulation... +info: Entering event queue @ 676044701500. Starting simulation... switching cpus -info: Entering event queue @ 676044727500. Starting simulation... +info: Entering event queue @ 676044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 677044727500. Starting simulation... +info: Entering event queue @ 677044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 678044727500. Starting simulation... +info: Entering event queue @ 678044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 679044727500. Starting simulation... -info: Entering event queue @ 686044720500. Starting simulation... -info: Entering event queue @ 686044727000. Starting simulation... +info: Entering event queue @ 679044706000. Starting simulation... +info: Entering event queue @ 686044694500. Starting simulation... +info: Entering event queue @ 686044701500. Starting simulation... switching cpus -info: Entering event queue @ 686044727500. Starting simulation... +info: Entering event queue @ 686044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 687044727500. Starting simulation... +info: Entering event queue @ 687044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 688044727500. Starting simulation... +info: Entering event queue @ 688044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 689044727500. Starting simulation... -info: Entering event queue @ 696044720500. Starting simulation... -info: Entering event queue @ 696044727000. Starting simulation... +info: Entering event queue @ 689044706000. Starting simulation... +info: Entering event queue @ 696044694500. Starting simulation... +info: Entering event queue @ 696044701500. Starting simulation... switching cpus -info: Entering event queue @ 696044727500. Starting simulation... +info: Entering event queue @ 696044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 697044727500. Starting simulation... +info: Entering event queue @ 697044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 698044727500. Starting simulation... +info: Entering event queue @ 698044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 699044727500. Starting simulation... -info: Entering event queue @ 706044720500. Starting simulation... -info: Entering event queue @ 706044727000. Starting simulation... +info: Entering event queue @ 699044706000. Starting simulation... +info: Entering event queue @ 706044695500. Starting simulation... +info: Entering event queue @ 706044702500. Starting simulation... switching cpus -info: Entering event queue @ 706044727500. Starting simulation... +info: Entering event queue @ 706044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 707044727500. Starting simulation... +info: Entering event queue @ 707044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 708044727500. Starting simulation... +info: Entering event queue @ 708044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 709044727500. Starting simulation... -info: Entering event queue @ 716044720500. Starting simulation... -info: Entering event queue @ 716044727000. Starting simulation... +info: Entering event queue @ 709044707000. Starting simulation... +info: Entering event queue @ 716044694500. Starting simulation... +info: Entering event queue @ 716044701500. Starting simulation... switching cpus -info: Entering event queue @ 716044727500. Starting simulation... +info: Entering event queue @ 716044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 717044727500. Starting simulation... +info: Entering event queue @ 717044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 718044727500. Starting simulation... +info: Entering event queue @ 718044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 719044727500. Starting simulation... -info: Entering event queue @ 726044720500. Starting simulation... -info: Entering event queue @ 726044727000. Starting simulation... +info: Entering event queue @ 719044706000. Starting simulation... +info: Entering event queue @ 726044694500. Starting simulation... +info: Entering event queue @ 726044701500. Starting simulation... switching cpus -info: Entering event queue @ 726044727500. Starting simulation... +info: Entering event queue @ 726044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 727044727500. Starting simulation... +info: Entering event queue @ 727044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 728044727500. Starting simulation... +info: Entering event queue @ 728044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 729044727500. Starting simulation... -info: Entering event queue @ 736044720500. Starting simulation... -info: Entering event queue @ 736044727000. Starting simulation... +info: Entering event queue @ 729044706000. Starting simulation... +info: Entering event queue @ 736044694500. Starting simulation... +info: Entering event queue @ 736044701000. Starting simulation... switching cpus -info: Entering event queue @ 736044727500. Starting simulation... +info: Entering event queue @ 736044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 737044727500. Starting simulation... +info: Entering event queue @ 737044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 738044727500. Starting simulation... +info: Entering event queue @ 738044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 739044727500. Starting simulation... -info: Entering event queue @ 746044720500. Starting simulation... -info: Entering event queue @ 746044727000. Starting simulation... +info: Entering event queue @ 739044701500. Starting simulation... +info: Entering event queue @ 746044694500. Starting simulation... +info: Entering event queue @ 746044701500. Starting simulation... switching cpus -info: Entering event queue @ 746044727500. Starting simulation... +info: Entering event queue @ 746044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 747044727500. Starting simulation... +info: Entering event queue @ 747044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 748044727500. Starting simulation... +info: Entering event queue @ 748044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 749044727500. Starting simulation... -info: Entering event queue @ 756044720500. Starting simulation... -info: Entering event queue @ 756044727000. Starting simulation... +info: Entering event queue @ 749044706000. Starting simulation... +info: Entering event queue @ 756044694500. Starting simulation... +info: Entering event queue @ 756044701500. Starting simulation... switching cpus -info: Entering event queue @ 756044727500. Starting simulation... +info: Entering event queue @ 756044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 757044727500. Starting simulation... +info: Entering event queue @ 757044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 758044727500. Starting simulation... +info: Entering event queue @ 758044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 759044727500. Starting simulation... -info: Entering event queue @ 766044720500. Starting simulation... -info: Entering event queue @ 766044727000. Starting simulation... +info: Entering event queue @ 759044706000. Starting simulation... +info: Entering event queue @ 766044695500. Starting simulation... +info: Entering event queue @ 766044762000. Starting simulation... switching cpus -info: Entering event queue @ 766044727500. Starting simulation... +info: Entering event queue @ 766044766500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 767044727500. Starting simulation... +info: Entering event queue @ 767044766500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 768044727500. Starting simulation... +info: Entering event queue @ 768044766500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 769044727500. Starting simulation... -info: Entering event queue @ 776044720500. Starting simulation... -info: Entering event queue @ 776044727000. Starting simulation... +info: Entering event queue @ 769044766500. Starting simulation... +info: Entering event queue @ 776044694500. Starting simulation... +info: Entering event queue @ 776044701500. Starting simulation... switching cpus -info: Entering event queue @ 776044727500. Starting simulation... +info: Entering event queue @ 776044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 777044727500. Starting simulation... +info: Entering event queue @ 777044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 778044727500. Starting simulation... +info: Entering event queue @ 778044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 779044727500. Starting simulation... -info: Entering event queue @ 786044720500. Starting simulation... -info: Entering event queue @ 786044727000. Starting simulation... +info: Entering event queue @ 779044706000. Starting simulation... +info: Entering event queue @ 786044694500. Starting simulation... +info: Entering event queue @ 786044701000. Starting simulation... switching cpus -info: Entering event queue @ 786044727500. Starting simulation... +info: Entering event queue @ 786044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 787044727500. Starting simulation... +info: Entering event queue @ 787044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 788044727500. Starting simulation... +info: Entering event queue @ 788044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 789044727500. Starting simulation... -info: Entering event queue @ 796044720500. Starting simulation... -info: Entering event queue @ 796044727000. Starting simulation... +info: Entering event queue @ 789044701500. Starting simulation... +info: Entering event queue @ 796044694500. Starting simulation... +info: Entering event queue @ 796044701500. Starting simulation... switching cpus -info: Entering event queue @ 796044727500. Starting simulation... +info: Entering event queue @ 796044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 797044727500. Starting simulation... +info: Entering event queue @ 797044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 798044727500. Starting simulation... +info: Entering event queue @ 798044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 799044727500. Starting simulation... -info: Entering event queue @ 806044720500. Starting simulation... -info: Entering event queue @ 806044727000. Starting simulation... +info: Entering event queue @ 799044706000. Starting simulation... +info: Entering event queue @ 806044694500. Starting simulation... +info: Entering event queue @ 806044701500. Starting simulation... switching cpus -info: Entering event queue @ 806044727500. Starting simulation... +info: Entering event queue @ 806044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 807044727500. Starting simulation... +info: Entering event queue @ 807044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 808044727500. Starting simulation... +info: Entering event queue @ 808044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 809044727500. Starting simulation... -info: Entering event queue @ 816044720500. Starting simulation... -info: Entering event queue @ 816044727000. Starting simulation... +info: Entering event queue @ 809044706000. Starting simulation... +info: Entering event queue @ 816044694500. Starting simulation... +info: Entering event queue @ 816044701500. Starting simulation... switching cpus -info: Entering event queue @ 816044727500. Starting simulation... +info: Entering event queue @ 816044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 817044727500. Starting simulation... +info: Entering event queue @ 817044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 818044727500. Starting simulation... +info: Entering event queue @ 818044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 819044727500. Starting simulation... -info: Entering event queue @ 826044720500. Starting simulation... -info: Entering event queue @ 826044727000. Starting simulation... +info: Entering event queue @ 819044706000. Starting simulation... +info: Entering event queue @ 826044694500. Starting simulation... +info: Entering event queue @ 826044701500. Starting simulation... switching cpus -info: Entering event queue @ 826044727500. Starting simulation... +info: Entering event queue @ 826044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 827044727500. Starting simulation... +info: Entering event queue @ 827044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 828044727500. Starting simulation... +info: Entering event queue @ 828044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 829044727500. Starting simulation... -info: Entering event queue @ 836044720500. Starting simulation... -info: Entering event queue @ 836044727000. Starting simulation... +info: Entering event queue @ 829044706000. Starting simulation... +info: Entering event queue @ 836044695500. Starting simulation... +info: Entering event queue @ 836044702500. Starting simulation... switching cpus -info: Entering event queue @ 836044727500. Starting simulation... +info: Entering event queue @ 836044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 837044727500. Starting simulation... +info: Entering event queue @ 837044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 838044727500. Starting simulation... +info: Entering event queue @ 838044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 839044727500. Starting simulation... -info: Entering event queue @ 846044720500. Starting simulation... -info: Entering event queue @ 846044727000. Starting simulation... +info: Entering event queue @ 839044707000. Starting simulation... +info: Entering event queue @ 846044695500. Starting simulation... +info: Entering event queue @ 846044703000. Starting simulation... switching cpus -info: Entering event queue @ 846044727500. Starting simulation... +info: Entering event queue @ 846044707500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 847044727500. Starting simulation... +info: Entering event queue @ 847044707500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 848044727500. Starting simulation... +info: Entering event queue @ 848044707500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 849044727500. Starting simulation... -info: Entering event queue @ 856044720500. Starting simulation... -info: Entering event queue @ 856100473000. Starting simulation... +info: Entering event queue @ 849044707500. Starting simulation... +info: Entering event queue @ 856044694500. Starting simulation... +info: Entering event queue @ 856163939000. Starting simulation... switching cpus -info: Entering event queue @ 856100475000. Starting simulation... +info: Entering event queue @ 856163941000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 857100475000. Starting simulation... +info: Entering event queue @ 857163941000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 858100475000. Starting simulation... +info: Entering event queue @ 858163941000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 859100475000. Starting simulation... -info: Entering event queue @ 866044720500. Starting simulation... -info: Entering event queue @ 866044727000. Starting simulation... +info: Entering event queue @ 859163941000. Starting simulation... +info: Entering event queue @ 866044695500. Starting simulation... +info: Entering event queue @ 866044702500. Starting simulation... switching cpus -info: Entering event queue @ 866044727500. Starting simulation... +info: Entering event queue @ 866044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 867044727500. Starting simulation... +info: Entering event queue @ 867044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 868044727500. Starting simulation... +info: Entering event queue @ 868044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 869044727500. Starting simulation... -info: Entering event queue @ 876044720500. Starting simulation... -info: Entering event queue @ 876044727000. Starting simulation... +info: Entering event queue @ 869044707000. Starting simulation... +info: Entering event queue @ 876044694500. Starting simulation... +info: Entering event queue @ 876044701500. Starting simulation... switching cpus -info: Entering event queue @ 876044727500. Starting simulation... +info: Entering event queue @ 876044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 877044727500. Starting simulation... +info: Entering event queue @ 877044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 878044727500. Starting simulation... +info: Entering event queue @ 878044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 879044727500. Starting simulation... -info: Entering event queue @ 886044720500. Starting simulation... -info: Entering event queue @ 886044727000. Starting simulation... +info: Entering event queue @ 879044706000. Starting simulation... +info: Entering event queue @ 886044695500. Starting simulation... +info: Entering event queue @ 886044703500. Starting simulation... switching cpus -info: Entering event queue @ 886044727500. Starting simulation... +info: Entering event queue @ 886044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 887044727500. Starting simulation... +info: Entering event queue @ 887044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 888044727500. Starting simulation... -info: Entering event queue @ 888837073000. Starting simulation... +info: Entering event queue @ 888044708000. Starting simulation... +info: Entering event queue @ 888900518000. Starting simulation... switching cpus -info: Entering event queue @ 888837075000. Starting simulation... +info: Entering event queue @ 888900520000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 889837075000. Starting simulation... -info: Entering event queue @ 896044720500. Starting simulation... -info: Entering event queue @ 896044727000. Starting simulation... +info: Entering event queue @ 889900520000. Starting simulation... +info: Entering event queue @ 896044694500. Starting simulation... +info: Entering event queue @ 896044701000. Starting simulation... switching cpus -info: Entering event queue @ 896044727500. Starting simulation... +info: Entering event queue @ 896044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 897044727500. Starting simulation... +info: Entering event queue @ 897044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 898044727500. Starting simulation... +info: Entering event queue @ 898044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 899044727500. Starting simulation... -info: Entering event queue @ 906044720500. Starting simulation... -info: Entering event queue @ 906044727000. Starting simulation... +info: Entering event queue @ 899044701500. Starting simulation... +info: Entering event queue @ 906044694500. Starting simulation... +info: Entering event queue @ 906044701500. Starting simulation... switching cpus -info: Entering event queue @ 906044727500. Starting simulation... +info: Entering event queue @ 906044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 907044727500. Starting simulation... +info: Entering event queue @ 907044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 908044727500. Starting simulation... +info: Entering event queue @ 908044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 909044727500. Starting simulation... -info: Entering event queue @ 916044720500. Starting simulation... -info: Entering event queue @ 916044727000. Starting simulation... +info: Entering event queue @ 909044706000. Starting simulation... +info: Entering event queue @ 916044694500. Starting simulation... +info: Entering event queue @ 916044701500. Starting simulation... switching cpus -info: Entering event queue @ 916044727500. Starting simulation... +info: Entering event queue @ 916044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 917044727500. Starting simulation... +info: Entering event queue @ 917044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 918044727500. Starting simulation... +info: Entering event queue @ 918044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 919044727500. Starting simulation... -info: Entering event queue @ 926044720500. Starting simulation... -info: Entering event queue @ 926044727000. Starting simulation... +info: Entering event queue @ 919044706000. Starting simulation... +info: Entering event queue @ 926044695500. Starting simulation... +info: Entering event queue @ 926044703500. Starting simulation... switching cpus -info: Entering event queue @ 926044727500. Starting simulation... +info: Entering event queue @ 926044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 927044727500. Starting simulation... +info: Entering event queue @ 927044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 928044727500. Starting simulation... +info: Entering event queue @ 928044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 929044727500. Starting simulation... -info: Entering event queue @ 936044720500. Starting simulation... -info: Entering event queue @ 936044727000. Starting simulation... +info: Entering event queue @ 929044708000. Starting simulation... +info: Entering event queue @ 936044694500. Starting simulation... +info: Entering event queue @ 936044701500. Starting simulation... switching cpus -info: Entering event queue @ 936044727500. Starting simulation... +info: Entering event queue @ 936044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 937044727500. Starting simulation... +info: Entering event queue @ 937044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 938044727500. Starting simulation... +info: Entering event queue @ 938044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 939044727500. Starting simulation... -info: Entering event queue @ 946044720500. Starting simulation... -info: Entering event queue @ 946044727000. Starting simulation... +info: Entering event queue @ 939044706000. Starting simulation... +info: Entering event queue @ 946044694500. Starting simulation... +info: Entering event queue @ 946044701000. Starting simulation... switching cpus -info: Entering event queue @ 946044727500. Starting simulation... +info: Entering event queue @ 946044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 947044727500. Starting simulation... +info: Entering event queue @ 947044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 948044727500. Starting simulation... +info: Entering event queue @ 948044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 949044727500. Starting simulation... -info: Entering event queue @ 956044720500. Starting simulation... -info: Entering event queue @ 956044727000. Starting simulation... +info: Entering event queue @ 949044701500. Starting simulation... +info: Entering event queue @ 956044694500. Starting simulation... +info: Entering event queue @ 956044701500. Starting simulation... switching cpus -info: Entering event queue @ 956044727500. Starting simulation... +info: Entering event queue @ 956044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 957044727500. Starting simulation... +info: Entering event queue @ 957044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 958044727500. Starting simulation... +info: Entering event queue @ 958044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 959044727500. Starting simulation... -info: Entering event queue @ 966044720500. Starting simulation... -info: Entering event queue @ 966044727000. Starting simulation... +info: Entering event queue @ 959044706000. Starting simulation... +info: Entering event queue @ 966044695500. Starting simulation... +info: Entering event queue @ 966044703500. Starting simulation... switching cpus -info: Entering event queue @ 966044727500. Starting simulation... +info: Entering event queue @ 966044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 967044727500. Starting simulation... +info: Entering event queue @ 967044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 968044727500. Starting simulation... +info: Entering event queue @ 968044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 969044727500. Starting simulation... -info: Entering event queue @ 976044720500. Starting simulation... -info: Entering event queue @ 976044727000. Starting simulation... +info: Entering event queue @ 969044704000. Starting simulation... +info: Entering event queue @ 976044695500. Starting simulation... +info: Entering event queue @ 976044703500. Starting simulation... switching cpus -info: Entering event queue @ 976044727500. Starting simulation... +info: Entering event queue @ 976044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 977044727500. Starting simulation... +info: Entering event queue @ 977044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 978044727500. Starting simulation... +info: Entering event queue @ 978044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 979044727500. Starting simulation... -info: Entering event queue @ 986044720500. Starting simulation... -info: Entering event queue @ 987045796000. Starting simulation... +info: Entering event queue @ 979044704000. Starting simulation... +info: Entering event queue @ 986044694500. Starting simulation... +info: Entering event queue @ 987109151000. Starting simulation... switching cpus -info: Entering event queue @ 987045798000. Starting simulation... +info: Entering event queue @ 987109153000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 988045798000. Starting simulation... +info: Entering event queue @ 988109153000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 989045798000. Starting simulation... +info: Entering event queue @ 989109153000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 990045798000. Starting simulation... -info: Entering event queue @ 996044720500. Starting simulation... -info: Entering event queue @ 996044727000. Starting simulation... +info: Entering event queue @ 990109153000. Starting simulation... +info: Entering event queue @ 996044695500. Starting simulation... +info: Entering event queue @ 996044702500. Starting simulation... switching cpus -info: Entering event queue @ 996044727500. Starting simulation... +info: Entering event queue @ 996044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 997044727500. Starting simulation... +info: Entering event queue @ 997044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 998044727500. Starting simulation... +info: Entering event queue @ 998044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 999044727500. Starting simulation... -info: Entering event queue @ 1006044720500. Starting simulation... -info: Entering event queue @ 1006044727000. Starting simulation... +info: Entering event queue @ 999044707000. Starting simulation... switching cpus -info: Entering event queue @ 1006044727500. Starting simulation... +info: Entering event queue @ 1006044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1007044727500. Starting simulation... +info: Entering event queue @ 1007044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1008044727500. Starting simulation... +info: Entering event queue @ 1008044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1009044727500. Starting simulation... -info: Entering event queue @ 1016044720500. Starting simulation... -info: Entering event queue @ 1016044727000. Starting simulation... +info: Entering event queue @ 1009044695500. Starting simulation... +info: Entering event queue @ 1016044694500. Starting simulation... +info: Entering event queue @ 1016044701500. Starting simulation... switching cpus -info: Entering event queue @ 1016044727500. Starting simulation... +info: Entering event queue @ 1016044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1017044727500. Starting simulation... +info: Entering event queue @ 1017044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1018044727500. Starting simulation... +info: Entering event queue @ 1018044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1019044727500. Starting simulation... -info: Entering event queue @ 1026044720500. Starting simulation... -info: Entering event queue @ 1026044727000. Starting simulation... +info: Entering event queue @ 1019044706000. Starting simulation... +info: Entering event queue @ 1026044695500. Starting simulation... +info: Entering event queue @ 1026044703500. Starting simulation... switching cpus -info: Entering event queue @ 1026044727500. Starting simulation... +info: Entering event queue @ 1026044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1027044727500. Starting simulation... +info: Entering event queue @ 1027044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1028044727500. Starting simulation... +info: Entering event queue @ 1028044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1029044727500. Starting simulation... -info: Entering event queue @ 1036044720500. Starting simulation... -info: Entering event queue @ 1036044727000. Starting simulation... +info: Entering event queue @ 1029044708000. Starting simulation... switching cpus -info: Entering event queue @ 1036044727500. Starting simulation... +info: Entering event queue @ 1036044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1037044727500. Starting simulation... +info: Entering event queue @ 1037044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1038044727500. Starting simulation... +info: Entering event queue @ 1038044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1039044727500. Starting simulation... -info: Entering event queue @ 1046044720500. Starting simulation... -info: Entering event queue @ 1046044727000. Starting simulation... +info: Entering event queue @ 1039044695500. Starting simulation... +info: Entering event queue @ 1046044694500. Starting simulation... +info: Entering event queue @ 1046044701500. Starting simulation... switching cpus -info: Entering event queue @ 1046044727500. Starting simulation... +info: Entering event queue @ 1046044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1047044727500. Starting simulation... +info: Entering event queue @ 1047044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1048044727500. Starting simulation... +info: Entering event queue @ 1048044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1049044727500. Starting simulation... -info: Entering event queue @ 1056044720500. Starting simulation... -info: Entering event queue @ 1056044727000. Starting simulation... +info: Entering event queue @ 1049044706000. Starting simulation... +info: Entering event queue @ 1056044694500. Starting simulation... +info: Entering event queue @ 1056044701500. Starting simulation... switching cpus -info: Entering event queue @ 1056044727500. Starting simulation... +info: Entering event queue @ 1056044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1057044727500. Starting simulation... +info: Entering event queue @ 1057044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1058044727500. Starting simulation... +info: Entering event queue @ 1058044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1059044727500. Starting simulation... -info: Entering event queue @ 1066044720500. Starting simulation... -info: Entering event queue @ 1066044727000. Starting simulation... +info: Entering event queue @ 1059044706000. Starting simulation... +info: Entering event queue @ 1066044694500. Starting simulation... +info: Entering event queue @ 1066044701000. Starting simulation... switching cpus -info: Entering event queue @ 1066044727500. Starting simulation... +info: Entering event queue @ 1066044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1067044727500. Starting simulation... +info: Entering event queue @ 1067044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1068044727500. Starting simulation... +info: Entering event queue @ 1068044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1069044727500. Starting simulation... -info: Entering event queue @ 1076044720500. Starting simulation... -info: Entering event queue @ 1076044727000. Starting simulation... +info: Entering event queue @ 1069044701500. Starting simulation... +info: Entering event queue @ 1076044694500. Starting simulation... +info: Entering event queue @ 1076044701500. Starting simulation... switching cpus -info: Entering event queue @ 1076044727500. Starting simulation... +info: Entering event queue @ 1076044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1077044727500. Starting simulation... +info: Entering event queue @ 1077044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1078044727500. Starting simulation... +info: Entering event queue @ 1078044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1079044727500. Starting simulation... -info: Entering event queue @ 1086044720500. Starting simulation... -info: Entering event queue @ 1086044727000. Starting simulation... +info: Entering event queue @ 1079044706000. Starting simulation... +info: Entering event queue @ 1086044694500. Starting simulation... +info: Entering event queue @ 1086044701500. Starting simulation... switching cpus -info: Entering event queue @ 1086044727500. Starting simulation... +info: Entering event queue @ 1086044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1087044727500. Starting simulation... +info: Entering event queue @ 1087044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1088044727500. Starting simulation... +info: Entering event queue @ 1088044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1089044727500. Starting simulation... -info: Entering event queue @ 1096044720500. Starting simulation... -info: Entering event queue @ 1096044727000. Starting simulation... +info: Entering event queue @ 1089044706000. Starting simulation... +info: Entering event queue @ 1096044695500. Starting simulation... +info: Entering event queue @ 1096044703500. Starting simulation... switching cpus -info: Entering event queue @ 1096044727500. Starting simulation... +info: Entering event queue @ 1096044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1097044727500. Starting simulation... +info: Entering event queue @ 1097044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1098044727500. Starting simulation... +info: Entering event queue @ 1098044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1099044727500. Starting simulation... -info: Entering event queue @ 1106044720500. Starting simulation... -info: Entering event queue @ 1106044727000. Starting simulation... +info: Entering event queue @ 1099044708000. Starting simulation... +info: Entering event queue @ 1106044694500. Starting simulation... +info: Entering event queue @ 1106044701500. Starting simulation... switching cpus -info: Entering event queue @ 1106044727500. Starting simulation... +info: Entering event queue @ 1106044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1107044727500. Starting simulation... +info: Entering event queue @ 1107044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1108044727500. Starting simulation... +info: Entering event queue @ 1108044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1109044727500. Starting simulation... -info: Entering event queue @ 1116044720500. Starting simulation... -info: Entering event queue @ 1116044727000. Starting simulation... +info: Entering event queue @ 1109044706000. Starting simulation... +info: Entering event queue @ 1116044694500. Starting simulation... +info: Entering event queue @ 1116044701000. Starting simulation... switching cpus -info: Entering event queue @ 1116044727500. Starting simulation... +info: Entering event queue @ 1116044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1117044727500. Starting simulation... +info: Entering event queue @ 1117044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1118044727500. Starting simulation... +info: Entering event queue @ 1118044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1119044727500. Starting simulation... -info: Entering event queue @ 1126044720500. Starting simulation... -info: Entering event queue @ 1126044727000. Starting simulation... +info: Entering event queue @ 1119044701500. Starting simulation... +info: Entering event queue @ 1126044694500. Starting simulation... +info: Entering event queue @ 1126044701500. Starting simulation... switching cpus -info: Entering event queue @ 1126044727500. Starting simulation... +info: Entering event queue @ 1126044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1127044727500. Starting simulation... +info: Entering event queue @ 1127044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1128044727500. Starting simulation... +info: Entering event queue @ 1128044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1129044727500. Starting simulation... -info: Entering event queue @ 1136044720500. Starting simulation... -info: Entering event queue @ 1136044727000. Starting simulation... +info: Entering event queue @ 1129044706000. Starting simulation... +info: Entering event queue @ 1136044695500. Starting simulation... +info: Entering event queue @ 1136044702500. Starting simulation... switching cpus -info: Entering event queue @ 1136044727500. Starting simulation... +info: Entering event queue @ 1136044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1137044727500. Starting simulation... +info: Entering event queue @ 1137044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1138044727500. Starting simulation... +info: Entering event queue @ 1138044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1139044727500. Starting simulation... -info: Entering event queue @ 1146044720500. Starting simulation... -info: Entering event queue @ 1146044727000. Starting simulation... +info: Entering event queue @ 1139044707000. Starting simulation... +info: Entering event queue @ 1146044694500. Starting simulation... +info: Entering event queue @ 1146044701500. Starting simulation... switching cpus -info: Entering event queue @ 1146044727500. Starting simulation... +info: Entering event queue @ 1146044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1147044727500. Starting simulation... +info: Entering event queue @ 1147044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1148044727500. Starting simulation... +info: Entering event queue @ 1148044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1149044727500. Starting simulation... -info: Entering event queue @ 1156044720500. Starting simulation... -info: Entering event queue @ 1156044727000. Starting simulation... +info: Entering event queue @ 1149044706000. Starting simulation... +info: Entering event queue @ 1156044694500. Starting simulation... +info: Entering event queue @ 1156044701500. Starting simulation... switching cpus -info: Entering event queue @ 1156044727500. Starting simulation... +info: Entering event queue @ 1156044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1157044727500. Starting simulation... +info: Entering event queue @ 1157044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1158044727500. Starting simulation... +info: Entering event queue @ 1158044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1159044727500. Starting simulation... -info: Entering event queue @ 1166044720500. Starting simulation... -info: Entering event queue @ 1166044727000. Starting simulation... +info: Entering event queue @ 1159044706000. Starting simulation... +info: Entering event queue @ 1166044695500. Starting simulation... +info: Entering event queue @ 1166044704000. Starting simulation... switching cpus -info: Entering event queue @ 1166044727500. Starting simulation... +info: Entering event queue @ 1166044708500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1167044727500. Starting simulation... +info: Entering event queue @ 1167044708500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1168044727500. Starting simulation... +info: Entering event queue @ 1168044708500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1169044727500. Starting simulation... -info: Entering event queue @ 1176044720500. Starting simulation... -info: Entering event queue @ 1176044727000. Starting simulation... +info: Entering event queue @ 1169044708500. Starting simulation... switching cpus -info: Entering event queue @ 1176044727500. Starting simulation... +info: Entering event queue @ 1176044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1177044727500. Starting simulation... +info: Entering event queue @ 1177044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1178044727500. Starting simulation... +info: Entering event queue @ 1178044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1179044727500. Starting simulation... -info: Entering event queue @ 1186044720500. Starting simulation... -info: Entering event queue @ 1186044727000. Starting simulation... +info: Entering event queue @ 1179044695500. Starting simulation... switching cpus -info: Entering event queue @ 1186044727500. Starting simulation... +info: Entering event queue @ 1186044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1187044727500. Starting simulation... +info: Entering event queue @ 1187044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1188044727500. Starting simulation... +info: Entering event queue @ 1188044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1189044727500. Starting simulation... -info: Entering event queue @ 1196044720500. Starting simulation... -info: Entering event queue @ 1196044727000. Starting simulation... +info: Entering event queue @ 1189044695500. Starting simulation... switching cpus -info: Entering event queue @ 1196044727500. Starting simulation... +info: Entering event queue @ 1196044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1197044727500. Starting simulation... +info: Entering event queue @ 1197044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1198044727500. Starting simulation... +info: Entering event queue @ 1198044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1199044727500. Starting simulation... -info: Entering event queue @ 1206044720500. Starting simulation... -info: Entering event queue @ 1206044727000. Starting simulation... +info: Entering event queue @ 1199044695500. Starting simulation... +info: Entering event queue @ 1206044694500. Starting simulation... +info: Entering event queue @ 1206044701500. Starting simulation... switching cpus -info: Entering event queue @ 1206044727500. Starting simulation... +info: Entering event queue @ 1206044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1207044727500. Starting simulation... +info: Entering event queue @ 1207044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1208044727500. Starting simulation... +info: Entering event queue @ 1208044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1209044727500. Starting simulation... -info: Entering event queue @ 1216044720500. Starting simulation... -info: Entering event queue @ 1216199554000. Starting simulation... +info: Entering event queue @ 1209044706000. Starting simulation... +info: Entering event queue @ 1216044695500. Starting simulation... +info: Entering event queue @ 1216263126000. Starting simulation... switching cpus -info: Entering event queue @ 1216199556000. Starting simulation... +info: Entering event queue @ 1216263128000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1217199556000. Starting simulation... +info: Entering event queue @ 1217263128000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1218199556000. Starting simulation... +info: Entering event queue @ 1218263128000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1219199556000. Starting simulation... -info: Entering event queue @ 1226044720500. Starting simulation... -info: Entering event queue @ 1226044727000. Starting simulation... +info: Entering event queue @ 1219263128000. Starting simulation... +info: Entering event queue @ 1226044694500. Starting simulation... +info: Entering event queue @ 1226044701000. Starting simulation... switching cpus -info: Entering event queue @ 1226044727500. Starting simulation... +info: Entering event queue @ 1226044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1227044727500. Starting simulation... +info: Entering event queue @ 1227044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1228044727500. Starting simulation... +info: Entering event queue @ 1228044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1229044727500. Starting simulation... -info: Entering event queue @ 1236044720500. Starting simulation... -info: Entering event queue @ 1236044727000. Starting simulation... +info: Entering event queue @ 1229044701500. Starting simulation... +info: Entering event queue @ 1236044694500. Starting simulation... +info: Entering event queue @ 1236044701500. Starting simulation... switching cpus -info: Entering event queue @ 1236044727500. Starting simulation... +info: Entering event queue @ 1236044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1237044727500. Starting simulation... +info: Entering event queue @ 1237044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1238044727500. Starting simulation... +info: Entering event queue @ 1238044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1239044727500. Starting simulation... -info: Entering event queue @ 1246044720500. Starting simulation... -info: Entering event queue @ 1246044727000. Starting simulation... +info: Entering event queue @ 1239044706000. Starting simulation... +info: Entering event queue @ 1246044694500. Starting simulation... +info: Entering event queue @ 1246044701500. Starting simulation... switching cpus -info: Entering event queue @ 1246044727500. Starting simulation... +info: Entering event queue @ 1246044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1247044727500. Starting simulation... +info: Entering event queue @ 1247044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1248044727500. Starting simulation... -info: Entering event queue @ 1248935845000. Starting simulation... +info: Entering event queue @ 1248044706000. Starting simulation... +info: Entering event queue @ 1248999726000. Starting simulation... switching cpus -info: Entering event queue @ 1248935847000. Starting simulation... +info: Entering event queue @ 1248999728000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1249935847000. Starting simulation... -info: Entering event queue @ 1256044720500. Starting simulation... -info: Entering event queue @ 1256044727000. Starting simulation... +info: Entering event queue @ 1249999728000. Starting simulation... +info: Entering event queue @ 1256044695500. Starting simulation... +info: Entering event queue @ 1256044703500. Starting simulation... switching cpus -info: Entering event queue @ 1256044727500. Starting simulation... +info: Entering event queue @ 1256044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1257044727500. Starting simulation... +info: Entering event queue @ 1257044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1258044727500. Starting simulation... +info: Entering event queue @ 1258044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1259044727500. Starting simulation... -info: Entering event queue @ 1266044720500. Starting simulation... -info: Entering event queue @ 1266044727000. Starting simulation... +info: Entering event queue @ 1259044708000. Starting simulation... +info: Entering event queue @ 1266044694500. Starting simulation... +info: Entering event queue @ 1266044701500. Starting simulation... switching cpus -info: Entering event queue @ 1266044727500. Starting simulation... +info: Entering event queue @ 1266044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1267044727500. Starting simulation... +info: Entering event queue @ 1267044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1268044727500. Starting simulation... +info: Entering event queue @ 1268044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1269044727500. Starting simulation... -info: Entering event queue @ 1276044720500. Starting simulation... -info: Entering event queue @ 1276044727000. Starting simulation... +info: Entering event queue @ 1269044706000. Starting simulation... +info: Entering event queue @ 1276044694500. Starting simulation... +info: Entering event queue @ 1276044701000. Starting simulation... switching cpus -info: Entering event queue @ 1276044727500. Starting simulation... +info: Entering event queue @ 1276044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1277044727500. Starting simulation... +info: Entering event queue @ 1277044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1278044727500. Starting simulation... +info: Entering event queue @ 1278044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1279044727500. Starting simulation... -info: Entering event queue @ 1286044720500. Starting simulation... -info: Entering event queue @ 1286044727000. Starting simulation... +info: Entering event queue @ 1279044701500. Starting simulation... +info: Entering event queue @ 1286044694500. Starting simulation... +info: Entering event queue @ 1286044701500. Starting simulation... switching cpus -info: Entering event queue @ 1286044727500. Starting simulation... +info: Entering event queue @ 1286044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1287044727500. Starting simulation... +info: Entering event queue @ 1287044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1288044727500. Starting simulation... +info: Entering event queue @ 1288044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1289044727500. Starting simulation... -info: Entering event queue @ 1296044720500. Starting simulation... -info: Entering event queue @ 1296044727000. Starting simulation... +info: Entering event queue @ 1289044706000. Starting simulation... +info: Entering event queue @ 1296044695500. Starting simulation... +info: Entering event queue @ 1296044702500. Starting simulation... switching cpus -info: Entering event queue @ 1296044727500. Starting simulation... +info: Entering event queue @ 1296044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1297044727500. Starting simulation... +info: Entering event queue @ 1297044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1298044727500. Starting simulation... +info: Entering event queue @ 1298044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1299044727500. Starting simulation... -info: Entering event queue @ 1306044720500. Starting simulation... -info: Entering event queue @ 1306044727000. Starting simulation... +info: Entering event queue @ 1299044707000. Starting simulation... +info: Entering event queue @ 1306044694500. Starting simulation... +info: Entering event queue @ 1306044701500. Starting simulation... switching cpus -info: Entering event queue @ 1306044727500. Starting simulation... +info: Entering event queue @ 1306044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1307044727500. Starting simulation... +info: Entering event queue @ 1307044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1308044727500. Starting simulation... +info: Entering event queue @ 1308044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1309044727500. Starting simulation... -info: Entering event queue @ 1316044720500. Starting simulation... -info: Entering event queue @ 1316044727000. Starting simulation... +info: Entering event queue @ 1309044706000. Starting simulation... +info: Entering event queue @ 1316044694500. Starting simulation... +info: Entering event queue @ 1316044701500. Starting simulation... switching cpus -info: Entering event queue @ 1316044727500. Starting simulation... +info: Entering event queue @ 1316044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1317044727500. Starting simulation... +info: Entering event queue @ 1317044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1318044727500. Starting simulation... +info: Entering event queue @ 1318044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1319044727500. Starting simulation... -info: Entering event queue @ 1326044720500. Starting simulation... -info: Entering event queue @ 1326044727000. Starting simulation... +info: Entering event queue @ 1319044706000. Starting simulation... +info: Entering event queue @ 1326044695500. Starting simulation... +info: Entering event queue @ 1326044702500. Starting simulation... switching cpus -info: Entering event queue @ 1326044727500. Starting simulation... +info: Entering event queue @ 1326044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1327044727500. Starting simulation... +info: Entering event queue @ 1327044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1328044727500. Starting simulation... +info: Entering event queue @ 1328044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1329044727500. Starting simulation... -info: Entering event queue @ 1336044720500. Starting simulation... -info: Entering event queue @ 1336044727000. Starting simulation... +info: Entering event queue @ 1329044707000. Starting simulation... +info: Entering event queue @ 1336044695500. Starting simulation... +info: Entering event queue @ 1336044702500. Starting simulation... switching cpus -info: Entering event queue @ 1336044727500. Starting simulation... +info: Entering event queue @ 1336044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1337044727500. Starting simulation... +info: Entering event queue @ 1337044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1338044727500. Starting simulation... +info: Entering event queue @ 1338044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1339044727500. Starting simulation... -info: Entering event queue @ 1346044720500. Starting simulation... -info: Entering event queue @ 1347144421000. Starting simulation... +info: Entering event queue @ 1339044707000. Starting simulation... +info: Entering event queue @ 1346044695500. Starting simulation... +info: Entering event queue @ 1347208355000. Starting simulation... switching cpus -info: Entering event queue @ 1347144423000. Starting simulation... +info: Entering event queue @ 1347208357000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1348144423000. Starting simulation... +info: Entering event queue @ 1348208357000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1349144423000. Starting simulation... +info: Entering event queue @ 1349208357000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1350144423000. Starting simulation... -info: Entering event queue @ 1356044720500. Starting simulation... -info: Entering event queue @ 1356044727000. Starting simulation... +info: Entering event queue @ 1350208357000. Starting simulation... switching cpus -info: Entering event queue @ 1356044727500. Starting simulation... +info: Entering event queue @ 1356044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1357044727500. Starting simulation... +info: Entering event queue @ 1357044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1358044727500. Starting simulation... +info: Entering event queue @ 1358044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1359044727500. Starting simulation... -info: Entering event queue @ 1366044720500. Starting simulation... -info: Entering event queue @ 1366044727000. Starting simulation... +info: Entering event queue @ 1359044695500. Starting simulation... +info: Entering event queue @ 1366044694500. Starting simulation... +info: Entering event queue @ 1366044701500. Starting simulation... switching cpus -info: Entering event queue @ 1366044727500. Starting simulation... +info: Entering event queue @ 1366044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1367044727500. Starting simulation... +info: Entering event queue @ 1367044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1368044727500. Starting simulation... +info: Entering event queue @ 1368044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1369044727500. Starting simulation... -info: Entering event queue @ 1376044720500. Starting simulation... -info: Entering event queue @ 1376044727000. Starting simulation... +info: Entering event queue @ 1369044706000. Starting simulation... +info: Entering event queue @ 1376044695500. Starting simulation... +info: Entering event queue @ 1376044703500. Starting simulation... switching cpus -info: Entering event queue @ 1376044727500. Starting simulation... +info: Entering event queue @ 1376044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1377044727500. Starting simulation... +info: Entering event queue @ 1377044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1378044727500. Starting simulation... +info: Entering event queue @ 1378044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1379044727500. Starting simulation... -info: Entering event queue @ 1386044720500. Starting simulation... -info: Entering event queue @ 1386044727000. Starting simulation... +info: Entering event queue @ 1379044708000. Starting simulation... +info: Entering event queue @ 1386044694500. Starting simulation... +info: Entering event queue @ 1386044701000. Starting simulation... switching cpus -info: Entering event queue @ 1386044727500. Starting simulation... +info: Entering event queue @ 1386044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1387044727500. Starting simulation... +info: Entering event queue @ 1387044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1388044727500. Starting simulation... +info: Entering event queue @ 1388044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1389044727500. Starting simulation... -info: Entering event queue @ 1396044720500. Starting simulation... -info: Entering event queue @ 1396044727000. Starting simulation... +info: Entering event queue @ 1389044701500. Starting simulation... +info: Entering event queue @ 1396044694500. Starting simulation... +info: Entering event queue @ 1396044701500. Starting simulation... switching cpus -info: Entering event queue @ 1396044727500. Starting simulation... +info: Entering event queue @ 1396044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1397044727500. Starting simulation... +info: Entering event queue @ 1397044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1398044727500. Starting simulation... +info: Entering event queue @ 1398044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1399044727500. Starting simulation... -info: Entering event queue @ 1406044720500. Starting simulation... -info: Entering event queue @ 1406044727000. Starting simulation... +info: Entering event queue @ 1399044706000. Starting simulation... switching cpus -info: Entering event queue @ 1406044727500. Starting simulation... +info: Entering event queue @ 1406044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1407044727500. Starting simulation... +info: Entering event queue @ 1407044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1408044727500. Starting simulation... +info: Entering event queue @ 1408044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1409044727500. Starting simulation... -info: Entering event queue @ 1416044720500. Starting simulation... -info: Entering event queue @ 1416044727000. Starting simulation... +info: Entering event queue @ 1409044695500. Starting simulation... +info: Entering event queue @ 1416044694500. Starting simulation... +info: Entering event queue @ 1416044701500. Starting simulation... switching cpus -info: Entering event queue @ 1416044727500. Starting simulation... +info: Entering event queue @ 1416044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1417044727500. Starting simulation... +info: Entering event queue @ 1417044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1418044727500. Starting simulation... +info: Entering event queue @ 1418044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1419044727500. Starting simulation... -info: Entering event queue @ 1426044720500. Starting simulation... -info: Entering event queue @ 1426044727000. Starting simulation... +info: Entering event queue @ 1419044706000. Starting simulation... +info: Entering event queue @ 1426044694500. Starting simulation... +info: Entering event queue @ 1426044701500. Starting simulation... switching cpus -info: Entering event queue @ 1426044727500. Starting simulation... +info: Entering event queue @ 1426044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1427044727500. Starting simulation... +info: Entering event queue @ 1427044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1428044727500. Starting simulation... +info: Entering event queue @ 1428044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1429044727500. Starting simulation... -info: Entering event queue @ 1436044720500. Starting simulation... -info: Entering event queue @ 1436044727000. Starting simulation... +info: Entering event queue @ 1429044706000. Starting simulation... +info: Entering event queue @ 1436044694500. Starting simulation... +info: Entering event queue @ 1436044701000. Starting simulation... switching cpus -info: Entering event queue @ 1436044727500. Starting simulation... +info: Entering event queue @ 1436044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1437044727500. Starting simulation... +info: Entering event queue @ 1437044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1438044727500. Starting simulation... +info: Entering event queue @ 1438044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1439044727500. Starting simulation... -info: Entering event queue @ 1446044720500. Starting simulation... -info: Entering event queue @ 1446044727000. Starting simulation... +info: Entering event queue @ 1439044701500. Starting simulation... +info: Entering event queue @ 1446044694500. Starting simulation... +info: Entering event queue @ 1446044701500. Starting simulation... switching cpus -info: Entering event queue @ 1446044727500. Starting simulation... +info: Entering event queue @ 1446044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1447044727500. Starting simulation... +info: Entering event queue @ 1447044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1448044727500. Starting simulation... +info: Entering event queue @ 1448044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1449044727500. Starting simulation... -info: Entering event queue @ 1456044720500. Starting simulation... -info: Entering event queue @ 1456044727000. Starting simulation... +info: Entering event queue @ 1449044706000. Starting simulation... +info: Entering event queue @ 1456044695500. Starting simulation... +info: Entering event queue @ 1456044702500. Starting simulation... switching cpus -info: Entering event queue @ 1456044727500. Starting simulation... +info: Entering event queue @ 1456044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1457044727500. Starting simulation... +info: Entering event queue @ 1457044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1458044727500. Starting simulation... +info: Entering event queue @ 1458044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1459044727500. Starting simulation... -info: Entering event queue @ 1466044720500. Starting simulation... -info: Entering event queue @ 1466044727000. Starting simulation... +info: Entering event queue @ 1459044707000. Starting simulation... +info: Entering event queue @ 1466044694500. Starting simulation... +info: Entering event queue @ 1466044701500. Starting simulation... switching cpus -info: Entering event queue @ 1466044727500. Starting simulation... +info: Entering event queue @ 1466044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1467044727500. Starting simulation... +info: Entering event queue @ 1467044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1468044727500. Starting simulation... +info: Entering event queue @ 1468044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1469044727500. Starting simulation... -info: Entering event queue @ 1476044720500. Starting simulation... -info: Entering event queue @ 1476044727000. Starting simulation... +info: Entering event queue @ 1469044706000. Starting simulation... +info: Entering event queue @ 1476044694500. Starting simulation... +info: Entering event queue @ 1476044701500. Starting simulation... switching cpus -info: Entering event queue @ 1476044727500. Starting simulation... +info: Entering event queue @ 1476044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1477044727500. Starting simulation... +info: Entering event queue @ 1477044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1478044727500. Starting simulation... +info: Entering event queue @ 1478044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1479044727500. Starting simulation... -info: Entering event queue @ 1486044720500. Starting simulation... -info: Entering event queue @ 1486044727000. Starting simulation... +info: Entering event queue @ 1479044706000. Starting simulation... +info: Entering event queue @ 1486044695500. Starting simulation... +info: Entering event queue @ 1486044702500. Starting simulation... switching cpus -info: Entering event queue @ 1486044727500. Starting simulation... +info: Entering event queue @ 1486044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1487044727500. Starting simulation... +info: Entering event queue @ 1487044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1488044727500. Starting simulation... +info: Entering event queue @ 1488044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1489044727500. Starting simulation... -info: Entering event queue @ 1496044720500. Starting simulation... -info: Entering event queue @ 1496044727000. Starting simulation... +info: Entering event queue @ 1489044707000. Starting simulation... +info: Entering event queue @ 1496044695500. Starting simulation... +info: Entering event queue @ 1496044702500. Starting simulation... switching cpus -info: Entering event queue @ 1496044727500. Starting simulation... +info: Entering event queue @ 1496044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1497044727500. Starting simulation... +info: Entering event queue @ 1497044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1498044727500. Starting simulation... +info: Entering event queue @ 1498044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1499044727500. Starting simulation... -info: Entering event queue @ 1506044720500. Starting simulation... -info: Entering event queue @ 1506044727000. Starting simulation... +info: Entering event queue @ 1499044707000. Starting simulation... switching cpus -info: Entering event queue @ 1506044727500. Starting simulation... +info: Entering event queue @ 1506044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1507044727500. Starting simulation... +info: Entering event queue @ 1507044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1508044727500. Starting simulation... +info: Entering event queue @ 1508044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1509044727500. Starting simulation... -info: Entering event queue @ 1516044720500. Starting simulation... -info: Entering event queue @ 1516044727000. Starting simulation... +info: Entering event queue @ 1509044695500. Starting simulation... switching cpus -info: Entering event queue @ 1516044727500. Starting simulation... +info: Entering event queue @ 1516044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1517044727500. Starting simulation... +info: Entering event queue @ 1517044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1518044727500. Starting simulation... +info: Entering event queue @ 1518044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1519044727500. Starting simulation... -info: Entering event queue @ 1526044720500. Starting simulation... -info: Entering event queue @ 1526044727000. Starting simulation... +info: Entering event queue @ 1519044695500. Starting simulation... +info: Entering event queue @ 1526044694500. Starting simulation... +info: Entering event queue @ 1526044701500. Starting simulation... switching cpus -info: Entering event queue @ 1526044727500. Starting simulation... +info: Entering event queue @ 1526044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1527044727500. Starting simulation... +info: Entering event queue @ 1527044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1528044727500. Starting simulation... +info: Entering event queue @ 1528044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1529044727500. Starting simulation... -info: Entering event queue @ 1536044720500. Starting simulation... -info: Entering event queue @ 1536044727000. Starting simulation... +info: Entering event queue @ 1529044706000. Starting simulation... +info: Entering event queue @ 1536044695500. Starting simulation... +info: Entering event queue @ 1536044703500. Starting simulation... switching cpus -info: Entering event queue @ 1536044727500. Starting simulation... +info: Entering event queue @ 1536044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1537044727500. Starting simulation... +info: Entering event queue @ 1537044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1538044727500. Starting simulation... +info: Entering event queue @ 1538044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1539044727500. Starting simulation... -info: Entering event queue @ 1546044720500. Starting simulation... -info: Entering event queue @ 1546044727000. Starting simulation... +info: Entering event queue @ 1539044708000. Starting simulation... +info: Entering event queue @ 1546044694500. Starting simulation... +info: Entering event queue @ 1546044701000. Starting simulation... switching cpus -info: Entering event queue @ 1546044727500. Starting simulation... +info: Entering event queue @ 1546044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1547044727500. Starting simulation... +info: Entering event queue @ 1547044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1548044727500. Starting simulation... +info: Entering event queue @ 1548044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1549044727500. Starting simulation... -info: Entering event queue @ 1556044720500. Starting simulation... -info: Entering event queue @ 1556044727000. Starting simulation... +info: Entering event queue @ 1549044701500. Starting simulation... +info: Entering event queue @ 1556044694500. Starting simulation... +info: Entering event queue @ 1556044701500. Starting simulation... switching cpus -info: Entering event queue @ 1556044727500. Starting simulation... +info: Entering event queue @ 1556044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1557044727500. Starting simulation... +info: Entering event queue @ 1557044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1558044727500. Starting simulation... +info: Entering event queue @ 1558044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1559044727500. Starting simulation... -info: Entering event queue @ 1566044720500. Starting simulation... -info: Entering event queue @ 1566044727000. Starting simulation... +info: Entering event queue @ 1559044706000. Starting simulation... +info: Entering event queue @ 1566044695500. Starting simulation... +info: Entering event queue @ 1566044703500. Starting simulation... switching cpus -info: Entering event queue @ 1566044727500. Starting simulation... +info: Entering event queue @ 1566044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1567044727500. Starting simulation... +info: Entering event queue @ 1567044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1568044727500. Starting simulation... +info: Entering event queue @ 1568044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1569044727500. Starting simulation... -info: Entering event queue @ 1576044720500. Starting simulation... -info: Entering event queue @ 1576298326000. Starting simulation... +info: Entering event queue @ 1569044708000. Starting simulation... +info: Entering event queue @ 1576044695500. Starting simulation... +info: Entering event queue @ 1576362334000. Starting simulation... switching cpus -info: Entering event queue @ 1576298328000. Starting simulation... +info: Entering event queue @ 1576362336000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1577298328000. Starting simulation... +info: Entering event queue @ 1577362336000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1578298328000. Starting simulation... +info: Entering event queue @ 1578362336000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1579298328000. Starting simulation... -info: Entering event queue @ 1586044720500. Starting simulation... -info: Entering event queue @ 1586044727000. Starting simulation... +info: Entering event queue @ 1579362336000. Starting simulation... +info: Entering event queue @ 1586044695500. Starting simulation... +info: Entering event queue @ 1586044703500. Starting simulation... switching cpus -info: Entering event queue @ 1586044727500. Starting simulation... +info: Entering event queue @ 1586044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1587044727500. Starting simulation... +info: Entering event queue @ 1587044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1588044727500. Starting simulation... +info: Entering event queue @ 1588044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1589044727500. Starting simulation... -info: Entering event queue @ 1596044720500. Starting simulation... -info: Entering event queue @ 1596044727000. Starting simulation... +info: Entering event queue @ 1589044708000. Starting simulation... +info: Entering event queue @ 1596044694500. Starting simulation... +info: Entering event queue @ 1596044701000. Starting simulation... switching cpus -info: Entering event queue @ 1596044727500. Starting simulation... +info: Entering event queue @ 1596044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1597044727500. Starting simulation... +info: Entering event queue @ 1597044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1598044727500. Starting simulation... +info: Entering event queue @ 1598044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1599044727500. Starting simulation... -info: Entering event queue @ 1606044720500. Starting simulation... -info: Entering event queue @ 1606044727000. Starting simulation... +info: Entering event queue @ 1599044701500. Starting simulation... +info: Entering event queue @ 1606044695500. Starting simulation... +info: Entering event queue @ 1606044703000. Starting simulation... switching cpus -info: Entering event queue @ 1606044727500. Starting simulation... +info: Entering event queue @ 1606044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1607044727500. Starting simulation... +info: Entering event queue @ 1607044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1608044727500. Starting simulation... -info: Entering event queue @ 1609034473000. Starting simulation... +info: Entering event queue @ 1608044703500. Starting simulation... +info: Entering event queue @ 1609097918000. Starting simulation... switching cpus -info: Entering event queue @ 1609034475000. Starting simulation... +info: Entering event queue @ 1609097920000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1610034475000. Starting simulation... -info: Entering event queue @ 1616044720500. Starting simulation... -info: Entering event queue @ 1616044727000. Starting simulation... +info: Entering event queue @ 1610097920000. Starting simulation... +info: Entering event queue @ 1616044694500. Starting simulation... +info: Entering event queue @ 1616044701500. Starting simulation... switching cpus -info: Entering event queue @ 1616044727500. Starting simulation... +info: Entering event queue @ 1616044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1617044727500. Starting simulation... +info: Entering event queue @ 1617044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1618044727500. Starting simulation... +info: Entering event queue @ 1618044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1619044727500. Starting simulation... -info: Entering event queue @ 1626044720500. Starting simulation... -info: Entering event queue @ 1626044727000. Starting simulation... +info: Entering event queue @ 1619044706000. Starting simulation... +info: Entering event queue @ 1626044694500. Starting simulation... +info: Entering event queue @ 1626044701500. Starting simulation... switching cpus -info: Entering event queue @ 1626044727500. Starting simulation... +info: Entering event queue @ 1626044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1627044727500. Starting simulation... +info: Entering event queue @ 1627044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1628044727500. Starting simulation... +info: Entering event queue @ 1628044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1629044727500. Starting simulation... -info: Entering event queue @ 1636044720500. Starting simulation... -info: Entering event queue @ 1636044727000. Starting simulation... +info: Entering event queue @ 1629044706000. Starting simulation... +info: Entering event queue @ 1636044694500. Starting simulation... +info: Entering event queue @ 1636044701500. Starting simulation... switching cpus -info: Entering event queue @ 1636044727500. Starting simulation... +info: Entering event queue @ 1636044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1637044727500. Starting simulation... +info: Entering event queue @ 1637044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1638044727500. Starting simulation... +info: Entering event queue @ 1638044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1639044727500. Starting simulation... -info: Entering event queue @ 1646044720500. Starting simulation... -info: Entering event queue @ 1646044727000. Starting simulation... +info: Entering event queue @ 1639044706000. Starting simulation... +info: Entering event queue @ 1646044695500. Starting simulation... +info: Entering event queue @ 1646044702500. Starting simulation... switching cpus -info: Entering event queue @ 1646044727500. Starting simulation... +info: Entering event queue @ 1646044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1647044727500. Starting simulation... +info: Entering event queue @ 1647044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1648044727500. Starting simulation... +info: Entering event queue @ 1648044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1649044727500. Starting simulation... -info: Entering event queue @ 1656044720500. Starting simulation... -info: Entering event queue @ 1656044727000. Starting simulation... +info: Entering event queue @ 1649044707000. Starting simulation... +info: Entering event queue @ 1656044695500. Starting simulation... +info: Entering event queue @ 1656044702500. Starting simulation... switching cpus -info: Entering event queue @ 1656044727500. Starting simulation... +info: Entering event queue @ 1656044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1657044727500. Starting simulation... +info: Entering event queue @ 1657044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1658044727500. Starting simulation... +info: Entering event queue @ 1658044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1659044727500. Starting simulation... -info: Entering event queue @ 1666044720500. Starting simulation... -info: Entering event queue @ 1666044727000. Starting simulation... +info: Entering event queue @ 1659044707000. Starting simulation... switching cpus -info: Entering event queue @ 1666044727500. Starting simulation... +info: Entering event queue @ 1666044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1667044727500. Starting simulation... +info: Entering event queue @ 1667044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1668044727500. Starting simulation... +info: Entering event queue @ 1668044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1669044727500. Starting simulation... -info: Entering event queue @ 1676044720500. Starting simulation... -info: Entering event queue @ 1676044727000. Starting simulation... +info: Entering event queue @ 1669044695500. Starting simulation... switching cpus -info: Entering event queue @ 1676044727500. Starting simulation... +info: Entering event queue @ 1676044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1677044727500. Starting simulation... +info: Entering event queue @ 1677044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1678044727500. Starting simulation... +info: Entering event queue @ 1678044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1679044727500. Starting simulation... -info: Entering event queue @ 1686044720500. Starting simulation... -info: Entering event queue @ 1686044727000. Starting simulation... +info: Entering event queue @ 1679044695500. Starting simulation... +info: Entering event queue @ 1686044694500. Starting simulation... +info: Entering event queue @ 1686044701500. Starting simulation... switching cpus -info: Entering event queue @ 1686044727500. Starting simulation... +info: Entering event queue @ 1686044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1687044727500. Starting simulation... +info: Entering event queue @ 1687044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1688044727500. Starting simulation... +info: Entering event queue @ 1688044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1689044727500. Starting simulation... -info: Entering event queue @ 1696044720500. Starting simulation... -info: Entering event queue @ 1696044727000. Starting simulation... +info: Entering event queue @ 1689044706000. Starting simulation... +info: Entering event queue @ 1696044695500. Starting simulation... +info: Entering event queue @ 1696044703500. Starting simulation... switching cpus -info: Entering event queue @ 1696044727500. Starting simulation... +info: Entering event queue @ 1696044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1697044727500. Starting simulation... +info: Entering event queue @ 1697044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1698044727500. Starting simulation... +info: Entering event queue @ 1698044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1699044727500. Starting simulation... -info: Entering event queue @ 1706044720500. Starting simulation... -info: Entering event queue @ 1707243505000. Starting simulation... +info: Entering event queue @ 1699044708000. Starting simulation... +info: Entering event queue @ 1706044694500. Starting simulation... +info: Entering event queue @ 1707307739000. Starting simulation... switching cpus -info: Entering event queue @ 1707243507000. Starting simulation... +info: Entering event queue @ 1707307741000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1708243507000. Starting simulation... +info: Entering event queue @ 1708307741000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1709243507000. Starting simulation... +info: Entering event queue @ 1709307741000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1710243507000. Starting simulation... -info: Entering event queue @ 1716044720500. Starting simulation... -info: Entering event queue @ 1716044727000. Starting simulation... +info: Entering event queue @ 1710307741000. Starting simulation... +info: Entering event queue @ 1716044694500. Starting simulation... +info: Entering event queue @ 1716044701500. Starting simulation... switching cpus -info: Entering event queue @ 1716044727500. Starting simulation... +info: Entering event queue @ 1716044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1717044727500. Starting simulation... +info: Entering event queue @ 1717044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1718044727500. Starting simulation... +info: Entering event queue @ 1718044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1719044727500. Starting simulation... -info: Entering event queue @ 1726044720500. Starting simulation... -info: Entering event queue @ 1726044727000. Starting simulation... +info: Entering event queue @ 1719044706000. Starting simulation... +info: Entering event queue @ 1726044694500. Starting simulation... +info: Entering event queue @ 1726044701500. Starting simulation... switching cpus -info: Entering event queue @ 1726044727500. Starting simulation... +info: Entering event queue @ 1726044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1727044727500. Starting simulation... +info: Entering event queue @ 1727044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1728044727500. Starting simulation... +info: Entering event queue @ 1728044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1729044727500. Starting simulation... -info: Entering event queue @ 1736044720500. Starting simulation... -info: Entering event queue @ 1736044727000. Starting simulation... +info: Entering event queue @ 1729044706000. Starting simulation... +info: Entering event queue @ 1736044695500. Starting simulation... +info: Entering event queue @ 1736044703500. Starting simulation... switching cpus -info: Entering event queue @ 1736044727500. Starting simulation... +info: Entering event queue @ 1736044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1737044727500. Starting simulation... +info: Entering event queue @ 1737044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1738044727500. Starting simulation... +info: Entering event queue @ 1738044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1739044727500. Starting simulation... -info: Entering event queue @ 1746044720500. Starting simulation... -info: Entering event queue @ 1746044727000. Starting simulation... +info: Entering event queue @ 1739044708000. Starting simulation... +info: Entering event queue @ 1746044695500. Starting simulation... +info: Entering event queue @ 1746044702500. Starting simulation... switching cpus -info: Entering event queue @ 1746044727500. Starting simulation... +info: Entering event queue @ 1746044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1747044727500. Starting simulation... +info: Entering event queue @ 1747044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1748044727500. Starting simulation... +info: Entering event queue @ 1748044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1749044727500. Starting simulation... -info: Entering event queue @ 1756044720500. Starting simulation... -info: Entering event queue @ 1756044727000. Starting simulation... +info: Entering event queue @ 1749044707000. Starting simulation... +info: Entering event queue @ 1756044694500. Starting simulation... +info: Entering event queue @ 1756044701000. Starting simulation... switching cpus -info: Entering event queue @ 1756044727500. Starting simulation... +info: Entering event queue @ 1756044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1757044727500. Starting simulation... +info: Entering event queue @ 1757044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1758044727500. Starting simulation... +info: Entering event queue @ 1758044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1759044727500. Starting simulation... -info: Entering event queue @ 1766044720500. Starting simulation... -info: Entering event queue @ 1766044727000. Starting simulation... +info: Entering event queue @ 1759044701500. Starting simulation... +info: Entering event queue @ 1766044694500. Starting simulation... +info: Entering event queue @ 1766044701500. Starting simulation... switching cpus -info: Entering event queue @ 1766044727500. Starting simulation... +info: Entering event queue @ 1766044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1767044727500. Starting simulation... +info: Entering event queue @ 1767044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1768044727500. Starting simulation... +info: Entering event queue @ 1768044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1769044727500. Starting simulation... -info: Entering event queue @ 1776044720500. Starting simulation... -info: Entering event queue @ 1776044727000. Starting simulation... +info: Entering event queue @ 1769044706000. Starting simulation... +info: Entering event queue @ 1776044695500. Starting simulation... +info: Entering event queue @ 1776044703000. Starting simulation... switching cpus -info: Entering event queue @ 1776044727500. Starting simulation... +info: Entering event queue @ 1776044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1777044727500. Starting simulation... +info: Entering event queue @ 1777044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1778044727500. Starting simulation... +info: Entering event queue @ 1778044703500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1779044727500. Starting simulation... -info: Entering event queue @ 1786044720500. Starting simulation... -info: Entering event queue @ 1786044727000. Starting simulation... +info: Entering event queue @ 1779044703500. Starting simulation... +info: Entering event queue @ 1786044694500. Starting simulation... +info: Entering event queue @ 1786044701500. Starting simulation... switching cpus -info: Entering event queue @ 1786044727500. Starting simulation... +info: Entering event queue @ 1786044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1787044727500. Starting simulation... +info: Entering event queue @ 1787044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1788044727500. Starting simulation... +info: Entering event queue @ 1788044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1789044727500. Starting simulation... -info: Entering event queue @ 1796044720500. Starting simulation... -info: Entering event queue @ 1796044727000. Starting simulation... +info: Entering event queue @ 1789044706000. Starting simulation... +info: Entering event queue @ 1796044694500. Starting simulation... +info: Entering event queue @ 1796044701500. Starting simulation... switching cpus -info: Entering event queue @ 1796044727500. Starting simulation... +info: Entering event queue @ 1796044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1797044727500. Starting simulation... +info: Entering event queue @ 1797044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1798044727500. Starting simulation... +info: Entering event queue @ 1798044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1799044727500. Starting simulation... -info: Entering event queue @ 1806044720500. Starting simulation... -info: Entering event queue @ 1806044727000. Starting simulation... +info: Entering event queue @ 1799044706000. Starting simulation... +info: Entering event queue @ 1806044695500. Starting simulation... +info: Entering event queue @ 1806044704000. Starting simulation... switching cpus -info: Entering event queue @ 1806044727500. Starting simulation... +info: Entering event queue @ 1806044704500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1807044727500. Starting simulation... +info: Entering event queue @ 1807044704500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1808044727500. Starting simulation... +info: Entering event queue @ 1808044704500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1809044727500. Starting simulation... -info: Entering event queue @ 1816044720500. Starting simulation... -info: Entering event queue @ 1816044727000. Starting simulation... +info: Entering event queue @ 1809044704500. Starting simulation... +info: Entering event queue @ 1816044694500. Starting simulation... +info: Entering event queue @ 1816044701500. Starting simulation... switching cpus -info: Entering event queue @ 1816044727500. Starting simulation... +info: Entering event queue @ 1816044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1817044727500. Starting simulation... +info: Entering event queue @ 1817044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1818044727500. Starting simulation... +info: Entering event queue @ 1818044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1819044727500. Starting simulation... -info: Entering event queue @ 1826044720500. Starting simulation... -info: Entering event queue @ 1826044727000. Starting simulation... +info: Entering event queue @ 1819044706000. Starting simulation... switching cpus -info: Entering event queue @ 1826044727500. Starting simulation... +info: Entering event queue @ 1826044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1827044727500. Starting simulation... +info: Entering event queue @ 1827044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1828044727500. Starting simulation... +info: Entering event queue @ 1828044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1829044727500. Starting simulation... -info: Entering event queue @ 1836044720500. Starting simulation... -info: Entering event queue @ 1836044727000. Starting simulation... +info: Entering event queue @ 1829044695500. Starting simulation... switching cpus -info: Entering event queue @ 1836044727500. Starting simulation... +info: Entering event queue @ 1836044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1837044727500. Starting simulation... +info: Entering event queue @ 1837044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1838044727500. Starting simulation... +info: Entering event queue @ 1838044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1839044727500. Starting simulation... -info: Entering event queue @ 1846044720500. Starting simulation... -info: Entering event queue @ 1846044727000. Starting simulation... +info: Entering event queue @ 1839044695500. Starting simulation... +info: Entering event queue @ 1846044694500. Starting simulation... +info: Entering event queue @ 1846044701500. Starting simulation... switching cpus -info: Entering event queue @ 1846044727500. Starting simulation... +info: Entering event queue @ 1846044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1847044727500. Starting simulation... +info: Entering event queue @ 1847044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1848044727500. Starting simulation... +info: Entering event queue @ 1848044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1849044727500. Starting simulation... -info: Entering event queue @ 1856044720500. Starting simulation... -info: Entering event queue @ 1856044727000. Starting simulation... +info: Entering event queue @ 1849044706000. Starting simulation... +info: Entering event queue @ 1856044695500. Starting simulation... +info: Entering event queue @ 1856044703500. Starting simulation... switching cpus -info: Entering event queue @ 1856044727500. Starting simulation... +info: Entering event queue @ 1856044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1857044727500. Starting simulation... +info: Entering event queue @ 1857044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1858044727500. Starting simulation... +info: Entering event queue @ 1858044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1859044727500. Starting simulation... -info: Entering event queue @ 1866044720500. Starting simulation... -info: Entering event queue @ 1866044727000. Starting simulation... +info: Entering event queue @ 1859044708000. Starting simulation... +info: Entering event queue @ 1866044694500. Starting simulation... +info: Entering event queue @ 1866044701000. Starting simulation... switching cpus -info: Entering event queue @ 1866044727500. Starting simulation... +info: Entering event queue @ 1866044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1867044727500. Starting simulation... +info: Entering event queue @ 1867044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1868044727500. Starting simulation... +info: Entering event queue @ 1868044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1869044727500. Starting simulation... -info: Entering event queue @ 1876044720500. Starting simulation... -info: Entering event queue @ 1876044727000. Starting simulation... +info: Entering event queue @ 1869044701500. Starting simulation... +info: Entering event queue @ 1876044694500. Starting simulation... +info: Entering event queue @ 1876044701500. Starting simulation... switching cpus -info: Entering event queue @ 1876044727500. Starting simulation... +info: Entering event queue @ 1876044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1877044727500. Starting simulation... +info: Entering event queue @ 1877044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1878044727500. Starting simulation... +info: Entering event queue @ 1878044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1879044727500. Starting simulation... -info: Entering event queue @ 1886044720500. Starting simulation... -info: Entering event queue @ 1886044727000. Starting simulation... +info: Entering event queue @ 1879044706000. Starting simulation... +info: Entering event queue @ 1886044694500. Starting simulation... +info: Entering event queue @ 1886044701500. Starting simulation... switching cpus -info: Entering event queue @ 1886044727500. Starting simulation... +info: Entering event queue @ 1886044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1887044727500. Starting simulation... +info: Entering event queue @ 1887044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1888044727500. Starting simulation... +info: Entering event queue @ 1888044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1889044727500. Starting simulation... -info: Entering event queue @ 1896044720500. Starting simulation... -info: Entering event queue @ 1896044727000. Starting simulation... +info: Entering event queue @ 1889044706000. Starting simulation... +info: Entering event queue @ 1896044695500. Starting simulation... +info: Entering event queue @ 1896044703500. Starting simulation... switching cpus -info: Entering event queue @ 1896044727500. Starting simulation... +info: Entering event queue @ 1896044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1897044727500. Starting simulation... +info: Entering event queue @ 1897044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1898044727500. Starting simulation... +info: Entering event queue @ 1898044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1899044727500. Starting simulation... -info: Entering event queue @ 1906044720500. Starting simulation... -info: Entering event queue @ 1906044727000. Starting simulation... +info: Entering event queue @ 1899044708000. Starting simulation... switching cpus -info: Entering event queue @ 1906044727500. Starting simulation... +info: Entering event queue @ 1906044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1907044727500. Starting simulation... +info: Entering event queue @ 1907044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1908044727500. Starting simulation... +info: Entering event queue @ 1908044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1909044727500. Starting simulation... -info: Entering event queue @ 1916044720500. Starting simulation... -info: Entering event queue @ 1916044727000. Starting simulation... +info: Entering event queue @ 1909044695500. Starting simulation... +info: Entering event queue @ 1916044694500. Starting simulation... +info: Entering event queue @ 1916044701000. Starting simulation... switching cpus -info: Entering event queue @ 1916044727500. Starting simulation... +info: Entering event queue @ 1916044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1917044727500. Starting simulation... +info: Entering event queue @ 1917044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1918044727500. Starting simulation... +info: Entering event queue @ 1918044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1919044727500. Starting simulation... -info: Entering event queue @ 1926044720500. Starting simulation... -info: Entering event queue @ 1926044727000. Starting simulation... +info: Entering event queue @ 1919044701500. Starting simulation... +info: Entering event queue @ 1926044694500. Starting simulation... +info: Entering event queue @ 1926044701500. Starting simulation... switching cpus -info: Entering event queue @ 1926044727500. Starting simulation... +info: Entering event queue @ 1926044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1927044727500. Starting simulation... +info: Entering event queue @ 1927044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1928044727500. Starting simulation... +info: Entering event queue @ 1928044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1929044727500. Starting simulation... -info: Entering event queue @ 1936044720500. Starting simulation... -info: Entering event queue @ 1936397407000. Starting simulation... +info: Entering event queue @ 1929044706000. Starting simulation... +info: Entering event queue @ 1936044695500. Starting simulation... +info: Entering event queue @ 1936460526000. Starting simulation... switching cpus -info: Entering event queue @ 1936397409000. Starting simulation... +info: Entering event queue @ 1936460528000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1937397409000. Starting simulation... +info: Entering event queue @ 1937460528000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1938397409000. Starting simulation... +info: Entering event queue @ 1938460528000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1939397409000. Starting simulation... -info: Entering event queue @ 1946044720500. Starting simulation... -info: Entering event queue @ 1946044727000. Starting simulation... +info: Entering event queue @ 1939460528000. Starting simulation... +info: Entering event queue @ 1946044694500. Starting simulation... +info: Entering event queue @ 1946044701500. Starting simulation... switching cpus -info: Entering event queue @ 1946044727500. Starting simulation... +info: Entering event queue @ 1946044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1947044727500. Starting simulation... +info: Entering event queue @ 1947044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1948044727500. Starting simulation... +info: Entering event queue @ 1948044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1949044727500. Starting simulation... -info: Entering event queue @ 1956044720500. Starting simulation... -info: Entering event queue @ 1956044727000. Starting simulation... +info: Entering event queue @ 1949044706000. Starting simulation... +info: Entering event queue @ 1956044694500. Starting simulation... +info: Entering event queue @ 1956044701500. Starting simulation... switching cpus -info: Entering event queue @ 1956044727500. Starting simulation... +info: Entering event queue @ 1956044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1957044727500. Starting simulation... +info: Entering event queue @ 1957044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1958044727500. Starting simulation... +info: Entering event queue @ 1958044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1959044727500. Starting simulation... -info: Entering event queue @ 1966044720500. Starting simulation... -info: Entering event queue @ 1966044727000. Starting simulation... +info: Entering event queue @ 1959044706000. Starting simulation... +info: Entering event queue @ 1966044695500. Starting simulation... +info: Entering event queue @ 1966044704000. Starting simulation... switching cpus -info: Entering event queue @ 1966044727500. Starting simulation... +info: Entering event queue @ 1966044704500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1967044727500. Starting simulation... +info: Entering event queue @ 1967044704500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 1968044727500. Starting simulation... -info: Entering event queue @ 1969133554000. Starting simulation... +info: Entering event queue @ 1968044704500. Starting simulation... +info: Entering event queue @ 1969197126000. Starting simulation... switching cpus -info: Entering event queue @ 1969133556000. Starting simulation... +info: Entering event queue @ 1969197128000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1970133556000. Starting simulation... -info: Entering event queue @ 1976044720500. Starting simulation... -info: Entering event queue @ 1976044727000. Starting simulation... +info: Entering event queue @ 1970197128000. Starting simulation... +info: Entering event queue @ 1976044695500. Starting simulation... +info: Entering event queue @ 1976044703000. Starting simulation... switching cpus -info: Entering event queue @ 1976044727500. Starting simulation... +info: Entering event queue @ 1976044703500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1977044727500. Starting simulation... +info: Entering event queue @ 1977044703500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1978044727500. Starting simulation... +info: Entering event queue @ 1978044703500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1979044727500. Starting simulation... -info: Entering event queue @ 1986044720500. Starting simulation... -info: Entering event queue @ 1986044727000. Starting simulation... +info: Entering event queue @ 1979044703500. Starting simulation... switching cpus -info: Entering event queue @ 1986044727500. Starting simulation... +info: Entering event queue @ 1986044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1987044727500. Starting simulation... +info: Entering event queue @ 1987044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1988044727500. Starting simulation... +info: Entering event queue @ 1988044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1989044727500. Starting simulation... -info: Entering event queue @ 1996044720500. Starting simulation... -info: Entering event queue @ 1996044727000. Starting simulation... +info: Entering event queue @ 1989044695500. Starting simulation... switching cpus -info: Entering event queue @ 1996044727500. Starting simulation... +info: Entering event queue @ 1996044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 1997044727500. Starting simulation... +info: Entering event queue @ 1997044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 1998044727500. Starting simulation... +info: Entering event queue @ 1998044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 1999044727500. Starting simulation... -info: Entering event queue @ 2006044720500. Starting simulation... -info: Entering event queue @ 2006044727000. Starting simulation... +info: Entering event queue @ 1999044695500. Starting simulation... +info: Entering event queue @ 2006044695500. Starting simulation... +info: Entering event queue @ 2006044703500. Starting simulation... switching cpus -info: Entering event queue @ 2006044727500. Starting simulation... +info: Entering event queue @ 2006044704000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2007044727500. Starting simulation... +info: Entering event queue @ 2007044704000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2008044727500. Starting simulation... +info: Entering event queue @ 2008044704000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2009044727500. Starting simulation... -info: Entering event queue @ 2016044720500. Starting simulation... -info: Entering event queue @ 2016044727000. Starting simulation... +info: Entering event queue @ 2009044704000. Starting simulation... +info: Entering event queue @ 2016044695500. Starting simulation... +info: Entering event queue @ 2016044702000. Starting simulation... switching cpus -info: Entering event queue @ 2016044727500. Starting simulation... +info: Entering event queue @ 2016044702500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2017044727500. Starting simulation... +info: Entering event queue @ 2017044702500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2018044727500. Starting simulation... +info: Entering event queue @ 2018044702500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2019044727500. Starting simulation... -info: Entering event queue @ 2026044720500. Starting simulation... -info: Entering event queue @ 2026044727000. Starting simulation... +info: Entering event queue @ 2019044702500. Starting simulation... +info: Entering event queue @ 2026044694500. Starting simulation... +info: Entering event queue @ 2026044701000. Starting simulation... switching cpus -info: Entering event queue @ 2026044727500. Starting simulation... +info: Entering event queue @ 2026044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2027044727500. Starting simulation... +info: Entering event queue @ 2027044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2028044727500. Starting simulation... +info: Entering event queue @ 2028044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2029044727500. Starting simulation... -info: Entering event queue @ 2036044720500. Starting simulation... -info: Entering event queue @ 2036044727000. Starting simulation... +info: Entering event queue @ 2029044701500. Starting simulation... +info: Entering event queue @ 2036044694500. Starting simulation... +info: Entering event queue @ 2036044701500. Starting simulation... switching cpus -info: Entering event queue @ 2036044727500. Starting simulation... +info: Entering event queue @ 2036044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2037044727500. Starting simulation... +info: Entering event queue @ 2037044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2038044727500. Starting simulation... +info: Entering event queue @ 2038044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2039044727500. Starting simulation... -info: Entering event queue @ 2046044720500. Starting simulation... -info: Entering event queue @ 2046044727000. Starting simulation... +info: Entering event queue @ 2039044706000. Starting simulation... +info: Entering event queue @ 2046044694500. Starting simulation... +info: Entering event queue @ 2046044701500. Starting simulation... switching cpus -info: Entering event queue @ 2046044727500. Starting simulation... +info: Entering event queue @ 2046044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2047044727500. Starting simulation... +info: Entering event queue @ 2047044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2048044727500. Starting simulation... +info: Entering event queue @ 2048044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2049044727500. Starting simulation... -info: Entering event queue @ 2056044720500. Starting simulation... -info: Entering event queue @ 2056044727000. Starting simulation... +info: Entering event queue @ 2049044706000. Starting simulation... +info: Entering event queue @ 2056044695500. Starting simulation... +info: Entering event queue @ 2056044703500. Starting simulation... switching cpus -info: Entering event queue @ 2056044727500. Starting simulation... +info: Entering event queue @ 2056044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2057044727500. Starting simulation... +info: Entering event queue @ 2057044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2058044727500. Starting simulation... +info: Entering event queue @ 2058044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2059044727500. Starting simulation... -info: Entering event queue @ 2066044720500. Starting simulation... -info: Entering event queue @ 2067342280000. Starting simulation... +info: Entering event queue @ 2059044708000. Starting simulation... +info: Entering event queue @ 2066044695500. Starting simulation... +info: Entering event queue @ 2067405755000. Starting simulation... switching cpus -info: Entering event queue @ 2067342282000. Starting simulation... +info: Entering event queue @ 2067405757000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2068342282000. Starting simulation... +info: Entering event queue @ 2068405757000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2069342282000. Starting simulation... +info: Entering event queue @ 2069405757000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2070342282000. Starting simulation... -info: Entering event queue @ 2076044720500. Starting simulation... -info: Entering event queue @ 2076044727000. Starting simulation... +info: Entering event queue @ 2070405757000. Starting simulation... +info: Entering event queue @ 2076044694500. Starting simulation... +info: Entering event queue @ 2076044701000. Starting simulation... switching cpus -info: Entering event queue @ 2076044727500. Starting simulation... +info: Entering event queue @ 2076044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2077044727500. Starting simulation... +info: Entering event queue @ 2077044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2078044727500. Starting simulation... +info: Entering event queue @ 2078044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2079044727500. Starting simulation... -info: Entering event queue @ 2086044720500. Starting simulation... -info: Entering event queue @ 2086044727000. Starting simulation... +info: Entering event queue @ 2079044701500. Starting simulation... +info: Entering event queue @ 2086044694500. Starting simulation... +info: Entering event queue @ 2086044701500. Starting simulation... switching cpus -info: Entering event queue @ 2086044727500. Starting simulation... +info: Entering event queue @ 2086044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2087044727500. Starting simulation... +info: Entering event queue @ 2087044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2088044727500. Starting simulation... +info: Entering event queue @ 2088044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2089044727500. Starting simulation... -info: Entering event queue @ 2096044720500. Starting simulation... -info: Entering event queue @ 2096044727000. Starting simulation... +info: Entering event queue @ 2089044706000. Starting simulation... +info: Entering event queue @ 2096044695500. Starting simulation... +info: Entering event queue @ 2096044702500. Starting simulation... switching cpus -info: Entering event queue @ 2096044727500. Starting simulation... +info: Entering event queue @ 2096044707000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2097044727500. Starting simulation... +info: Entering event queue @ 2097044707000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2098044727500. Starting simulation... +info: Entering event queue @ 2098044707000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2099044727500. Starting simulation... -info: Entering event queue @ 2106044720500. Starting simulation... -info: Entering event queue @ 2106044727000. Starting simulation... +info: Entering event queue @ 2099044707000. Starting simulation... +info: Entering event queue @ 2106044694500. Starting simulation... +info: Entering event queue @ 2106044701500. Starting simulation... switching cpus -info: Entering event queue @ 2106044727500. Starting simulation... +info: Entering event queue @ 2106044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2107044727500. Starting simulation... +info: Entering event queue @ 2107044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2108044727500. Starting simulation... +info: Entering event queue @ 2108044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2109044727500. Starting simulation... -info: Entering event queue @ 2116044720500. Starting simulation... -info: Entering event queue @ 2116044727000. Starting simulation... +info: Entering event queue @ 2109044706000. Starting simulation... +info: Entering event queue @ 2116044694500. Starting simulation... +info: Entering event queue @ 2116044701500. Starting simulation... switching cpus -info: Entering event queue @ 2116044727500. Starting simulation... +info: Entering event queue @ 2116044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2117044727500. Starting simulation... +info: Entering event queue @ 2117044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2118044727500. Starting simulation... +info: Entering event queue @ 2118044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2119044727500. Starting simulation... -info: Entering event queue @ 2126044720500. Starting simulation... -info: Entering event queue @ 2126044727000. Starting simulation... +info: Entering event queue @ 2119044706000. Starting simulation... +info: Entering event queue @ 2126044695500. Starting simulation... +info: Entering event queue @ 2126044704000. Starting simulation... switching cpus -info: Entering event queue @ 2126044727500. Starting simulation... +info: Entering event queue @ 2126044708500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2127044727500. Starting simulation... +info: Entering event queue @ 2127044708500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2128044727500. Starting simulation... +info: Entering event queue @ 2128044708500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2129044727500. Starting simulation... -info: Entering event queue @ 2136044720500. Starting simulation... -info: Entering event queue @ 2136044727000. Starting simulation... +info: Entering event queue @ 2129044708500. Starting simulation... switching cpus -info: Entering event queue @ 2136044727500. Starting simulation... +info: Entering event queue @ 2136044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2137044727500. Starting simulation... +info: Entering event queue @ 2137044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2138044727500. Starting simulation... +info: Entering event queue @ 2138044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2139044727500. Starting simulation... -info: Entering event queue @ 2146044720500. Starting simulation... -info: Entering event queue @ 2146044727000. Starting simulation... +info: Entering event queue @ 2139044695500. Starting simulation... switching cpus -info: Entering event queue @ 2146044727500. Starting simulation... +info: Entering event queue @ 2146044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2147044727500. Starting simulation... +info: Entering event queue @ 2147044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2148044727500. Starting simulation... +info: Entering event queue @ 2148044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2149044727500. Starting simulation... -info: Entering event queue @ 2156044720500. Starting simulation... -info: Entering event queue @ 2156044727000. Starting simulation... +info: Entering event queue @ 2149044695500. Starting simulation... switching cpus -info: Entering event queue @ 2156044727500. Starting simulation... +info: Entering event queue @ 2156044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2157044727500. Starting simulation... +info: Entering event queue @ 2157044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2158044727500. Starting simulation... +info: Entering event queue @ 2158044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2159044727500. Starting simulation... -info: Entering event queue @ 2166044720500. Starting simulation... -info: Entering event queue @ 2166044727000. Starting simulation... +info: Entering event queue @ 2159044695500. Starting simulation... +info: Entering event queue @ 2166044694500. Starting simulation... +info: Entering event queue @ 2166044701500. Starting simulation... switching cpus -info: Entering event queue @ 2166044727500. Starting simulation... +info: Entering event queue @ 2166044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2167044727500. Starting simulation... +info: Entering event queue @ 2167044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2168044727500. Starting simulation... +info: Entering event queue @ 2168044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2169044727500. Starting simulation... -info: Entering event queue @ 2176044720500. Starting simulation... -info: Entering event queue @ 2176044727000. Starting simulation... +info: Entering event queue @ 2169044706000. Starting simulation... +info: Entering event queue @ 2176044694500. Starting simulation... +info: Entering event queue @ 2176044701500. Starting simulation... switching cpus -info: Entering event queue @ 2176044727500. Starting simulation... +info: Entering event queue @ 2176044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2177044727500. Starting simulation... +info: Entering event queue @ 2177044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2178044727500. Starting simulation... +info: Entering event queue @ 2178044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2179044727500. Starting simulation... -info: Entering event queue @ 2186044720500. Starting simulation... -info: Entering event queue @ 2186044727000. Starting simulation... +info: Entering event queue @ 2179044706000. Starting simulation... +info: Entering event queue @ 2186044694500. Starting simulation... +info: Entering event queue @ 2186044701000. Starting simulation... switching cpus -info: Entering event queue @ 2186044727500. Starting simulation... +info: Entering event queue @ 2186044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2187044727500. Starting simulation... +info: Entering event queue @ 2187044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2188044727500. Starting simulation... +info: Entering event queue @ 2188044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2189044727500. Starting simulation... -info: Entering event queue @ 2196044720500. Starting simulation... -info: Entering event queue @ 2196044727000. Starting simulation... +info: Entering event queue @ 2189044701500. Starting simulation... +info: Entering event queue @ 2196044694500. Starting simulation... +info: Entering event queue @ 2196044701500. Starting simulation... switching cpus -info: Entering event queue @ 2196044727500. Starting simulation... +info: Entering event queue @ 2196044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2197044727500. Starting simulation... +info: Entering event queue @ 2197044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2198044727500. Starting simulation... +info: Entering event queue @ 2198044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2199044727500. Starting simulation... -info: Entering event queue @ 2206044720500. Starting simulation... -info: Entering event queue @ 2206044727000. Starting simulation... +info: Entering event queue @ 2199044706000. Starting simulation... switching cpus -info: Entering event queue @ 2206044727500. Starting simulation... +info: Entering event queue @ 2206044695500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2207044727500. Starting simulation... +info: Entering event queue @ 2207044695500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2208044727500. Starting simulation... +info: Entering event queue @ 2208044695500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2209044727500. Starting simulation... -info: Entering event queue @ 2216044720500. Starting simulation... -info: Entering event queue @ 2216044727000. Starting simulation... +info: Entering event queue @ 2209044695500. Starting simulation... +info: Entering event queue @ 2216044694500. Starting simulation... +info: Entering event queue @ 2216044701500. Starting simulation... switching cpus -info: Entering event queue @ 2216044727500. Starting simulation... +info: Entering event queue @ 2216044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2217044727500. Starting simulation... +info: Entering event queue @ 2217044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2218044727500. Starting simulation... +info: Entering event queue @ 2218044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2219044727500. Starting simulation... -info: Entering event queue @ 2226044720500. Starting simulation... -info: Entering event queue @ 2226044727000. Starting simulation... +info: Entering event queue @ 2219044706000. Starting simulation... +info: Entering event queue @ 2226044695500. Starting simulation... +info: Entering event queue @ 2226044703500. Starting simulation... switching cpus -info: Entering event queue @ 2226044727500. Starting simulation... +info: Entering event queue @ 2226044708000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2227044727500. Starting simulation... +info: Entering event queue @ 2227044708000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2228044727500. Starting simulation... +info: Entering event queue @ 2228044708000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2229044727500. Starting simulation... -info: Entering event queue @ 2236044720500. Starting simulation... -info: Entering event queue @ 2236044727000. Starting simulation... +info: Entering event queue @ 2229044708000. Starting simulation... +info: Entering event queue @ 2236044694500. Starting simulation... +info: Entering event queue @ 2236044701000. Starting simulation... switching cpus -info: Entering event queue @ 2236044727500. Starting simulation... +info: Entering event queue @ 2236044701500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2237044727500. Starting simulation... +info: Entering event queue @ 2237044701500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2238044727500. Starting simulation... +info: Entering event queue @ 2238044701500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2239044727500. Starting simulation... -info: Entering event queue @ 2246044720500. Starting simulation... -info: Entering event queue @ 2246044727000. Starting simulation... +info: Entering event queue @ 2239044701500. Starting simulation... +info: Entering event queue @ 2246044694500. Starting simulation... +info: Entering event queue @ 2246044701500. Starting simulation... switching cpus -info: Entering event queue @ 2246044727500. Starting simulation... +info: Entering event queue @ 2246044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2247044727500. Starting simulation... +info: Entering event queue @ 2247044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2248044727500. Starting simulation... +info: Entering event queue @ 2248044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2249044727500. Starting simulation... -info: Entering event queue @ 2256044720500. Starting simulation... -info: Entering event queue @ 2256044727000. Starting simulation... +info: Entering event queue @ 2249044706000. Starting simulation... +info: Entering event queue @ 2256044694500. Starting simulation... +info: Entering event queue @ 2256044701500. Starting simulation... switching cpus -info: Entering event queue @ 2256044727500. Starting simulation... +info: Entering event queue @ 2256044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2257044727500. Starting simulation... +info: Entering event queue @ 2257044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU switching cpus -info: Entering event queue @ 2258044727500. Starting simulation... +info: Entering event queue @ 2258044706000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2259044727500. Starting simulation... -info: Entering event queue @ 2266044720500. Starting simulation... -info: Entering event queue @ 2266044727000. Starting simulation... +info: Entering event queue @ 2259044706000. Starting simulation... +info: Entering event queue @ 2266044694500. Starting simulation... +info: Entering event queue @ 2266044701500. Starting simulation... switching cpus -info: Entering event queue @ 2266044727500. Starting simulation... +info: Entering event queue @ 2266044706000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2267044727500. Starting simulation... +info: Entering event queue @ 2267044706000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2268044727500. Starting simulation... +info: Entering event queue @ 2268044706000. Starting simulation... switching cpus -info: Entering event queue @ 2268044728500. Starting simulation... +info: Entering event queue @ 2268044713500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2269044728500. Starting simulation... +info: Entering event queue @ 2269044713500. Starting simulation... switching cpus -info: Entering event queue @ 2269044739000. Starting simulation... +info: Entering event queue @ 2269044786000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2270044739000. Starting simulation... +info: Entering event queue @ 2270044786000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2271044739000. Starting simulation... +info: Entering event queue @ 2271044786000. Starting simulation... switching cpus -info: Entering event queue @ 2271044767000. Starting simulation... +info: Entering event queue @ 2271044847000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2272044767000. Starting simulation... +info: Entering event queue @ 2272044847000. Starting simulation... switching cpus -info: Entering event queue @ 2272044790000. Starting simulation... +info: Entering event queue @ 2272044909000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2273044790000. Starting simulation... +info: Entering event queue @ 2273044909000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2274044790000. Starting simulation... +info: Entering event queue @ 2274044909000. Starting simulation... switching cpus -info: Entering event queue @ 2274044828000. Starting simulation... +info: Entering event queue @ 2274045051000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2275044828000. Starting simulation... +info: Entering event queue @ 2275045051000. Starting simulation... switching cpus -info: Entering event queue @ 2275044925000. Starting simulation... +info: Entering event queue @ 2275045114000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 2276045114000. Starting simulation... switching cpus -info: Entering event queue @ 2276044925000. Starting simulation... +info: Entering event queue @ 2276045117500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2277044925000. Starting simulation... +info: Entering event queue @ 2277045117500. Starting simulation... switching cpus -info: Entering event queue @ 2277045053000. Starting simulation... +info: Entering event queue @ 2277045208000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2278045053000. Starting simulation... +info: Entering event queue @ 2278045208000. Starting simulation... switching cpus -info: Entering event queue @ 2278045122000. Starting simulation... +info: Entering event queue @ 2278045280000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2279045122000. Starting simulation... +info: Entering event queue @ 2279045280000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2280045122000. Starting simulation... +info: Entering event queue @ 2280045280000. Starting simulation... switching cpus -info: Entering event queue @ 2280045138000. Starting simulation... +info: Entering event queue @ 2280045384000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2281045138000. Starting simulation... +info: Entering event queue @ 2281045384000. Starting simulation... switching cpus -info: Entering event queue @ 2281045900000. Starting simulation... +info: Entering event queue @ 2281048528000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2282045900000. Starting simulation... +info: Entering event queue @ 2282048528000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2283045900000. Starting simulation... +info: Entering event queue @ 2283048528000. Starting simulation... switching cpus -info: Entering event queue @ 2283045901000. Starting simulation... +info: Entering event queue @ 2283048535500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2284045901000. Starting simulation... +info: Entering event queue @ 2284048535500. Starting simulation... switching cpus -info: Entering event queue @ 2284045960000. Starting simulation... +info: Entering event queue @ 2284048596000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2285045960000. Starting simulation... +info: Entering event queue @ 2285048596000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2286045960000. Starting simulation... +info: Entering event queue @ 2286048596000. Starting simulation... switching cpus -info: Entering event queue @ 2286045982000. Starting simulation... +info: Entering event queue @ 2286048638000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2287045982000. Starting simulation... +info: Entering event queue @ 2287048638000. Starting simulation... switching cpus -info: Entering event queue @ 2287045989000. Starting simulation... +info: Entering event queue @ 2287048678500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2288045989000. Starting simulation... +info: Entering event queue @ 2288048678500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2289045989000. Starting simulation... +info: Entering event queue @ 2289048678500. Starting simulation... switching cpus -info: Entering event queue @ 2289046000000. Starting simulation... +info: Entering event queue @ 2289048766000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2290046000000. Starting simulation... +info: Entering event queue @ 2290048766000. Starting simulation... switching cpus -info: Entering event queue @ 2290046070000. Starting simulation... +info: Entering event queue @ 2290048836000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2291046070000. Starting simulation... +info: Entering event queue @ 2291048836000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2292046070000. Starting simulation... +info: Entering event queue @ 2292048836000. Starting simulation... switching cpus -info: Entering event queue @ 2292046106000. Starting simulation... +info: Entering event queue @ 2292048927000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2293046106000. Starting simulation... +info: Entering event queue @ 2293048927000. Starting simulation... switching cpus -info: Entering event queue @ 2293046137000. Starting simulation... +info: Entering event queue @ 2293049027000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2294046137000. Starting simulation... +info: Entering event queue @ 2294049027000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2295046137000. Starting simulation... -info: Entering event queue @ 2296496182000. Starting simulation... +info: Entering event queue @ 2295049027000. Starting simulation... +info: Entering event queue @ 2296559734000. Starting simulation... switching cpus -info: Entering event queue @ 2296496184000. Starting simulation... +info: Entering event queue @ 2296559736000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2297496184000. Starting simulation... +info: Entering event queue @ 2297559736000. Starting simulation... switching cpus -info: Entering event queue @ 2297496268000. Starting simulation... +info: Entering event queue @ 2297559885000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2298496268000. Starting simulation... +info: Entering event queue @ 2298559885000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2299496268000. Starting simulation... +info: Entering event queue @ 2299559885000. Starting simulation... switching cpus -info: Entering event queue @ 2299496348000. Starting simulation... +info: Entering event queue @ 2299559978000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2300496348000. Starting simulation... +info: Entering event queue @ 2300559978000. Starting simulation... switching cpus -info: Entering event queue @ 2300496430000. Starting simulation... +info: Entering event queue @ 2300560079000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2301496430000. Starting simulation... +info: Entering event queue @ 2301560079000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2302496430000. Starting simulation... +info: Entering event queue @ 2302560079000. Starting simulation... switching cpus -info: Entering event queue @ 2302496531000. Starting simulation... +info: Entering event queue @ 2302560132000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2303496531000. Starting simulation... +info: Entering event queue @ 2303560132000. Starting simulation... switching cpus -info: Entering event queue @ 2303496584000. Starting simulation... +info: Entering event queue @ 2303560241000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2304496584000. Starting simulation... +info: Entering event queue @ 2304560241000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2305496584000. Starting simulation... +info: Entering event queue @ 2305560241000. Starting simulation... switching cpus -info: Entering event queue @ 2305496661000. Starting simulation... +info: Entering event queue @ 2305560280000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2306496661000. Starting simulation... +info: Entering event queue @ 2306560280000. Starting simulation... switching cpus -info: Entering event queue @ 2306496732000. Starting simulation... +info: Entering event queue @ 2306560431000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2307496732000. Starting simulation... +info: Entering event queue @ 2307560431000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2308496732000. Starting simulation... +info: Entering event queue @ 2308560431000. Starting simulation... switching cpus -info: Entering event queue @ 2308496815000. Starting simulation... +info: Entering event queue @ 2308560560000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2309496815000. Starting simulation... +info: Entering event queue @ 2309560560000. Starting simulation... switching cpus -info: Entering event queue @ 2309496944500. Starting simulation... +info: Entering event queue @ 2309560642000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2310496944500. Starting simulation... +info: Entering event queue @ 2310560642000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2311496944500. Starting simulation... +info: Entering event queue @ 2311560642000. Starting simulation... switching cpus -info: Entering event queue @ 2311496968000. Starting simulation... +info: Entering event queue @ 2311560786000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2312496968000. Starting simulation... +info: Entering event queue @ 2312560786000. Starting simulation... switching cpus -info: Entering event queue @ 2312497014000. Starting simulation... +info: Entering event queue @ 2312560905000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2313497014000. Starting simulation... +info: Entering event queue @ 2313560905000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2314497014000. Starting simulation... +info: Entering event queue @ 2314560905000. Starting simulation... switching cpus -info: Entering event queue @ 2314497034000. Starting simulation... +info: Entering event queue @ 2314561028000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2315497034000. Starting simulation... +info: Entering event queue @ 2315561028000. Starting simulation... switching cpus -info: Entering event queue @ 2315497085000. Starting simulation... +info: Entering event queue @ 2315561054000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2316497085000. Starting simulation... +info: Entering event queue @ 2316561054000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2317497085000. Starting simulation... +info: Entering event queue @ 2317561054000. Starting simulation... switching cpus -info: Entering event queue @ 2317497141000. Starting simulation... +info: Entering event queue @ 2317561176000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2318497141000. Starting simulation... +info: Entering event queue @ 2318561176000. Starting simulation... switching cpus -info: Entering event queue @ 2318497292000. Starting simulation... +info: Entering event queue @ 2318561200000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2319497292000. Starting simulation... +info: Entering event queue @ 2319561200000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2320497292000. Starting simulation... +info: Entering event queue @ 2320561200000. Starting simulation... switching cpus -info: Entering event queue @ 2320497349000. Starting simulation... +info: Entering event queue @ 2320561287000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2321497349000. Starting simulation... +info: Entering event queue @ 2321561287000. Starting simulation... switching cpus -info: Entering event queue @ 2321497426000. Starting simulation... +info: Entering event queue @ 2321561319000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2322497426000. Starting simulation... +info: Entering event queue @ 2322561319000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2323497426000. Starting simulation... +info: Entering event queue @ 2323561319000. Starting simulation... switching cpus -info: Entering event queue @ 2323497512000. Starting simulation... +info: Entering event queue @ 2323561362000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2324497512000. Starting simulation... +info: Entering event queue @ 2324561362000. Starting simulation... switching cpus -info: Entering event queue @ 2324497588000. Starting simulation... +info: Entering event queue @ 2324561408000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2325497588000. Starting simulation... +info: Entering event queue @ 2325561408000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2326497588000. Starting simulation... +info: Entering event queue @ 2326561408000. Starting simulation... switching cpus -info: Entering event queue @ 2326497667000. Starting simulation... +info: Entering event queue @ 2326561540000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2327497667000. Starting simulation... +info: Entering event queue @ 2327561540000. Starting simulation... switching cpus -info: Entering event queue @ 2327497830500. Starting simulation... +info: Entering event queue @ 2327561579000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2328497830500. Starting simulation... +info: Entering event queue @ 2328561579000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2329497830500. Starting simulation... +info: Entering event queue @ 2329561579000. Starting simulation... switching cpus -info: Entering event queue @ 2329497980000. Starting simulation... +info: Entering event queue @ 2329561703000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2330497980000. Starting simulation... +info: Entering event queue @ 2330561703000. Starting simulation... switching cpus -info: Entering event queue @ 2330498019000. Starting simulation... +info: Entering event queue @ 2330561718000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2331498019000. Starting simulation... +info: Entering event queue @ 2331561718000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2332498019000. Starting simulation... +info: Entering event queue @ 2332561718000. Starting simulation... switching cpus -info: Entering event queue @ 2332498021000. Starting simulation... +info: Entering event queue @ 2332561741000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2333498021000. Starting simulation... +info: Entering event queue @ 2333561741000. Starting simulation... switching cpus -info: Entering event queue @ 2333498144000. Starting simulation... +info: Entering event queue @ 2333561793000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2334498144000. Starting simulation... +info: Entering event queue @ 2334561793000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2335498144000. Starting simulation... +info: Entering event queue @ 2335561793000. Starting simulation... switching cpus -info: Entering event queue @ 2335498177000. Starting simulation... +info: Entering event queue @ 2335561883000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2336498177000. Starting simulation... +info: Entering event queue @ 2336561883000. Starting simulation... switching cpus -info: Entering event queue @ 2336498207000. Starting simulation... +info: Entering event queue @ 2336561949000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2337498207000. Starting simulation... +info: Entering event queue @ 2337561949000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2338498207000. Starting simulation... +info: Entering event queue @ 2338561949000. Starting simulation... switching cpus -info: Entering event queue @ 2338498322500. Starting simulation... +info: Entering event queue @ 2338562083000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2339498322500. Starting simulation... +info: Entering event queue @ 2339562083000. Starting simulation... switching cpus -info: Entering event queue @ 2339498342500. Starting simulation... +info: Entering event queue @ 2339562223000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2340498342500. Starting simulation... +info: Entering event queue @ 2340562223000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2341498342500. Starting simulation... +info: Entering event queue @ 2341562223000. Starting simulation... switching cpus -info: Entering event queue @ 2341498465000. Starting simulation... +info: Entering event queue @ 2341562231000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2342498465000. Starting simulation... +info: Entering event queue @ 2342562231000. Starting simulation... switching cpus -info: Entering event queue @ 2342498545000. Starting simulation... +info: Entering event queue @ 2342562288000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2343498545000. Starting simulation... +info: Entering event queue @ 2343562288000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2344498545000. Starting simulation... +info: Entering event queue @ 2344562288000. Starting simulation... switching cpus -info: Entering event queue @ 2344498670000. Starting simulation... +info: Entering event queue @ 2344562311000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2345498670000. Starting simulation... +info: Entering event queue @ 2345562311000. Starting simulation... switching cpus -info: Entering event queue @ 2345498729000. Starting simulation... +info: Entering event queue @ 2345562459000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2346498729000. Starting simulation... +info: Entering event queue @ 2346562459000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2347498729000. Starting simulation... +info: Entering event queue @ 2347562459000. Starting simulation... switching cpus -info: Entering event queue @ 2347498836000. Starting simulation... +info: Entering event queue @ 2347562517000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2348498836000. Starting simulation... +info: Entering event queue @ 2348562517000. Starting simulation... switching cpus -info: Entering event queue @ 2348498903500. Starting simulation... +info: Entering event queue @ 2348562659000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2349498903500. Starting simulation... +info: Entering event queue @ 2349562659000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2350498903500. Starting simulation... +info: Entering event queue @ 2350562659000. Starting simulation... switching cpus -info: Entering event queue @ 2350499004000. Starting simulation... +info: Entering event queue @ 2350562734000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2351499004000. Starting simulation... +info: Entering event queue @ 2351562734000. Starting simulation... switching cpus -info: Entering event queue @ 2351499092000. Starting simulation... +info: Entering event queue @ 2351562890000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2352499092000. Starting simulation... +info: Entering event queue @ 2352562890000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2353499092000. Starting simulation... +info: Entering event queue @ 2353562890000. Starting simulation... switching cpus -info: Entering event queue @ 2353499228000. Starting simulation... +info: Entering event queue @ 2353562986000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2354499228000. Starting simulation... +info: Entering event queue @ 2354562986000. Starting simulation... switching cpus -info: Entering event queue @ 2354499241000. Starting simulation... +info: Entering event queue @ 2354563105000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2355499241000. Starting simulation... +info: Entering event queue @ 2355563105000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2356499241000. Starting simulation... +info: Entering event queue @ 2356563105000. Starting simulation... switching cpus -info: Entering event queue @ 2356499328000. Starting simulation... +info: Entering event queue @ 2356563162000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2357499328000. Starting simulation... +info: Entering event queue @ 2357563162000. Starting simulation... switching cpus -info: Entering event queue @ 2357499348000. Starting simulation... +info: Entering event queue @ 2357568596000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2358499348000. Starting simulation... +info: Entering event queue @ 2358568596000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2359499348000. Starting simulation... +info: Entering event queue @ 2359568596000. Starting simulation... switching cpus -info: Entering event queue @ 2359499378000. Starting simulation... +info: Entering event queue @ 2359568661000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2360499378000. Starting simulation... -info: Entering event queue @ 2361968926000. Starting simulation... +info: Entering event queue @ 2360568661000. Starting simulation... +info: Entering event queue @ 2362032934000. Starting simulation... switching cpus -info: Entering event queue @ 2361968928000. Starting simulation... +info: Entering event queue @ 2362032936000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2362968928000. Starting simulation... +info: Entering event queue @ 2363032936000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2363968928000. Starting simulation... +info: Entering event queue @ 2364032936000. Starting simulation... switching cpus -info: Entering event queue @ 2363969050000. Starting simulation... +info: Entering event queue @ 2364033051000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2364969050000. Starting simulation... +info: Entering event queue @ 2365033051000. Starting simulation... switching cpus -info: Entering event queue @ 2364969072000. Starting simulation... +info: Entering event queue @ 2365033171000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2365969072000. Starting simulation... +info: Entering event queue @ 2366033171000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2366969072000. Starting simulation... +info: Entering event queue @ 2367033171000. Starting simulation... switching cpus -info: Entering event queue @ 2366969074000. Starting simulation... +info: Entering event queue @ 2367033178500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2367969074000. Starting simulation... +info: Entering event queue @ 2368033178500. Starting simulation... switching cpus -info: Entering event queue @ 2367969092500. Starting simulation... +info: Entering event queue @ 2368033187500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2368969092500. Starting simulation... +info: Entering event queue @ 2369033187500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2369969092500. Starting simulation... +info: Entering event queue @ 2370033187500. Starting simulation... switching cpus -info: Entering event queue @ 2369969184000. Starting simulation... +info: Entering event queue @ 2370033205000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2370969184000. Starting simulation... +info: Entering event queue @ 2371033205000. Starting simulation... switching cpus -info: Entering event queue @ 2370969281000. Starting simulation... +info: Entering event queue @ 2371033365500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2371969281000. Starting simulation... +info: Entering event queue @ 2372033365500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2372969281000. Starting simulation... +info: Entering event queue @ 2373033365500. Starting simulation... +info: Entering event queue @ 2373033604000. Starting simulation... switching cpus -info: Entering event queue @ 2372969283000. Starting simulation... +info: Entering event queue @ 2373033611500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2373969283000. Starting simulation... +info: Entering event queue @ 2374033611500. Starting simulation... switching cpus -info: Entering event queue @ 2373969828500. Starting simulation... +info: Entering event queue @ 2374033619000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2374969828500. Starting simulation... +info: Entering event queue @ 2375033619000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2375969828500. Starting simulation... +info: Entering event queue @ 2376033619000. Starting simulation... switching cpus -info: Entering event queue @ 2375969851000. Starting simulation... +info: Entering event queue @ 2376033645000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2376969851000. Starting simulation... +info: Entering event queue @ 2377033645000. Starting simulation... switching cpus -info: Entering event queue @ 2376969901000. Starting simulation... +info: Entering event queue @ 2377043485500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2377969901000. Starting simulation... +info: Entering event queue @ 2378043485500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2378969901000. Starting simulation... +info: Entering event queue @ 2379043485500. Starting simulation... switching cpus -info: Entering event queue @ 2378969954000. Starting simulation... +info: Entering event queue @ 2379043518000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2379969954000. Starting simulation... +info: Entering event queue @ 2380043518000. Starting simulation... switching cpus -info: Entering event queue @ 2379970086500. Starting simulation... +info: Entering event queue @ 2380043682500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2380970086500. Starting simulation... +info: Entering event queue @ 2381043682500. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2381970086500. Starting simulation... +info: Entering event queue @ 2382043682500. Starting simulation... switching cpus -info: Entering event queue @ 2381970242000. Starting simulation... +info: Entering event queue @ 2382043698000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2382970242000. Starting simulation... +info: Entering event queue @ 2383043698000. Starting simulation... switching cpus -info: Entering event queue @ 2382978620000. Starting simulation... +info: Entering event queue @ 2383051750000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2383978620000. Starting simulation... +info: Entering event queue @ 2384051750000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2384978620000. Starting simulation... +info: Entering event queue @ 2385051750000. Starting simulation... switching cpus -info: Entering event queue @ 2384978773000. Starting simulation... +info: Entering event queue @ 2385051891000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2385978773000. Starting simulation... +info: Entering event queue @ 2386051891000. Starting simulation... +info: Entering event queue @ 2386051935000. Starting simulation... switching cpus -info: Entering event queue @ 2385978776000. Starting simulation... +info: Entering event queue @ 2386052242750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2386978776000. Starting simulation... +info: Entering event queue @ 2387052242750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2387978776000. Starting simulation... +info: Entering event queue @ 2388052242750. Starting simulation... switching cpus -info: Entering event queue @ 2387978777500. Starting simulation... +info: Entering event queue @ 2388052250250. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2388978777500. Starting simulation... +info: Entering event queue @ 2389052250250. Starting simulation... switching cpus -info: Entering event queue @ 2388978785000. Starting simulation... +info: Entering event queue @ 2389052257750. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2389978785000. Starting simulation... +info: Entering event queue @ 2390052257750. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2390978785000. Starting simulation... +info: Entering event queue @ 2391052257750. Starting simulation... switching cpus -info: Entering event queue @ 2390978786000. Starting simulation... +info: Entering event queue @ 2391052265250. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2391978786000. Starting simulation... -info: Entering event queue @ 2391978831000. Starting simulation... -info: Entering event queue @ 2391978840500. Starting simulation... -info: Entering event queue @ 2391978845000. Starting simulation... +info: Entering event queue @ 2392052265250. Starting simulation... switching cpus -info: Entering event queue @ 2391978846000. Starting simulation... +info: Entering event queue @ 2392062139500. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU +info: Entering event queue @ 2393062139500. Starting simulation... switching cpus -info: Entering event queue @ 2392978846000. Starting simulation... +info: Entering event queue @ 2393062140000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2393978846000. Starting simulation... -info: Entering event queue @ 2394705526000. Starting simulation... +info: Entering event queue @ 2394062140000. Starting simulation... +info: Entering event queue @ 2394135530000. Starting simulation... switching cpus -info: Entering event queue @ 2394705528000. Starting simulation... +info: Entering event queue @ 2394135532000. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2395705528000. Starting simulation... +info: Entering event queue @ 2395135532000. Starting simulation... switching cpus -info: Entering event queue @ 2395708224000. Starting simulation... +info: Entering event queue @ 2395135538000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2396708224000. Starting simulation... +info: Entering event queue @ 2396135538000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2397708224000. Starting simulation... +info: Entering event queue @ 2397135538000. Starting simulation... switching cpus -info: Entering event queue @ 2397708236000. Starting simulation... +info: Entering event queue @ 2397135545500. Starting simulation... Switching CPUs... Next CPU: AtomicSimpleCPU -info: Entering event queue @ 2398708236000. Starting simulation... +info: Entering event queue @ 2398135545500. Starting simulation... switching cpus -info: Entering event queue @ 2398708269500. Starting simulation... +info: Entering event queue @ 2398135611000. Starting simulation... Switching CPUs... Next CPU: TimingSimpleCPU switching cpus -info: Entering event queue @ 2399708269500. Starting simulation... +info: Entering event queue @ 2399135611000. Starting simulation... Switching CPUs... Next CPU: DerivO3CPU -info: Entering event queue @ 2400708269500. Starting simulation... +info: Entering event queue @ 2400135611000. Starting simulation... switching cpus -info: Entering event queue @ 2400708271500. Starting simulation... +info: Entering event queue @ 2400135618500. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 7a69bab79..6bf02cff4 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,175 +1,167 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.401336 # Number of seconds simulated -sim_ticks 2401336466000 # Number of ticks simulated -final_tick 2401336466000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.400708 # Number of seconds simulated +sim_ticks 2400708253000 # Number of ticks simulated +final_tick 2400708253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 184517 # Simulator instruction rate (inst/s) -host_op_rate 236966 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7343776984 # Simulator tick rate (ticks/s) -host_mem_usage 427572 # Number of bytes of host memory used -host_seconds 326.99 # Real time elapsed on the host -sim_insts 60334938 # Number of instructions simulated -sim_ops 77485485 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 71724 # Simulator instruction rate (inst/s) +host_op_rate 92116 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2854182500 # Simulator tick rate (ticks/s) +host_mem_usage 441348 # Number of bytes of host memory used +host_seconds 841.12 # Real time elapsed on the host +sim_insts 60328852 # Number of instructions simulated +sim_ops 77480507 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 500256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7098320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 503328 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7113744 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 85696 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 673152 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 178560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1305852 # Number of bytes read from this memory -system.physmem.bytes_read::total 124661996 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 500256 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 85696 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 178560 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 764512 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3746176 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1490900 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 199456 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1325460 # Number of bytes written to this memory -system.physmem.bytes_written::total 6761992 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 84352 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 676992 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 320 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 176960 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1286200 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661288 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 503328 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 84352 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 176960 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764640 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3747008 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1490172 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1326192 # Number of bytes written to this memory +system.physmem.bytes_written::total 6762824 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110945 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14067 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 111186 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1339 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10518 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2790 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20418 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512430 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58534 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 372725 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 49864 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 331365 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812488 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47814654 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1318 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10578 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 5 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2765 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20110 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58547 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 372543 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49863 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 331548 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812501 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47827166 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 208324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2955987 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 209658 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2963186 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 35687 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 280324 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 346 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 74359 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 543802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51913590 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 208324 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 35687 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 74359 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 318369 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1560038 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 620863 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 83060 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 551968 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2815929 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1560038 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47814654 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 35136 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 281997 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 73712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 535759 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51926879 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 209658 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 35136 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 73712 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 318506 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560793 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 620722 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83080 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 552417 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2817012 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560793 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47827166 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 208324 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3576850 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 209658 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3583907 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 35687 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 363384 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 346 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 74359 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1095770 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54729518 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 12617991 # Total number of read requests seen -system.physmem.writeReqs 398645 # Total number of write requests seen -system.physmem.cpureqs 54826 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 807551424 # Total number of bytes read from memory -system.physmem.bytesWritten 25513280 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 102907452 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2639540 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 35136 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 365077 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 133 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 73712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1088176 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54743891 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12544378 # Total number of read requests seen +system.physmem.writeReqs 398835 # Total number of write requests seen +system.physmem.cpureqs 54540 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 802840192 # Total number of bytes read from memory +system.physmem.bytesWritten 25525440 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 102301752 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 2640780 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 2346 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 789133 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 788799 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 788883 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 789207 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 789032 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 788708 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 788885 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 788938 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 788613 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 788036 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 788045 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 788296 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 788257 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 788088 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 788320 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 788751 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 24965 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 24839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 24775 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 25066 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 24855 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 24641 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 25248 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 25299 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 25161 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 24839 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 24628 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 24359 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 24939 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 24843 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 24962 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 25226 # Track writes on a per bank basis +system.physmem.neitherReadNorWrite 2352 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 784491 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 784138 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 784232 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 784566 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 784404 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 784106 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 784266 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 784324 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 783997 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 783399 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 783436 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 783681 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 783642 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 783494 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 783837 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 784365 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 24962 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 24829 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 24774 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 25058 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 24838 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 24650 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 24877 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 25285 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 25156 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 24816 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 24782 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 24769 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 24956 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 24888 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 24972 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 25223 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 14345 # Number of times wr buffer was full causing retry -system.physmem.totGap 2400301266000 # Total gap between requests +system.physmem.numWrRetry 14353 # Number of times wr buffer was full causing retry +system.physmem.totGap 2399673084000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 15 # Categorize read packet sizes -system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::2 14 # Categorize read packet sizes +system.physmem.readPktSize::3 12509600 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35064 # Categorize read packet sizes +system.physmem.readPktSize::6 34764 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 381229 # Categorize write packet sizes +system.physmem.writePktSize::2 381411 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17416 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 815827 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 792038 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 797714 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2998166 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2260876 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2261203 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2249594 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 49322 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 49193 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 91361 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 133530 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 91345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 6960 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 6956 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 6952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 6952 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17424 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 811080 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 787373 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 793054 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 2980679 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2247655 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2247973 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2236496 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 48996 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 48907 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 90849 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 132798 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 90866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 6937 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 6917 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 6901 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 6892 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -185,326 +177,356 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2977 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2986 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2990 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 3015 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 3013 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 3010 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 3005 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2983 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2989 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2991 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3008 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 3009 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 3006 # What write queue length does an incoming req see system.physmem.wrQLenPdf::7 3004 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 3000 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 17339 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 17335 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 17331 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 17328 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 17325 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 17317 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 17311 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 17307 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 17304 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 17300 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 17295 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 17291 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 17290 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 17286 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 14404 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 14392 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 14384 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 14356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 14354 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 14352 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 14350 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 14348 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 14346 # What write queue length does an incoming req see -system.physmem.totQLat 277202035000 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 353023032500 # Sum of mem lat for all requests -system.physmem.totBusLat 63089955000 # Total cycles spent in databus access -system.physmem.totBankLat 12731042500 # Total cycles spent in bank access -system.physmem.avgQLat 21968.79 # Average queueing delay per request -system.physmem.avgBankLat 1008.96 # Average bank access latency per request +system.physmem.wrQLenPdf::8 3001 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 17347 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 17345 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 17341 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 17336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 17328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 17325 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 17319 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 17315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 17311 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 17309 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 17305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 17301 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 17298 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 17295 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 14410 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 14399 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 14391 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 14365 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 14363 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 14361 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 14359 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 14357 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 14355 # What write queue length does an incoming req see +system.physmem.totQLat 275491085000 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 350869643750 # Sum of mem lat for all requests +system.physmem.totBusLat 62721890000 # Total cycles spent in databus access +system.physmem.totBankLat 12656668750 # Total cycles spent in bank access +system.physmem.avgQLat 21961.32 # Average queueing delay per request +system.physmem.avgBankLat 1008.95 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27977.75 # Average memory access latency -system.physmem.avgRdBW 336.29 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 10.62 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 42.85 # Average consumed read bandwidth in MB/s +system.physmem.avgMemAccLat 27970.27 # Average memory access latency +system.physmem.avgRdBW 334.42 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 10.63 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.61 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 1.10 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.71 # Data bus utilization in percentage +system.physmem.busUtil 2.70 # Data bus utilization in percentage system.physmem.avgRdQLen 0.15 # Average read queue length over time system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 12563370 # Number of row buffer hits during reads -system.physmem.writeRowHits 392291 # Number of row buffer hits during writes +system.physmem.readRowHits 12490088 # Number of row buffer hits during reads +system.physmem.writeRowHits 392491 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate 98.41 # Row buffer hit rate for writes -system.physmem.avgGap 184402.58 # Average gap between requests -system.l2c.replacements 63266 # number of replacements -system.l2c.tagsinuse 50361.629322 # Cycle average of tags in use -system.l2c.total_refs 1749187 # Total number of references to valid blocks. -system.l2c.sampled_refs 128660 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.595422 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2374413040000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36831.903030 # Average occupied blocks per requestor +system.physmem.avgGap 185400.11 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 63256 # number of replacements +system.l2c.tagsinuse 50350.042137 # Cycle average of tags in use +system.l2c.total_refs 1749849 # Total number of references to valid blocks. +system.l2c.sampled_refs 128650 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.601625 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374435455000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36844.077748 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 5145.178956 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 3770.285257 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 800.231814 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 751.654048 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.dtb.walker 12.723407 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1461.831435 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 1586.827913 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.562010 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 5153.281590 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3773.823073 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 798.045066 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 747.763007 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 4.909443 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.itb.walker 0.003957 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1438.233653 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1588.911142 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.562196 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.078509 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.057530 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.078633 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.057584 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.012211 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.011469 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.dtb.walker 0.000194 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.022306 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.024213 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.768457 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3213 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 461136 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 170235 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2537 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1106 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 134711 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 65741 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 17822 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4190 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 284203 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 137164 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290958 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597590 # number of Writeback hits -system.l2c.Writeback_hits::total 597590 # number of Writeback hits +system.l2c.occ_percent::cpu1.inst 0.012177 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.011410 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000075 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.021946 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.024245 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.768281 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8858 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3206 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 462948 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 169043 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2530 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1092 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 132569 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 65266 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18106 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4114 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 284351 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 139144 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1291227 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597831 # number of Writeback hits +system.l2c.Writeback_hits::total 597831 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 13 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 30 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61031 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 19032 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33560 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113623 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8900 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3213 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 461136 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 231266 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2537 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1106 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 134711 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 84773 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 17822 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4190 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 284203 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 170724 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404581 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8900 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3213 # number of overall hits -system.l2c.overall_hits::cpu0.inst 461136 # number of overall hits -system.l2c.overall_hits::cpu0.data 231266 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2537 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1106 # number of overall hits -system.l2c.overall_hits::cpu1.inst 134711 # number of overall hits -system.l2c.overall_hits::cpu1.data 84773 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 17822 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4190 # number of overall hits -system.l2c.overall_hits::cpu2.inst 284203 # number of overall hits -system.l2c.overall_hits::cpu2.data 170724 # number of overall hits -system.l2c.overall_hits::total 1404581 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 32 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 60787 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 19416 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33391 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113594 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8858 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3206 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 462948 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 229830 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2530 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1092 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 132569 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 84682 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 18106 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4114 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 284351 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 172535 # number of demand (read+write) hits +system.l2c.demand_hits::total 1404821 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8858 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3206 # number of overall hits +system.l2c.overall_hits::cpu0.inst 462948 # number of overall hits +system.l2c.overall_hits::cpu0.data 229830 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2530 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1092 # number of overall hits +system.l2c.overall_hits::cpu1.inst 132569 # number of overall hits +system.l2c.overall_hits::cpu1.data 84682 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 18106 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4114 # number of overall hits +system.l2c.overall_hits::cpu2.inst 284351 # number of overall hits +system.l2c.overall_hits::cpu2.data 172535 # number of overall hits +system.l2c.overall_hits::total 1404821 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.inst 7403 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 6349 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7451 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 6381 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 1339 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 1210 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.dtb.walker 13 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2790 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 2574 # number of ReadReq misses -system.l2c.ReadReq_misses::total 21682 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1194 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 5 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2765 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2549 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21668 # number of ReadReq misses system.l2c.UpgradeReq_misses::cpu0.data 1421 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 495 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2903 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 105359 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 9583 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 18426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133368 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu1.data 507 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 980 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2908 # number of UpgradeReq misses +system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses +system.l2c.SCUpgradeReq_misses::total 1 # number of SCUpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 105561 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9656 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18147 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133364 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.inst 7403 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 111708 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7451 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 111942 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 1339 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 10793 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.dtb.walker 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2790 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 21000 # number of demand (read+write) misses -system.l2c.demand_misses::total 155050 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1318 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 10850 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 5 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 2765 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 20696 # number of demand (read+write) misses +system.l2c.demand_misses::total 155032 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses -system.l2c.overall_misses::cpu0.inst 7403 # number of overall misses -system.l2c.overall_misses::cpu0.data 111708 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7451 # number of overall misses +system.l2c.overall_misses::cpu0.data 111942 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses -system.l2c.overall_misses::cpu1.inst 1339 # number of overall misses -system.l2c.overall_misses::cpu1.data 10793 # number of overall misses -system.l2c.overall_misses::cpu2.dtb.walker 13 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2790 # number of overall misses -system.l2c.overall_misses::cpu2.data 21000 # number of overall misses -system.l2c.overall_misses::total 155050 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1318 # number of overall misses +system.l2c.overall_misses::cpu1.data 10850 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 5 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu2.inst 2765 # number of overall misses +system.l2c.overall_misses::cpu2.data 20696 # number of overall misses +system.l2c.overall_misses::total 155032 # number of overall misses system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 76508500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.data 69917500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 783000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 178873500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.data 152904999 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 479056499 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2.data 69000 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 160500 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1.data 429692000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2.data 973653500 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1403345500 # number of ReadExReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 73618000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 68964500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 344500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 69000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 180915000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 155129499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 479109499 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 115000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 90000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 205000 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 433667500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 956422000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1390089500 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.inst 76508500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1.data 499609500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.dtb.walker 783000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.inst 178873500 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2.data 1126558499 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 1882401999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 73618000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 502632000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 344500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 69000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 180915000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1111551499 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1869198999 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.inst 76508500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1.data 499609500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.dtb.walker 783000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.inst 178873500 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2.data 1126558499 # number of overall miss cycles -system.l2c.overall_miss_latency::total 1882401999 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0.dtb.walker 8901 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.itb.walker 3215 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.inst 468539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 176584 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.dtb.walker 2538 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.itb.walker 1106 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 136050 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 66951 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.dtb.walker 17835 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.itb.walker 4190 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 286993 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 139738 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1312640 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 597590 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 597590 # number of Writeback accesses(hits+misses) +system.l2c.overall_miss_latency::cpu1.inst 73618000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 502632000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 344500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 69000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 180915000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1111551499 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1869198999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8859 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3208 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 470399 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 175424 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2531 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1092 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 133887 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 66460 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 18111 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4115 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 287116 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 141693 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1312895 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597831 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597831 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu0.data 1434 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 499 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 1000 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2933 # number of UpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 166390 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 28615 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 51986 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 246991 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 8901 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 3215 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 468539 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 342974 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 2538 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1106 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 136050 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 95566 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.dtb.walker 17835 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.itb.walker 4190 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 286993 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 191724 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1559631 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 8901 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 3215 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 468539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 342974 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 2538 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1106 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 136050 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 95566 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.dtb.walker 17835 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.itb.walker 4190 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 286993 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 191724 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1559631 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000622 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015800 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.035955 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009842 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.018073 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.009721 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.018420 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016518 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_accesses::cpu1.data 511 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 995 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2940 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 4 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 166348 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 29072 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 51538 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 246958 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8859 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3208 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 470399 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 341772 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2531 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1092 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 133887 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 95532 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 18111 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4115 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 287116 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 193231 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1559853 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8859 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3208 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 470399 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 341772 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2531 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1092 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 133887 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 95532 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 18111 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4115 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 287116 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 193231 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1559853 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000623 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.015840 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.036375 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.009844 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.017966 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000243 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.009630 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.017990 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016504 # miss rate for ReadReq accesses system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990934 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991984 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 0.987000 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.989772 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.633205 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.334894 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 0.354442 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539971 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000622 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015800 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.325704 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009842 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.112938 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.009721 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.109532 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.099415 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000112 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000622 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015800 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.325704 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000394 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009842 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.112938 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000729 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.009721 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.109532 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.099415 # miss rate for overall accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.992172 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.984925 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989116 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.250000 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.634579 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.332141 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.352109 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.540027 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000623 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.015840 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.327534 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.009844 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.113575 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000243 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.009630 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.107105 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.099389 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000623 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.015840 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.327534 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000395 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.009844 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.113575 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000276 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000243 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.009630 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.107105 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.099389 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 57138.536221 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.data 57783.057851 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 64112.365591 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.data 59403.651515 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 22094.663730 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 184.848485 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 69.908815 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 55.287633 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44838.985704 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52841.284055 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 10522.355438 # average ReadExReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 55855.842185 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 57759.212730 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 68900 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 69000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 65430.379747 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 60858.963907 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 22111.385407 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 226.824458 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 91.836735 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 70.495186 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44911.712925 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 52704.138425 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10423.273897 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 12140.612699 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 55855.842185 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 46325.529954 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 68900 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 69000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 65430.379747 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 53708.518506 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12056.859223 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.inst 57138.536221 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1.data 46290.141759 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 60230.769231 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.inst 64112.365591 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2.data 53645.642810 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 12140.612699 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 55855.842185 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 46325.529954 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 68900 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 69000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 65430.379747 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 53708.518506 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12056.859223 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -513,8 +535,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 58534 # number of writebacks -system.l2c.writebacks::total 58534 # number of writebacks +system.l2c.writebacks::writebacks 58547 # number of writebacks +system.l2c.writebacks::total 58547 # number of writebacks system.l2c.ReadReq_mshr_hits::cpu2.data 8 # number of ReadReq MSHR hits system.l2c.ReadReq_mshr_hits::total 8 # number of ReadReq MSHR hits system.l2c.demand_mshr_hits::cpu2.data 8 # number of demand (read+write) MSHR hits @@ -522,122 +544,142 @@ system.l2c.demand_mshr_hits::total 8 # nu system.l2c.overall_mshr_hits::cpu2.data 8 # number of overall MSHR hits system.l2c.overall_mshr_hits::total 8 # number of overall MSHR hits system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.inst 1339 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1.data 1210 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 13 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.inst 2790 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2.data 2566 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 7919 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1.data 495 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 1482 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1.data 9583 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2.data 18426 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 28009 # number of ReadExReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1318 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1194 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 5 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 2765 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2541 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 7825 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 507 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 980 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1487 # number of UpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses +system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9656 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18147 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 27803 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.inst 1339 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1.data 10793 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.dtb.walker 13 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.inst 2790 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2.data 20992 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 35928 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1318 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 10850 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 5 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 2765 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 20688 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 35628 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.inst 1339 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1.data 10793 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.dtb.walker 13 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.inst 2790 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2.data 20992 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 35928 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1318 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 10850 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 5 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 2765 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 20688 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 35628 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56251 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 59716089 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54808460 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 621263 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 144123701 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2.data 120589158 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 379914922 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4988470 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 14859457 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 310362321 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 743903257 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1054265578 # number of ReadExReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 57085318 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 54060944 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 281255 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 56251 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 146465179 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 123133891 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 381139089 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 5113480 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9800980 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14914460 # number of UpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 313418646 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 730113588 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1043532234 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56251 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.inst 59716089 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1.data 365170781 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 621263 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.inst 144123701 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2.data 864492415 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1434180500 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 57085318 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 367479590 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 281255 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 56251 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 146465179 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 853247479 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1424671323 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56251 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.inst 59716089 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1.data 365170781 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 621263 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.inst 144123701 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2.data 864492415 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1434180500 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25160642000 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26578724012 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 51739366012 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 647954364 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9829694360 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 10477648724 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25808596364 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36408418372 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 62217014736 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.018073 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018363 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.006033 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991984 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.987000 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.505285 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.334894 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.354442 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.113401 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023036 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000394 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009842 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.112938 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000729 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009721 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.109491 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023036 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 57085318 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 367479590 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 281255 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 56251 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 146465179 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 853247479 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1424671323 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25256982500 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26555773011 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51812755511 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 643112863 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 9826950545 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 10470063408 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25900095363 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 36382723556 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 62282818919 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017966 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.017933 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005960 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.992172 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.984925 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.505782 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.250000 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.332141 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.352109 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.112582 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.022841 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000395 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.009844 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.113575 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000276 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000243 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.009630 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.107064 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.022841 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45296.247934 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 46994.995323 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 47975.113272 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10077.717172 # average UpgradeReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45277.172529 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 48458.831562 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 48707.870799 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10085.759369 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10026.624157 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32386.759992 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40372.476772 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 37640.243422 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10029.899126 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 32458.434756 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40233.294098 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 37533.080387 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 44597.527259 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33834.038821 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 47789.461538 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 51657.240502 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41181.993855 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39918.183589 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 43312.077390 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 33869.086636 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56251 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 52971.131646 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41243.594306 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39987.406618 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -656,436 +698,436 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8079595 # DTB read hits -system.cpu0.dtb.read_misses 6254 # DTB read misses -system.cpu0.dtb.write_hits 6630051 # DTB write hits -system.cpu0.dtb.write_misses 2055 # DTB write misses +system.cpu0.dtb.read_hits 8066044 # DTB read hits +system.cpu0.dtb.read_misses 6218 # DTB read misses +system.cpu0.dtb.write_hits 6637384 # DTB write hits +system.cpu0.dtb.write_misses 2035 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5732 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 128 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 221 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8085849 # DTB read accesses -system.cpu0.dtb.write_accesses 6632106 # DTB write accesses +system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 8072262 # DTB read accesses +system.cpu0.dtb.write_accesses 6639419 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14709646 # DTB hits -system.cpu0.dtb.misses 8309 # DTB misses -system.cpu0.dtb.accesses 14717955 # DTB accesses -system.cpu0.itb.inst_hits 32707746 # ITB inst hits -system.cpu0.itb.inst_misses 3496 # ITB inst misses +system.cpu0.dtb.hits 14703428 # DTB hits +system.cpu0.dtb.misses 8253 # DTB misses +system.cpu0.dtb.accesses 14711681 # DTB accesses +system.cpu0.itb.inst_hits 32696148 # ITB inst hits +system.cpu0.itb.inst_misses 3481 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 718 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 692 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2601 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2588 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32711242 # ITB inst accesses -system.cpu0.itb.hits 32707746 # DTB hits -system.cpu0.itb.misses 3496 # DTB misses -system.cpu0.itb.accesses 32711242 # DTB accesses -system.cpu0.numCycles 113988289 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32699629 # ITB inst accesses +system.cpu0.itb.hits 32696148 # DTB hits +system.cpu0.itb.misses 3481 # DTB misses +system.cpu0.itb.accesses 32699629 # DTB accesses +system.cpu0.numCycles 114001235 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 32205724 # Number of instructions committed -system.cpu0.committedOps 42407604 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37554027 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5120 # Number of float alu accesses -system.cpu0.num_func_calls 1187729 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4239348 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37554027 # number of integer instructions -system.cpu0.num_fp_insts 5120 # number of float instructions -system.cpu0.num_int_register_reads 191333530 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39644160 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3702 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1420 # number of times the floating registers were written -system.cpu0.num_mem_refs 15372618 # number of memory refs -system.cpu0.num_load_insts 8447076 # Number of load instructions -system.cpu0.num_store_insts 6925542 # Number of store instructions -system.cpu0.num_idle_cycles 13415449988.373053 # Number of idle cycles -system.cpu0.num_busy_cycles -13301461699.373053 # Number of busy cycles -system.cpu0.not_idle_fraction -116.691476 # Percentage of non-idle cycles -system.cpu0.idle_fraction 117.691476 # Percentage of idle cycles +system.cpu0.committedInsts 32202356 # Number of instructions committed +system.cpu0.committedOps 42405748 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37555932 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5136 # Number of float alu accesses +system.cpu0.num_func_calls 1189098 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4237826 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37555932 # number of integer instructions +system.cpu0.num_fp_insts 5136 # number of float instructions +system.cpu0.num_int_register_reads 191328019 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39633304 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3646 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu0.num_mem_refs 15368046 # number of memory refs +system.cpu0.num_load_insts 8434010 # Number of load instructions +system.cpu0.num_store_insts 6934036 # Number of store instructions +system.cpu0.num_idle_cycles 13414288023.648659 # Number of idle cycles +system.cpu0.num_busy_cycles -13300286788.648659 # Number of busy cycles +system.cpu0.not_idle_fraction -116.667918 # Percentage of non-idle cycles +system.cpu0.idle_fraction 117.667918 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 82896 # number of quiesce instructions executed -system.cpu0.icache.replacements 892496 # number of replacements -system.cpu0.icache.tagsinuse 511.604237 # Cycle average of tags in use -system.cpu0.icache.total_refs 44360992 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 893008 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 49.675918 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 8108819000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 478.427369 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 17.974038 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu2.inst 15.202829 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.934428 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.035106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu2.inst 0.029693 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.999227 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 32241170 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8377396 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3742426 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 44360992 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 32241170 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8377396 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3742426 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 44360992 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 32241170 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8377396 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3742426 # number of overall hits -system.cpu0.icache.overall_hits::total 44360992 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 469261 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 136323 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 311228 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916812 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 469261 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 136323 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 311228 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 916812 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 469261 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 136323 # number of overall misses -system.cpu0.icache.overall_misses::cpu2.inst 311228 # number of overall misses -system.cpu0.icache.overall_misses::total 916812 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1838935000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4152917486 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5991852486 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 1838935000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu2.inst 4152917486 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5991852486 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 1838935000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu2.inst 4152917486 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5991852486 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 32710431 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 8513719 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu2.inst 4053654 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 45277804 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 32710431 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 8513719 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu2.inst 4053654 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 45277804 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 32710431 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 8513719 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu2.inst 4053654 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 45277804 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014346 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016012 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076777 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.020249 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014346 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016012 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076777 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.020249 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014346 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016012 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076777 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.020249 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13489.543217 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13343.649948 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 6535.530170 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 6535.530170 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13489.543217 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13343.649948 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 6535.530170 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 3861 # number of cycles access was blocked +system.cpu0.kern.inst.quiesce 82893 # number of quiesce instructions executed +system.cpu0.icache.replacements 892329 # number of replacements +system.cpu0.icache.tagsinuse 511.602586 # Cycle average of tags in use +system.cpu0.icache.total_refs 44224471 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 892841 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 49.532303 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 8120621000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 478.364653 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 17.665639 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 15.572294 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.934306 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.034503 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.030415 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 32227698 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8245303 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3751470 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 44224471 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 32227698 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8245303 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3751470 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 44224471 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 32227698 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8245303 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3751470 # number of overall hits +system.cpu0.icache.overall_hits::total 44224471 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 471122 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 134159 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 311537 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 916818 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 471122 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 134159 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 311537 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 916818 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 471122 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 134159 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 311537 # number of overall misses +system.cpu0.icache.overall_misses::total 916818 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1808055500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4158384493 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5966439993 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1808055500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4158384493 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5966439993 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1808055500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4158384493 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5966439993 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 32698820 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8379462 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 4063007 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 45141289 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 32698820 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8379462 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 4063007 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 45141289 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 32698820 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8379462 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 4063007 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 45141289 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014408 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.016010 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076676 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020310 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014408 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.016010 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076676 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020310 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014408 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.016010 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076676 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020310 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13476.960174 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13347.963462 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6507.769255 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6507.769255 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13476.960174 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13347.963462 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6507.769255 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 5517 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 220 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 195 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 17.550000 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 28.292308 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23796 # number of ReadReq MSHR hits -system.cpu0.icache.ReadReq_mshr_hits::total 23796 # number of ReadReq MSHR hits -system.cpu0.icache.demand_mshr_hits::cpu2.inst 23796 # number of demand (read+write) MSHR hits -system.cpu0.icache.demand_mshr_hits::total 23796 # number of demand (read+write) MSHR hits -system.cpu0.icache.overall_mshr_hits::cpu2.inst 23796 # number of overall MSHR hits -system.cpu0.icache.overall_mshr_hits::total 23796 # number of overall MSHR hits -system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 136323 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287432 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 423755 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu1.inst 136323 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu2.inst 287432 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 423755 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu1.inst 136323 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu2.inst 287432 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 423755 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1566289000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3388078986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4954367986 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1566289000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3388078986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4954367986 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1566289000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3388078986 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4954367986 # number of overall MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009359 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.009359 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016012 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070907 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.009359 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.585907 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11489.543217 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11787.410539 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.585907 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 23964 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 23964 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 23964 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 23964 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 23964 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 23964 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 134159 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 287573 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 421732 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 134159 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 287573 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 421732 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 134159 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 287573 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 421732 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1539737500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3392264993 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4932002493 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1539737500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3392264993 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4932002493 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1539737500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3392264993 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4932002493 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009342 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009342 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.016010 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070778 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009342 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11694.636625 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11476.960174 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11796.187379 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11694.636625 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 629752 # number of replacements -system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use -system.cpu0.dcache.total_refs 23211225 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 630264 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 36.827782 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 630023 # number of replacements +system.cpu0.dcache.tagsinuse 511.997115 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23223254 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630535 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.831031 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.729006 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu1.data 9.821503 # Average occupied blocks per requestor -system.cpu0.dcache.occ_blocks::cpu2.data 6.446607 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.968221 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu1.data 0.019183 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::cpu2.data 0.012591 # Average percentage of cache occupancy +system.cpu0.dcache.occ_blocks::cpu0.data 495.880002 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 9.605532 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.511582 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.968516 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.018761 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012718 # Average percentage of cache occupancy system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6959921 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1905228 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4437258 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13302407 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5951579 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1349529 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2119159 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9420267 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131066 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34182 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72930 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238178 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137461 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35898 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74040 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247399 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12911500 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3254757 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6556417 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22722674 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12911500 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3254757 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6556417 # number of overall hits -system.cpu0.dcache.overall_hits::total 22722674 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 170189 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 65235 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 281776 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 517200 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 167824 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 29114 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 599232 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 796170 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6395 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1716 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3875 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11986 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 338013 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 94349 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 881008 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1313370 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 338013 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 94349 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 881008 # number of overall misses -system.cpu0.dcache.overall_misses::total 1313370 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 910187500 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4059279000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4969466500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 718682500 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 18333372895 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 19052055395 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22464000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52254000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 74718000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1628870000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 22392651895 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 24021521895 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1628870000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 22392651895 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 24021521895 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7130110 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1970463 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4719034 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13819607 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6119403 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1378643 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2718391 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216437 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137461 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35898 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76805 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250164 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137461 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35898 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74042 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247401 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13249513 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3349106 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7437425 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24036044 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13249513 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3349106 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7437425 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24036044 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023869 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033106 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059711 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.037425 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027425 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021118 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220436 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.077930 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046522 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047802 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050452 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047913 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025511 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028171 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118456 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054642 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025511 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028171 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.118456 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054642 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13952.441174 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14406.049486 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9608.403906 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24685.117126 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30594.782814 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 23929.632359 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13090.909091 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13484.903226 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6233.772735 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 18289.988271 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17264.305928 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25417.081224 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 18289.988271 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 9551 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 1722 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 1090 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.762385 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 37.434783 # average number of cycles each access was blocked +system.cpu0.dcache.ReadReq_hits::cpu0.data 6947766 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1882163 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4477345 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13307274 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5958886 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1342354 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2125973 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9427213 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131324 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 34069 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 72982 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238375 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137698 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 35791 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 73904 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247393 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12906652 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3224517 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6603318 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22734487 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12906652 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3224517 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6603318 # number of overall hits +system.cpu0.dcache.overall_hits::total 22734487 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 169050 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 64738 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 285084 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 518872 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167782 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 29583 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 591784 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 789149 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6374 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1722 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3871 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11967 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 4 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 4 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 336832 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 94321 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 876868 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1308021 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 336832 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 94321 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 876868 # number of overall misses +system.cpu0.dcache.overall_misses::total 1308021 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 902894500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 4121906000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 5024800500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 728179000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 17993273399 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 18721452399 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22543500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 52244000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 74787500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 64000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 64000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1631073500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 22115179399 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 23746252899 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1631073500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 22115179399 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 23746252899 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7116816 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1946901 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4762429 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13826146 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6126668 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1371937 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2717757 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216362 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137698 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 35791 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 76853 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250342 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137698 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 35791 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 73908 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 247397 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13243484 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3318838 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7480186 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24042508 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13243484 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3318838 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7480186 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24042508 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.023754 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033252 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.059861 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037528 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027386 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021563 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.217747 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077244 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046290 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.048113 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.050369 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047803 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.025434 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028420 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.117225 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054405 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.025434 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028420 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.117225 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054405 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 13946.901356 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14458.566598 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9684.084900 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 24614.778758 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 30405.136670 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 23723.596430 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13091.463415 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13496.254198 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6249.477730 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18154.336130 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17292.792697 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 25220.648261 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18154.336130 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8894 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 919 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1121 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 44 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 7.933988 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.886364 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597590 # number of writebacks -system.cpu0.dcache.writebacks::total 597590 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145454 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 145454 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 546284 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 546284 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 421 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 421 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 691738 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 691738 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 691738 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 691738 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 65235 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 136322 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 201557 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29114 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52948 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 82062 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1716 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3454 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5170 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu1.data 94349 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu2.data 189270 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 283619 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu1.data 94349 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu2.data 189270 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 283619 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 779717500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1769361500 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2549079000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 660454500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1423557990 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2084012490 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19032000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40419500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59451500 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1440172000 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3192919490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 4633091490 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1440172000 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3192919490 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 4633091490 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27487398000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29017842000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56505240000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1281263000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147361293 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15428624293 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28768661000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43165203293 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71933864293 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033106 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.028888 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014585 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021118 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019478 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008032 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047802 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.044971 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020666 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011800 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028171 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025448 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011800 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11952.441174 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12979.280674 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12646.938583 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22685.117126 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26885.963398 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25395.584924 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11090.909091 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11702.229299 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11499.323017 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15264.305928 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16869.654409 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16335.617466 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597831 # number of writebacks +system.cpu0.dcache.writebacks::total 597831 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 146824 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 146824 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 539280 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 539280 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 409 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 409 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 686104 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 686104 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 686104 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 686104 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 64738 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 138260 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 202998 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 29583 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52504 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 82087 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1722 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3462 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5184 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 4 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 94321 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 190764 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 285085 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 94321 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 190764 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 285085 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 773418500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1795552000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2568970500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 669013000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1403739991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2072752991 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19099500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 40608500 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 59708000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1442431500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3199291991 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4641723491 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1442431500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3199291991 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4641723491 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27592956500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28992541000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56585497500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1276098000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 14147117763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 15423215763 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28869054500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 43139658763 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 72008713263 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033252 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.029031 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014682 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021563 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019319 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008035 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048113 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.045047 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020708 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011858 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028420 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.025503 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011858 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11946.901356 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12986.778533 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12655.151775 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 22614.778758 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 26735.867572 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 25250.685139 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11091.463415 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11729.780474 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11517.746914 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15292.792697 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 16770.942059 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16281.893088 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1098,388 +1140,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2185339 # DTB read hits -system.cpu1.dtb.read_misses 2099 # DTB read misses -system.cpu1.dtb.write_hits 1465312 # DTB write hits -system.cpu1.dtb.write_misses 382 # DTB write misses +system.cpu1.dtb.read_hits 2162379 # DTB read hits +system.cpu1.dtb.read_misses 2097 # DTB read misses +system.cpu1.dtb.write_hits 1458481 # DTB write hits +system.cpu1.dtb.write_misses 389 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID -system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1728 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1709 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 70 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2187438 # DTB read accesses -system.cpu1.dtb.write_accesses 1465694 # DTB write accesses +system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2164476 # DTB read accesses +system.cpu1.dtb.write_accesses 1458870 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3650651 # DTB hits -system.cpu1.dtb.misses 2481 # DTB misses -system.cpu1.dtb.accesses 3653132 # DTB accesses -system.cpu1.itb.inst_hits 8513719 # ITB inst hits -system.cpu1.itb.inst_misses 1131 # ITB inst misses +system.cpu1.dtb.hits 3620860 # DTB hits +system.cpu1.dtb.misses 2486 # DTB misses +system.cpu1.dtb.accesses 3623346 # DTB accesses +system.cpu1.itb.inst_hits 8379462 # ITB inst hits +system.cpu1.itb.inst_misses 1132 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID -system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 841 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_tlb_mva_asid 242 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 830 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8514850 # ITB inst accesses -system.cpu1.itb.hits 8513719 # DTB hits -system.cpu1.itb.misses 1131 # DTB misses -system.cpu1.itb.accesses 8514850 # DTB accesses -system.cpu1.numCycles 574637078 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8380594 # ITB inst accesses +system.cpu1.itb.hits 8379462 # DTB hits +system.cpu1.itb.misses 1132 # DTB misses +system.cpu1.itb.accesses 8380594 # DTB accesses +system.cpu1.numCycles 573333879 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 8294211 # Number of instructions committed -system.cpu1.committedOps 10531754 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9421872 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2078 # Number of float alu accesses -system.cpu1.num_func_calls 319530 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1158784 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9421872 # number of integer instructions -system.cpu1.num_fp_insts 2078 # number of float instructions -system.cpu1.num_int_register_reads 54337439 # number of times the integer registers were read -system.cpu1.num_int_register_writes 10233618 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1565 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3824850 # number of memory refs -system.cpu1.num_load_insts 2281405 # Number of load instructions -system.cpu1.num_store_insts 1543445 # Number of store instructions -system.cpu1.num_idle_cycles 540667957.850120 # Number of idle cycles -system.cpu1.num_busy_cycles 33969120.149880 # Number of busy cycles -system.cpu1.not_idle_fraction 0.059114 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.940886 # Percentage of idle cycles +system.cpu1.committedInsts 8178203 # Number of instructions committed +system.cpu1.committedOps 10418210 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9330752 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1998 # Number of float alu accesses +system.cpu1.num_func_calls 315480 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1141385 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9330752 # number of integer instructions +system.cpu1.num_fp_insts 1998 # number of float instructions +system.cpu1.num_int_register_reads 53785556 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10103056 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1549 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written +system.cpu1.num_mem_refs 3793769 # number of memory refs +system.cpu1.num_load_insts 2257716 # Number of load instructions +system.cpu1.num_store_insts 1536053 # Number of store instructions +system.cpu1.num_idle_cycles 537669981.200710 # Number of idle cycles +system.cpu1.num_busy_cycles 35663897.799290 # Number of busy cycles +system.cpu1.not_idle_fraction 0.062204 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.937796 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4687055 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3808844 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 220686 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3132450 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2515746 # Number of BTB hits +system.cpu2.branchPred.lookups 4726334 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843092 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222010 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 2958856 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2529751 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.312407 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 409998 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21415 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 85.497604 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412073 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21648 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10844149 # DTB read hits -system.cpu2.dtb.read_misses 22603 # DTB read misses -system.cpu2.dtb.write_hits 3263914 # DTB write hits -system.cpu2.dtb.write_misses 5857 # DTB write misses +system.cpu2.dtb.read_hits 10884010 # DTB read hits +system.cpu2.dtb.read_misses 22849 # DTB read misses +system.cpu2.dtb.write_hits 3265307 # DTB write hits +system.cpu2.dtb.write_misses 5901 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID -system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2308 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 825 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 2317 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 675 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 176 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 466 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10866752 # DTB read accesses -system.cpu2.dtb.write_accesses 3269771 # DTB write accesses +system.cpu2.dtb.perms_faults 462 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10906859 # DTB read accesses +system.cpu2.dtb.write_accesses 3271208 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14108063 # DTB hits -system.cpu2.dtb.misses 28460 # DTB misses -system.cpu2.dtb.accesses 14136523 # DTB accesses -system.cpu2.itb.inst_hits 4055013 # ITB inst hits -system.cpu2.itb.inst_misses 4560 # ITB inst misses +system.cpu2.dtb.hits 14149317 # DTB hits +system.cpu2.dtb.misses 28750 # DTB misses +system.cpu2.dtb.accesses 14178067 # DTB accesses +system.cpu2.itb.inst_hits 4064296 # ITB inst hits +system.cpu2.itb.inst_misses 4509 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 500 # Number of times TLB was flushed by MVA & ASID -system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1575 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_tlb_mva_asid 505 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1562 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1017 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 968 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4059573 # ITB inst accesses -system.cpu2.itb.hits 4055013 # DTB hits -system.cpu2.itb.misses 4560 # DTB misses -system.cpu2.itb.accesses 4059573 # DTB accesses -system.cpu2.numCycles 88254759 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4068805 # ITB inst accesses +system.cpu2.itb.hits 4064296 # DTB hits +system.cpu2.itb.misses 4509 # DTB misses +system.cpu2.itb.accesses 4068805 # DTB accesses +system.cpu2.numCycles 88279018 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9429776 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32237470 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4687055 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2925744 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6801535 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1807730 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 51877 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19337159 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 319 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 987 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33898 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 57137 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 401 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4053658 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 309769 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36952841 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.047181 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.432989 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9458864 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32433194 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4726334 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2941824 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6832879 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1816174 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51286 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19337351 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 2080 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 975 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33815 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 56915 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 312 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4063011 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 310021 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1911 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37021672 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.050656 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.436806 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30156381 81.61% 81.61% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 380935 1.03% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 507291 1.37% 84.01% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 812322 2.20% 86.21% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 657376 1.78% 87.99% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 343317 0.93% 88.92% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1003055 2.71% 91.63% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 237893 0.64% 92.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2854271 7.72% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30193705 81.56% 81.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 383800 1.04% 82.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 509282 1.38% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 813035 2.20% 86.17% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 655040 1.77% 87.93% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344627 0.93% 88.87% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1013096 2.74% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 238978 0.65% 92.25% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2870109 7.75% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36952841 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053108 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.365277 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 10041048 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19275643 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6155197 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 292391 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1187539 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 608222 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53447 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36559853 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 181421 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1187539 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10612647 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6555727 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11181502 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5856266 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1558172 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34319277 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2410 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 422959 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 872955 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 107 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 36779919 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 156919879 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 156892837 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 27042 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 25654971 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 11124947 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231561 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 207869 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3330119 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6484809 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3835337 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 528235 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 785937 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 31561835 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 513874 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34144653 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 53839 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7344925 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19731311 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 156774 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36952841 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.924006 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.578400 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37021672 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053539 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367394 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 10074280 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19273281 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6183203 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 295071 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1194753 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 612486 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53708 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36748038 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 181597 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1194753 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10649029 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6564844 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11163009 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5883991 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1564995 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34501786 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2424 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 422794 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 878812 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 93 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37014698 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 157694934 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 157667196 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27738 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 25798325 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11216372 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 231057 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 207527 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3357295 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6536002 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3838530 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 533894 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 787090 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 31736542 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511835 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34275347 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54662 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7411950 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19918044 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 155690 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37021672 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.925818 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.580792 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24411645 66.06% 66.06% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3911686 10.59% 76.65% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2348900 6.36% 83.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1966009 5.32% 88.32% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2782600 7.53% 95.85% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 888012 2.40% 98.26% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 476049 1.29% 99.55% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 133134 0.36% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34806 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24452597 66.05% 66.05% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3909614 10.56% 76.61% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2349010 6.34% 82.95% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1972018 5.33% 88.28% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2798812 7.56% 95.84% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 886009 2.39% 98.23% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 484017 1.31% 99.54% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 134496 0.36% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 35099 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36952841 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37021672 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 16764 1.09% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.09% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407478 91.75% 92.84% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109853 7.16% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 18701 1.22% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.22% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1408658 91.63% 92.85% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 109949 7.15% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61419 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19283233 56.48% 56.65% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 25726 0.08% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 370 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.73% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11342799 33.22% 89.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3431088 10.05% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61376 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19371931 56.52% 56.70% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 25889 0.08% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.77% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11383572 33.21% 89.99% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3432179 10.01% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34144653 # Type of FU issued -system.cpu2.iq.rate 0.386887 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1534095 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044929 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 106851627 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39425823 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 27268218 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6778 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3706 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3093 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 35613758 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3571 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 205973 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34275347 # Type of FU issued +system.cpu2.iq.rate 0.388262 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1537308 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044852 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 107186070 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39665615 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 27402348 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6887 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3783 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3156 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 35747644 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3635 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 208180 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1568043 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1874 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9216 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 577978 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1582611 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1901 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9388 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 582353 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5372164 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 352557 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5366761 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 352360 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1187539 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 4864839 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 90375 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32148379 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60078 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6484809 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3835337 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 371219 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 30634 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2404 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9216 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 105461 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 87459 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 192920 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33152533 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11055310 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 992120 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1194753 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4874895 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 91791 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32329432 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60600 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6536002 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3838530 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 369520 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31433 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2533 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9388 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 105889 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 88624 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 194513 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33284218 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11095059 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 991129 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 72670 # number of nop insts executed -system.cpu2.iew.exec_refs 14453415 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3670278 # Number of branches executed -system.cpu2.iew.exec_stores 3398105 # Number of stores executed -system.cpu2.iew.exec_rate 0.375646 # Inst execution rate -system.cpu2.iew.wb_sent 32735616 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 27271311 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 15591378 # num instructions producing a value -system.cpu2.iew.wb_consumers 28369462 # num instructions consuming a value +system.cpu2.iew.exec_nop 81055 # number of nop insts executed +system.cpu2.iew.exec_refs 14494094 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3696710 # Number of branches executed +system.cpu2.iew.exec_stores 3399035 # Number of stores executed +system.cpu2.iew.exec_rate 0.377034 # Inst execution rate +system.cpu2.iew.wb_sent 32864100 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 27405504 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 15677727 # num instructions producing a value +system.cpu2.iew.wb_consumers 28502633 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.309007 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.549583 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.310442 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.550045 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7280422 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 357100 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 167971 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35765164 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.687670 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.714660 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7348668 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356145 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 169071 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35826783 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.689728 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.717733 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27144865 75.90% 75.90% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4185503 11.70% 87.60% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1252343 3.50% 91.10% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 650255 1.82% 92.92% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 570350 1.59% 94.51% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 312906 0.87% 95.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 397008 1.11% 96.50% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 289788 0.81% 97.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 962146 2.69% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27184585 75.88% 75.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4182145 11.67% 87.55% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1258559 3.51% 91.06% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 654760 1.83% 92.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 571167 1.59% 94.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 316320 0.88% 95.37% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 401210 1.12% 96.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 290625 0.81% 97.30% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 967412 2.70% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35765164 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 19883492 # Number of instructions committed -system.cpu2.commit.committedOps 24594616 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35826783 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20002486 # Number of instructions committed +system.cpu2.commit.committedOps 24710742 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8174125 # Number of memory references committed -system.cpu2.commit.loads 4916766 # Number of loads committed -system.cpu2.commit.membars 94500 # Number of memory barriers committed -system.cpu2.commit.branches 3146107 # Number of branches committed -system.cpu2.commit.fp_insts 3055 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 21842455 # Number of committed integer instructions. -system.cpu2.commit.function_calls 293773 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 962146 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8209568 # Number of memory references committed +system.cpu2.commit.loads 4953391 # Number of loads committed +system.cpu2.commit.membars 94240 # Number of memory barriers committed +system.cpu2.commit.branches 3168906 # Number of branches committed +system.cpu2.commit.fp_insts 3119 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 21931175 # Number of committed integer instructions. +system.cpu2.commit.function_calls 294969 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 967412 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66150526 # The number of ROB reads -system.cpu2.rob.rob_writes 64978873 # The number of ROB writes -system.cpu2.timesIdled 360296 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51301918 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3567267972 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 19835003 # Number of Instructions Simulated -system.cpu2.committedOps 24546127 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 19835003 # Number of Instructions Simulated -system.cpu2.cpi 4.449445 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.449445 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.224747 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.224747 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 153135451 # number of integer regfile reads -system.cpu2.int_regfile_writes 29084509 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22287 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20832 # number of floating regfile writes -system.cpu2.misc_regfile_reads 8972562 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241289 # number of misc regfile writes +system.cpu2.rob.rob_reads 66393860 # The number of ROB reads +system.cpu2.rob.rob_writes 65354684 # The number of ROB writes +system.cpu2.timesIdled 360581 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51257346 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3567291742 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 19948293 # Number of Instructions Simulated +system.cpu2.committedOps 24656549 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 19948293 # Number of Instructions Simulated +system.cpu2.cpi 4.425392 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.425392 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.225969 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.225969 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 153783407 # number of integer regfile reads +system.cpu2.int_regfile_writes 29255277 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22374 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9021581 # number of misc regfile reads +system.cpu2.misc_regfile_writes 240632 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1494,10 +1536,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 981130976648 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 981130976648 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 981130976648 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 981130976648 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 975317722127 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 975317722127 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 975317722127 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 975317722127 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |