diff options
| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:52 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2013-01-07 13:05:52 -0500 |
| commit | 5fb00e1df6b2b7d9db472d0c25765263ed1b839f (patch) | |
| tree | 2f94ca554d9f92d1fe737ed98931856e43b52f6a /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | e09e9fa279dec86b171b5e3efeb7057fa0d21cc9 (diff) | |
| download | gem5-5fb00e1df6b2b7d9db472d0c25765263ed1b839f.tar.xz | |
tests: Add CPU switching tests
This changeset adds a set of tests that stress the CPU switching
code. It adds the following test configurations:
* tsunami-switcheroo-full -- Alpha system (atomic, timing, O3)
* realview-switcheroo-atomic -- ARM system (atomic<->atomic)
* realview-switcheroo-timing -- ARM system (timing<->timing)
* realview-switcheroo-o3 -- ARM system (O3<->O3)
* realview-switcheroo-full -- ARM system (atomic, timing, O3)
Reference data is provided for the 10.linux-boot test case. All of the
tests trigger a CPU switch once per millisecond during the boot
process.
The in-order CPU model was not included in any of the tests as it does
not support CPU handover.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
5 files changed, 6910 insertions, 0 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini new file mode 100644 index 000000000..fbde95c56 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -0,0 +1,1204 @@ +[root] +type=Root +children=system +full_system=true +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=LinuxArmSystem +children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +atags_addr=256 +boot_loader=/arm/scratch/sysexplr/dist/binaries/boot.arm +boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +clock=1000 +dtb_filename= +early_kernel_symbols=false +enable_context_switch_stats_dump=false +flags_addr=268435504 +gic_cpu_addr=520093952 +init_param=0 +kernel=/arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +load_addr_mask=268435455 +machine_type=RealView_PBX +mem_mode=atomic +mem_ranges=0:134217727 +memories=system.physmem system.realview.nvmem +multi_proc=true +num_work_ids=16 +panic_on_oops=true +panic_on_panic=true +readfile=tests/halt.sh +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[0] + +[system.bridge] +type=Bridge +clock=1000 +delay=50000 +ranges=268435456:520093695 1073741824:1610612735 +req_size=16 +resp_size=16 +master=system.iobus.slave[0] +slave=system.membus.master[0] + +[system.cf0] +type=IdeDisk +children=image +delay=1000000 +driveID=master +image=system.cf0.image + +[system.cf0.image] +type=CowDiskImage +children=child +child=system.cf0.image.child +image_file= +read_only=false +table_size=65536 + +[system.cf0.image.child] +type=RawDiskImage +image_file=/arm/scratch/sysexplr/dist/disks/linux-arm-ael.img +read_only=true + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts isa itb tracer +checker=Null +clock=500 +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +switched_out=false +system=system +tracer=system.cpu0.tracer +width=1 +workload= +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +size=32768 +system=system +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=2 +is_top_level=true +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +size=32768 +system=system +tgts_per_mshr=20 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=ArmInterrupts + +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + +[system.cpu0.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu1] +type=TimingSimpleCPU +children=dtb interrupts isa itb tracer +checker=Null +clock=500 +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +isa=system.cpu1.isa +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +switched_out=true +system=system +tracer=system.cpu1.tracer +workload= + +[system.cpu1.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system + +[system.cpu1.interrupts] +type=ArmInterrupts + +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + +[system.cpu1.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=DerivO3CPU +children=dtb fuPool interrupts isa itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu2.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu2.interrupts +isa=system.cpu2.isa +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu2.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +switched_out=true +system=system +tracer=system.cpu2.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload= + +[system.cpu2.dtb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system + +[system.cpu2.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 + +[system.cpu2.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu2.fuPool.FUList0.opList + +[system.cpu2.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu2.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 + +[system.cpu2.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu2.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu2.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 + +[system.cpu2.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu2.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu2.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu2.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 + +[system.cpu2.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu2.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu2.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu2.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu2.fuPool.FUList4.opList + +[system.cpu2.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 + +[system.cpu2.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu2.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu2.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu2.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu2.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu2.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu2.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu2.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu2.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu2.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu2.fuPool.FUList6.opList + +[system.cpu2.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 + +[system.cpu2.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu2.fuPool.FUList8.opList + +[system.cpu2.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu2.interrupts] +type=ArmInterrupts + +[system.cpu2.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + +[system.cpu2.itb] +type=ArmTLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=ArmTableWalker +clock=500 +num_squash_per_cycle=2 +sys=system + +[system.cpu2.tracer] +type=ExeTracer + +[system.intrctrl] +type=IntrControl +sys=system + +[system.iobus] +type=NoncoherentBus +block_size=64 +clock=1000 +header_cycles=1 +use_default_range=false +width=8 +master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side +slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma + +[system.iocache] +type=BaseCache +addr_ranges=0:134217727 +assoc=8 +block_size=64 +clock=1000 +forward_snoops=false +hit_latency=50 +is_top_level=true +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=50 +size=1024 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.iobus.master[25] +mem_side=system.membus.slave[2] + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +size=4194304 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.membus] +type=CoherentBus +children=badaddr_responder +block_size=64 +clock=1000 +header_cycles=1 +use_default_range=false +width=8 +default=system.membus.badaddr_responder.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +slave=system.system_port system.l2c.mem_side system.iocache.mem_side + +[system.membus.badaddr_responder] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=0 +pio_latency=100000 +pio_size=8 +ret_bad_addr=true +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access=warn +pio=system.membus.default + +[system.physmem] +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 +conf_table_reported=true +in_addr_map=true +lines_per_rowbuffer=64 +mem_sched_policy=fcfs +null=false +page_policy=open +range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 +zero=false +port=system.membus.master[2] + +[system.realview] +type=RealView +children=a9scu aaci_fake cf_ctrl clcd dmac_fake flash_fake gic gpio0_fake gpio1_fake gpio2_fake kmi0 kmi1 l2x0_fake local_cpu_timer mmc_fake nvmem realview_io rtc sci_fake smc_fake sp810_fake ssp_fake timer0 timer1 uart uart1_fake uart2_fake uart3_fake watchdog_fake +intrctrl=system.intrctrl +max_mem_size=268435456 +mem_start_addr=0 +pci_cfg_base=0 +system=system + +[system.realview.a9scu] +type=A9SCU +clock=1000 +pio_addr=520093696 +pio_latency=100000 +system=system +pio=system.membus.master[5] + +[system.realview.aaci_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268451840 +pio_latency=100000 +system=system +pio=system.iobus.master[21] + +[system.realview.cf_ctrl] +type=IdeController +BAR0=402653184 +BAR0LegacyIO=true +BAR0Size=16 +BAR1=402653440 +BAR1LegacyIO=true +BAR1Size=1 +BAR2=1 +BAR2LegacyIO=false +BAR2Size=8 +BAR3=1 +BAR3LegacyIO=false +BAR3Size=4 +BAR4=1 +BAR4LegacyIO=false +BAR4Size=16 +BAR5=1 +BAR5LegacyIO=false +BAR5Size=0 +BIST=0 +CacheLineSize=0 +CardbusCIS=0 +ClassCode=1 +Command=1 +DeviceID=28945 +ExpansionROM=0 +HeaderType=0 +InterruptLine=31 +InterruptPin=1 +LatencyTimer=0 +MaximumLatency=0 +MinimumGrant=0 +ProgIF=133 +Revision=0 +Status=640 +SubClassCode=1 +SubsystemID=0 +SubsystemVendorID=0 +VendorID=32902 +clock=1000 +config_latency=20000 +ctrl_offset=2 +disks=system.cf0 +io_shift=1 +pci_bus=2 +pci_dev=7 +pci_func=0 +pio_latency=30000 +platform=system.realview +system=system +config=system.iobus.master[8] +dma=system.iobus.slave[2] +pio=system.iobus.master[7] + +[system.realview.clcd] +type=Pl111 +amba_id=1315089 +clock=1000 +gic=system.realview.gic +int_num=55 +pio_addr=268566528 +pio_latency=10000 +pixel_clock=41667 +system=system +vnc=system.vncserver +dma=system.iobus.slave[1] +pio=system.iobus.master[4] + +[system.realview.dmac_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268632064 +pio_latency=100000 +system=system +pio=system.iobus.master[9] + +[system.realview.flash_fake] +type=IsaFake +clock=1000 +fake_mem=true +pio_addr=1073741824 +pio_latency=100000 +pio_size=536870912 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.iobus.master[24] + +[system.realview.gic] +type=Gic +clock=1000 +cpu_addr=520093952 +cpu_pio_delay=10000 +dist_addr=520097792 +dist_pio_delay=10000 +int_latency=10000 +it_lines=128 +platform=system.realview +system=system +pio=system.membus.master[3] + +[system.realview.gpio0_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268513280 +pio_latency=100000 +system=system +pio=system.iobus.master[16] + +[system.realview.gpio1_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268517376 +pio_latency=100000 +system=system +pio=system.iobus.master[17] + +[system.realview.gpio2_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268521472 +pio_latency=100000 +system=system +pio=system.iobus.master[18] + +[system.realview.kmi0] +type=Pl050 +amba_id=1314896 +clock=1000 +gic=system.realview.gic +int_delay=1000000 +int_num=52 +is_mouse=false +pio_addr=268460032 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[5] + +[system.realview.kmi1] +type=Pl050 +amba_id=1314896 +clock=1000 +gic=system.realview.gic +int_delay=1000000 +int_num=53 +is_mouse=true +pio_addr=268464128 +pio_latency=100000 +system=system +vnc=system.vncserver +pio=system.iobus.master[6] + +[system.realview.l2x0_fake] +type=IsaFake +clock=1000 +fake_mem=false +pio_addr=520101888 +pio_latency=100000 +pio_size=4095 +ret_bad_addr=false +ret_data16=65535 +ret_data32=4294967295 +ret_data64=18446744073709551615 +ret_data8=255 +system=system +update_data=false +warn_access= +pio=system.membus.master[4] + +[system.realview.local_cpu_timer] +type=CpuLocalTimer +clock=1000 +gic=system.realview.gic +int_num_timer=29 +int_num_watchdog=30 +pio_addr=520095232 +pio_latency=100000 +system=system +pio=system.membus.master[6] + +[system.realview.mmc_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268455936 +pio_latency=100000 +system=system +pio=system.iobus.master[22] + +[system.realview.nvmem] +type=SimpleMemory +bandwidth=73.000000 +clock=1000 +conf_table_reported=false +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=2147483648:2214592511 +zero=true +port=system.membus.master[1] + +[system.realview.realview_io] +type=RealViewCtrl +clock=1000 +idreg=0 +pio_addr=268435456 +pio_latency=100000 +proc_id0=201326592 +proc_id1=201327138 +system=system +pio=system.iobus.master[1] + +[system.realview.rtc] +type=PL031 +amba_id=3412017 +clock=1000 +gic=system.realview.gic +int_delay=100000 +int_num=42 +pio_addr=268529664 +pio_latency=100000 +system=system +time=Thu Jan 1 00:00:00 2009 +pio=system.iobus.master[23] + +[system.realview.sci_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268492800 +pio_latency=100000 +system=system +pio=system.iobus.master[20] + +[system.realview.smc_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=269357056 +pio_latency=100000 +system=system +pio=system.iobus.master[13] + +[system.realview.sp810_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=true +pio_addr=268439552 +pio_latency=100000 +system=system +pio=system.iobus.master[14] + +[system.realview.ssp_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268488704 +pio_latency=100000 +system=system +pio=system.iobus.master[19] + +[system.realview.timer0] +type=Sp804 +amba_id=1316868 +clock=1000 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=36 +int_num1=36 +pio_addr=268505088 +pio_latency=100000 +system=system +pio=system.iobus.master[2] + +[system.realview.timer1] +type=Sp804 +amba_id=1316868 +clock=1000 +clock0=1000000 +clock1=1000000 +gic=system.realview.gic +int_num0=37 +int_num1=37 +pio_addr=268509184 +pio_latency=100000 +system=system +pio=system.iobus.master[3] + +[system.realview.uart] +type=Pl011 +clock=1000 +end_on_eot=false +gic=system.realview.gic +int_delay=100000 +int_num=44 +pio_addr=268472320 +pio_latency=100000 +platform=system.realview +system=system +terminal=system.terminal +pio=system.iobus.master[0] + +[system.realview.uart1_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268476416 +pio_latency=100000 +system=system +pio=system.iobus.master[10] + +[system.realview.uart2_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268480512 +pio_latency=100000 +system=system +pio=system.iobus.master[11] + +[system.realview.uart3_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268484608 +pio_latency=100000 +system=system +pio=system.iobus.master[12] + +[system.realview.watchdog_fake] +type=AmbaFake +amba_id=0 +clock=1000 +ignore_access=false +pio_addr=268500992 +pio_latency=100000 +system=system +pio=system.iobus.master[15] + +[system.terminal] +type=Terminal +intr_control=system.intrctrl +number=0 +output=true +port=3456 + +[system.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=8 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port + +[system.vncserver] +type=VncServer +frame_capture=false +number=0 +port=5900 + diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr new file mode 100755 index 000000000..d34d93526 --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simerr @@ -0,0 +1,28 @@ +warn: Sockets disabled, not accepting vnc client connections +warn: Sockets disabled, not accepting terminal connections +warn: Sockets disabled, not accepting gdb connections +warn: The clidr register always reports 0 caches. +warn: clidr LoUIS field of 0b001 to match current ARM implementations. +warn: The csselr register isn't implemented. +warn: The ccsidr register isn't implemented and always reads as 0. +warn: instruction 'mcr bpiallis' unimplemented +warn: instruction 'mcr icialluis' unimplemented +hack: be nice to actually delete the event here +warn: instruction 'mcr dccimvac' unimplemented +warn: instruction 'mcr dccmvau' unimplemented +warn: instruction 'mcr icimvau' unimplemented +warn: LCD dual screen mode not supported +warn: instruction 'mcr icialluis' unimplemented +warn: instruction 'mcr bpiallis' unimplemented +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR +warn: User mode does not have SPSR diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout new file mode 100755 index 000000000..f0052292c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -0,0 +1,4106 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Dec 11 2012 16:28:23 +gem5 started Dec 11 2012 16:28:35 +gem5 executing on e103721-lin +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +Global frequency set at 1000000000000 ticks per second +info: kernel located at: /arm/scratch/sysexplr/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: Using bootloader at address 0x80000000 +info: Entering event queue @ 0. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1000000000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2000000000. Starting simulation... +switching cpus +info: Entering event queue @ 2000001000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 3000001000. Starting simulation... +switching cpus +info: Entering event queue @ 3000008500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 4000008500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 5000008500. Starting simulation... +switching cpus +info: Entering event queue @ 5000009000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 6000009000. Starting simulation... +switching cpus +info: Entering event queue @ 6000041500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 7000041500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 8000041500. Starting simulation... +switching cpus +info: Entering event queue @ 8000042500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 9000042500. Starting simulation... +info: Entering event queue @ 9000050500. Starting simulation... +info: Entering event queue @ 9000061000. Starting simulation... +switching cpus +info: Entering event queue @ 9000065500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 10000065500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 11000065500. Starting simulation... +switching cpus +info: Entering event queue @ 11000066500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 12000066500. Starting simulation... +info: Entering event queue @ 12000080000. Starting simulation... +switching cpus +info: Entering event queue @ 12000084500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 13000084500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 14000084500. Starting simulation... +switching cpus +info: Entering event queue @ 14000088000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 15000088000. Starting simulation... +switching cpus +info: Entering event queue @ 15000331000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 16000331000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 17000331000. Starting simulation... +switching cpus +info: Entering event queue @ 17000332000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 18000332000. Starting simulation... +info: Entering event queue @ 26175972000. Starting simulation... +info: Entering event queue @ 26175979000. Starting simulation... +switching cpus +info: Entering event queue @ 26175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 27175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 28175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 29175983500. Starting simulation... +info: Entering event queue @ 36175972000. Starting simulation... +info: Entering event queue @ 36175979000. Starting simulation... +switching cpus +info: Entering event queue @ 36175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 37175983500. Starting simulation... +switching cpus +info: Entering event queue @ 37175984000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 38175984000. Starting simulation... +info: Entering event queue @ 38175999500. Starting simulation... +switching cpus +info: Entering event queue @ 38176040500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 39176040500. Starting simulation... +switching cpus +info: Entering event queue @ 39176113500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 40176113500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 41176113500. Starting simulation... +switching cpus +info: Entering event queue @ 41176114500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 42176114500. Starting simulation... +switching cpus +info: Entering event queue @ 42176477500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 43176477500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 44176477500. Starting simulation... +switching cpus +info: Entering event queue @ 44176479000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 45176479000. Starting simulation... +info: Entering event queue @ 45176488000. Starting simulation... +switching cpus +info: Entering event queue @ 45176492500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 46176492500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 47176492500. Starting simulation... +info: Entering event queue @ 47176497000. Starting simulation... +switching cpus +info: Entering event queue @ 47176499500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 48176499500. Starting simulation... +info: Entering event queue @ 48176506500. Starting simulation... +info: Entering event queue @ 48176516500. Starting simulation... +info: Entering event queue @ 48176521000. Starting simulation... +switching cpus +info: Entering event queue @ 48176522000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 49176522000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 50176522000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 51176522000. Starting simulation... +info: Entering event queue @ 56175972000. Starting simulation... +info: Entering event queue @ 56175979000. Starting simulation... +switching cpus +info: Entering event queue @ 56175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 57175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 58175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 59175983500. Starting simulation... +info: Entering event queue @ 66175972000. Starting simulation... +info: Entering event queue @ 66175979000. Starting simulation... +switching cpus +info: Entering event queue @ 66175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 67175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 68175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 69175983500. Starting simulation... +info: Entering event queue @ 76175972000. Starting simulation... +info: Entering event queue @ 76175979000. Starting simulation... +switching cpus +info: Entering event queue @ 76175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 77175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 78175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 79175983500. Starting simulation... +info: Entering event queue @ 86175972000. Starting simulation... +info: Entering event queue @ 86175979000. Starting simulation... +switching cpus +info: Entering event queue @ 86175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 87175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 88175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 89175983500. Starting simulation... +info: Entering event queue @ 96175973000. Starting simulation... +info: Entering event queue @ 96175982000. Starting simulation... +switching cpus +info: Entering event queue @ 96175986500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 97175986500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 98175986500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 99175986500. Starting simulation... +info: Entering event queue @ 106175972000. Starting simulation... +info: Entering event queue @ 106175978500. Starting simulation... +switching cpus +info: Entering event queue @ 106175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 107175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 108175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 109175979000. Starting simulation... +info: Entering event queue @ 116175972000. Starting simulation... +info: Entering event queue @ 116175978500. Starting simulation... +switching cpus +info: Entering event queue @ 116175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 117175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 118175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 119175979000. Starting simulation... +info: Entering event queue @ 126175972000. Starting simulation... +info: Entering event queue @ 126175978500. Starting simulation... +switching cpus +info: Entering event queue @ 126175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 127175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 128175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 129175979000. Starting simulation... +info: Entering event queue @ 136175972000. Starting simulation... +info: Entering event queue @ 136175978500. Starting simulation... +switching cpus +info: Entering event queue @ 136175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 137175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 138175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 139175979000. Starting simulation... +info: Entering event queue @ 146175972000. Starting simulation... +info: Entering event queue @ 146175979000. Starting simulation... +switching cpus +info: Entering event queue @ 146175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 147175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 148175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 149175983500. Starting simulation... +info: Entering event queue @ 156175972000. Starting simulation... +info: Entering event queue @ 156175979000. Starting simulation... +switching cpus +info: Entering event queue @ 156175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 157175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 158175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 159175983500. Starting simulation... +info: Entering event queue @ 166175972000. Starting simulation... +info: Entering event queue @ 166175978500. Starting simulation... +switching cpus +info: Entering event queue @ 166175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 167175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 168175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 169175979000. Starting simulation... +info: Entering event queue @ 176175972000. Starting simulation... +info: Entering event queue @ 176175978500. Starting simulation... +switching cpus +info: Entering event queue @ 176175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 177175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 178175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 179175979000. Starting simulation... +info: Entering event queue @ 186175972000. Starting simulation... +info: Entering event queue @ 186175978500. Starting simulation... +switching cpus +info: Entering event queue @ 186175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 187175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 188175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 189175979000. Starting simulation... +info: Entering event queue @ 196175972000. Starting simulation... +info: Entering event queue @ 196175978500. Starting simulation... +switching cpus +info: Entering event queue @ 196175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 197175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 198175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 199175979000. Starting simulation... +info: Entering event queue @ 206175972000. Starting simulation... +info: Entering event queue @ 206175979000. Starting simulation... +switching cpus +info: Entering event queue @ 206175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 207175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 208175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 209175983500. Starting simulation... +info: Entering event queue @ 216175972000. Starting simulation... +info: Entering event queue @ 216175979000. Starting simulation... +switching cpus +info: Entering event queue @ 216175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 217175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 218175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 219175983500. Starting simulation... +info: Entering event queue @ 226175972000. Starting simulation... +info: Entering event queue @ 226175979000. Starting simulation... +switching cpus +info: Entering event queue @ 226175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 227175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 228175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 229175983500. Starting simulation... +info: Entering event queue @ 236175972000. Starting simulation... +info: Entering event queue @ 236175979000. Starting simulation... +switching cpus +info: Entering event queue @ 236175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 237175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 238175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 239175983500. Starting simulation... +info: Entering event queue @ 246175972000. Starting simulation... +info: Entering event queue @ 246175979000. Starting simulation... +switching cpus +info: Entering event queue @ 246175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 247175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 248175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 249175983500. Starting simulation... +info: Entering event queue @ 256175973000. Starting simulation... +info: Entering event queue @ 256175984500. Starting simulation... +switching cpus +info: Entering event queue @ 256175989000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 257175989000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 258175989000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 259175989000. Starting simulation... +info: Entering event queue @ 266175972000. Starting simulation... +info: Entering event queue @ 266979463000. Starting simulation... +switching cpus +info: Entering event queue @ 266979465000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 267979465000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 268979465000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 269979465000. Starting simulation... +info: Entering event queue @ 276175972000. Starting simulation... +info: Entering event queue @ 276175978500. Starting simulation... +switching cpus +info: Entering event queue @ 276175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 277175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 278175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 279175979000. Starting simulation... +info: Entering event queue @ 286175972000. Starting simulation... +info: Entering event queue @ 286175978500. Starting simulation... +switching cpus +info: Entering event queue @ 286175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 287175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 288175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 289175979000. Starting simulation... +info: Entering event queue @ 296175972000. Starting simulation... +info: Entering event queue @ 296175978500. Starting simulation... +switching cpus +info: Entering event queue @ 296175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 297175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 298175979000. Starting simulation... +info: Entering event queue @ 299715607000. Starting simulation... +switching cpus +info: Entering event queue @ 299715609000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 300715609000. Starting simulation... +info: Entering event queue @ 306175972000. Starting simulation... +info: Entering event queue @ 306175979000. Starting simulation... +switching cpus +info: Entering event queue @ 306175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 307175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 308175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 309175983500. Starting simulation... +info: Entering event queue @ 316175972000. Starting simulation... +info: Entering event queue @ 316175979000. Starting simulation... +switching cpus +info: Entering event queue @ 316175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 317175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 318175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 319175983500. Starting simulation... +info: Entering event queue @ 326175972000. Starting simulation... +info: Entering event queue @ 326175978500. Starting simulation... +switching cpus +info: Entering event queue @ 326175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 327175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 328175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 329175979000. Starting simulation... +info: Entering event queue @ 336175972000. Starting simulation... +info: Entering event queue @ 336175978500. Starting simulation... +switching cpus +info: Entering event queue @ 336175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 337175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 338175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 339175979000. Starting simulation... +info: Entering event queue @ 346175972000. Starting simulation... +info: Entering event queue @ 346175978500. Starting simulation... +switching cpus +info: Entering event queue @ 346175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 347175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 348175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 349175979000. Starting simulation... +info: Entering event queue @ 356175972000. Starting simulation... +info: Entering event queue @ 356175978500. Starting simulation... +switching cpus +info: Entering event queue @ 356175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 357175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 358175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 359175979000. Starting simulation... +info: Entering event queue @ 366175972000. Starting simulation... +info: Entering event queue @ 366175979000. Starting simulation... +switching cpus +info: Entering event queue @ 366175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 367175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 368175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 369175983500. Starting simulation... +info: Entering event queue @ 376175972000. Starting simulation... +info: Entering event queue @ 376175979000. Starting simulation... +switching cpus +info: Entering event queue @ 376175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 377175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 378175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 379175983500. Starting simulation... +info: Entering event queue @ 386175973000. Starting simulation... +info: Entering event queue @ 386175980000. Starting simulation... +switching cpus +info: Entering event queue @ 386175984500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 387175984500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 388175984500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 389175984500. Starting simulation... +switching cpus +info: Entering event queue @ 396175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 397175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 398175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 399175973000. Starting simulation... +info: Entering event queue @ 406175973000. Starting simulation... +info: Entering event queue @ 406175981500. Starting simulation... +switching cpus +info: Entering event queue @ 406175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 407175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 408175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 409175986000. Starting simulation... +info: Entering event queue @ 416175972000. Starting simulation... +info: Entering event queue @ 416175979000. Starting simulation... +switching cpus +info: Entering event queue @ 416175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 417175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 418175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 419175983500. Starting simulation... +info: Entering event queue @ 426175972000. Starting simulation... +info: Entering event queue @ 426175978500. Starting simulation... +switching cpus +info: Entering event queue @ 426175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 427175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 428175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 429175979000. Starting simulation... +info: Entering event queue @ 436175972000. Starting simulation... +info: Entering event queue @ 436175978500. Starting simulation... +switching cpus +info: Entering event queue @ 436175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 437175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 438175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 439175979000. Starting simulation... +info: Entering event queue @ 446175972000. Starting simulation... +info: Entering event queue @ 446175978500. Starting simulation... +switching cpus +info: Entering event queue @ 446175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 447175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 448175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 449175979000. Starting simulation... +info: Entering event queue @ 456175972000. Starting simulation... +info: Entering event queue @ 456175978500. Starting simulation... +switching cpus +info: Entering event queue @ 456175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 457175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 458175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 459175979000. Starting simulation... +info: Entering event queue @ 466175972000. Starting simulation... +info: Entering event queue @ 466175979000. Starting simulation... +switching cpus +info: Entering event queue @ 466175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 467175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 468175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 469175983500. Starting simulation... +info: Entering event queue @ 476175972000. Starting simulation... +info: Entering event queue @ 476175979000. Starting simulation... +switching cpus +info: Entering event queue @ 476175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 477175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 478175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 479175983500. Starting simulation... +info: Entering event queue @ 486175972000. Starting simulation... +info: Entering event queue @ 486175978500. Starting simulation... +switching cpus +info: Entering event queue @ 486175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 487175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 488175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 489175979000. Starting simulation... +info: Entering event queue @ 496175972000. Starting simulation... +info: Entering event queue @ 496175978500. Starting simulation... +switching cpus +info: Entering event queue @ 496175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 497175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 498175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 499175979000. Starting simulation... +info: Entering event queue @ 506175972000. Starting simulation... +info: Entering event queue @ 506175978500. Starting simulation... +switching cpus +info: Entering event queue @ 506175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 507175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 508175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 509175979000. Starting simulation... +info: Entering event queue @ 516175972000. Starting simulation... +info: Entering event queue @ 516175978500. Starting simulation... +switching cpus +info: Entering event queue @ 516175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 517175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 518175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 519175979000. Starting simulation... +info: Entering event queue @ 526175972000. Starting simulation... +info: Entering event queue @ 526175979000. Starting simulation... +switching cpus +info: Entering event queue @ 526175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 527175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 528175983500. Starting simulation... +info: Entering event queue @ 528869056000. Starting simulation... +switching cpus +info: Entering event queue @ 528869058000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 529869058000. Starting simulation... +info: Entering event queue @ 536175972000. Starting simulation... +info: Entering event queue @ 536175979000. Starting simulation... +switching cpus +info: Entering event queue @ 536175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 537175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 538175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 539175983500. Starting simulation... +switching cpus +info: Entering event queue @ 546175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 547175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 548175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 549175973000. Starting simulation... +info: Entering event queue @ 556175973000. Starting simulation... +info: Entering event queue @ 556175985000. Starting simulation... +switching cpus +info: Entering event queue @ 556175989500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 557175989500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 558175989500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 559175989500. Starting simulation... +switching cpus +info: Entering event queue @ 566175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 567175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 568175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 569175973000. Starting simulation... +switching cpus +info: Entering event queue @ 576175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 577175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 578175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 579175973000. Starting simulation... +switching cpus +info: Entering event queue @ 586175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 587175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 588175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 589175973000. Starting simulation... +info: Entering event queue @ 596175973000. Starting simulation... +info: Entering event queue @ 596175981500. Starting simulation... +switching cpus +info: Entering event queue @ 596175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 597175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 598175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 599175986000. Starting simulation... +switching cpus +info: Entering event queue @ 606175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 607175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 608175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 609175973000. Starting simulation... +info: Entering event queue @ 616175972000. Starting simulation... +info: Entering event queue @ 616175978500. Starting simulation... +switching cpus +info: Entering event queue @ 616175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 617175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 618175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 619175979000. Starting simulation... +info: Entering event queue @ 626175972000. Starting simulation... +info: Entering event queue @ 627078091000. Starting simulation... +switching cpus +info: Entering event queue @ 627078093000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 628078093000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 629078093000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 630078093000. Starting simulation... +info: Entering event queue @ 636175972000. Starting simulation... +info: Entering event queue @ 636175978500. Starting simulation... +switching cpus +info: Entering event queue @ 636175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 637175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 638175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 639175979000. Starting simulation... +info: Entering event queue @ 646175972000. Starting simulation... +info: Entering event queue @ 646175978500. Starting simulation... +switching cpus +info: Entering event queue @ 646175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 647175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 648175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 649175979000. Starting simulation... +info: Entering event queue @ 656175972000. Starting simulation... +info: Entering event queue @ 656175979000. Starting simulation... +switching cpus +info: Entering event queue @ 656175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 657175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 658175983500. Starting simulation... +info: Entering event queue @ 659814382000. Starting simulation... +switching cpus +info: Entering event queue @ 659814384000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 660814384000. Starting simulation... +info: Entering event queue @ 666175972000. Starting simulation... +info: Entering event queue @ 666175979000. Starting simulation... +switching cpus +info: Entering event queue @ 666175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 667175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 668175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 669175983500. Starting simulation... +info: Entering event queue @ 676175972000. Starting simulation... +info: Entering event queue @ 676175978500. Starting simulation... +switching cpus +info: Entering event queue @ 676175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 677175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 678175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 679175979000. Starting simulation... +info: Entering event queue @ 686175972000. Starting simulation... +info: Entering event queue @ 686175978500. Starting simulation... +switching cpus +info: Entering event queue @ 686175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 687175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 688175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 689175979000. Starting simulation... +info: Entering event queue @ 696175972000. Starting simulation... +info: Entering event queue @ 696175978500. Starting simulation... +switching cpus +info: Entering event queue @ 696175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 697175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 698175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 699175979000. Starting simulation... +info: Entering event queue @ 706175972000. Starting simulation... +info: Entering event queue @ 706175978500. Starting simulation... +switching cpus +info: Entering event queue @ 706175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 707175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 708175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 709175979000. Starting simulation... +info: Entering event queue @ 716175972000. Starting simulation... +info: Entering event queue @ 716175979000. Starting simulation... +switching cpus +info: Entering event queue @ 716175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 717175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 718175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 719175983500. Starting simulation... +info: Entering event queue @ 726175972000. Starting simulation... +info: Entering event queue @ 726175979000. Starting simulation... +switching cpus +info: Entering event queue @ 726175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 727175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 728175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 729175983500. Starting simulation... +info: Entering event queue @ 736175973000. Starting simulation... +info: Entering event queue @ 736175981000. Starting simulation... +switching cpus +info: Entering event queue @ 736175985500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 737175985500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 738175985500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 739175985500. Starting simulation... +info: Entering event queue @ 746175973000. Starting simulation... +info: Entering event queue @ 746175980500. Starting simulation... +switching cpus +info: Entering event queue @ 746175985000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 747175985000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 748175985000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 749175985000. Starting simulation... +info: Entering event queue @ 756175972000. Starting simulation... +info: Entering event queue @ 756175979000. Starting simulation... +switching cpus +info: Entering event queue @ 756175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 757175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 758175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 759175983500. Starting simulation... +info: Entering event queue @ 766175973000. Starting simulation... +info: Entering event queue @ 766175980000. Starting simulation... +switching cpus +info: Entering event queue @ 766175984500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 767175984500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 768175984500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 769175984500. Starting simulation... +info: Entering event queue @ 776175972000. Starting simulation... +info: Entering event queue @ 776175978500. Starting simulation... +switching cpus +info: Entering event queue @ 776175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 777175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 778175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 779175979000. Starting simulation... +info: Entering event queue @ 786175972000. Starting simulation... +info: Entering event queue @ 786175978500. Starting simulation... +switching cpus +info: Entering event queue @ 786175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 787175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 788175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 789175979000. Starting simulation... +info: Entering event queue @ 796175972000. Starting simulation... +info: Entering event queue @ 796175978500. Starting simulation... +switching cpus +info: Entering event queue @ 796175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 797175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 798175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 799175979000. Starting simulation... +info: Entering event queue @ 806175972000. Starting simulation... +info: Entering event queue @ 806175978500. Starting simulation... +switching cpus +info: Entering event queue @ 806175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 807175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 808175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 809175979000. Starting simulation... +info: Entering event queue @ 816175972000. Starting simulation... +info: Entering event queue @ 816175979000. Starting simulation... +switching cpus +info: Entering event queue @ 816175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 817175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 818175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 819175983500. Starting simulation... +info: Entering event queue @ 826175972000. Starting simulation... +info: Entering event queue @ 826175979000. Starting simulation... +switching cpus +info: Entering event queue @ 826175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 827175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 828175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 829175983500. Starting simulation... +info: Entering event queue @ 836175972000. Starting simulation... +info: Entering event queue @ 836175978500. Starting simulation... +switching cpus +info: Entering event queue @ 836175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 837175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 838175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 839175979000. Starting simulation... +info: Entering event queue @ 846175972000. Starting simulation... +info: Entering event queue @ 846175978500. Starting simulation... +switching cpus +info: Entering event queue @ 846175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 847175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 848175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 849175979000. Starting simulation... +info: Entering event queue @ 856175972000. Starting simulation... +info: Entering event queue @ 856231996000. Starting simulation... +switching cpus +info: Entering event queue @ 856231998000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 857231998000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 858231998000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 859231998000. Starting simulation... +info: Entering event queue @ 866175972000. Starting simulation... +info: Entering event queue @ 866175978500. Starting simulation... +switching cpus +info: Entering event queue @ 866175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 867175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 868175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 869175979000. Starting simulation... +info: Entering event queue @ 876175972000. Starting simulation... +info: Entering event queue @ 876175979000. Starting simulation... +switching cpus +info: Entering event queue @ 876175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 877175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 878175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 879175983500. Starting simulation... +info: Entering event queue @ 886175972000. Starting simulation... +info: Entering event queue @ 886175979000. Starting simulation... +switching cpus +info: Entering event queue @ 886175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 887175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 888175983500. Starting simulation... +info: Entering event queue @ 888968137000. Starting simulation... +switching cpus +info: Entering event queue @ 888968139000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 889968139000. Starting simulation... +info: Entering event queue @ 896175973000. Starting simulation... +info: Entering event queue @ 896175981000. Starting simulation... +switching cpus +info: Entering event queue @ 896175985500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 897175985500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 898175985500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 899175985500. Starting simulation... +switching cpus +info: Entering event queue @ 906175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 907175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 908175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 909175973000. Starting simulation... +info: Entering event queue @ 916175972000. Starting simulation... +info: Entering event queue @ 916175979000. Starting simulation... +switching cpus +info: Entering event queue @ 916175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 917175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 918175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 919175983500. Starting simulation... +info: Entering event queue @ 926175973000. Starting simulation... +info: Entering event queue @ 926175981500. Starting simulation... +switching cpus +info: Entering event queue @ 926175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 927175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 928175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 929175986000. Starting simulation... +info: Entering event queue @ 936175972000. Starting simulation... +info: Entering event queue @ 936175978500. Starting simulation... +switching cpus +info: Entering event queue @ 936175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 937175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 938175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 939175979000. Starting simulation... +info: Entering event queue @ 946175972000. Starting simulation... +info: Entering event queue @ 946175978500. Starting simulation... +switching cpus +info: Entering event queue @ 946175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 947175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 948175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 949175979000. Starting simulation... +info: Entering event queue @ 956175972000. Starting simulation... +info: Entering event queue @ 956175978500. Starting simulation... +switching cpus +info: Entering event queue @ 956175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 957175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 958175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 959175979000. Starting simulation... +info: Entering event queue @ 966175972000. Starting simulation... +info: Entering event queue @ 966175978500. Starting simulation... +switching cpus +info: Entering event queue @ 966175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 967175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 968175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 969175979000. Starting simulation... +info: Entering event queue @ 976175972000. Starting simulation... +info: Entering event queue @ 976175979000. Starting simulation... +switching cpus +info: Entering event queue @ 976175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 977175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 978175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 979175983500. Starting simulation... +info: Entering event queue @ 986175973000. Starting simulation... +info: Entering event queue @ 987176863000. Starting simulation... +switching cpus +info: Entering event queue @ 987176865000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 988176865000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 989176865000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 990176865000. Starting simulation... +info: Entering event queue @ 996175972000. Starting simulation... +info: Entering event queue @ 996175978500. Starting simulation... +switching cpus +info: Entering event queue @ 996175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 997175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 998175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 999175979000. Starting simulation... +info: Entering event queue @ 1006175972000. Starting simulation... +info: Entering event queue @ 1006175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1006175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1007175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1008175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1009175979000. Starting simulation... +info: Entering event queue @ 1016175972000. Starting simulation... +info: Entering event queue @ 1016175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1016175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1017175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1018175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1019175979000. Starting simulation... +info: Entering event queue @ 1026175972000. Starting simulation... +info: Entering event queue @ 1026175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1026175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1027175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1028175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1029175979000. Starting simulation... +info: Entering event queue @ 1036175972000. Starting simulation... +info: Entering event queue @ 1036175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1036175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1037175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1038175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1039175983500. Starting simulation... +info: Entering event queue @ 1046175972000. Starting simulation... +info: Entering event queue @ 1046175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1046175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1047175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1048175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1049175983500. Starting simulation... +info: Entering event queue @ 1056175972000. Starting simulation... +info: Entering event queue @ 1056175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1056175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1057175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1058175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1059175983500. Starting simulation... +info: Entering event queue @ 1066175972000. Starting simulation... +info: Entering event queue @ 1066175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1066175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1067175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1068175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1069175983500. Starting simulation... +info: Entering event queue @ 1076175972000. Starting simulation... +info: Entering event queue @ 1076175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1076175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1077175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1078175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1079175983500. Starting simulation... +info: Entering event queue @ 1086175973000. Starting simulation... +info: Entering event queue @ 1086175981500. Starting simulation... +switching cpus +info: Entering event queue @ 1086175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1087175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1088175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1089175986000. Starting simulation... +info: Entering event queue @ 1096175972000. Starting simulation... +info: Entering event queue @ 1096175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1096175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1097175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1098175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1099175979000. Starting simulation... +info: Entering event queue @ 1106175972000. Starting simulation... +info: Entering event queue @ 1106175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1106175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1107175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1108175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1109175979000. Starting simulation... +info: Entering event queue @ 1116175972000. Starting simulation... +info: Entering event queue @ 1116175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1116175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1117175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1118175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1119175979000. Starting simulation... +info: Entering event queue @ 1126175972000. Starting simulation... +info: Entering event queue @ 1126175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1126175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1127175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1128175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1129175979000. Starting simulation... +info: Entering event queue @ 1136175972000. Starting simulation... +info: Entering event queue @ 1136175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1136175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1137175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1138175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1139175983500. Starting simulation... +info: Entering event queue @ 1146175972000. Starting simulation... +info: Entering event queue @ 1146175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1146175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1147175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1148175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1149175983500. Starting simulation... +info: Entering event queue @ 1156175972000. Starting simulation... +info: Entering event queue @ 1156175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1156175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1157175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1158175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1159175979000. Starting simulation... +info: Entering event queue @ 1166175972000. Starting simulation... +info: Entering event queue @ 1166175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1166175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1167175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1168175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1169175979000. Starting simulation... +info: Entering event queue @ 1176175972000. Starting simulation... +info: Entering event queue @ 1176175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1176175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1177175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1178175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1179175979000. Starting simulation... +info: Entering event queue @ 1186175972000. Starting simulation... +info: Entering event queue @ 1186175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1186175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1187175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1188175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1189175979000. Starting simulation... +info: Entering event queue @ 1196175972000. Starting simulation... +info: Entering event queue @ 1196175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1196175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1197175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1198175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1199175983500. Starting simulation... +info: Entering event queue @ 1206175972000. Starting simulation... +info: Entering event queue @ 1206175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1206175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1207175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1208175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1209175983500. Starting simulation... +info: Entering event queue @ 1216175973000. Starting simulation... +info: Entering event queue @ 1216330621000. Starting simulation... +switching cpus +info: Entering event queue @ 1216330623000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1217330623000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1218330623000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1219330623000. Starting simulation... +info: Entering event queue @ 1226175973000. Starting simulation... +info: Entering event queue @ 1226175980500. Starting simulation... +switching cpus +info: Entering event queue @ 1226175985000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1227175985000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1228175985000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1229175985000. Starting simulation... +info: Entering event queue @ 1236175972000. Starting simulation... +info: Entering event queue @ 1236175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1236175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1237175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1238175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1239175983500. Starting simulation... +info: Entering event queue @ 1246175973000. Starting simulation... +info: Entering event queue @ 1246175981500. Starting simulation... +switching cpus +info: Entering event queue @ 1246175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1247175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1248175986000. Starting simulation... +info: Entering event queue @ 1249067221000. Starting simulation... +switching cpus +info: Entering event queue @ 1249067223000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1250067223000. Starting simulation... +info: Entering event queue @ 1256175972000. Starting simulation... +info: Entering event queue @ 1256175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1256175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1257175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1258175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1259175979000. Starting simulation... +info: Entering event queue @ 1266175972000. Starting simulation... +info: Entering event queue @ 1266175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1266175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1267175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1268175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1269175979000. Starting simulation... +info: Entering event queue @ 1276175972000. Starting simulation... +info: Entering event queue @ 1276175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1276175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1277175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1278175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1279175979000. Starting simulation... +info: Entering event queue @ 1286175972000. Starting simulation... +info: Entering event queue @ 1286175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1286175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1287175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1288175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1289175979000. Starting simulation... +info: Entering event queue @ 1296175972000. Starting simulation... +info: Entering event queue @ 1296175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1296175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1297175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1298175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1299175983500. Starting simulation... +info: Entering event queue @ 1306175972000. Starting simulation... +info: Entering event queue @ 1306175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1306175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1307175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1308175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1309175983500. Starting simulation... +info: Entering event queue @ 1316175972000. Starting simulation... +info: Entering event queue @ 1316175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1316175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1317175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1318175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1319175979000. Starting simulation... +info: Entering event queue @ 1326175972000. Starting simulation... +info: Entering event queue @ 1326175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1326175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1327175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1328175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1329175979000. Starting simulation... +info: Entering event queue @ 1336175972000. Starting simulation... +info: Entering event queue @ 1336175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1336175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1337175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1338175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1339175979000. Starting simulation... +info: Entering event queue @ 1346175972000. Starting simulation... +info: Entering event queue @ 1347275947000. Starting simulation... +switching cpus +info: Entering event queue @ 1347275949000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1348275949000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1349275949000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1350275949000. Starting simulation... +info: Entering event queue @ 1356175972000. Starting simulation... +info: Entering event queue @ 1356175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1356175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1357175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1358175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1359175983500. Starting simulation... +info: Entering event queue @ 1366175972000. Starting simulation... +info: Entering event queue @ 1366175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1366175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1367175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1368175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1369175983500. Starting simulation... +switching cpus +info: Entering event queue @ 1376175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1377175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1378175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1379175973000. Starting simulation... +switching cpus +info: Entering event queue @ 1386175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1387175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1388175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1389175973000. Starting simulation... +info: Entering event queue @ 1396175973000. Starting simulation... +info: Entering event queue @ 1396175981500. Starting simulation... +switching cpus +info: Entering event queue @ 1396175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1397175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1398175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1399175986000. Starting simulation... +switching cpus +info: Entering event queue @ 1406175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1407175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1408175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1409175973000. Starting simulation... +info: Entering event queue @ 1416175972000. Starting simulation... +info: Entering event queue @ 1416175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1416175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1417175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1418175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1419175979000. Starting simulation... +info: Entering event queue @ 1426175972000. Starting simulation... +info: Entering event queue @ 1426175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1426175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1427175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1428175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1429175979000. Starting simulation... +info: Entering event queue @ 1436175972000. Starting simulation... +info: Entering event queue @ 1436175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1436175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1437175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1438175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1439175979000. Starting simulation... +info: Entering event queue @ 1446175972000. Starting simulation... +info: Entering event queue @ 1446175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1446175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1447175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1448175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1449175979000. Starting simulation... +info: Entering event queue @ 1456175972000. Starting simulation... +info: Entering event queue @ 1456175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1456175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1457175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1458175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1459175983500. Starting simulation... +info: Entering event queue @ 1466175972000. Starting simulation... +info: Entering event queue @ 1466175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1466175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1467175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1468175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1469175983500. Starting simulation... +info: Entering event queue @ 1476175972000. Starting simulation... +info: Entering event queue @ 1476175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1476175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1477175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1478175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1479175979000. Starting simulation... +info: Entering event queue @ 1486175972000. Starting simulation... +info: Entering event queue @ 1486175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1486175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1487175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1488175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1489175979000. Starting simulation... +info: Entering event queue @ 1496175972000. Starting simulation... +info: Entering event queue @ 1496175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1496175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1497175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1498175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1499175979000. Starting simulation... +info: Entering event queue @ 1506175972000. Starting simulation... +info: Entering event queue @ 1506175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1506175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1507175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1508175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1509175979000. Starting simulation... +info: Entering event queue @ 1516175972000. Starting simulation... +info: Entering event queue @ 1516175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1516175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1517175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1518175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1519175983500. Starting simulation... +info: Entering event queue @ 1526175972000. Starting simulation... +info: Entering event queue @ 1526175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1526175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1527175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1528175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1529175983500. Starting simulation... +switching cpus +info: Entering event queue @ 1536175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1537175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1538175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1539175973000. Starting simulation... +switching cpus +info: Entering event queue @ 1546175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1547175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1548175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1549175973000. Starting simulation... +info: Entering event queue @ 1556175972000. Starting simulation... +info: Entering event queue @ 1556175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1556175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1557175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1558175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1559175983500. Starting simulation... +info: Entering event queue @ 1566175973000. Starting simulation... +info: Entering event queue @ 1566175981500. Starting simulation... +switching cpus +info: Entering event queue @ 1566175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1567175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1568175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1569175986000. Starting simulation... +info: Entering event queue @ 1576175972000. Starting simulation... +info: Entering event queue @ 1576429705000. Starting simulation... +switching cpus +info: Entering event queue @ 1576429707000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1577429707000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1578429707000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1579429707000. Starting simulation... +info: Entering event queue @ 1586175972000. Starting simulation... +info: Entering event queue @ 1586175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1586175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1587175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1588175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1589175979000. Starting simulation... +info: Entering event queue @ 1596175972000. Starting simulation... +info: Entering event queue @ 1596175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1596175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1597175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1598175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1599175979000. Starting simulation... +info: Entering event queue @ 1606175972000. Starting simulation... +info: Entering event queue @ 1606175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1606175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1607175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1608175979000. Starting simulation... +info: Entering event queue @ 1609165996000. Starting simulation... +switching cpus +info: Entering event queue @ 1609165998000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1610165998000. Starting simulation... +info: Entering event queue @ 1616175972000. Starting simulation... +info: Entering event queue @ 1616175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1616175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1617175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1618175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1619175983500. Starting simulation... +info: Entering event queue @ 1626175972000. Starting simulation... +info: Entering event queue @ 1626175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1626175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1627175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1628175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1629175983500. Starting simulation... +info: Entering event queue @ 1636175972000. Starting simulation... +info: Entering event queue @ 1636175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1636175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1637175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1638175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1639175979000. Starting simulation... +info: Entering event queue @ 1646175972000. Starting simulation... +info: Entering event queue @ 1646175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1646175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1647175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1648175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1649175979000. Starting simulation... +info: Entering event queue @ 1656175972000. Starting simulation... +info: Entering event queue @ 1656175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1656175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1657175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1658175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1659175979000. Starting simulation... +info: Entering event queue @ 1666175972000. Starting simulation... +info: Entering event queue @ 1666175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1666175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1667175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1668175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1669175979000. Starting simulation... +info: Entering event queue @ 1676175972000. Starting simulation... +info: Entering event queue @ 1676175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1676175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1677175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1678175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1679175983500. Starting simulation... +info: Entering event queue @ 1686175972000. Starting simulation... +info: Entering event queue @ 1686175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1686175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1687175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1688175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1689175983500. Starting simulation... +switching cpus +info: Entering event queue @ 1696175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1697175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1698175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1699175973000. Starting simulation... +info: Entering event queue @ 1706175973000. Starting simulation... +info: Entering event queue @ 1707375031000. Starting simulation... +switching cpus +info: Entering event queue @ 1707375033000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1708375033000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1709375033000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1710375033000. Starting simulation... +info: Entering event queue @ 1716175972000. Starting simulation... +info: Entering event queue @ 1716175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1716175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1717175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1718175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1719175983500. Starting simulation... +info: Entering event queue @ 1726175973000. Starting simulation... +info: Entering event queue @ 1726175981500. Starting simulation... +switching cpus +info: Entering event queue @ 1726175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1727175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1728175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1729175986000. Starting simulation... +info: Entering event queue @ 1736175972000. Starting simulation... +info: Entering event queue @ 1736175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1736175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1737175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1738175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1739175979000. Starting simulation... +info: Entering event queue @ 1746175972000. Starting simulation... +info: Entering event queue @ 1746175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1746175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1747175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1748175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1749175979000. Starting simulation... +info: Entering event queue @ 1756175972000. Starting simulation... +info: Entering event queue @ 1756175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1756175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1757175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1758175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1759175979000. Starting simulation... +info: Entering event queue @ 1766175972000. Starting simulation... +info: Entering event queue @ 1766175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1766175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1767175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1768175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1769175979000. Starting simulation... +info: Entering event queue @ 1776175972000. Starting simulation... +info: Entering event queue @ 1776175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1776175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1777175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1778175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1779175983500. Starting simulation... +info: Entering event queue @ 1786175972000. Starting simulation... +info: Entering event queue @ 1786175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1786175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1787175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1788175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1789175983500. Starting simulation... +info: Entering event queue @ 1796175972000. Starting simulation... +info: Entering event queue @ 1796175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1796175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1797175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1798175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1799175979000. Starting simulation... +info: Entering event queue @ 1806175972000. Starting simulation... +info: Entering event queue @ 1806175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1806175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1807175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1808175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1809175979000. Starting simulation... +info: Entering event queue @ 1816175972000. Starting simulation... +info: Entering event queue @ 1816175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1816175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1817175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1818175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1819175979000. Starting simulation... +info: Entering event queue @ 1826175972000. Starting simulation... +info: Entering event queue @ 1826175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1826175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1827175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1828175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1829175979000. Starting simulation... +info: Entering event queue @ 1836175972000. Starting simulation... +info: Entering event queue @ 1836175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1836175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1837175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1838175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1839175983500. Starting simulation... +info: Entering event queue @ 1846175972000. Starting simulation... +info: Entering event queue @ 1846175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1846175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1847175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1848175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1849175983500. Starting simulation... +switching cpus +info: Entering event queue @ 1856175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1857175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1858175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1859175973000. Starting simulation... +switching cpus +info: Entering event queue @ 1866175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1867175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1868175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1869175973000. Starting simulation... +info: Entering event queue @ 1876175972000. Starting simulation... +info: Entering event queue @ 1876175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1876175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1877175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1878175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1879175983500. Starting simulation... +info: Entering event queue @ 1886175973000. Starting simulation... +info: Entering event queue @ 1886175981500. Starting simulation... +switching cpus +info: Entering event queue @ 1886175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1887175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1888175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1889175986000. Starting simulation... +info: Entering event queue @ 1896175972000. Starting simulation... +info: Entering event queue @ 1896175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1896175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1897175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1898175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1899175979000. Starting simulation... +info: Entering event queue @ 1906175972000. Starting simulation... +info: Entering event queue @ 1906175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1906175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1907175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1908175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1909175979000. Starting simulation... +info: Entering event queue @ 1916175972000. Starting simulation... +info: Entering event queue @ 1916175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1916175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1917175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1918175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1919175979000. Starting simulation... +info: Entering event queue @ 1926175972000. Starting simulation... +info: Entering event queue @ 1926175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1926175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1927175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1928175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1929175979000. Starting simulation... +info: Entering event queue @ 1936175972000. Starting simulation... +info: Entering event queue @ 1936528480000. Starting simulation... +switching cpus +info: Entering event queue @ 1936528482000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1937528482000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1938528482000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1939528482000. Starting simulation... +info: Entering event queue @ 1946175972000. Starting simulation... +info: Entering event queue @ 1946175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1946175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1947175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1948175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1949175983500. Starting simulation... +info: Entering event queue @ 1956175972000. Starting simulation... +info: Entering event queue @ 1956175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1956175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1957175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1958175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1959175979000. Starting simulation... +info: Entering event queue @ 1966175972000. Starting simulation... +info: Entering event queue @ 1966175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1966175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1967175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 1968175979000. Starting simulation... +info: Entering event queue @ 1969264621000. Starting simulation... +switching cpus +info: Entering event queue @ 1969264623000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1970264623000. Starting simulation... +info: Entering event queue @ 1976175972000. Starting simulation... +info: Entering event queue @ 1976175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1976175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1977175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1978175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1979175979000. Starting simulation... +info: Entering event queue @ 1986175972000. Starting simulation... +info: Entering event queue @ 1986175978500. Starting simulation... +switching cpus +info: Entering event queue @ 1986175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1987175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1988175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1989175979000. Starting simulation... +info: Entering event queue @ 1996175972000. Starting simulation... +info: Entering event queue @ 1996175979000. Starting simulation... +switching cpus +info: Entering event queue @ 1996175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 1997175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 1998175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 1999175983500. Starting simulation... +info: Entering event queue @ 2006175972000. Starting simulation... +info: Entering event queue @ 2006175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2006175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2007175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2008175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2009175983500. Starting simulation... +switching cpus +info: Entering event queue @ 2016175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2017175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2018175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2019175973000. Starting simulation... +info: Entering event queue @ 2026175973000. Starting simulation... +info: Entering event queue @ 2026175980500. Starting simulation... +switching cpus +info: Entering event queue @ 2026175985000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2027175985000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2028175985000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2029175985000. Starting simulation... +info: Entering event queue @ 2036175972000. Starting simulation... +info: Entering event queue @ 2036175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2036175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2037175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2038175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2039175983500. Starting simulation... +info: Entering event queue @ 2046175973000. Starting simulation... +info: Entering event queue @ 2046175981500. Starting simulation... +switching cpus +info: Entering event queue @ 2046175986000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2047175986000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2048175986000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2049175986000. Starting simulation... +info: Entering event queue @ 2056175972000. Starting simulation... +info: Entering event queue @ 2056175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2056175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2057175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2058175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2059175979000. Starting simulation... +info: Entering event queue @ 2066175972000. Starting simulation... +info: Entering event queue @ 2067473656000. Starting simulation... +switching cpus +info: Entering event queue @ 2067473658000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2068473658000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2069473658000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2070473658000. Starting simulation... +info: Entering event queue @ 2076175972000. Starting simulation... +info: Entering event queue @ 2076175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2076175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2077175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2078175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2079175979000. Starting simulation... +info: Entering event queue @ 2086175972000. Starting simulation... +info: Entering event queue @ 2086175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2086175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2087175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2088175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2089175979000. Starting simulation... +info: Entering event queue @ 2096175972000. Starting simulation... +info: Entering event queue @ 2096175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2096175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2097175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2098175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2099175983500. Starting simulation... +info: Entering event queue @ 2106175972000. Starting simulation... +info: Entering event queue @ 2106175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2106175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2107175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2108175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2109175983500. Starting simulation... +info: Entering event queue @ 2116175972000. Starting simulation... +info: Entering event queue @ 2116175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2116175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2117175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2118175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2119175979000. Starting simulation... +info: Entering event queue @ 2126175972000. Starting simulation... +info: Entering event queue @ 2126175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2126175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2127175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2128175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2129175979000. Starting simulation... +info: Entering event queue @ 2136175972000. Starting simulation... +info: Entering event queue @ 2136175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2136175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2137175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2138175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2139175979000. Starting simulation... +info: Entering event queue @ 2146175972000. Starting simulation... +info: Entering event queue @ 2146175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2146175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2147175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2148175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2149175979000. Starting simulation... +info: Entering event queue @ 2156175972000. Starting simulation... +info: Entering event queue @ 2156175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2156175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2157175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2158175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2159175983500. Starting simulation... +info: Entering event queue @ 2166175972000. Starting simulation... +info: Entering event queue @ 2166175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2166175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2167175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2168175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2169175983500. Starting simulation... +info: Entering event queue @ 2176175972000. Starting simulation... +info: Entering event queue @ 2176175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2176175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2177175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2178175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2179175983500. Starting simulation... +info: Entering event queue @ 2186175972000. Starting simulation... +info: Entering event queue @ 2186175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2186175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2187175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2188175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2189175983500. Starting simulation... +switching cpus +info: Entering event queue @ 2196175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2197175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2198175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2199175973000. Starting simulation... +switching cpus +info: Entering event queue @ 2206175973000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2207175973000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2208175973000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2209175973000. Starting simulation... +info: Entering event queue @ 2216175972000. Starting simulation... +info: Entering event queue @ 2216175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2216175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2217175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2218175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2219175979000. Starting simulation... +info: Entering event queue @ 2226175972000. Starting simulation... +info: Entering event queue @ 2226175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2226175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2227175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2228175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2229175979000. Starting simulation... +info: Entering event queue @ 2236175972000. Starting simulation... +info: Entering event queue @ 2236175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2236175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2237175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2238175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2239175979000. Starting simulation... +info: Entering event queue @ 2246175972000. Starting simulation... +info: Entering event queue @ 2246175978500. Starting simulation... +switching cpus +info: Entering event queue @ 2246175979000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2247175979000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2248175979000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2249175979000. Starting simulation... +info: Entering event queue @ 2256175972000. Starting simulation... +info: Entering event queue @ 2256175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2256175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2257175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +switching cpus +info: Entering event queue @ 2258175983500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2259175983500. Starting simulation... +info: Entering event queue @ 2266175972000. Starting simulation... +info: Entering event queue @ 2266175979000. Starting simulation... +switching cpus +info: Entering event queue @ 2266175983500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2267175983500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2268175983500. Starting simulation... +switching cpus +info: Entering event queue @ 2268175984500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2269175984500. Starting simulation... +switching cpus +info: Entering event queue @ 2269176099000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2270176099000. Starting simulation... +switching cpus +info: Entering event queue @ 2270176101000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2271176101000. Starting simulation... +switching cpus +info: Entering event queue @ 2271176134000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2272176134000. Starting simulation... +switching cpus +info: Entering event queue @ 2272176298000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2273176298000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2274176298000. Starting simulation... +switching cpus +info: Entering event queue @ 2274176358000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2275176358000. Starting simulation... +switching cpus +info: Entering event queue @ 2275176444000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2276176444000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2277176444000. Starting simulation... +switching cpus +info: Entering event queue @ 2277176548000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2278176548000. Starting simulation... +switching cpus +info: Entering event queue @ 2278176623000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2279176623000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2280176623000. Starting simulation... +switching cpus +info: Entering event queue @ 2280176733000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2281176733000. Starting simulation... +switching cpus +info: Entering event queue @ 2281177431000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2282177431000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2283177431000. Starting simulation... +switching cpus +info: Entering event queue @ 2283177432000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2284177432000. Starting simulation... +switching cpus +info: Entering event queue @ 2284177537000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2285177537000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2286177537000. Starting simulation... +switching cpus +info: Entering event queue @ 2286177620000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2287177620000. Starting simulation... +switching cpus +info: Entering event queue @ 2287177681000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2288177681000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2289177681000. Starting simulation... +switching cpus +info: Entering event queue @ 2289177796000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2290177796000. Starting simulation... +switching cpus +info: Entering event queue @ 2290177891000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2291177891000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2292177891000. Starting simulation... +switching cpus +info: Entering event queue @ 2292177955000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2293177955000. Starting simulation... +switching cpus +info: Entering event queue @ 2293178118500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2294178118500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2295178118500. Starting simulation... +info: Entering event queue @ 2296627561000. Starting simulation... +switching cpus +info: Entering event queue @ 2296627563000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2297627563000. Starting simulation... +switching cpus +info: Entering event queue @ 2297627577000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2298627577000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2299627577000. Starting simulation... +switching cpus +info: Entering event queue @ 2299627643000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2300627643000. Starting simulation... +switching cpus +info: Entering event queue @ 2300627767000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2301627767000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2302627767000. Starting simulation... +switching cpus +info: Entering event queue @ 2302627826000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2303627826000. Starting simulation... +switching cpus +info: Entering event queue @ 2303627914000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2304627914000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2305627914000. Starting simulation... +switching cpus +info: Entering event queue @ 2305628068000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2306628068000. Starting simulation... +switching cpus +info: Entering event queue @ 2306628219000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2307628219000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2308628219000. Starting simulation... +switching cpus +info: Entering event queue @ 2308628231000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2309628231000. Starting simulation... +switching cpus +info: Entering event queue @ 2309628374500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2310628374500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2311628374500. Starting simulation... +switching cpus +info: Entering event queue @ 2311628440000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2312628440000. Starting simulation... +switching cpus +info: Entering event queue @ 2312628571000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2313628571000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2314628571000. Starting simulation... +switching cpus +info: Entering event queue @ 2314628586000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2315628586000. Starting simulation... +switching cpus +info: Entering event queue @ 2315628609000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2316628609000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2317628609000. Starting simulation... +switching cpus +info: Entering event queue @ 2317628760000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2318628760000. Starting simulation... +switching cpus +info: Entering event queue @ 2318628871500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2319628871500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2320628871500. Starting simulation... +switching cpus +info: Entering event queue @ 2320628950000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2321628950000. Starting simulation... +switching cpus +info: Entering event queue @ 2321628957000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2322628957000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2323628957000. Starting simulation... +switching cpus +info: Entering event queue @ 2323629079000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2324629079000. Starting simulation... +switching cpus +info: Entering event queue @ 2324629126000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2325629126000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2326629126000. Starting simulation... +switching cpus +info: Entering event queue @ 2326629176000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2327629176000. Starting simulation... +switching cpus +info: Entering event queue @ 2327629301000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2328629301000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2329629301000. Starting simulation... +switching cpus +info: Entering event queue @ 2329629399000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2330629399000. Starting simulation... +switching cpus +info: Entering event queue @ 2330629558000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2331629558000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2332629558000. Starting simulation... +switching cpus +info: Entering event queue @ 2332629573000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2333629573000. Starting simulation... +switching cpus +info: Entering event queue @ 2333629640000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2334629640000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2335629640000. Starting simulation... +switching cpus +info: Entering event queue @ 2335629779000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2336629779000. Starting simulation... +switching cpus +info: Entering event queue @ 2336629888500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2337629888500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2338629888500. Starting simulation... +switching cpus +info: Entering event queue @ 2338630042000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2339630042000. Starting simulation... +switching cpus +info: Entering event queue @ 2339630075000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2340630075000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2341630075000. Starting simulation... +switching cpus +info: Entering event queue @ 2341630098000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2342630098000. Starting simulation... +switching cpus +info: Entering event queue @ 2342630224500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2343630224500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2344630224500. Starting simulation... +switching cpus +info: Entering event queue @ 2344630308000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2345630308000. Starting simulation... +switching cpus +info: Entering event queue @ 2345630440000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2346630440000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2347630440000. Starting simulation... +switching cpus +info: Entering event queue @ 2347630481000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2348630481000. Starting simulation... +switching cpus +info: Entering event queue @ 2348630538000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2349630538000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2350630538000. Starting simulation... +switching cpus +info: Entering event queue @ 2350630623000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2351630623000. Starting simulation... +switching cpus +info: Entering event queue @ 2351630640000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2352630640000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2353630640000. Starting simulation... +switching cpus +info: Entering event queue @ 2353630748000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2354630748000. Starting simulation... +switching cpus +info: Entering event queue @ 2354630878000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2355630878000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2356630878000. Starting simulation... +switching cpus +info: Entering event queue @ 2356630895000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2357630895000. Starting simulation... +switching cpus +info: Entering event queue @ 2357630943000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2358630943000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2359630943000. Starting simulation... +switching cpus +info: Entering event queue @ 2359630963000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2360630963000. Starting simulation... +info: Entering event queue @ 2362100305000. Starting simulation... +switching cpus +info: Entering event queue @ 2362100307000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2363100307000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2364100307000. Starting simulation... +switching cpus +info: Entering event queue @ 2364100364000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2365100364000. Starting simulation... +switching cpus +info: Entering event queue @ 2365100522000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2366100522000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2367100522000. Starting simulation... +info: Entering event queue @ 2367100525000. Starting simulation... +switching cpus +info: Entering event queue @ 2367100527500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2368100527500. Starting simulation... +switching cpus +info: Entering event queue @ 2368100529500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2369100529500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2370100529500. Starting simulation... +switching cpus +info: Entering event queue @ 2370100533000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2371100533000. Starting simulation... +switching cpus +info: Entering event queue @ 2371100682500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2372100682500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2373100682500. Starting simulation... +switching cpus +info: Entering event queue @ 2373100683500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2374100683500. Starting simulation... +switching cpus +info: Entering event queue @ 2374102804500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2375102804500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2376102804500. Starting simulation... +switching cpus +info: Entering event queue @ 2376102808000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2377102808000. Starting simulation... +switching cpus +info: Entering event queue @ 2377102891000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2378102891000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2379102891000. Starting simulation... +switching cpus +info: Entering event queue @ 2379102993000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2380102993000. Starting simulation... +switching cpus +info: Entering event queue @ 2380103021000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2381103021000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2382103021000. Starting simulation... +switching cpus +info: Entering event queue @ 2382103048000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2383103048000. Starting simulation... +switching cpus +info: Entering event queue @ 2383112179000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2384112179000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2385112179000. Starting simulation... +switching cpus +info: Entering event queue @ 2385112305000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2386112305000. Starting simulation... +switching cpus +info: Entering event queue @ 2386112310500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2387112310500. Starting simulation... +switching cpus +info: Entering event queue @ 2387112312500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2388112312500. Starting simulation... +switching cpus +info: Entering event queue @ 2388112314500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2389112314500. Starting simulation... +switching cpus +info: Entering event queue @ 2389112333500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2390112333500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2391112333500. Starting simulation... +switching cpus +info: Entering event queue @ 2391112334500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2392112334500. Starting simulation... +switching cpus +info: Entering event queue @ 2392112630500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2393112630500. Starting simulation... +switching cpus +info: Entering event queue @ 2393112631000. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2394112631000. Starting simulation... +info: Entering event queue @ 2394836596000. Starting simulation... +switching cpus +info: Entering event queue @ 2394836598000. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2395836598000. Starting simulation... +switching cpus +info: Entering event queue @ 2395839042500. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +switching cpus +info: Entering event queue @ 2396839042500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2397839042500. Starting simulation... +switching cpus +info: Entering event queue @ 2397839043500. Starting simulation... +Switching CPUs... +Next CPU: AtomicSimpleCPU +info: Entering event queue @ 2398839043500. Starting simulation... +switching cpus +info: Entering event queue @ 2398839190000. Starting simulation... +Switching CPUs... +Next CPU: TimingSimpleCPU +info: Entering event queue @ 2399839190000. Starting simulation... +switching cpus +info: Entering event queue @ 2399839190500. Starting simulation... +Switching CPUs... +Next CPU: DerivO3CPU +info: Entering event queue @ 2400839190500. Starting simulation... +info: Entering event queue @ 2400839197500. Starting simulation... +switching cpus +info: Entering event queue @ 2400839201000. Starting simulation... diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt new file mode 100644 index 000000000..ba425396c --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -0,0 +1,1572 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 2.401421 # Number of seconds simulated +sim_ticks 2401421439000 # Number of ticks simulated +final_tick 2401421439000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 170882 # Simulator instruction rate (inst/s) +host_op_rate 219406 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6786575645 # Simulator tick rate (ticks/s) +host_mem_usage 393972 # Number of bytes of host memory used +host_seconds 353.85 # Real time elapsed on the host +sim_insts 60466509 # Number of instructions simulated +sim_ops 77636591 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 478816 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7027600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 73664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 716876 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 1216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.itb.walker 128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 218496 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1332556 # Number of bytes read from this memory +system.physmem.bytes_read::total 124668680 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 478816 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 73664 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 218496 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 770976 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3748032 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1052216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 199484 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1764144 # Number of bytes written to this memory +system.physmem.bytes_written::total 6763876 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 13684 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 109840 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1151 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 11204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 19 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.itb.walker 2 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 3414 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20824 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512526 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58563 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 263054 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 49871 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 441036 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812524 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47812962 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199389 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2926433 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 30675 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 298522 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 506 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 53 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 90986 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 554903 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51914536 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199389 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 30675 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 90986 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 321050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1560756 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 438164 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 83069 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 734625 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2816613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1560756 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47812962 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 199389 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3364597 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 30675 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 381591 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 506 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 90986 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1289528 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54731150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 12619527 # Total number of read requests seen +system.physmem.writeReqs 508095 # Total number of write requests seen +system.physmem.cpureqs 56153 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 807649728 # Total number of bytes read from memory +system.physmem.bytesWritten 32518080 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 103006296 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 3063660 # bytesWritten derated as per pkt->getSize() +system.physmem.servicedByWrQ 2 # Number of read reqs serviced by write Q +system.physmem.neitherReadNorWrite 2356 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 788374 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 788516 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 788173 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 788282 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 788267 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 788268 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 788411 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 789077 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 789904 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 789864 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 789609 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 789636 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 788668 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 788108 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 788208 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 788160 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 30462 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 31339 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 31367 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 31519 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 31434 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 31463 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 31715 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 32144 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 32667 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 32642 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 32415 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 32370 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 31797 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 31479 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 31921 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 31361 # Track writes on a per bank basis +system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry +system.physmem.numWrRetry 317403 # Number of times wr buffer was full causing retry +system.physmem.totGap 2400386249000 # Total gap between requests +system.physmem.readPktSize::0 0 # Categorize read packet sizes +system.physmem.readPktSize::1 0 # Categorize read packet sizes +system.physmem.readPktSize::2 6 # Categorize read packet sizes +system.physmem.readPktSize::3 12582912 # Categorize read packet sizes +system.physmem.readPktSize::4 0 # Categorize read packet sizes +system.physmem.readPktSize::5 0 # Categorize read packet sizes +system.physmem.readPktSize::6 36609 # Categorize read packet sizes +system.physmem.readPktSize::7 0 # Categorize read packet sizes +system.physmem.readPktSize::8 0 # Categorize read packet sizes +system.physmem.writePktSize::0 0 # categorize write packet sizes +system.physmem.writePktSize::1 0 # categorize write packet sizes +system.physmem.writePktSize::2 808310 # categorize write packet sizes +system.physmem.writePktSize::3 0 # categorize write packet sizes +system.physmem.writePktSize::4 0 # categorize write packet sizes +system.physmem.writePktSize::5 0 # categorize write packet sizes +system.physmem.writePktSize::6 17188 # categorize write packet sizes +system.physmem.writePktSize::7 0 # categorize write packet sizes +system.physmem.writePktSize::8 0 # categorize write packet sizes +system.physmem.neitherpktsize::0 0 # categorize neither packet sizes +system.physmem.neitherpktsize::1 0 # categorize neither packet sizes +system.physmem.neitherpktsize::2 0 # categorize neither packet sizes +system.physmem.neitherpktsize::3 0 # categorize neither packet sizes +system.physmem.neitherpktsize::4 0 # categorize neither packet sizes +system.physmem.neitherpktsize::5 0 # categorize neither packet sizes +system.physmem.neitherpktsize::6 2356 # categorize neither packet sizes +system.physmem.neitherpktsize::7 0 # categorize neither packet sizes +system.physmem.neitherpktsize::8 0 # categorize neither packet sizes +system.physmem.rdQLenPdf::0 817282 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 792530 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 787018 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 816081 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2309777 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2310026 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 4565188 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 24972 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 24597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 24594 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 24587 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 47867 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 24582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 47847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 1291 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 1284 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see +system.physmem.wrQLenPdf::0 3518 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 3552 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 3620 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 3760 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 3937 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 4056 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 4161 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 4250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 4415 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 22096 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 22090 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 22088 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 22084 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 22079 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 22076 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 22070 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 22068 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 22064 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 22061 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 22055 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 22051 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 22047 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 22044 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 18625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 18585 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 18515 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 18369 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 18188 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 18065 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 17957 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 17859 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 17690 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.physmem.totQLat 234691241923 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 297448055923 # Sum of mem lat for all requests +system.physmem.totBusLat 50478100000 # Total cycles spent in databus access +system.physmem.totBankLat 12278714000 # Total cycles spent in bank access +system.physmem.avgQLat 18597.47 # Average queueing delay per request +system.physmem.avgBankLat 972.99 # Average bank access latency per request +system.physmem.avgBusLat 4000.00 # Average bus latency per request +system.physmem.avgMemAccLat 23570.46 # Average memory access latency +system.physmem.avgRdBW 336.32 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 13.54 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 42.89 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 1.28 # Average consumed write bandwidth in MB/s +system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s +system.physmem.busUtil 2.19 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.12 # Average read queue length over time +system.physmem.avgWrQLen 0.40 # Average write queue length over time +system.physmem.readRowHits 12589945 # Number of row buffer hits during reads +system.physmem.writeRowHits 499132 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.77 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 98.24 # Row buffer hit rate for writes +system.physmem.avgGap 182850.04 # Average gap between requests +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 63371 # number of replacements +system.l2c.tagsinuse 50440.930838 # Cycle average of tags in use +system.l2c.total_refs 1764263 # Total number of references to valid blocks. +system.l2c.sampled_refs 128761 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.701843 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2374519462500 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36775.045658 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4782.596749 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 3401.388842 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 0.993264 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 624.225892 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 1084.430901 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.dtb.walker 16.710319 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.itb.walker 0.970933 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2110.368967 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 1644.199171 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.561143 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.072977 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.051901 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.009525 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.016547 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.dtb.walker 0.000255 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.032202 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.025088 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.769668 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8850 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3418 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467065 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 185990 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2576 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 127160 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 58153 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 32653 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4529 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 285923 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 129158 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1306614 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597611 # number of Writeback hits +system.l2c.Writeback_hits::total 597611 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 13 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2.data 14 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 31 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 6 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 6 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 62389 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18579 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 32685 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113653 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8850 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3418 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 467065 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 248379 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.dtb.walker 2576 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.itb.walker 1139 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 127160 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 76732 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.dtb.walker 32653 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.itb.walker 4529 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 285923 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 161843 # number of demand (read+write) hits +system.l2c.demand_hits::total 1420267 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.dtb.walker 8850 # number of overall hits +system.l2c.overall_hits::cpu0.itb.walker 3418 # number of overall hits +system.l2c.overall_hits::cpu0.inst 467065 # number of overall hits +system.l2c.overall_hits::cpu0.data 248379 # number of overall hits +system.l2c.overall_hits::cpu1.dtb.walker 2576 # number of overall hits +system.l2c.overall_hits::cpu1.itb.walker 1139 # number of overall hits +system.l2c.overall_hits::cpu1.inst 127160 # number of overall hits +system.l2c.overall_hits::cpu1.data 76732 # number of overall hits +system.l2c.overall_hits::cpu2.dtb.walker 32653 # number of overall hits +system.l2c.overall_hits::cpu2.itb.walker 4529 # number of overall hits +system.l2c.overall_hits::cpu2.inst 285923 # number of overall hits +system.l2c.overall_hits::cpu2.data 161843 # number of overall hits +system.l2c.overall_hits::total 1420267 # number of overall hits +system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.inst 7068 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 5964 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 1151 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 1562 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.dtb.walker 19 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.itb.walker 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 3416 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 2619 # number of ReadReq misses +system.l2c.ReadReq_misses::total 21805 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0.data 1429 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1.data 489 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2.data 987 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0.data 104629 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1.data 9911 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2.data 18825 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133365 # number of ReadExReq misses +system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.inst 7068 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 110593 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.inst 1151 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1.data 11473 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.dtb.walker 19 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.itb.walker 2 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.inst 3416 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2.data 21444 # number of demand (read+write) misses +system.l2c.demand_misses::total 155170 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu0.inst 7068 # number of overall misses +system.l2c.overall_misses::cpu0.data 110593 # number of overall misses +system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses +system.l2c.overall_misses::cpu1.inst 1151 # number of overall misses +system.l2c.overall_misses::cpu1.data 11473 # number of overall misses +system.l2c.overall_misses::cpu2.dtb.walker 19 # number of overall misses +system.l2c.overall_misses::cpu2.itb.walker 2 # number of overall misses +system.l2c.overall_misses::cpu2.inst 3416 # number of overall misses +system.l2c.overall_misses::cpu2.data 21444 # number of overall misses +system.l2c.overall_misses::total 155170 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 69000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 59181000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.data 81935500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 1348500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.itb.walker 137000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 197768500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.data 150939499 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 491378999 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1.data 91500 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2.data 137000 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 228500 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 442251500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 1015620500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1457872000 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu1.dtb.walker 69000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 59181000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 524187000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.dtb.walker 1348500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.itb.walker 137000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 197768500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 1166559999 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 1949250999 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu1.dtb.walker 69000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 59181000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 524187000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.dtb.walker 1348500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.itb.walker 137000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 197768500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 1166559999 # number of overall miss cycles +system.l2c.overall_miss_latency::total 1949250999 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0.dtb.walker 8851 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 3420 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 474133 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 191954 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 2577 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1139 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 128311 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 59715 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.dtb.walker 32672 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.itb.walker 4531 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.inst 289339 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 131777 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1328419 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 597611 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 597611 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 1442 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 493 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2.data 1001 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2936 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu2.data 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 6 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 167018 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 28490 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 51510 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247018 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 8851 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 3420 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 474133 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 358972 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 2577 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1139 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 128311 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 88205 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.dtb.walker 32672 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.itb.walker 4531 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.inst 289339 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2.data 183287 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1575437 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 8851 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 3420 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 474133 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 358972 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 2577 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1139 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 128311 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 88205 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.dtb.walker 32672 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.itb.walker 4531 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 289339 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 183287 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1575437 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000585 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.014907 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.031070 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.008970 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.026158 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.itb.walker 0.000441 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.011806 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.019874 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016414 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990985 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991886 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2.data 0.986014 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.989441 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.626453 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.347876 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 0.365463 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539900 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.000585 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.014907 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.308083 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.008970 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.130072 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.itb.walker 0.000441 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.011806 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.116997 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.098493 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000113 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.000585 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.014907 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.308083 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000388 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.008970 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.130072 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000582 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.itb.walker 0.000441 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.011806 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.116997 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.098493 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 69000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 51417.028671 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.data 52455.505762 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.itb.walker 68500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 57894.759953 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.data 57632.492936 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 22535.152442 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 187.116564 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 138.804458 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 78.657487 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1.data 44622.288366 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2.data 53950.624170 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 10931.443782 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.inst 51417.028671 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1.data 45688.747494 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.inst 57894.759953 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2.data 54400.298405 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 12562.035181 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 69000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.inst 51417.028671 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 45688.747494 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 70973.684211 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.itb.walker 68500 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 57894.759953 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 54400.298405 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 12562.035181 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.writebacks::writebacks 58563 # number of writebacks +system.l2c.writebacks::total 58563 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu2.inst 2 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2.data 15 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.l2c.demand_mshr_hits::cpu2.inst 2 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2.data 15 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu2.inst 2 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2.data 15 # number of overall MSHR hits +system.l2c.overall_mshr_hits::total 17 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.inst 1151 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1.data 1562 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 19 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.itb.walker 2 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.inst 3414 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2.data 2604 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 8753 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1.data 489 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2.data 987 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 1476 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1.data 9911 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2.data 18825 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 28736 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.inst 1151 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1.data 11473 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.dtb.walker 19 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.itb.walker 2 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.inst 3414 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2.data 21429 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 37489 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.inst 1151 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1.data 11473 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.dtb.walker 19 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.itb.walker 2 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.inst 3414 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2.data 21429 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 37489 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 56002 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 44565780 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1.data 61910606 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.itb.walker 112004 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 154485385 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2.data 117079807 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 379316119 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4947956 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 9870987 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 14818943 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 315063958 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 780713218 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1095777176 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 56002 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 44565780 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 376974564 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.itb.walker 112004 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 154485385 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 897793025 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1475093295 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 56002 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 44565780 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 376974564 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 1106535 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.itb.walker 112004 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 154485385 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 897793025 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1475093295 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25233133000 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26572368004 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 51805501004 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 640106868 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 7144945536 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 7785052404 # number of WriteReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 76004 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.LoadLockedReq_mshr_uncacheable_latency::total 76004 # number of LoadLockedReq MSHR uncacheable cycles +system.l2c.StoreCondReq_mshr_uncacheable_latency::cpu1.data 30003 # number of StoreCondReq MSHR uncacheable cycles +system.l2c.StoreCondReq_mshr_uncacheable_latency::total 30003 # number of StoreCondReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25873239868 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 33717313540 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 59590553408 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.026158 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.019761 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.006589 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991886 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.986014 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.502725 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347876 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365463 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.116332 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.130072 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116915 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023796 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008970 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.130072 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000582 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.itb.walker 0.000441 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011799 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116915 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023796 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 39635.471191 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 44961.523425 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 43335.555695 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10118.519427 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10039.934282 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 31789.320755 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 41472.149695 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38132.557628 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 38719.183319 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 32857.540661 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 58238.684211 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 56002 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 45250.552138 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 41896.169910 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39347.363093 # average overall mshr miss latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency +system.l2c.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency +system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency +system.l2c.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate +system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). +system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). +system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). +system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. +system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. +system.cf0.dma_write_txs 0 # Number of DMA write transactions. +system.cpu0.dtb.inst_hits 0 # ITB inst hits +system.cpu0.dtb.inst_misses 0 # ITB inst misses +system.cpu0.dtb.read_hits 7902224 # DTB read hits +system.cpu0.dtb.read_misses 6242 # DTB read misses +system.cpu0.dtb.write_hits 6537817 # DTB write hits +system.cpu0.dtb.write_misses 1923 # DTB write misses +system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.dtb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 113 # Number of TLB faults due to prefetch +system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.dtb.perms_faults 213 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7908466 # DTB read accesses +system.cpu0.dtb.write_accesses 6539740 # DTB write accesses +system.cpu0.dtb.inst_accesses 0 # ITB inst accesses +system.cpu0.dtb.hits 14440041 # DTB hits +system.cpu0.dtb.misses 8165 # DTB misses +system.cpu0.dtb.accesses 14448206 # DTB accesses +system.cpu0.itb.inst_hits 31853127 # ITB inst hits +system.cpu0.itb.inst_misses 3518 # ITB inst misses +system.cpu0.itb.read_hits 0 # DTB read hits +system.cpu0.itb.read_misses 0 # DTB read misses +system.cpu0.itb.write_hits 0 # DTB write hits +system.cpu0.itb.write_misses 0 # DTB write misses +system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed +system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu0.itb.flush_tlb_mva_asid 688 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID +system.cpu0.itb.flush_entries 2622 # Number of entries that have been flushed from TLB +system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.read_accesses 0 # DTB read accesses +system.cpu0.itb.write_accesses 0 # DTB write accesses +system.cpu0.itb.inst_accesses 31856645 # ITB inst accesses +system.cpu0.itb.hits 31853127 # DTB hits +system.cpu0.itb.misses 3518 # DTB misses +system.cpu0.itb.accesses 31856645 # DTB accesses +system.cpu0.numCycles 112931028 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 31362077 # Number of instructions committed +system.cpu0.committedOps 41448320 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 36567470 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5105 # Number of float alu accesses +system.cpu0.num_func_calls 1216492 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4268853 # number of instructions that are conditional controls +system.cpu0.num_int_insts 36567470 # number of integer instructions +system.cpu0.num_fp_insts 5105 # number of float instructions +system.cpu0.num_int_register_reads 186633277 # number of times the integer registers were read +system.cpu0.num_int_register_writes 38778240 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3615 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1492 # number of times the floating registers were written +system.cpu0.num_mem_refs 15097186 # number of memory refs +system.cpu0.num_load_insts 8269911 # Number of load instructions +system.cpu0.num_store_insts 6827275 # Number of store instructions +system.cpu0.num_idle_cycles 13401980962.617596 # Number of idle cycles +system.cpu0.num_busy_cycles -13289049934.617596 # Number of busy cycles +system.cpu0.not_idle_fraction -117.674037 # Percentage of non-idle cycles +system.cpu0.idle_fraction 118.674037 # Percentage of idle cycles +system.cpu0.kern.inst.arm 0 # number of arm instructions executed +system.cpu0.kern.inst.quiesce 84468 # number of quiesce instructions executed +system.cpu0.icache.replacements 892780 # number of replacements +system.cpu0.icache.tagsinuse 511.591234 # Cycle average of tags in use +system.cpu0.icache.total_refs 43441886 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 893292 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 48.631227 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 8001805000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 491.376976 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 7.109245 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu2.inst 13.105014 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.959721 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.013885 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu2.inst 0.025596 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.999202 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 31380980 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 8436238 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu2.inst 3624668 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 43441886 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 31380980 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 8436238 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu2.inst 3624668 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 43441886 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 31380980 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 8436238 # number of overall hits +system.cpu0.icache.overall_hits::cpu2.inst 3624668 # number of overall hits +system.cpu0.icache.overall_hits::total 43441886 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 474853 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 128587 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu2.inst 314740 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 918180 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 474853 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 128587 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu2.inst 314740 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 918180 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 474853 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 128587 # number of overall misses +system.cpu0.icache.overall_misses::cpu2.inst 314740 # number of overall misses +system.cpu0.icache.overall_misses::total 918180 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1722310000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4209726988 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5932036988 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 1722310000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu2.inst 4209726988 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5932036988 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 1722310000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu2.inst 4209726988 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5932036988 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 31855833 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 8564825 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu2.inst 3939408 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 44360066 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 31855833 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 8564825 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu2.inst 3939408 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 44360066 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 31855833 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 8564825 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu2.inst 3939408 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 44360066 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014906 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015013 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.079895 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.020698 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014906 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015013 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu2.inst 0.079895 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.020698 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014906 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015013 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu2.inst 0.079895 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.020698 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13394.122267 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13375.252551 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 6460.647137 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13394.122267 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13375.252551 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 6460.647137 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13394.122267 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13375.252551 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 6460.647137 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 3469 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 241 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 14.394191 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24876 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 24876 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu2.inst 24876 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 24876 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu2.inst 24876 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 24876 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 128587 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 289864 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 418451 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu1.inst 128587 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu2.inst 289864 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 418451 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu1.inst 128587 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu2.inst 289864 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 418451 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1465136000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3427061488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4892197488 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1465136000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3427061488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4892197488 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1465136000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3427061488 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4892197488 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009433 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.009433 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015013 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.073581 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.009433 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11691.207544 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11691.207544 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11394.122267 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11822.997985 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11691.207544 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 629952 # number of replacements +system.cpu0.dcache.tagsinuse 511.997116 # Cycle average of tags in use +system.cpu0.dcache.total_refs 23322161 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 630464 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 36.992058 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 497.280136 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu1.data 8.191597 # Average occupied blocks per requestor +system.cpu0.dcache.occ_blocks::cpu2.data 6.525382 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.971250 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu1.data 0.015999 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::cpu2.data 0.012745 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6763167 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1877822 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4718068 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13359057 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5963557 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1365617 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2102817 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9431991 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 135570 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32797 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 91307 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 259674 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 142092 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34425 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 91924 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 268441 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12726724 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3243439 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6820885 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22791048 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12726724 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3243439 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6820885 # number of overall hits +system.cpu0.dcache.overall_hits::total 22791048 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 185432 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 58086 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 273913 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 517431 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 168460 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28983 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 595876 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 793319 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6522 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1629 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3810 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11961 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu2.data 6 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 6 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 353892 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu1.data 87069 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::cpu2.data 869789 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 1310750 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 353892 # number of overall misses +system.cpu0.dcache.overall_misses::cpu1.data 87069 # number of overall misses +system.cpu0.dcache.overall_misses::cpu2.data 869789 # number of overall misses +system.cpu0.dcache.overall_misses::total 1310750 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 824588500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3876286000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4700874500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 726126000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 19133055918 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 19859181918 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 21335000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 51226000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 72561000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 78000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 78000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1550714500 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 23009341918 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 24560056418 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1550714500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 23009341918 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 24560056418 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6948599 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1935908 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4991981 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13876488 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6132017 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1394600 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2698693 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10225310 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 142092 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34426 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 95117 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 271635 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 142092 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34425 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 91930 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 268447 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 13080616 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3330508 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7690674 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24101798 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13080616 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3330508 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7690674 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24101798 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.026686 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.030005 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054871 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037288 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027472 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.020782 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.220802 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.077584 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.045900 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.047319 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.040056 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.044033 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000065 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000022 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.027055 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.026143 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.113097 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054384 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.027055 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.026143 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.113097 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054384 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14195.993871 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14151.522564 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9085.026796 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 25053.514129 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 32109.123237 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 25033.034527 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13096.992020 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13445.144357 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6066.466015 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 18737.407147 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 17810.179283 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 26453.935285 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 18737.407147 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 6963 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 952 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 771 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 46 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.031128 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 20.695652 # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 597611 # number of writebacks +system.cpu0.dcache.writebacks::total 597611 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 145491 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 145491 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 543392 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 543392 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 428 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 428 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 688883 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 688883 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 688883 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 688883 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 58086 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 128422 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 186508 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28983 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 52484 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81467 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1629 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3382 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5011 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 6 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu1.data 87069 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu2.data 180906 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 267975 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu1.data 87069 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu2.data 180906 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 267975 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 708416500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1664999000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2373415500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 668160000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1456004992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2124164992 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 18077000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 39418000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57495000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 66000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1376576500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3121003992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 4497580492 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1376576500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3121003992 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 4497580492 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27568021500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 29009742000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56577763500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1272962000 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 12893978360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14166940360 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 117500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 117500 # number of LoadLockedReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840983500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41903720360 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70744703860 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.030005 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.025726 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.013441 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.020782 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019448 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007967 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047319 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.035556 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.018448 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000065 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000022 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.026143 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.023523 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011118 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.026143 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.023523 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011118 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12195.993871 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12965.060504 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12725.542604 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 23053.514129 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 27741.883088 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26073.931678 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11096.992020 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11655.233590 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11473.757733 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 15810.179283 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 17252.075619 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 16783.582394 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 15810.179283 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 17252.075619 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 16783.582394 # average overall mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::cpu1.data inf # average LoadLockedReq mshr uncacheable latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_uncacheable_latency::total inf # average LoadLockedReq mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::cpu1.data inf # average StoreCondReq mshr uncacheable latency +system.cpu0.dcache.StoreCondReq_avg_mshr_uncacheable_latency::total inf # average StoreCondReq mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency +system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dtb.inst_hits 0 # ITB inst hits +system.cpu1.dtb.inst_misses 0 # ITB inst misses +system.cpu1.dtb.read_hits 2149941 # DTB read hits +system.cpu1.dtb.read_misses 2094 # DTB read misses +system.cpu1.dtb.write_hits 1479770 # DTB write hits +system.cpu1.dtb.write_misses 382 # DTB write misses +system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.dtb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.dtb.flush_entries 1681 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 46 # Number of TLB faults due to prefetch +system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2152035 # DTB read accesses +system.cpu1.dtb.write_accesses 1480152 # DTB write accesses +system.cpu1.dtb.inst_accesses 0 # ITB inst accesses +system.cpu1.dtb.hits 3629711 # DTB hits +system.cpu1.dtb.misses 2476 # DTB misses +system.cpu1.dtb.accesses 3632187 # DTB accesses +system.cpu1.itb.inst_hits 8564825 # ITB inst hits +system.cpu1.itb.inst_misses 1128 # ITB inst misses +system.cpu1.itb.read_hits 0 # DTB read hits +system.cpu1.itb.read_misses 0 # DTB read misses +system.cpu1.itb.write_hits 0 # DTB write hits +system.cpu1.itb.write_misses 0 # DTB write misses +system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed +system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu1.itb.flush_tlb_mva_asid 240 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_asid 11 # Number of times TLB was flushed by ASID +system.cpu1.itb.flush_entries 827 # Number of entries that have been flushed from TLB +system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.read_accesses 0 # DTB read accesses +system.cpu1.itb.write_accesses 0 # DTB write accesses +system.cpu1.itb.inst_accesses 8565953 # ITB inst accesses +system.cpu1.itb.hits 8564825 # DTB hits +system.cpu1.itb.misses 1128 # DTB misses +system.cpu1.itb.accesses 8565953 # DTB accesses +system.cpu1.numCycles 573618226 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 8360582 # Number of instructions committed +system.cpu1.committedOps 10552123 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9474069 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2062 # Number of float alu accesses +system.cpu1.num_func_calls 304948 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1122653 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9474069 # number of integer instructions +system.cpu1.num_fp_insts 2062 # number of float instructions +system.cpu1.num_int_register_reads 54388368 # number of times the integer registers were read +system.cpu1.num_int_register_writes 10296894 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1613 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 450 # number of times the floating registers were written +system.cpu1.num_mem_refs 3801129 # number of memory refs +system.cpu1.num_load_insts 2242444 # Number of load instructions +system.cpu1.num_store_insts 1558685 # Number of store instructions +system.cpu1.num_idle_cycles -28470862.464355 # Number of idle cycles +system.cpu1.num_busy_cycles 602089088.464355 # Number of busy cycles +system.cpu1.not_idle_fraction 1.049634 # Percentage of non-idle cycles +system.cpu1.idle_fraction -0.049634 # Percentage of idle cycles +system.cpu1.kern.inst.arm 0 # number of arm instructions executed +system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed +system.cpu2.dtb.inst_hits 0 # ITB inst hits +system.cpu2.dtb.inst_misses 0 # ITB inst misses +system.cpu2.dtb.read_hits 11072336 # DTB read hits +system.cpu2.dtb.read_misses 27162 # DTB read misses +system.cpu2.dtb.write_hits 3379244 # DTB write hits +system.cpu2.dtb.write_misses 7485 # DTB write misses +system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.dtb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu2.dtb.flush_entries 3059 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 210 # Number of TLB faults due to prefetch +system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 11099498 # DTB read accesses +system.cpu2.dtb.write_accesses 3386729 # DTB write accesses +system.cpu2.dtb.inst_accesses 0 # ITB inst accesses +system.cpu2.dtb.hits 14451580 # DTB hits +system.cpu2.dtb.misses 34647 # DTB misses +system.cpu2.dtb.accesses 14486227 # DTB accesses +system.cpu2.itb.inst_hits 3940913 # ITB inst hits +system.cpu2.itb.inst_misses 4663 # ITB inst misses +system.cpu2.itb.read_hits 0 # DTB read hits +system.cpu2.itb.read_misses 0 # DTB read misses +system.cpu2.itb.write_hits 0 # DTB write hits +system.cpu2.itb.write_misses 0 # DTB write misses +system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed +system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu2.itb.flush_tlb_mva_asid 511 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_asid 22 # Number of times TLB was flushed by ASID +system.cpu2.itb.flush_entries 1673 # Number of entries that have been flushed from TLB +system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu2.itb.perms_faults 1015 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.read_accesses 0 # DTB read accesses +system.cpu2.itb.write_accesses 0 # DTB write accesses +system.cpu2.itb.inst_accesses 3945576 # ITB inst accesses +system.cpu2.itb.hits 3940913 # DTB hits +system.cpu2.itb.misses 4663 # DTB misses +system.cpu2.itb.accesses 3945576 # DTB accesses +system.cpu2.numCycles 88228970 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.BPredUnit.lookups 4678533 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 3809806 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 231267 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 3069092 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 2498136 # Number of BTB hits +system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.BPredUnit.usedRAS 412114 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 22380 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 9360105 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 31976282 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4678533 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2910250 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6786917 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1728503 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 53808 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19342330 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 594 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 913 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 36859 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 59251 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 389 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 3939412 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 244088 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2174 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36830548 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.047719 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.434253 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30048718 81.59% 81.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 408687 1.11% 82.70% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 492187 1.34% 84.03% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 812698 2.21% 86.24% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 611463 1.66% 87.90% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 330922 0.90% 88.80% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1062958 2.89% 91.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 224607 0.61% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2838308 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 36830548 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053027 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.362424 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9885763 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19327017 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6180149 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 300885 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1135792 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 597498 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 54848 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36565818 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 186819 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1135792 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10385247 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6621320 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11277395 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5962558 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1447335 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34838937 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2719 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 250879 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 912957 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 22201 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37227895 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159446068 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 159418988 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 27080 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26794485 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10433409 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 254044 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 230219 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3142941 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6628278 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3915406 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 518992 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 767543 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32164019 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 534132 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 35030885 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 59969 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 6868407 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 17749072 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 150741 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36830548 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.951137 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.612264 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24216483 65.75% 65.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3835065 10.41% 76.16% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2287291 6.21% 82.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1980355 5.38% 87.75% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2800040 7.60% 95.35% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 1007857 2.74% 98.09% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 517219 1.40% 99.49% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 152490 0.41% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 33748 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36830548 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 17662 1.14% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.14% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1415792 91.50% 92.64% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 113850 7.36% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 60995 0.17% 0.17% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19871242 56.72% 56.90% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 29695 0.08% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 372 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11515486 32.87% 89.86% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3553080 10.14% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 35030885 # Type of FU issued +system.cpu2.iq.rate 0.397045 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1547304 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044170 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108527324 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39572230 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28399462 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 6790 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3711 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36513628 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3566 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 191014 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 1467031 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2011 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9738 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 545094 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 5365251 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 332989 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 1135792 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 4899150 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 89921 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32779082 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 64376 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6628278 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3915406 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 386018 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 31359 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2570 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9738 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 111294 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 92702 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 203996 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 34250844 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11286425 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 780041 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 80931 # number of nop insts executed +system.cpu2.iew.exec_refs 14805022 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3673391 # Number of branches executed +system.cpu2.iew.exec_stores 3518597 # Number of stores executed +system.cpu2.iew.exec_rate 0.388204 # Inst execution rate +system.cpu2.iew.wb_sent 33866957 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28402589 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16335424 # num instructions producing a value +system.cpu2.iew.wb_consumers 29431571 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 0.321919 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.555031 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitSquashedInsts 6831747 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 383391 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 177223 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35694573 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.719725 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.780912 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 26969912 75.56% 75.56% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4228252 11.85% 87.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1198360 3.36% 90.76% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 616402 1.73% 92.49% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 527161 1.48% 93.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 311066 0.87% 94.84% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 434912 1.22% 96.05% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 325428 0.91% 96.97% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1083080 3.03% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 35694573 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20797962 # Number of instructions committed +system.cpu2.commit.committedOps 25690260 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 8531559 # Number of memory references committed +system.cpu2.commit.loads 5161247 # Number of loads committed +system.cpu2.commit.membars 98356 # Number of memory barriers committed +system.cpu2.commit.branches 3158165 # Number of branches committed +system.cpu2.commit.fp_insts 3087 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22900752 # Number of committed integer instructions. +system.cpu2.commit.function_calls 287889 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1083080 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 66589270 # The number of ROB reads +system.cpu2.rob.rob_writes 66235051 # The number of ROB writes +system.cpu2.timesIdled 359715 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51398422 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3569788363 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20743850 # Number of Instructions Simulated +system.cpu2.committedOps 25636148 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20743850 # Number of Instructions Simulated +system.cpu2.cpi 4.253259 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.253259 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.235114 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.235114 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 159046643 # number of integer regfile reads +system.cpu2.int_regfile_writes 30194860 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22317 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20822 # number of floating regfile writes +system.cpu2.misc_regfile_reads 41979427 # number of misc regfile reads +system.cpu2.misc_regfile_writes 278833 # number of misc regfile writes +system.iocache.replacements 0 # number of replacements +system.iocache.tagsinuse 0 # Cycle average of tags in use +system.iocache.total_refs 0 # Total number of references to valid blocks. +system.iocache.sampled_refs 0 # Sample count of references to valid blocks. +system.iocache.avg_refs nan # Average number of references to valid blocks. +system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked +system.iocache.blocked::no_targets 0 # number of cycles access was blocked +system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.iocache.fast_writes 0 # number of fast writes performed +system.iocache.cache_copies 0 # number of cache copies performed +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 925539770424 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 925539770424 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 925539770424 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 925539770424 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency +system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency +system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.kern.inst.arm 0 # number of arm instructions executed +system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed + +---------- End Simulation Statistics ---------- diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal Binary files differnew file mode 100644 index 000000000..fa29081ad --- /dev/null +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal |