diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-03-23 11:12:19 -0400 |
| commit | 8b4b1dcb86b0799a8c32056427581a8b6249a3bf (patch) | |
| tree | 96016b415513dc6c2c29877e1a76220e0edae629 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | a00383a40aeb8347af7e05f3966ab141484921a5 (diff) | |
| download | gem5-8b4b1dcb86b0799a8c32056427581a8b6249a3bf.tar.xz | |
stats: Update stats for DRAM changes
This patch updates the stats to reflect the changes to the DRAM
controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 3105 |
1 files changed, 1469 insertions, 1636 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index c90f786a8..8e01cba8d 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,172 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403672 # Number of seconds simulated -sim_ticks 2403671650000 # Number of ticks simulated -final_tick 2403671650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403854 # Number of seconds simulated +sim_ticks 2403853586500 # Number of ticks simulated +final_tick 2403853586500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 179946 # Simulator instruction rate (inst/s) -host_op_rate 231118 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7169234406 # Simulator tick rate (ticks/s) -host_mem_usage 425424 # Number of bytes of host memory used -host_seconds 335.28 # Real time elapsed on the host -sim_insts 60331512 # Number of instructions simulated -sim_ops 77488235 # Number of ops (including micro ops) simulated +host_inst_rate 171159 # Simulator instruction rate (inst/s) +host_op_rate 219830 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6819657603 # Simulator tick rate (ticks/s) +host_mem_usage 469520 # Number of bytes of host memory used +host_seconds 352.49 # Real time elapsed on the host +sim_insts 60331708 # Number of instructions simulated +sim_ops 77487722 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7063576 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512776 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7053720 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 678080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 63616 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 681152 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186240 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1335136 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660096 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64640 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186240 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743616 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298488 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558028 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759432 # Number of bytes written to this memory +system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 186368 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1342304 # Number of bytes read from this memory +system.physmem.bytes_read::total 124659968 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512776 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 63616 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 186368 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 762760 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3743360 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298364 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558196 # Number of bytes written to this memory +system.physmem.bytes_written::total 6759176 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110404 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14224 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110250 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1010 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10595 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 994 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10643 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2910 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 20869 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512405 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58494 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324622 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389507 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812448 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47768202 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2912 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 20981 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512403 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58490 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324591 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389549 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812444 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764586 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2938661 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2934338 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26892 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 282102 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26464 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 283358 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77481 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 555457 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51862365 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213197 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26892 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77481 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317571 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557457 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540210 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648187 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557457 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47768202 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 558397 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858386 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26464 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77529 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317307 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557233 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540118 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648208 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2811809 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557233 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764586 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213197 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3478871 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3474456 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26892 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348375 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 26464 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 349609 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77481 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1203644 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54674493 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13478771 # Number of read requests accepted -system.physmem.writeReqs 446331 # Number of write requests accepted -system.physmem.readBursts 13478771 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446331 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 862641344 # Total number of bytes read from DRAM -system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue -system.physmem.bytesWritten 2859200 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109811808 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2805264 # Total written bytes from the system interface side -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 401653 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2355 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 837730 # Per bank write bursts -system.physmem.perBankRdBursts::1 837384 # Per bank write bursts -system.physmem.perBankRdBursts::2 837568 # Per bank write bursts -system.physmem.perBankRdBursts::3 837998 # Per bank write bursts -system.physmem.perBankRdBursts::4 839137 # Per bank write bursts -system.physmem.perBankRdBursts::5 839827 # Per bank write bursts -system.physmem.perBankRdBursts::6 839940 # Per bank write bursts -system.physmem.perBankRdBursts::7 841195 # Per bank write bursts -system.physmem.perBankRdBursts::8 842685 # Per bank write bursts -system.physmem.perBankRdBursts::9 845257 # Per bank write bursts -system.physmem.perBankRdBursts::10 845425 # Per bank write bursts -system.physmem.perBankRdBursts::11 845905 # Per bank write bursts -system.physmem.perBankRdBursts::12 847162 # Per bank write bursts -system.physmem.perBankRdBursts::13 848062 # Per bank write bursts -system.physmem.perBankRdBursts::14 846854 # Per bank write bursts -system.physmem.perBankRdBursts::15 846642 # Per bank write bursts -system.physmem.perBankWrBursts::0 2730 # Per bank write bursts -system.physmem.perBankWrBursts::1 2572 # Per bank write bursts -system.physmem.perBankWrBursts::2 2588 # Per bank write bursts -system.physmem.perBankWrBursts::3 3028 # Per bank write bursts -system.physmem.perBankWrBursts::4 3463 # Per bank write bursts -system.physmem.perBankWrBursts::5 3194 # Per bank write bursts -system.physmem.perBankWrBursts::6 2521 # Per bank write bursts -system.physmem.perBankWrBursts::7 2322 # Per bank write bursts -system.physmem.perBankWrBursts::8 2234 # Per bank write bursts -system.physmem.perBankWrBursts::9 2386 # Per bank write bursts -system.physmem.perBankWrBursts::10 2377 # Per bank write bursts -system.physmem.perBankWrBursts::11 2814 # Per bank write bursts -system.physmem.perBankWrBursts::12 3729 # Per bank write bursts -system.physmem.perBankWrBursts::13 3501 # Per bank write bursts -system.physmem.perBankWrBursts::14 2651 # Per bank write bursts -system.physmem.perBankWrBursts::15 2565 # Per bank write bursts +system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1206604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54670195 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13446822 # Number of read requests accepted +system.physmem.writeReqs 446449 # Number of write requests accepted +system.physmem.readBursts 13446822 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446449 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860596480 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 128 # Total number of bytes read from write queue +system.physmem.bytesWritten 2823168 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109564448 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2810956 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 2 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 402307 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2362 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835680 # Per bank write bursts +system.physmem.perBankRdBursts::1 835344 # Per bank write bursts +system.physmem.perBankRdBursts::2 835508 # Per bank write bursts +system.physmem.perBankRdBursts::3 835965 # Per bank write bursts +system.physmem.perBankRdBursts::4 837088 # Per bank write bursts +system.physmem.perBankRdBursts::5 837779 # Per bank write bursts +system.physmem.perBankRdBursts::6 837907 # Per bank write bursts +system.physmem.perBankRdBursts::7 839147 # Per bank write bursts +system.physmem.perBankRdBursts::8 840641 # Per bank write bursts +system.physmem.perBankRdBursts::9 843268 # Per bank write bursts +system.physmem.perBankRdBursts::10 843373 # Per bank write bursts +system.physmem.perBankRdBursts::11 843869 # Per bank write bursts +system.physmem.perBankRdBursts::12 845852 # Per bank write bursts +system.physmem.perBankRdBursts::13 846016 # Per bank write bursts +system.physmem.perBankRdBursts::14 844806 # Per bank write bursts +system.physmem.perBankRdBursts::15 844577 # Per bank write bursts +system.physmem.perBankWrBursts::0 2668 # Per bank write bursts +system.physmem.perBankWrBursts::1 2526 # Per bank write bursts +system.physmem.perBankWrBursts::2 2530 # Per bank write bursts +system.physmem.perBankWrBursts::3 3005 # Per bank write bursts +system.physmem.perBankWrBursts::4 3419 # Per bank write bursts +system.physmem.perBankWrBursts::5 3167 # Per bank write bursts +system.physmem.perBankWrBursts::6 2515 # Per bank write bursts +system.physmem.perBankWrBursts::7 2303 # Per bank write bursts +system.physmem.perBankWrBursts::8 2186 # Per bank write bursts +system.physmem.perBankWrBursts::9 2396 # Per bank write bursts +system.physmem.perBankWrBursts::10 2346 # Per bank write bursts +system.physmem.perBankWrBursts::11 2792 # Per bank write bursts +system.physmem.perBankWrBursts::12 3710 # Per bank write bursts +system.physmem.perBankWrBursts::13 3446 # Per bank write bursts +system.physmem.perBankWrBursts::14 2600 # Per bank write bursts +system.physmem.perBankWrBursts::15 2503 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402635561500 # Total gap between requests +system.physmem.totGap 2402817511500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 8 # Read request sizes (log2) -system.physmem.readPktSize::3 13443376 # Read request sizes (log2) +system.physmem.readPktSize::3 13411280 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35387 # Read request sizes (log2) +system.physmem.readPktSize::6 35534 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429332 # Write request sizes (log2) +system.physmem.writePktSize::2 429363 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 16999 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 985231 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 962596 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 957159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3278666 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2351782 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2351346 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2368287 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 47071 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 52789 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 17803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 17814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 17764 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 17625 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 17616 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 17601 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 17598 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17086 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 867414 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 844196 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 838512 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 839224 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 838671 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 838847 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2475363 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2475187 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3292199 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 20391 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 19694 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 19741 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 19565 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 19474 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 19175 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 19145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 22 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,369 +182,159 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2018 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2412 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2043 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2191 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2298 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2012 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2035 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1989 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1974 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1969 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1955 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1949 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1945 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 48736 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 17758.945502 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 3164.892038 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 18326.287457 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-71 8690 17.83% 17.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-135 4827 9.90% 27.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-199 1035 2.12% 29.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-263 694 1.42% 31.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-327 398 0.82% 32.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-391 429 0.88% 32.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-455 259 0.53% 33.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-519 302 0.62% 34.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-583 176 0.36% 34.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-647 149 0.31% 34.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-711 171 0.35% 35.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-775 272 0.56% 35.71% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-839 78 0.16% 35.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-903 84 0.17% 36.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-967 41 0.08% 36.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1031 422 0.87% 36.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1095 26 0.05% 37.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1159 34 0.07% 37.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1287 232 0.48% 37.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1351 28 0.06% 37.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1415 166 0.34% 38.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1479 13 0.03% 38.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1543 104 0.21% 38.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1607 12 0.02% 38.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1671 32 0.07% 38.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1735 7 0.01% 38.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1799 80 0.16% 38.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1863 11 0.02% 38.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1991 7 0.01% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2055 239 0.49% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2119 4 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2183 11 0.02% 39.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2247 7 0.01% 39.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2311 71 0.15% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2375 4 0.01% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2439 5 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2567 72 0.15% 39.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2759 1 0.00% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2823 3 0.01% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2951 6 0.01% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3015 4 0.01% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3079 360 0.74% 40.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3143 3 0.01% 40.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3207 3 0.01% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3271 2 0.00% 40.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3335 69 0.14% 40.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3527 6 0.01% 40.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3847 67 0.14% 40.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3904-3911 5 0.01% 40.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3968-3975 9 0.02% 40.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4039 4 0.01% 40.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4103 338 0.69% 41.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4160-4167 3 0.01% 41.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4359 70 0.14% 41.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4423 13 0.03% 41.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4480-4487 5 0.01% 41.68% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4544-4551 7 0.01% 41.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4608-4615 72 0.15% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4679 1 0.00% 41.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4736-4743 5 0.01% 41.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4807 3 0.01% 41.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4864-4871 64 0.13% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4935 3 0.01% 41.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5056-5063 3 0.01% 42.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5127 280 0.57% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5248-5255 2 0.00% 42.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5383 73 0.15% 42.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5447 4 0.01% 42.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5504-5511 4 0.01% 42.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5568-5575 1 0.00% 42.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5632-5639 129 0.26% 43.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5888-5895 176 0.36% 43.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6144-6151 327 0.67% 44.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6208-6215 5 0.01% 44.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6279 7 0.01% 44.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.12% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6400-6407 98 0.20% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6471 1 0.00% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6535 1 0.00% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6656-6663 73 0.15% 44.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6720-6727 4 0.01% 44.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6855 2 0.00% 44.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6912-6919 60 0.12% 44.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6983 5 0.01% 44.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7175 268 0.55% 45.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7296-7303 1 0.00% 45.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7367 7 0.01% 45.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7431 66 0.14% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7616-7623 1 0.00% 45.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7687 64 0.13% 45.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7943 42 0.09% 45.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8071 2 0.00% 45.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8199 515 1.06% 46.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8455 42 0.09% 46.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8704-8711 66 0.14% 46.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8967 65 0.13% 46.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9223 267 0.55% 47.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9479 59 0.12% 47.66% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9728-9735 69 0.14% 47.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9984-9991 94 0.19% 47.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10240-10247 322 0.66% 48.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10496-10503 138 0.28% 48.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::10752-10759 128 0.26% 49.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11008-11015 70 0.14% 49.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11264-11271 279 0.57% 49.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11520-11527 60 0.12% 50.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11648-11655 1 0.00% 50.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::11776-11783 64 0.13% 50.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12039 65 0.13% 50.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12288-12295 328 0.67% 50.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12544-12551 63 0.13% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12608-12615 1 0.00% 51.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12800-12807 64 0.13% 51.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13056-13063 64 0.13% 51.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13312-13319 357 0.73% 52.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::13952-13959 1 0.00% 52.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14208-14215 1 0.00% 52.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14336-14343 229 0.47% 52.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14592-14599 64 0.13% 52.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14855 64 0.13% 53.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15104-15111 190 0.39% 53.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15360-15367 321 0.66% 54.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16128-16135 64 0.13% 54.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16384-16391 672 1.38% 55.80% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16640-16647 64 0.13% 55.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17152-17159 64 0.13% 56.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17415 321 0.66% 56.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17671 189 0.39% 57.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17920-17927 65 0.13% 57.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18176-18183 64 0.13% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18368-18375 1 0.00% 57.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18432-18439 229 0.47% 57.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::18944-18951 63 0.13% 58.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19456-19463 357 0.73% 58.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19712-19719 65 0.13% 58.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19904-19911 1 0.00% 58.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20231 64 0.13% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20352-20359 1 0.00% 59.25% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20480-20487 327 0.67% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20608-20615 1 0.00% 59.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20736-20743 64 0.13% 60.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21248-21255 61 0.13% 60.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21504-21511 274 0.56% 60.87% # Bytes accessed per row activation -system.physmem.bytesPerActivate::21760-21767 69 0.14% 61.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22016-22023 128 0.26% 61.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22272-22279 137 0.28% 61.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22336-22343 1 0.00% 61.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22528-22535 323 0.66% 62.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22791 93 0.19% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22848-22855 1 0.00% 62.41% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23040-23047 68 0.14% 62.55% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23296-23303 57 0.12% 62.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23552-23559 268 0.55% 63.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::23808-23815 65 0.13% 63.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24064-24071 65 0.13% 63.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24320-24327 43 0.09% 63.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24583 514 1.05% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24768-24775 1 0.00% 64.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24832-24839 42 0.09% 64.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25088-25095 66 0.14% 64.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25344-25351 64 0.13% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25408-25415 1 0.00% 64.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25472-25479 1 0.00% 64.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25600-25607 264 0.54% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25863 57 0.12% 65.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26112-26119 69 0.14% 65.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26368-26375 95 0.19% 65.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26624-26631 323 0.66% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26752-26759 1 0.00% 66.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::26880-26887 137 0.28% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27008-27015 1 0.00% 66.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27136-27143 127 0.26% 67.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27392-27399 68 0.14% 67.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27655 275 0.56% 67.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27904-27911 61 0.13% 68.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28160-28167 64 0.13% 68.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28416-28423 65 0.13% 68.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28672-28679 329 0.68% 68.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::28928-28935 65 0.13% 69.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29184-29191 64 0.13% 69.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29447 64 0.13% 69.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29696-29703 356 0.73% 70.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30208-30215 65 0.13% 70.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30727 228 0.47% 70.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30976-30983 64 0.13% 70.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31239 64 0.13% 71.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31488-31495 189 0.39% 71.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31744-31751 321 0.66% 72.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32000-32007 63 0.13% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32512-32519 64 0.13% 72.39% # Bytes accessed per row activation -system.physmem.bytesPerActivate::32768-32775 673 1.38% 73.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33031 64 0.13% 73.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33799 321 0.66% 74.70% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34048-34055 189 0.39% 75.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34311 64 0.13% 75.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34560-34567 65 0.13% 75.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34823 229 0.47% 75.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35328-35335 65 0.13% 76.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35847 356 0.73% 76.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36096-36103 64 0.13% 76.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::36864-36871 329 0.68% 77.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37120-37127 65 0.13% 78.02% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37632-37639 61 0.13% 78.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37895 276 0.57% 78.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38144-38151 68 0.14% 78.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38400-38407 127 0.26% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38528-38535 1 0.00% 79.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38656-38663 137 0.28% 79.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38919 322 0.66% 80.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39168-39175 94 0.19% 80.38% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39424-39431 69 0.14% 80.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39680-39687 57 0.12% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.64% # Bytes accessed per row activation -system.physmem.bytesPerActivate::39936-39943 264 0.54% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40128-40135 1 0.00% 81.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40199 64 0.13% 81.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40448-40455 65 0.13% 81.45% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40704-40711 42 0.09% 81.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40967 513 1.05% 82.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41216-41223 43 0.09% 82.67% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.81% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41728-41735 65 0.13% 82.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41991 266 0.55% 83.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42240-42247 57 0.12% 83.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42496-42503 68 0.14% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42688-42695 1 0.00% 83.74% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42759 93 0.19% 83.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43008-43015 323 0.66% 84.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43264-43271 137 0.28% 84.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43520-43527 128 0.26% 85.14% # Bytes accessed per row activation -system.physmem.bytesPerActivate::43776-43783 69 0.14% 85.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44032-44039 274 0.56% 85.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44288-44295 61 0.13% 85.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44544-44551 64 0.13% 86.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44800-44807 64 0.13% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::44928-44935 1 0.00% 86.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45056-45063 327 0.67% 86.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45184-45191 1 0.00% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45312-45319 64 0.13% 87.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45568-45575 64 0.13% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45632-45639 1 0.00% 87.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::45824-45831 64 0.13% 87.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46080-46087 356 0.73% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46528-46535 1 0.00% 88.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46592-46599 63 0.13% 88.17% # Bytes accessed per row activation -system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47104-47111 228 0.47% 88.77% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47360-47367 64 0.13% 88.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47616-47623 65 0.13% 89.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47879 190 0.39% 89.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48128-48135 322 0.66% 90.08% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::48896-48903 64 0.13% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::49152-49159 4701 9.65% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 48736 # Bytes accessed per row activation -system.physmem.totQLat 326317088000 # Total ticks spent queuing -system.physmem.totMemAccLat 407972525500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67393855000 # Total ticks spent in databus transfers -system.physmem.totBankLat 14261582500 # Total ticks spent accessing banks -system.physmem.avgQLat 24209.71 # Average queueing delay per DRAM burst -system.physmem.avgBankLat 1058.08 # Average bank access latency per DRAM burst +system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 93 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 94 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1109 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1147 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1244 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1477 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1625 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1655 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 1647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 1678 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 1696 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1634 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 1798 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 1677 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 1653 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 1860 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 1651 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 1605 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 1601 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 1586 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 921 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 694 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 710 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::36 756 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::37 736 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::38 686 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::39 713 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::40 689 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::41 683 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::42 692 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::43 654 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::44 671 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::45 647 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::46 642 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::47 640 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::48 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::49 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::50 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::51 635 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::52 638 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::53 646 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::54 10 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::55 2 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.physmem.bytesPerActivate::samples 844644 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 1019.942660 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 1014.395909 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 58.300980 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 1516 0.18% 0.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 1237 0.15% 0.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 570 0.07% 0.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 375 0.04% 0.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 256 0.03% 0.47% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 198 0.02% 0.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 155 0.02% 0.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 158 0.02% 0.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 840179 99.47% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 844644 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 1621 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 8295.373226 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 315033.644502 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 1620 99.94% 99.94% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.06% 100.00% # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::total 1621 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 1621 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 27.212832 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 24.563019 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 12.121341 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 1 0.06% 0.06% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.12% 0.19% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 1 0.06% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.06% 0.31% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.06% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.06% 0.43% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.06% 0.49% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::12 2 0.12% 0.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 6 0.37% 0.99% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 488 30.10% 31.09% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 27 1.67% 32.76% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 60 3.70% 36.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 333 20.54% 57.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 10 0.62% 57.62% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 3 0.19% 57.80% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 2 0.12% 57.93% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 3 0.19% 58.11% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 2 0.12% 58.24% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 3 0.19% 58.42% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 5 0.31% 58.73% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.25% 58.98% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 5 0.31% 59.28% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 7 0.43% 59.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 3 0.19% 59.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 2 0.12% 60.02% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 8 0.49% 60.52% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::33 2 0.12% 60.64% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::34 1 0.06% 60.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::39 50 3.08% 63.79% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::40 4 0.25% 64.03% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::41 167 10.30% 74.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::42 328 20.23% 94.57% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::43 16 0.99% 95.56% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::44 15 0.93% 96.48% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::45 23 1.42% 97.90% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::46 17 1.05% 98.95% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::47 13 0.80% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::48 2 0.12% 99.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::49 2 0.12% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 1621 # Writes before turning the bus around for reads +system.physmem.totQLat 510864117000 # Total ticks spent queuing +system.physmem.totMemAccLat 601782495750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67234100000 # Total ticks spent in databus transfers +system.physmem.totBankLat 23684278750 # Total ticks spent accessing banks +system.physmem.avgQLat 37991.44 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1761.33 # Average bank access latency per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 30267.78 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s -system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44752.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.01 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing -system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing -system.physmem.readRowHits 13435330 # Number of row buffer hits during reads -system.physmem.writeRowHits 39380 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes -system.physmem.avgGap 172539.89 # Average gap between requests -system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined -system.physmem.prechargeAllPercent 0.87 # Percentage of time for which DRAM has all the banks in precharge state +system.physmem.avgRdQLen 8.42 # Average read queue length when enqueuing +system.physmem.avgWrQLen 5.41 # Average write queue length when enqueuing +system.physmem.readRowHits 12595156 # Number of row buffer hits during reads +system.physmem.writeRowHits 38053 # Number of row buffer hits during writes +system.physmem.readRowHitRate 93.67 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 86.21 # Row buffer hit rate for writes +system.physmem.avgGap 172948.29 # Average gap between requests +system.physmem.pageHitRate 93.64 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 2.74 # Percentage of time for which DRAM has all the banks in precharge state system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory @@ -553,322 +347,341 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55671828 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13814146 # Transaction distribution -system.membus.trans_dist::ReadResp 13814146 # Transaction distribution -system.membus.trans_dist::WriteReq 432166 # Transaction distribution -system.membus.trans_dist::WriteResp 432166 # Transaction distribution -system.membus.trans_dist::Writeback 16999 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2355 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2355 # Transaction distribution -system.membus.trans_dist::ReadExReq 27802 # Transaction distribution -system.membus.trans_dist::ReadExResp 27802 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731808 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951163 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683185 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26886752 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28569937 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735681 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070064 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5806173 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107547008 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107547008 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113353181 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816795 # Total data (bytes) +system.membus.throughput 55667457 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13781916 # Transaction distribution +system.membus.trans_dist::ReadResp 13781916 # Transaction distribution +system.membus.trans_dist::WriteReq 432200 # Transaction distribution +system.membus.trans_dist::WriteResp 432200 # Transaction distribution +system.membus.trans_dist::Writeback 17086 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2361 # Transaction distribution +system.membus.trans_dist::SCUpgradeReq 1 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2362 # Transaction distribution +system.membus.trans_dist::ReadExReq 27973 # Transaction distribution +system.membus.trans_dist::ReadExResp 27973 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731598 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 210 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951620 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1683428 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26822560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26822560 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28505988 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735468 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 420 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5085164 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5821052 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107290240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107290240 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113111292 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133816415 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416936000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 416850000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 202000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 198000 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607946000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14576843000 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1594364889 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1595419615 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30360976750 # Layer occupancy (ticks) -system.membus.respLayer2.utilization 1.3 # Layer utilization (%) +system.membus.respLayer2.occupancy 33523642000 # Layer occupancy (ticks) +system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63237 # number of replacements -system.l2c.tags.tagsinuse 50379.569066 # Cycle average of tags in use -system.l2c.tags.total_refs 1749643 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128631 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.602032 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375594870500 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36839.610574 # Average occupied blocks per requestor +system.l2c.tags.replacements 63235 # number of replacements +system.l2c.tags.tagsinuse 50381.174231 # Cycle average of tags in use +system.l2c.tags.total_refs 1749008 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128627 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.597518 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375559570500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36838.397677 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5231.934240 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3832.971184 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.inst 5238.516596 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3833.196793 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 504.116293 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 687.425497 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.900489 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1683.581513 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1591.035818 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562128 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu1.inst 493.229672 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 688.317801 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.879272 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.itb.walker 0.004789 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1684.639749 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1594.998425 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562109 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079833 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058486 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079933 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058490 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007692 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010489 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000121 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025689 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024277 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768731 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65392 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6494 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55883 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997803 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683980 # Number of tag accesses -system.l2c.tags.data_accesses 17683980 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8701 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3143 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 467937 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177040 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2608 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1169 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 128901 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64374 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18792 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4308 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 282422 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131846 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291241 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597674 # number of Writeback hits -system.l2c.Writeback_hits::total 597674 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007526 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010503 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000135 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.itb.walker 0.000000 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025706 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024338 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768756 # Average percentage of cache occupancy +system.l2c.tags.occ_task_id_blocks::1023 6 # Occupied blocks per task id +system.l2c.tags.occ_task_id_blocks::1024 65386 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1023::4 6 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::1 337 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::2 2640 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::3 6490 # Occupied blocks per task id +system.l2c.tags.age_task_id_blocks_1024::4 55882 # Occupied blocks per task id +system.l2c.tags.occ_task_id_percent::1023 0.000092 # Percentage of cache occupancy per task id +system.l2c.tags.occ_task_id_percent::1024 0.997711 # Percentage of cache occupancy per task id +system.l2c.tags.tag_accesses 17681539 # Number of tag accesses +system.l2c.tags.data_accesses 17681539 # Number of data accesses +system.l2c.ReadReq_hits::cpu0.dtb.walker 8692 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 468000 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 177035 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2622 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1183 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 129681 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64527 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18896 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281169 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 131701 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290860 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597704 # number of Writeback hits +system.l2c.Writeback_hits::total 597704 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 62009 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18402 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33187 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113598 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8701 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3143 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 467937 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239049 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2608 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1169 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 128901 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 82776 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.dtb.walker 18792 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.itb.walker 4308 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 282422 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 165033 # number of demand (read+write) hits -system.l2c.demand_hits::total 1404839 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.dtb.walker 8701 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3143 # number of overall hits -system.l2c.overall_hits::cpu0.inst 467937 # number of overall hits -system.l2c.overall_hits::cpu0.data 239049 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2608 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1169 # number of overall hits -system.l2c.overall_hits::cpu1.inst 128901 # number of overall hits -system.l2c.overall_hits::cpu1.data 82776 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18792 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4308 # number of overall hits -system.l2c.overall_hits::cpu2.inst 282422 # number of overall hits -system.l2c.overall_hits::cpu2.data 165033 # number of overall hits -system.l2c.overall_hits::total 1404839 # number of overall hits +system.l2c.UpgradeReq_hits::cpu2.data 15 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 33 # number of UpgradeReq hits +system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits +system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits +system.l2c.ReadExReq_hits::cpu0.data 61997 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 18431 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2.data 33199 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113627 # number of ReadExReq hits +system.l2c.demand_hits::cpu0.dtb.walker 8692 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.itb.walker 3137 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.inst 468000 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 239032 # 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average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.itb.walker 62500 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 62767.771291 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61949.052146 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61833.263466 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1021,52 +854,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58818769 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1020134 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1020133 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432166 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432166 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265053 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80260 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80260 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831165 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419053 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15627 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52402 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3318247 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26575552 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37346205 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85644 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64029309 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141280603 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100404 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176001251 # Layer occupancy (ticks) +system.toL2Bus.throughput 58805312 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1019677 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1019676 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432200 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432200 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265274 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1507 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1511 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80476 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80476 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830192 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419562 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15560 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52654 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3317968 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26544384 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37373820 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21604 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86116 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64025924 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141258487 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 100872 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2176910263 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1872526171 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1870334166 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845075146 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1845880168 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10168460 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10179455 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31121231 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31260469 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48762623 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13806510 # Transaction distribution -system.iobus.trans_dist::ReadResp 13806510 # Transaction distribution -system.iobus.trans_dist::WriteReq 2770 # Transaction distribution -system.iobus.trans_dist::WriteResp 2770 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11390 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758934 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13774305 # Transaction distribution +system.iobus.trans_dist::ReadResp 13774305 # Transaction distribution +system.iobus.trans_dist::WriteReq 2774 # Transaction distribution +system.iobus.trans_dist::WriteResp 2774 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11404 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3022 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 252 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716834 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716614 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -1082,18 +915,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731808 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886752 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26886752 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27618560 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15354 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 731598 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26822560 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26822560 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27554158 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15368 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6044 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 504 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713159 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 712940 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -1109,18 +942,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735681 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107547008 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107547008 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108282689 # Cumulative packet size per connected master and slave (bytes) -system.iobus.data_through_bus 117209335 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7953000 # Layer occupancy (ticks) +system.iobus.tot_pkt_size_system.bridge.master::total 735468 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107290240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107290240 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108025708 # Cumulative packet size per connected master and slave (bytes) +system.iobus.data_through_bus 117209339 # Total data (bytes) +system.iobus.reqLayer0.occupancy 7964000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1511000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 126000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -1128,7 +961,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358920000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 358810000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -1160,12 +993,12 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443376000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13411280000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 729038000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 728824000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36855449250 # Layer occupancy (ticks) -system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) +system.iobus.respLayer1.occupancy 33525822000 # Layer occupancy (ticks) +system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1189,25 +1022,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7998897 # DTB read hits +system.cpu0.dtb.read_hits 7997782 # DTB read hits system.cpu0.dtb.read_misses 6203 # DTB read misses -system.cpu0.dtb.write_hits 6598042 # DTB write hits -system.cpu0.dtb.write_misses 1992 # DTB write misses +system.cpu0.dtb.write_hits 6595987 # DTB write hits +system.cpu0.dtb.write_misses 1983 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5672 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5673 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8005100 # DTB read accesses -system.cpu0.dtb.write_accesses 6600034 # DTB write accesses +system.cpu0.dtb.read_accesses 8003985 # DTB read accesses +system.cpu0.dtb.write_accesses 6597970 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14596939 # DTB hits -system.cpu0.dtb.misses 8195 # DTB misses -system.cpu0.dtb.accesses 14605134 # DTB accesses +system.cpu0.dtb.hits 14593769 # DTB hits +system.cpu0.dtb.misses 8186 # DTB misses +system.cpu0.dtb.accesses 14601955 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1229,15 +1062,15 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32342389 # ITB inst hits -system.cpu0.itb.inst_misses 3452 # ITB inst misses +system.cpu0.itb.inst_hits 32336935 # ITB inst hits +system.cpu0.itb.inst_misses 3451 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions @@ -1246,416 +1079,416 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32345841 # ITB inst accesses -system.cpu0.itb.hits 32342389 # DTB hits -system.cpu0.itb.misses 3452 # DTB misses -system.cpu0.itb.accesses 32345841 # DTB accesses -system.cpu0.numCycles 113704712 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32340386 # ITB inst accesses +system.cpu0.itb.hits 32336935 # DTB hits +system.cpu0.itb.misses 3451 # DTB misses +system.cpu0.itb.accesses 32340386 # DTB accesses +system.cpu0.numCycles 113724377 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31867189 # Number of instructions committed -system.cpu0.committedOps 42038889 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37421309 # Number of integer alu accesses +system.cpu0.committedInsts 31861763 # Number of instructions committed +system.cpu0.committedOps 42032224 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37415212 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1198994 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4247035 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37421309 # number of integer instructions +system.cpu0.num_func_calls 1199152 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4246542 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37415212 # number of integer instructions system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193973220 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39529492 # number of times the integer registers were written +system.cpu0.num_int_register_reads 193939915 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39523913 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15264742 # number of memory refs -system.cpu0.num_load_insts 8367651 # Number of load instructions -system.cpu0.num_store_insts 6897091 # Number of store instructions -system.cpu0.num_idle_cycles 111017320.581957 # Number of idle cycles -system.cpu0.num_busy_cycles 2687391.418043 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023635 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976365 # Percentage of idle cycles -system.cpu0.Branches 5615714 # Number of branches fetched +system.cpu0.num_mem_refs 15261638 # number of memory refs +system.cpu0.num_load_insts 8366552 # Number of load instructions +system.cpu0.num_store_insts 6895086 # Number of store instructions +system.cpu0.num_idle_cycles 110931893.434026 # Number of idle cycles +system.cpu0.num_busy_cycles 2792483.565974 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024555 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975445 # Percentage of idle cycles +system.cpu0.Branches 5615139 # Number of branches fetched system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891676 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602493 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43661110 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892188 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.937119 # Average number of references to valid blocks. +system.cpu0.icache.tags.replacements 891249 # number of replacements +system.cpu0.icache.tags.tagsinuse 511.602369 # Cycle average of tags in use +system.cpu0.icache.tags.total_refs 43668526 # Total number of references to valid blocks. +system.cpu0.icache.tags.sampled_refs 891761 # Sample count of references to valid blocks. +system.cpu0.icache.tags.avg_refs 48.968867 # Average number of references to valid blocks. system.cpu0.icache.tags.warmup_cycle 8187850250 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.418624 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.559512 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.624357 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967615 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014765 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.016844 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.923201 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.626935 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.052233 # Average occupied blocks per requestor +system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966647 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014896 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017680 # Average percentage of cache occupancy +system.cpu0.icache.tags.occ_percent::total 0.999223 # Average percentage of cache occupancy system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id -system.cpu0.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::0 134 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::1 209 # Occupied blocks per task id +system.cpu0.icache.tags.age_task_id_blocks_1024::2 166 # Occupied blocks per task id system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.icache.tags.tag_accesses 45469557 # Number of tag accesses -system.cpu0.icache.tags.data_accesses 45469557 # Number of data accesses -system.cpu0.icache.ReadReq_hits::cpu0.inst 31868764 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 8050810 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu2.inst 3741536 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 43661110 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 31868764 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 8050810 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu2.inst 3741536 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 43661110 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 31868764 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 8050810 # number of overall hits -system.cpu0.icache.overall_hits::cpu2.inst 3741536 # number of overall hits -system.cpu0.icache.overall_hits::total 43661110 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 476273 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 130180 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu2.inst 309800 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 916253 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 476273 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 130180 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu2.inst 309800 # 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Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970843 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015816 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013335 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.048952 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.104316 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.843850 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970799 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015829 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013367 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 302 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98826568 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98826568 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6868032 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1817018 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4638626 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13323676 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5966375 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1312197 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2134420 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9412992 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131825 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32972 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73365 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 238162 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138288 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34722 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74382 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 12834407 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu1.data 3129215 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::cpu2.data 6773046 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 22736668 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 12834407 # number of overall hits -system.cpu0.dcache.overall_hits::cpu1.data 3129215 # number of overall hits -system.cpu0.dcache.overall_hits::cpu2.data 6773046 # number of overall hits -system.cpu0.dcache.overall_hits::total 22736668 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 177045 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu1.data 63739 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::cpu2.data 270648 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 511432 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 168130 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu1.data 28623 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::cpu2.data 606733 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 803486 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6464 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1750 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3698 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 11912 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 345175 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92362 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 877381 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1314918 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345175 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92362 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 877381 # number of overall misses -system.cpu0.dcache.overall_misses::total 1314918 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908043250 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3905088066 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4813131316 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1020010237 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23150589506 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 24170599743 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23020750 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49421249 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 72441999 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu1.data 1928053487 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::cpu2.data 27055677572 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 28983731059 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1928053487 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 27055677572 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28983731059 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7045077 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1880757 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4909274 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13835108 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6134505 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1340820 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2741153 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216478 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138289 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34722 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77063 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250074 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138288 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34722 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74384 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 247394 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 13179582 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3221577 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7650427 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24051586 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13179582 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3221577 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7650427 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24051586 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025130 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033890 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055130 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027407 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021347 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221342 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078646 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046743 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050400 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047987 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047634 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028670 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114684 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054671 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028670 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114684 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054671 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14246.273867 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14428.660348 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.087527 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35636.035251 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38156.140355 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 30082.166638 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13154.714286 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13364.318280 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6081.430406 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20874.964672 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30836.862859 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22042.234618 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20874.964672 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30836.862859 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22042.234618 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7997 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3099 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 875 # 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number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025134 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033899 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055023 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.036930 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027390 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021352 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221987 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078780 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046753 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050558 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048174 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047720 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026184 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028675 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114836 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054706 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026184 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028675 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114836 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054706 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14247.871141 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14407.358418 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9395.764623 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35137.812348 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37790.547259 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 29809.294069 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13146.105742 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13340.088608 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6086.600402 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 16125.250000 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 16125.250000 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20723.829629 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30600.203178 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 21882.044193 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20723.829629 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30600.203178 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 21882.044193 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 7912 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2132 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 872 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 43 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.073394 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 49.581395 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597674 # number of writebacks -system.cpu0.dcache.writebacks::total 597674 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139516 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 139516 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 553631 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 553631 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 397 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 397 # 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number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2479004099 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 960165763 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1859721243 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2819887006 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19520250 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38036501 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57556751 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1740534513 # 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number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13338859363 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14777965857 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840139494 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41912317863 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70752457357 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033890 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026711 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014085 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019372 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007999 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050400 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042835 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020198 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011500 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011500 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12243.190982 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12953.629541 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12721.257134 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33545.252524 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35021.679843 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34504.582515 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11154.428571 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11522.720691 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.119976 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597704 # number of writebacks +system.cpu0.dcache.writebacks::total 597704 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139099 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 139099 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 554931 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 554931 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 402 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::total 402 # number of LoadLockedReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu2.data 694030 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 694030 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu2.data 694030 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 694030 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63884 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130960 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 194844 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28702 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53249 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 81951 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1759 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3311 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5070 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 4 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1850547743 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2799145253 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19606000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38066251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57672251 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 56499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 56499 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1730851510 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543754841 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5274606351 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1730851510 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543754841 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5274606351 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27378129500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579482250 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55957611750 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439295977 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341687506 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14780983483 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817425477 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41921169756 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70738595233 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033899 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026683 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014082 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021352 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019436 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008021 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050558 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042958 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020268 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011508 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028675 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024087 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011508 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12244.912654 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12929.192868 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.836166 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33049.874922 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34752.722924 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34156.328208 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11146.105742 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11496.904561 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11375.197436 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 14124.750000 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18694.527358 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19237.685678 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19056.003002 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1689,25 +1522,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2093956 # DTB read hits -system.cpu1.dtb.read_misses 2077 # DTB read misses -system.cpu1.dtb.write_hits 1416211 # DTB write hits +system.cpu1.dtb.read_hits 2097642 # DTB read hits +system.cpu1.dtb.read_misses 2089 # DTB read misses +system.cpu1.dtb.write_hits 1419704 # DTB write hits system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1760 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1767 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2096033 # DTB read accesses -system.cpu1.dtb.write_accesses 1416584 # DTB write accesses +system.cpu1.dtb.read_accesses 2099731 # DTB read accesses +system.cpu1.dtb.write_accesses 1420077 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3510167 # DTB hits -system.cpu1.dtb.misses 2450 # DTB misses -system.cpu1.dtb.accesses 3512617 # DTB accesses +system.cpu1.dtb.hits 3517346 # DTB hits +system.cpu1.dtb.misses 2462 # DTB misses +system.cpu1.dtb.accesses 3519808 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1729,8 +1562,8 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8180990 # ITB inst hits -system.cpu1.itb.inst_misses 1185 # ITB inst misses +system.cpu1.itb.inst_hits 8195558 # ITB inst hits +system.cpu1.itb.inst_misses 1195 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -1739,51 +1572,51 @@ system.cpu1.itb.flush_tlb 554 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 944 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8182175 # ITB inst accesses -system.cpu1.itb.hits 8180990 # DTB hits -system.cpu1.itb.misses 1185 # DTB misses -system.cpu1.itb.accesses 8182175 # DTB accesses -system.cpu1.numCycles 581419148 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8196753 # ITB inst accesses +system.cpu1.itb.hits 8195558 # DTB hits +system.cpu1.itb.misses 1195 # DTB misses +system.cpu1.itb.accesses 8196753 # DTB accesses +system.cpu1.numCycles 584703165 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7970398 # Number of instructions committed -system.cpu1.committedOps 10116193 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9089557 # Number of integer alu accesses +system.cpu1.committedInsts 7984738 # Number of instructions committed +system.cpu1.committedOps 10135701 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9107037 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304010 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1112792 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9089557 # number of integer instructions +system.cpu1.num_func_calls 304651 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1115193 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9107037 # number of integer instructions system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 52989642 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9881584 # number of times the integer registers were written +system.cpu1.num_int_register_reads 53092313 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9899825 # number of times the integer registers were written system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3676962 # number of memory refs -system.cpu1.num_load_insts 2186992 # Number of load instructions -system.cpu1.num_store_insts 1489970 # Number of store instructions -system.cpu1.num_idle_cycles 545339727.510646 # Number of idle cycles -system.cpu1.num_busy_cycles 36079420.489354 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062054 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937946 # Percentage of idle cycles -system.cpu1.Branches 1445114 # Number of branches fetched +system.cpu1.num_mem_refs 3684662 # number of memory refs +system.cpu1.num_load_insts 2190856 # Number of load instructions +system.cpu1.num_store_insts 1493806 # Number of store instructions +system.cpu1.num_idle_cycles 548865377.428164 # Number of idle cycles +system.cpu1.num_busy_cycles 35837787.571836 # Number of busy cycles +system.cpu1.not_idle_fraction 0.061292 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.938708 # Percentage of idle cycles +system.cpu1.Branches 1448177 # Number of branches fetched system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4780240 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3898194 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223690 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3180058 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2524004 # Number of BTB hits +system.cpu2.branchPred.lookups 4782343 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3901882 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223184 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3184465 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2528356 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.369747 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 414035 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21682 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.396571 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 413120 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21664 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1807,25 +1640,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10926394 # DTB read hits -system.cpu2.dtb.read_misses 23081 # DTB read misses -system.cpu2.dtb.write_hits 3349602 # DTB write hits -system.cpu2.dtb.write_misses 6536 # DTB write misses +system.cpu2.dtb.read_hits 10925413 # DTB read hits +system.cpu2.dtb.read_misses 23157 # DTB read misses +system.cpu2.dtb.write_hits 3347832 # DTB write hits +system.cpu2.dtb.write_misses 6500 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 728 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 164 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2330 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 739 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10949475 # DTB read accesses -system.cpu2.dtb.write_accesses 3356138 # DTB write accesses +system.cpu2.dtb.perms_faults 476 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10948570 # DTB read accesses +system.cpu2.dtb.write_accesses 3354332 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14275996 # DTB hits -system.cpu2.dtb.misses 29617 # DTB misses -system.cpu2.dtb.accesses 14305613 # DTB accesses +system.cpu2.dtb.hits 14273245 # DTB hits +system.cpu2.dtb.misses 29657 # DTB misses +system.cpu2.dtb.accesses 14302902 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1847,294 +1680,294 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4052754 # ITB inst hits -system.cpu2.itb.inst_misses 4681 # ITB inst misses +system.cpu2.itb.inst_hits 4050371 # ITB inst hits +system.cpu2.itb.inst_misses 4655 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 542 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1722 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1717 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 963 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 991 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4057435 # ITB inst accesses -system.cpu2.itb.hits 4052754 # DTB hits -system.cpu2.itb.misses 4681 # DTB misses -system.cpu2.itb.accesses 4057435 # DTB accesses -system.cpu2.numCycles 88329548 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4055026 # ITB inst accesses +system.cpu2.itb.hits 4050371 # DTB hits +system.cpu2.itb.misses 4655 # DTB misses +system.cpu2.itb.accesses 4055026 # DTB accesses +system.cpu2.numCycles 88306923 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9368286 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32480016 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4780240 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2938039 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6853051 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1759446 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50956 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19165610 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 867 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33412 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 724302 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4051341 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290206 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37405927 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.043731 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431289 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9346989 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32490356 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4782343 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2941476 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6854845 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1758076 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51100 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 19188137 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 264 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 924 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 33833 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 718254 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 435 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4048944 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289644 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 2020 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37402774 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.043825 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.431125 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30558019 81.69% 81.69% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385772 1.03% 82.72% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 515915 1.38% 84.10% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 819609 2.19% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 625256 1.67% 87.97% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 342326 0.92% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1044683 2.79% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 230213 0.62% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2884134 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30553136 81.69% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385541 1.03% 82.72% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 516309 1.38% 84.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 819811 2.19% 86.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 629209 1.68% 87.97% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 341976 0.91% 88.89% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1043472 2.79% 91.68% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229749 0.61% 92.29% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2883571 7.71% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37405927 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054118 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367714 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9993670 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19739606 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6190224 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 324742 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1156786 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609493 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53173 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36942390 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178785 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1156786 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10542033 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6802518 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11433975 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5951508 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1518203 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34853467 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 325261 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 883658 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 140 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37388012 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 160878048 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148313673 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3357 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26544776 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10843235 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285604 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261905 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3322163 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6624625 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3901879 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530898 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 772979 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32179363 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 501455 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34749523 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55329 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7166724 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19100923 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 145150 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37405927 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.928984 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.590317 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37402774 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054156 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367925 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9974482 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19754417 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6192036 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 324676 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1156258 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608942 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 52938 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36945008 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178323 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1156258 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10522715 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6823267 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11427905 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5953488 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1518249 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34855169 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 93 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 324878 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 884563 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 125 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37394312 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 160859531 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148302897 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3365 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26531284 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10863027 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 285247 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 261616 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3319534 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6621271 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3899723 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 529692 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 779693 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32174765 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 504636 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34747602 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 55361 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7180763 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19089893 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 148627 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37402774 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.929011 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.590003 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24720555 66.09% 66.09% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3979487 10.64% 76.73% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2312001 6.18% 82.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1968335 5.26% 88.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2779247 7.43% 95.60% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 968566 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 497905 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144867 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34964 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24715445 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3980638 10.64% 76.72% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2310084 6.18% 82.90% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1974798 5.28% 88.18% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2777209 7.43% 95.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 968528 2.59% 98.19% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 496348 1.33% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144954 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34770 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37405927 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37402774 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19427 1.28% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1392100 91.45% 92.73% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 110700 7.27% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19778 1.30% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.30% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1391818 91.56% 92.86% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 108581 7.14% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8337 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19784762 56.94% 56.96% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28044 0.08% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.04% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11409832 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3518152 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8338 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19786480 56.94% 56.97% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28071 0.08% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.05% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11408808 32.83% 89.88% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3515506 10.12% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34749523 # Type of FU issued -system.cpu2.iq.rate 0.393408 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1522228 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043806 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108504523 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39852721 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28051848 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7496 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3959 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3344 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36259410 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 4004 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206643 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34747602 # Type of FU issued +system.cpu2.iq.rate 0.393487 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1520177 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.043749 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108495492 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39865371 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28048299 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7541 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3951 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3361 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36255412 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4029 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205816 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1533647 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2027 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9444 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562515 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1533232 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1949 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9487 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562230 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5286265 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344866 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5287398 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344554 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1156786 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5177746 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87629 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32763326 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61736 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6624625 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3901879 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 359192 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29253 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2415 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9444 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107780 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89787 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197567 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33835206 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11139307 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 914317 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1156258 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5195373 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 88422 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32761739 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 61550 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6621271 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3899723 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362828 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 29785 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2577 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9487 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107399 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89296 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196695 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33832847 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11137918 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914755 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82508 # number of nop insts executed -system.cpu2.iew.exec_refs 14623996 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3761047 # Number of branches executed -system.cpu2.iew.exec_stores 3484689 # Number of stores executed -system.cpu2.iew.exec_rate 0.383056 # Inst execution rate -system.cpu2.iew.wb_sent 33433924 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28055192 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16098734 # num instructions producing a value -system.cpu2.iew.wb_consumers 29085804 # num instructions consuming a value +system.cpu2.iew.exec_nop 82338 # number of nop insts executed +system.cpu2.iew.exec_refs 14620271 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3761250 # Number of branches executed +system.cpu2.iew.exec_stores 3482353 # Number of stores executed +system.cpu2.iew.exec_rate 0.383128 # Inst execution rate +system.cpu2.iew.wb_sent 33431998 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28051660 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16098716 # num instructions producing a value +system.cpu2.iew.wb_consumers 29087027 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317620 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553491 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317661 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.553467 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7134883 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356305 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171320 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36248935 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700393 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.738300 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7131660 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 356009 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 171002 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 36246314 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.700075 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.737192 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27340525 75.42% 75.42% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4430140 12.22% 87.65% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1255420 3.46% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 637620 1.76% 92.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 510981 1.41% 94.28% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 317875 0.88% 95.15% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 419132 1.16% 96.31% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 311355 0.86% 97.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1025887 2.83% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27334959 75.41% 75.41% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4433375 12.23% 87.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1255912 3.46% 91.11% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 639801 1.77% 92.88% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 511761 1.41% 94.29% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 317445 0.88% 95.16% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 418775 1.16% 96.32% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 310656 0.86% 97.18% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1023630 2.82% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36248935 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20549284 # Number of instructions committed -system.cpu2.commit.committedOps 25388512 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 36246314 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20540563 # Number of instructions committed +system.cpu2.commit.committedOps 25375153 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8430342 # Number of memory references committed -system.cpu2.commit.loads 5090978 # Number of loads committed -system.cpu2.commit.membars 94231 # Number of memory barriers committed -system.cpu2.commit.branches 3241086 # Number of branches committed +system.cpu2.commit.refs 8425532 # Number of memory references committed +system.cpu2.commit.loads 5088039 # Number of loads committed +system.cpu2.commit.membars 94081 # Number of memory barriers committed +system.cpu2.commit.branches 3238597 # Number of branches committed system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22644563 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295800 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1025887 # number cycles where commit BW limit reached +system.cpu2.commit.int_insts 22633154 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295425 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1023630 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67225559 # The number of ROB reads -system.cpu2.rob.rob_writes 66247729 # The number of ROB writes -system.cpu2.timesIdled 359329 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50923621 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3554004914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20493925 # Number of Instructions Simulated -system.cpu2.committedOps 25333153 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20493925 # Number of Instructions Simulated -system.cpu2.cpi 4.310036 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.310036 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232017 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232017 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157011420 # number of integer regfile reads -system.cpu2.int_regfile_writes 29864331 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46835 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes -system.cpu2.misc_regfile_reads 66864323 # number of misc regfile reads -system.cpu2.misc_regfile_writes 296992 # number of misc regfile writes +system.cpu2.rob.rob_reads 67208837 # The number of ROB reads +system.cpu2.rob.rob_writes 66213984 # The number of ROB writes +system.cpu2.timesIdled 359252 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 50904149 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3546216081 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20485207 # Number of Instructions Simulated +system.cpu2.committedOps 25319797 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20485207 # Number of Instructions Simulated +system.cpu2.cpi 4.310765 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.310765 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231977 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231977 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 156999830 # number of integer regfile reads +system.cpu2.int_regfile_writes 29869338 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46882 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45194 # number of floating regfile writes +system.cpu2.misc_regfile_reads 67020139 # number of misc regfile reads +system.cpu2.misc_regfile_writes 296788 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2151,10 +1984,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1347826044250 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1347826044250 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1539425711000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1539425711000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1539425711000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |