diff options
| author | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-11-01 11:56:34 -0400 |
| commit | ccfdc533b9d679f1596d43d647a093885d5e74ab (patch) | |
| tree | 4c785a5e7a7e2d7244fbdbb0a316405898f99e75 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | 460cc77d6db46eef34b14a458816084bf6097b32 (diff) | |
| download | gem5-ccfdc533b9d679f1596d43d647a093885d5e74ab.tar.xz | |
stats: Bump stats to match DRAM controller changes
This patch encompasses all the stats updates needed to reflect the
changes to the DRAM controller.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
| -rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt | 3156 |
1 files changed, 1645 insertions, 1511 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 2afd1181d..506582551 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,182 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403596 # Number of seconds simulated -sim_ticks 2403595690000 # Number of ticks simulated -final_tick 2403595690000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403658 # Number of seconds simulated +sim_ticks 2403657545000 # Number of ticks simulated +final_tick 2403657545000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 196358 # Simulator instruction rate (inst/s) -host_op_rate 252199 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 7823307249 # Simulator tick rate (ticks/s) -host_mem_usage 401444 # Number of bytes of host memory used -host_seconds 307.24 # Real time elapsed on the host -sim_insts 60328186 # Number of instructions simulated -sim_ops 77484426 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 183148 # Simulator instruction rate (inst/s) +host_op_rate 235229 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7297160965 # Simulator tick rate (ticks/s) +host_mem_usage 427808 # Number of bytes of host memory used +host_seconds 329.40 # Real time elapsed on the host +sim_insts 60328152 # Number of instructions simulated +sim_ops 77483430 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511520 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7050896 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 512416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7048656 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 64832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 677568 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 448 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.itb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 64128 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 675392 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 704 # Number of bytes read from this memory system.physmem.bytes_read::cpu2.inst 187392 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1347680 # Number of bytes read from this memory -system.physmem.bytes_read::total 124659728 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511520 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 64832 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu2.data 1353632 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661648 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 512416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 64128 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu2.inst 187392 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763744 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743680 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298324 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558192 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759496 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 763936 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3744384 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298192 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159304 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558320 # Number of bytes written to this memory +system.physmem.bytes_written::total 6760200 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14195 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110204 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14209 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110169 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 1013 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10587 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 7 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.itb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 1002 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10553 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 11 # Number of read requests responded to by this memory system.physmem.num_reads::cpu2.inst 2928 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21065 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512388 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58495 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324581 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389548 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812449 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47769711 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu2.data 21158 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512418 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58506 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324548 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39826 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389580 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812460 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47768482 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 212814 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2933478 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 213182 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2932471 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26973 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 281898 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.itb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77963 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560693 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51863851 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 212814 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26973 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77963 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317751 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557533 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540159 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 26679 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 280985 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 293 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 77961 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 563155 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51863315 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 213182 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 26679 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 77961 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317822 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1557786 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540090 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu1.data 66276 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648275 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2812243 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557533 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47769711 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648312 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812464 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1557786 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47768482 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 212814 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3473637 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 213182 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3472561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26973 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 348173 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.itb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77963 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1208969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54676094 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13479442 # Total number of read requests accepted by DRAM controller -system.physmem.writeReqs 446461 # Total number of write requests accepted by DRAM controller -system.physmem.readBursts 13479442 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts -system.physmem.writeBursts 446461 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts -system.physmem.bytesRead 862684288 # Total number of bytes read from memory -system.physmem.bytesWritten 28573504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 109828768 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 2811124 # bytesWritten derated as per pkt->getSize() -system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q -system.physmem.neitherReadNorWrite 2349 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 837727 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 837365 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 837535 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 838843 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 839834 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 839919 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 839832 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 840753 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 841921 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 844340 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 845026 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 846543 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 848256 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 848014 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 846904 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 846630 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 2743 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 2603 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 2565 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 3057 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 3449 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 3230 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 2572 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 2333 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 2233 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 2428 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 2377 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 2821 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 3826 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 3451 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 2698 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 2556 # Track writes on a per bank basis -system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2402560453500 # Total gap between requests -system.physmem.readPktSize::0 0 # Categorize read packet sizes -system.physmem.readPktSize::1 0 # Categorize read packet sizes -system.physmem.readPktSize::2 8 # Categorize read packet sizes -system.physmem.readPktSize::3 13443840 # Categorize read packet sizes -system.physmem.readPktSize::4 0 # Categorize read packet sizes -system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 35594 # Categorize read packet sizes -system.physmem.writePktSize::0 0 # Categorize write packet sizes -system.physmem.writePktSize::1 0 # Categorize write packet sizes -system.physmem.writePktSize::2 429373 # Categorize write packet sizes -system.physmem.writePktSize::3 0 # Categorize write packet sizes -system.physmem.writePktSize::4 0 # Categorize write packet sizes -system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 17088 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 871692 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 848345 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 868847 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3321058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2492431 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2492072 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2465727 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 13654 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 13341 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 25821 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 38140 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 25648 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 671 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 665 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 651 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 19 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::17 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::18 1 # What read queue length does an incoming req see +system.physmem.bw_total::cpu1.inst 26679 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 347261 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 293 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 77961 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1211467 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54675779 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13467317 # Number of read requests accepted +system.physmem.writeReqs 446508 # Number of write requests accepted +system.physmem.readBursts 13467317 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446508 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 861908288 # Total number of bytes read from DRAM +system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue +system.physmem.bytesWritten 2866432 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109734624 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2812152 # Total written bytes from the system interface side +system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.physmem.mergedWrBursts 401719 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2372 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 837719 # Per bank write bursts +system.physmem.perBankRdBursts::1 837389 # Per bank write bursts +system.physmem.perBankRdBursts::2 837556 # Per bank write bursts +system.physmem.perBankRdBursts::3 837999 # Per bank write bursts +system.physmem.perBankRdBursts::4 838842 # Per bank write bursts +system.physmem.perBankRdBursts::5 838880 # Per bank write bursts +system.physmem.perBankRdBursts::6 838796 # Per bank write bursts +system.physmem.perBankRdBursts::7 839742 # Per bank write bursts +system.physmem.perBankRdBursts::8 840911 # Per bank write bursts +system.physmem.perBankRdBursts::9 843323 # Per bank write bursts +system.physmem.perBankRdBursts::10 844015 # Per bank write bursts +system.physmem.perBankRdBursts::11 845500 # Per bank write bursts +system.physmem.perBankRdBursts::12 847242 # Per bank write bursts +system.physmem.perBankRdBursts::13 846993 # Per bank write bursts +system.physmem.perBankRdBursts::14 845867 # Per bank write bursts +system.physmem.perBankRdBursts::15 846543 # Per bank write bursts +system.physmem.perBankWrBursts::0 2729 # Per bank write bursts +system.physmem.perBankWrBursts::1 2587 # Per bank write bursts +system.physmem.perBankWrBursts::2 2574 # Per bank write bursts +system.physmem.perBankWrBursts::3 3045 # Per bank write bursts +system.physmem.perBankWrBursts::4 3468 # Per bank write bursts +system.physmem.perBankWrBursts::5 3206 # Per bank write bursts +system.physmem.perBankWrBursts::6 2544 # Per bank write bursts +system.physmem.perBankWrBursts::7 2321 # Per bank write bursts +system.physmem.perBankWrBursts::8 2236 # Per bank write bursts +system.physmem.perBankWrBursts::9 2427 # Per bank write bursts +system.physmem.perBankWrBursts::10 2367 # Per bank write bursts +system.physmem.perBankWrBursts::11 2798 # Per bank write bursts +system.physmem.perBankWrBursts::12 3813 # Per bank write bursts +system.physmem.perBankWrBursts::13 3444 # Per bank write bursts +system.physmem.perBankWrBursts::14 2680 # Per bank write bursts +system.physmem.perBankWrBursts::15 2549 # Per bank write bursts +system.physmem.numRdRetry 0 # Number of times read queue was full causing retry +system.physmem.numWrRetry 0 # Number of times write queue was full causing retry +system.physmem.totGap 2402622305000 # Total gap between requests +system.physmem.readPktSize::0 0 # Read request sizes (log2) +system.physmem.readPktSize::1 0 # Read request sizes (log2) +system.physmem.readPktSize::2 8 # Read request sizes (log2) +system.physmem.readPktSize::3 13431664 # Read request sizes (log2) +system.physmem.readPktSize::4 0 # Read request sizes (log2) +system.physmem.readPktSize::5 0 # Read request sizes (log2) +system.physmem.readPktSize::6 35645 # Read request sizes (log2) +system.physmem.writePktSize::0 0 # Write request sizes (log2) +system.physmem.writePktSize::1 0 # Write request sizes (log2) +system.physmem.writePktSize::2 429406 # Write request sizes (log2) +system.physmem.writePktSize::3 0 # Write request sizes (log2) +system.physmem.writePktSize::4 0 # Write request sizes (log2) +system.physmem.writePktSize::5 0 # Write request sizes (log2) +system.physmem.writePktSize::6 17102 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 965936 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 943404 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 937737 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3274872 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2367219 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2366833 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2384991 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 47923 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 55146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 17633 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 17621 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 17612 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 17600 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 17597 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 17588 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 17582 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see @@ -190,30 +176,30 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2007 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 1997 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 1991 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 1988 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 1985 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 1980 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 1971 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 1966 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 1962 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 1958 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 1954 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 1947 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 1942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 1937 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1934 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 1930 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 1926 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 1922 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 1917 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 1914 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 1909 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 1908 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2023 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2425 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2046 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2214 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2287 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2028 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2021 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2042 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 1996 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 1992 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 1980 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 1974 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 1966 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 1967 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1959 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 1970 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 1961 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 1942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 1944 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2053 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 28 # What write queue length does an incoming req see system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see @@ -222,473 +208,633 @@ system.physmem.wrQLenPdf::28 0 # Wh system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 22080 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 39201.023188 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 6463.207550 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 31878.388388 # Bytes accessed per row activation -system.physmem.bytesPerActivate::64-79 3036 13.75% 13.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-143 1347 6.10% 19.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::192-207 793 3.59% 23.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-271 589 2.67% 26.11% # Bytes accessed per row activation -system.physmem.bytesPerActivate::320-335 391 1.77% 27.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-399 355 1.61% 29.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::448-463 279 1.26% 30.75% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-527 235 1.06% 31.82% # Bytes accessed per row activation -system.physmem.bytesPerActivate::576-591 172 0.78% 32.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-655 146 0.66% 33.26% # Bytes accessed per row activation -system.physmem.bytesPerActivate::704-719 130 0.59% 33.85% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-783 164 0.74% 34.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::832-847 77 0.35% 34.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-911 80 0.36% 35.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::960-975 63 0.29% 35.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1039 74 0.34% 35.92% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1088-1103 30 0.14% 36.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1152-1167 39 0.18% 36.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1216-1231 22 0.10% 36.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1280-1295 39 0.18% 36.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1344-1359 28 0.13% 36.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1408-1423 83 0.38% 37.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1472-1487 95 0.43% 37.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1536-1551 108 0.49% 37.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1600-1615 17 0.08% 38.01% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1664-1679 45 0.20% 38.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1728-1743 23 0.10% 38.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1792-1807 32 0.14% 38.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1856-1871 10 0.05% 38.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1920-1935 20 0.09% 38.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1984-1999 6 0.03% 38.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2048-2063 23 0.10% 38.73% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2112-2127 8 0.04% 38.76% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2176-2191 15 0.07% 38.83% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2240-2255 1 0.00% 38.84% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2304-2319 6 0.03% 38.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2368-2383 4 0.02% 38.88% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2432-2447 10 0.05% 38.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2496-2511 3 0.01% 38.94% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2560-2575 2 0.01% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2624-2639 1 0.00% 38.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2688-2703 3 0.01% 38.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2752-2767 5 0.02% 38.99% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2816-2831 8 0.04% 39.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2880-2895 3 0.01% 39.04% # Bytes accessed per row activation -system.physmem.bytesPerActivate::2944-2959 3 0.01% 39.05% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3008-3023 1 0.00% 39.06% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3072-3087 6 0.03% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3136-3151 2 0.01% 39.09% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3200-3215 2 0.01% 39.10% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3264-3279 5 0.02% 39.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3328-3343 6 0.03% 39.15% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3392-3407 2 0.01% 39.16% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3456-3471 3 0.01% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3520-3535 1 0.00% 39.18% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3584-3599 2 0.01% 39.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3648-3663 2 0.01% 39.20% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3712-3727 2 0.01% 39.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3776-3791 3 0.01% 39.22% # Bytes accessed per row activation -system.physmem.bytesPerActivate::3840-3855 1 0.00% 39.23% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4032-4047 3 0.01% 39.24% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4096-4111 7 0.03% 39.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4352-4367 3 0.01% 39.28% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4416-4431 1 0.00% 39.29% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4672-4687 2 0.01% 39.30% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4800-4815 2 0.01% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4928-4943 1 0.00% 39.31% # Bytes accessed per row activation -system.physmem.bytesPerActivate::4992-5007 2 0.01% 39.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5120-5135 1 0.00% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5376-5391 2 0.01% 39.33% # Bytes accessed per row activation -system.physmem.bytesPerActivate::5440-5455 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6272-6287 1 0.00% 39.34% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6464-6479 1 0.00% 39.35% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6528-6543 3 0.01% 39.36% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6784-6799 15 0.07% 39.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6848-6863 2 0.01% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::6976-6991 1 0.00% 39.44% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7040-7055 3 0.01% 39.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7168-7183 3 0.01% 39.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7360-7375 2 0.01% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7424-7439 1 0.00% 39.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7680-7695 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7744-7759 1 0.00% 39.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::7936-7951 2 0.01% 39.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8064-8079 1 0.00% 39.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8192-8207 3 0.01% 39.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8448-8463 45 0.20% 39.72% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8512-8527 150 0.68% 40.40% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8576-8591 12 0.05% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::8960-8975 1 0.00% 40.46% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9216-9231 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::9472-9487 1 0.00% 40.47% # Bytes accessed per row activation -system.physmem.bytesPerActivate::12032-12047 2 0.01% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::14848-14863 1 0.00% 40.48% # Bytes accessed per row activation -system.physmem.bytesPerActivate::16320-16335 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17408-17423 1 0.00% 40.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::17664-17679 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::20224-20239 1 0.00% 40.50% # Bytes accessed per row activation -system.physmem.bytesPerActivate::22784-22799 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::24576-24591 1 0.00% 40.51% # Bytes accessed per row activation -system.physmem.bytesPerActivate::25856-25871 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::27648-27663 1 0.00% 40.52% # Bytes accessed per row activation -system.physmem.bytesPerActivate::29440-29455 1 0.00% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::30720-30735 2 0.01% 40.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::31232-31247 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33024-33039 1 0.00% 40.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33280-33295 3 0.01% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::33792-33807 1 0.00% 40.56% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34304-34319 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::34816-34831 1 0.00% 40.57% # Bytes accessed per row activation -system.physmem.bytesPerActivate::35840-35855 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::37888-37903 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::38912-38927 1 0.00% 40.58% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40192-40207 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::40960-40975 1 0.00% 40.59% # Bytes accessed per row activation -system.physmem.bytesPerActivate::41984-41999 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::42752-42767 1 0.00% 40.60% # Bytes accessed per row activation -system.physmem.bytesPerActivate::47872-47887 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::52224-52239 1 0.00% 40.61% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53248-53263 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::53504-53519 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::56064-56079 1 0.00% 40.62% # Bytes accessed per row activation -system.physmem.bytesPerActivate::59392-59407 1 0.00% 40.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::65536-65551 13109 59.37% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 22080 # Bytes accessed per row activation -system.physmem.totQLat 259652718750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 339530350000 # Sum of mem lat for all requests -system.physmem.totBusLat 67397210000 # Total cycles spent in databus access -system.physmem.totBankLat 12480421250 # Total cycles spent in bank access -system.physmem.avgQLat 19262.87 # Average queueing delay per request -system.physmem.avgBankLat 925.89 # Average bank access latency per request -system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25188.75 # Average memory access latency -system.physmem.avgRdBW 358.91 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 11.89 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 45.69 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 1.17 # Average consumed write bandwidth in MB/s -system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 2.90 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.14 # Average read queue length over time -system.physmem.avgWrQLen 0.39 # Average write queue length over time -system.physmem.readRowHits 13462207 # Number of row buffer hits during reads -system.physmem.writeRowHits 40077 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.87 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 8.98 # Row buffer hit rate for writes -system.physmem.avgGap 172524.57 # Average gap between requests -system.membus.throughput 55673401 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13817014 # Transaction distribution -system.membus.trans_dist::ReadResp 13817014 # Transaction distribution -system.membus.trans_dist::WriteReq 432240 # Transaction distribution -system.membus.trans_dist::WriteResp 432240 # Transaction distribution -system.membus.trans_dist::Writeback 17088 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2349 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2349 # Transaction distribution -system.membus.trans_dist::ReadExReq 28007 # Transaction distribution -system.membus.trans_dist::ReadExResp 28007 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 736658 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 234 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951736 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1688628 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26887680 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28576308 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 740538 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 468 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5089172 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5830178 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113380898 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133816346 # Total data (bytes) +system.physmem.bytesPerActivate::samples 48451 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 17848.429795 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 3200.071202 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 18346.519598 # Bytes accessed per row activation +system.physmem.bytesPerActivate::64-71 8608 17.77% 17.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-135 4824 9.96% 27.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::192-199 1006 2.08% 29.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-263 654 1.35% 31.15% # Bytes accessed per row activation +system.physmem.bytesPerActivate::320-327 399 0.82% 31.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-391 406 0.84% 32.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::448-455 283 0.58% 33.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-519 297 0.61% 34.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::576-583 176 0.36% 34.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-647 170 0.35% 34.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::704-711 172 0.35% 35.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-775 155 0.32% 35.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::832-839 77 0.16% 35.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-903 80 0.17% 35.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::960-967 48 0.10% 35.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1031 416 0.86% 36.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1088-1095 18 0.04% 36.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1152-1159 23 0.05% 36.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1216-1223 23 0.05% 36.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1280-1287 108 0.22% 37.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1344-1351 17 0.04% 37.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1408-1415 165 0.34% 37.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1472-1479 12 0.02% 37.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1536-1543 112 0.23% 37.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1600-1607 15 0.03% 37.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1664-1671 32 0.07% 37.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1728-1735 7 0.01% 37.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1792-1799 140 0.29% 38.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1856-1863 6 0.01% 38.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1920-1927 13 0.03% 38.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1984-1991 8 0.02% 38.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2048-2055 455 0.94% 39.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2112-2119 3 0.01% 39.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2176-2183 12 0.02% 39.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2240-2247 2 0.00% 39.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2304-2311 72 0.15% 39.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2368-2375 6 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2432-2439 4 0.01% 39.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2560-2567 5 0.01% 39.28% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2624-2631 6 0.01% 39.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2752-2759 5 0.01% 39.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2816-2823 10 0.02% 39.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2880-2887 5 0.01% 39.34% # Bytes accessed per row activation +system.physmem.bytesPerActivate::2944-2951 8 0.02% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3008-3015 2 0.00% 39.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3072-3079 505 1.04% 40.40% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3136-3143 5 0.01% 40.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3200-3207 5 0.01% 40.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3264-3271 5 0.01% 40.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3328-3335 65 0.13% 40.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3392-3399 6 0.01% 40.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3456-3463 5 0.01% 40.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3520-3527 9 0.02% 40.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3584-3591 15 0.03% 40.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3648-3655 3 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3712-3719 4 0.01% 40.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3776-3783 6 0.01% 40.67% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3840-3847 66 0.14% 40.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3904-3911 4 0.01% 40.81% # Bytes accessed per row activation +system.physmem.bytesPerActivate::3968-3975 6 0.01% 40.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4032-4039 3 0.01% 40.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4096-4103 327 0.67% 41.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4160-4167 5 0.01% 41.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4224-4231 8 0.02% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4288-4295 2 0.00% 41.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4352-4359 130 0.27% 41.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4416-4423 6 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4480-4487 4 0.01% 41.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4544-4551 3 0.01% 41.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4608-4615 68 0.14% 41.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4672-4679 3 0.01% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4736-4743 2 0.00% 41.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4800-4807 5 0.01% 41.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4864-4871 4 0.01% 42.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4928-4935 4 0.01% 42.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5056-5063 7 0.01% 42.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5120-5127 258 0.53% 42.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5184-5191 5 0.01% 42.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5248-5255 4 0.01% 42.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5312-5319 3 0.01% 42.59% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5376-5383 88 0.18% 42.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5440-5447 3 0.01% 42.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5504-5511 8 0.02% 42.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5568-5575 3 0.01% 42.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5632-5639 92 0.19% 42.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5696-5703 4 0.01% 43.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5760-5767 7 0.01% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5824-5831 2 0.00% 43.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5888-5895 102 0.21% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::5952-5959 2 0.00% 43.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6016-6023 3 0.01% 43.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6144-6151 481 0.99% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6208-6215 2 0.00% 44.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6272-6279 3 0.01% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6400-6407 1 0.00% 44.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6528-6535 3 0.01% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6656-6663 67 0.14% 44.41% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6784-6791 5 0.01% 44.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6848-6855 6 0.01% 44.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6912-6919 131 0.27% 44.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::6976-6983 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7040-7047 1 0.00% 44.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.72% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7168-7175 72 0.15% 44.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7232-7239 1 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7296-7303 2 0.00% 44.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7360-7367 13 0.03% 44.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7424-7431 133 0.27% 45.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7680-7687 66 0.14% 45.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::7936-7943 64 0.13% 45.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8192-8199 385 0.79% 46.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8448-8455 65 0.13% 46.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8704-8711 65 0.13% 46.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::8960-8967 128 0.26% 46.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9216-9223 73 0.15% 46.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9472-9479 128 0.26% 47.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9728-9735 64 0.13% 47.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::9984-9991 1 0.00% 47.32% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10240-10247 478 0.99% 48.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10496-10503 63 0.13% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10624-10631 1 0.00% 48.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::10752-10759 89 0.18% 48.62% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11008-11015 86 0.18% 48.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11264-11271 257 0.53% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11520-11527 1 0.00% 49.33% # Bytes accessed per row activation +system.physmem.bytesPerActivate::11776-11783 65 0.13% 49.46% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12032-12039 128 0.26% 49.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12288-12295 320 0.66% 50.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12544-12551 64 0.13% 50.52% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12800-12807 14 0.03% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::12992-12999 1 0.00% 50.55% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13056-13063 64 0.13% 50.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::13312-13319 499 1.03% 51.71% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14080-14087 64 0.13% 51.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14336-14343 442 0.91% 52.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14592-14599 128 0.26% 53.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::14848-14855 66 0.14% 53.16% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15104-15111 72 0.15% 53.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15360-15367 362 0.75% 54.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::15872-15879 2 0.00% 54.06% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16128-16135 6 0.01% 54.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16384-16391 781 1.61% 55.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16640-16647 7 0.01% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::16896-16903 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17024-17031 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17152-17159 1 0.00% 55.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17408-17415 362 0.75% 56.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17664-17671 72 0.15% 56.60% # Bytes accessed per row activation +system.physmem.bytesPerActivate::17920-17927 64 0.13% 56.73% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18176-18183 128 0.26% 56.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18240-18247 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18432-18439 442 0.91% 57.91% # Bytes accessed per row activation +system.physmem.bytesPerActivate::18688-18695 64 0.13% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19456-19463 499 1.03% 59.07% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19712-19719 64 0.13% 59.21% # Bytes accessed per row activation +system.physmem.bytesPerActivate::19968-19975 12 0.02% 59.23% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20224-20231 66 0.14% 59.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20480-20487 320 0.66% 60.03% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20736-20743 128 0.26% 60.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21504-21511 256 0.53% 60.95% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21760-21767 85 0.18% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::21888-21895 1 0.00% 61.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22016-22023 87 0.18% 61.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22272-22279 64 0.13% 61.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::22528-22535 478 0.99% 62.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23040-23047 67 0.14% 62.57% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23296-23303 128 0.26% 62.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23552-23559 71 0.15% 62.98% # Bytes accessed per row activation +system.physmem.bytesPerActivate::23808-23815 129 0.27% 63.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24064-24071 64 0.13% 63.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24320-24327 64 0.13% 63.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24576-24583 384 0.79% 64.30% # Bytes accessed per row activation +system.physmem.bytesPerActivate::24832-24839 64 0.13% 64.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25088-25095 64 0.13% 64.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25344-25351 129 0.27% 64.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25600-25607 70 0.14% 64.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::25856-25863 128 0.26% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26048-26055 1 0.00% 65.24% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26112-26119 66 0.14% 65.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26624-26631 480 0.99% 66.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::26880-26887 64 0.13% 66.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27136-27143 89 0.18% 66.68% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27392-27399 86 0.18% 66.86% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27648-27655 256 0.53% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::27904-27911 1 0.00% 67.39% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28160-28167 65 0.13% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28288-28295 1 0.00% 67.53% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28416-28423 127 0.26% 67.79% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28672-28679 320 0.66% 68.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::28928-28935 65 0.13% 68.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29184-29191 13 0.03% 68.61% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29440-29447 64 0.13% 68.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29696-29703 497 1.03% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::29824-29831 1 0.00% 69.77% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30464-30471 64 0.13% 69.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30720-30727 442 0.91% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30912-30919 1 0.00% 70.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::30976-30983 129 0.27% 71.08% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31232-31239 65 0.13% 71.22% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31488-31495 72 0.15% 71.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::31744-31751 362 0.75% 72.11% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32256-32263 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32320-32327 1 0.00% 72.12% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32512-32519 6 0.01% 72.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::32768-32775 778 1.61% 73.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33024-33031 5 0.01% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33216-33223 1 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33280-33287 2 0.00% 73.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::33792-33799 362 0.75% 74.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34048-34055 72 0.15% 74.65% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34304-34311 66 0.14% 74.78% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34560-34567 128 0.26% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34688-34695 1 0.00% 75.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::34816-34823 443 0.91% 75.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35072-35079 64 0.13% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35712-35719 1 0.00% 76.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::35840-35847 499 1.03% 77.13% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36096-36103 64 0.13% 77.26% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36352-36359 13 0.03% 77.29% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::36864-36871 321 0.66% 78.09% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37120-37127 127 0.26% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37248-37255 1 0.00% 78.35% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37632-37639 1 0.00% 78.48% # Bytes accessed per row activation +system.physmem.bytesPerActivate::37888-37895 257 0.53% 79.01% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38016-38023 1 0.00% 79.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38144-38151 86 0.18% 79.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38400-38407 89 0.18% 79.38% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38656-38663 65 0.13% 79.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::38912-38919 479 0.99% 80.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39424-39431 65 0.13% 80.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39488-39495 1 0.00% 80.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39680-39687 128 0.26% 80.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::39936-39943 71 0.15% 81.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40192-40199 128 0.26% 81.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40448-40455 64 0.13% 81.44% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40704-40711 64 0.13% 81.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::40960-40967 384 0.79% 82.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41216-41223 64 0.13% 82.50% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.63% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41728-41735 129 0.27% 82.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::41984-41991 71 0.15% 83.04% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42240-42247 128 0.26% 83.31% # Bytes accessed per row activation +system.physmem.bytesPerActivate::42496-42503 67 0.14% 83.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43008-43015 477 0.98% 84.43% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43264-43271 64 0.13% 84.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43520-43527 87 0.18% 84.74% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43648-43655 1 0.00% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::43776-43783 84 0.17% 84.92% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44032-44039 256 0.53% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44224-44231 1 0.00% 85.45% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44544-44551 64 0.13% 85.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::44800-44807 128 0.26% 85.85% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45056-45063 320 0.66% 86.51% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45312-45319 65 0.13% 86.64% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45568-45575 12 0.02% 86.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::45824-45831 64 0.13% 86.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46080-46087 498 1.03% 87.82% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46336-46343 1 0.00% 87.83% # Bytes accessed per row activation +system.physmem.bytesPerActivate::46848-46855 64 0.13% 87.96% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47104-47111 443 0.91% 88.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47360-47367 128 0.26% 89.14% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47616-47623 66 0.14% 89.27% # Bytes accessed per row activation +system.physmem.bytesPerActivate::47872-47879 72 0.15% 89.42% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48128-48135 362 0.75% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48384-48391 2 0.00% 90.17% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48512-48519 2 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48640-48647 1 0.00% 90.18% # Bytes accessed per row activation +system.physmem.bytesPerActivate::48896-48903 7 0.01% 90.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.20% # Bytes accessed per row activation +system.physmem.bytesPerActivate::49152-49159 4749 9.80% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 48451 # Bytes accessed per row activation +system.physmem.totQLat 326245474250 # Total ticks spent queuing +system.physmem.totMemAccLat 407559786750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67336585000 # Total ticks spent in databus transfers +system.physmem.totBankLat 13977727500 # Total ticks spent accessing banks +system.physmem.avgQLat 24224.98 # Average queueing delay per DRAM burst +system.physmem.avgBankLat 1037.90 # Average bank access latency per DRAM burst +system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.physmem.avgMemAccLat 30262.88 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 358.58 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s +system.physmem.avgRdBWSys 45.65 # Average system read bandwidth in MiByte/s +system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s +system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.physmem.busUtil 2.81 # Data bus utilization in percentage +system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads +system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes +system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing +system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing +system.physmem.readRowHits 13424164 # Number of row buffer hits during reads +system.physmem.writeRowHits 39490 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 88.17 # Row buffer hit rate for writes +system.physmem.avgGap 172678.78 # Average gap between requests +system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined +system.physmem.prechargeAllPercent 0.76 # Percentage of time for which DRAM has all the banks in precharge state +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.membus.throughput 55673060 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13803640 # Transaction distribution +system.membus.trans_dist::ReadResp 13803640 # Transaction distribution +system.membus.trans_dist::WriteReq 432247 # Transaction distribution +system.membus.trans_dist::WriteResp 432247 # Transaction distribution +system.membus.trans_dist::Writeback 17102 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2372 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2372 # Transaction distribution +system.membus.trans_dist::ReadExReq 28053 # Transaction distribution +system.membus.trans_dist::ReadExResp 28053 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 734214 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951964 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1686398 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26863328 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28549726 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 738102 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5093464 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5832006 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113285318 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133818970 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 415555000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417653000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 219000 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14607219000 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14595653500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1602404901 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1597948868 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 30345557250 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 30334798000 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.3 # Layer utilization (%) -system.l2c.tags.replacements 63232 # number of replacements -system.l2c.tags.tagsinuse 50385.545216 # Cycle average of tags in use -system.l2c.tags.total_refs 1748703 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128626 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.595253 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375561795000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36863.517049 # Average occupied blocks per requestor +system.l2c.tags.replacements 63262 # number of replacements +system.l2c.tags.tagsinuse 50391.923695 # Cycle average of tags in use +system.l2c.tags.total_refs 1749292 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128659 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.596344 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375568862000 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36846.357046 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5225.910742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3838.689123 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 514.601539 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 693.553663 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 6.833611 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.itb.walker 0.974677 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1665.560742 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1574.910611 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562493 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5224.016956 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3834.498559 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 503.830830 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 691.484420 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 9.832714 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1696.766805 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.142905 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562231 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079741 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058574 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079712 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058510 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007852 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010583 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000104 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025414 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024031 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.768822 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 8792 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3229 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468268 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177348 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2569 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1162 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 128925 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64565 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18612 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4274 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281840 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131110 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1290694 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597529 # number of Writeback hits -system.l2c.Writeback_hits::total 597529 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007688 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010551 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000150 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025891 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.data 0.024172 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::total 0.768920 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 8708 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 3160 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 467622 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 176862 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 2604 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.itb.walker 1190 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 130139 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 64269 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.dtb.walker 18599 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.itb.walker 4205 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 281217 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 132179 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1290754 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 597747 # number of Writeback hits +system.l2c.Writeback_hits::total 597747 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits -system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits -system.l2c.SCUpgradeReq_hits::total 3 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 61796 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 18660 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2.data 33186 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113642 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.dtb.walker 8792 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.itb.walker 3229 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.inst 468268 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 239144 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.dtb.walker 2569 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.itb.walker 1162 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 128925 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 83225 # 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average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -853,52 +987,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58805533 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1021031 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1021030 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432240 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432240 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 264941 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1503 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1506 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80714 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80714 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830128 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423683 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15492 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 51832 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3321135 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26541184 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37337186 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21748 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84756 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 63984874 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141242678 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 102048 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176255494 # Layer occupancy (ticks) +system.toL2Bus.throughput 58815755 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1021426 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1021425 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432247 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432247 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265552 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1513 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1515 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80586 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80586 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831264 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2423236 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15497 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52067 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3322064 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26578304 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37416070 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21580 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 84860 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64100814 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141271334 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 101600 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2179143758 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870489205 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1872769954 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1849664390 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1848854181 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10070717 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10116966 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 30771737 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 30973250 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48764104 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13809372 # Transaction distribution -system.iobus.trans_dist::ReadResp 13809372 # Transaction distribution -system.iobus.trans_dist::WriteReq 2797 # Transaction distribution -system.iobus.trans_dist::WriteResp 2797 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11494 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3026 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 22 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48762849 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13795996 # Transaction distribution +system.iobus.trans_dist::ReadResp 13795996 # Transaction distribution +system.iobus.trans_dist::WriteReq 2775 # Transaction distribution +system.iobus.trans_dist::WriteResp 2775 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11418 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3030 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 256 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 721570 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 719202 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -914,18 +1048,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 736658 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26887680 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27624338 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15458 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6052 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 44 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 734214 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26863328 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27597542 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15382 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6060 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 512 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 717892 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 715532 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -941,18 +1075,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 740538 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107550720 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108291258 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 738102 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107453312 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108191414 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209190 # Total data (bytes) -system.iobus.reqLayer0.occupancy 8031000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 7974000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1513000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1515000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 22000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 128000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -960,7 +1094,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 361287000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 360101000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -992,444 +1126,444 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13443840000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13431664000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 733861000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 731439000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 36856295750 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 36823110000 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.5 # Layer utilization (%) system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 8004008 # DTB read hits -system.cpu0.dtb.read_misses 6222 # DTB read misses -system.cpu0.dtb.write_hits 6595133 # DTB write hits -system.cpu0.dtb.write_misses 2001 # DTB write misses +system.cpu0.dtb.read_hits 7991455 # DTB read hits +system.cpu0.dtb.read_misses 6184 # DTB read misses +system.cpu0.dtb.write_hits 6591541 # DTB write hits +system.cpu0.dtb.write_misses 1989 # DTB write misses system.cpu0.dtb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5693 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.dtb.prefetch_faults 118 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 212 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8010230 # DTB read accesses -system.cpu0.dtb.write_accesses 6597134 # DTB write accesses +system.cpu0.dtb.perms_faults 208 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7997639 # DTB read accesses +system.cpu0.dtb.write_accesses 6593530 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14599141 # DTB hits -system.cpu0.dtb.misses 8223 # DTB misses -system.cpu0.dtb.accesses 14607364 # DTB accesses -system.cpu0.itb.inst_hits 32379967 # ITB inst hits -system.cpu0.itb.inst_misses 3492 # ITB inst misses +system.cpu0.dtb.hits 14582996 # DTB hits +system.cpu0.dtb.misses 8173 # DTB misses +system.cpu0.dtb.accesses 14591169 # DTB accesses +system.cpu0.itb.inst_hits 32325256 # ITB inst hits +system.cpu0.itb.inst_misses 3454 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 279 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 685 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 674 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2598 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2571 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32383459 # ITB inst accesses -system.cpu0.itb.hits 32379967 # DTB hits -system.cpu0.itb.misses 3492 # DTB misses -system.cpu0.itb.accesses 32383459 # DTB accesses -system.cpu0.numCycles 113662532 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32328710 # ITB inst accesses +system.cpu0.itb.hits 32325256 # DTB hits +system.cpu0.itb.misses 3454 # DTB misses +system.cpu0.itb.accesses 32328710 # DTB accesses +system.cpu0.numCycles 113673861 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31896171 # Number of instructions committed -system.cpu0.committedOps 42061376 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37196625 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5021 # Number of float alu accesses -system.cpu0.num_func_calls 1200231 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4252287 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37196625 # number of integer instructions -system.cpu0.num_fp_insts 5021 # number of float instructions -system.cpu0.num_int_register_reads 189594254 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39319391 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3591 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1432 # number of times the floating registers were written -system.cpu0.num_mem_refs 15267333 # number of memory refs -system.cpu0.num_load_insts 8373046 # Number of load instructions -system.cpu0.num_store_insts 6894287 # Number of store instructions -system.cpu0.num_idle_cycles 110849279.389256 # Number of idle cycles -system.cpu0.num_busy_cycles 2813252.610744 # Number of busy cycles -system.cpu0.not_idle_fraction 0.024751 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.975249 # Percentage of idle cycles +system.cpu0.committedInsts 31847112 # Number of instructions committed +system.cpu0.committedOps 42008964 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37152656 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1198427 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4245737 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37152656 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 189368889 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39264582 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15250074 # number of memory refs +system.cpu0.num_load_insts 8359762 # Number of load instructions +system.cpu0.num_store_insts 6890312 # Number of store instructions +system.cpu0.num_idle_cycles 110868175.114613 # Number of idle cycles +system.cpu0.num_busy_cycles 2805685.885387 # Number of busy cycles +system.cpu0.not_idle_fraction 0.024682 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.975318 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891479 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.603901 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43691974 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 891991 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.982528 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8175687500 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 493.614782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.336202 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 10.652916 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.964091 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014329 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.020806 # 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average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.368470 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11897.029005 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11769.832849 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629636 # number of replacements +system.cpu0.dcache.tags.replacements 629916 # number of replacements system.cpu0.dcache.tags.tagsinuse 511.997119 # Cycle average of tags in use -system.cpu0.dcache.tags.total_refs 23222123 # Total number of references to valid blocks. -system.cpu0.dcache.tags.sampled_refs 630148 # Sample count of references to valid blocks. -system.cpu0.dcache.tags.avg_refs 36.851855 # Average number of references to valid blocks. +system.cpu0.dcache.tags.total_refs 23219265 # Total number of references to valid blocks. +system.cpu0.dcache.tags.sampled_refs 630428 # Sample count of references to valid blocks. +system.cpu0.dcache.tags.avg_refs 36.830955 # Average number of references to valid blocks. system.cpu0.dcache.tags.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.117005 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.034615 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.845498 # Average occupied blocks per requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970932 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015693 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013370 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.028749 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.124022 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.844348 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970759 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015867 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013368 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6875315 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1820667 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4627275 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 13323257 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5963983 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu1.data 1316466 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::cpu2.data 2129753 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 9410202 # 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number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238419 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138143 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34804 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74442 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247389 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12822555 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3135149 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6772754 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22730458 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12822555 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3135149 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6772754 # number of overall hits +system.cpu0.dcache.overall_hits::total 22730458 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 176872 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu1.data 63653 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::cpu2.data 271744 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 512269 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167825 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu1.data 28657 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::cpu2.data 610336 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 806818 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6461 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1738 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3756 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 11955 # 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number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 4826087335 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1012897489 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23468295787 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 24481193276 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 22815750 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 50223749 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 73039499 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu1.data 1918694239 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 27388586372 # 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number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu1.data 3229966 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::cpu2.data 7635722 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 24050069 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 13184381 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu1.data 3229966 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu2.data 7635722 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 24050069 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025147 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033937 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.054974 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036902 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027354 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021462 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222511 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078905 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046706 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049643 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048881 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047786 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000040 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000012 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026174 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028741 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115077 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054745 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026174 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028741 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115077 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054745 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14203.302115 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14398.161185 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9371.494127 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 31590.920863 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37103.466442 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29186.007060 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13129.185912 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13398.486996 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6123.536461 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13167252 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3227459 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7654834 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24049545 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13167252 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3227459 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7654834 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24049545 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033793 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055338 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.037032 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027385 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021325 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222405 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.078973 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046770 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.049937 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048510 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047749 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026178 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028601 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::cpu2.data 0.115232 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.054849 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026178 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028601 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::cpu2.data 0.115232 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.054849 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14230.228740 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14426.410832 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9421.002120 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35345.552186 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38451.436237 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 30342.894279 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.589183 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13371.605165 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6109.535675 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21503.313850 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19611.401646 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30148.029688 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21503.313850 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 7835 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 2458 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 871 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8.995408 # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets 49.160000 # average number of cycles each access was blocked +system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22217.852659 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20785.334622 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 31050.002689 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22217.852659 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 8471 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 2566 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 892 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 49 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.496637 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets 52.367347 # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 597529 # number of writebacks -system.cpu0.dcache.writebacks::total 597529 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 138849 # number of ReadReq MSHR hits -system.cpu0.dcache.ReadReq_mshr_hits::total 138849 # number of ReadReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.WriteReq_mshr_hits::total 556206 # number of WriteReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.LoadLockedReq_mshr_hits::total 431 # number of LoadLockedReq MSHR hits -system.cpu0.dcache.demand_mshr_hits::cpu2.data 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.demand_mshr_hits::total 695055 # number of demand (read+write) MSHR hits -system.cpu0.dcache.overall_mshr_hits::cpu2.data 695055 # number of overall MSHR hits -system.cpu0.dcache.overall_mshr_hits::total 695055 # number of overall MSHR hits -system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63959 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 130326 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 194285 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28874 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53313 # 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number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1629798751 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3452469351 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5082268102 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1629798751 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3452469351 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5082268102 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27446152500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28893354250 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56339506750 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1446442000 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341405748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14787847748 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28892594500 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42234759998 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 71127354498 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033937 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026616 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014044 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019462 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008045 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049643 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043290 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020256 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011496 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028741 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024050 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011496 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12194.749762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12898.277013 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12666.674473 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 29432.525836 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 33228.077598 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31894.621436 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11128.319861 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11672.760264 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11486.733281 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597747 # number of writebacks +system.cpu0.dcache.writebacks::total 597747 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 140335 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 556925 # number of WriteReq MSHR hits +system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 415 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1731249761 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3596884562 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5328134323 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1731249761 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3596884562 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5328134323 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27375287500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28782575500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56157863000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1442314990 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13341314242 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14783629232 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28817602490 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42123889742 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70941492232 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033793 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026760 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014101 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021325 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019463 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008033 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049937 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043150 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020286 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011523 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028601 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024144 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011523 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12227.125980 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12926.558181 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12698.318145 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33253.882507 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35539.841568 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34741.616574 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.301496 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11583.283747 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11427.249655 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 17556.243480 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 18800.305768 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18382.577990 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18754.736876 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19461.554821 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19226.118872 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1442,388 +1576,388 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2098287 # DTB read hits -system.cpu1.dtb.read_misses 2070 # DTB read misses -system.cpu1.dtb.write_hits 1420937 # DTB write hits -system.cpu1.dtb.write_misses 371 # DTB write misses +system.cpu1.dtb.read_hits 2096740 # DTB read hits +system.cpu1.dtb.read_misses 2075 # DTB read misses +system.cpu1.dtb.write_hits 1419315 # DTB write hits +system.cpu1.dtb.write_misses 373 # DTB write misses system.cpu1.dtb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1726 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1735 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 38 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 39 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2100357 # DTB read accesses -system.cpu1.dtb.write_accesses 1421308 # DTB write accesses +system.cpu1.dtb.read_accesses 2098815 # DTB read accesses +system.cpu1.dtb.write_accesses 1419688 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3519224 # DTB hits -system.cpu1.dtb.misses 2441 # DTB misses -system.cpu1.dtb.accesses 3521665 # DTB accesses -system.cpu1.itb.inst_hits 8185092 # ITB inst hits -system.cpu1.itb.inst_misses 1172 # ITB inst misses +system.cpu1.dtb.hits 3516055 # DTB hits +system.cpu1.dtb.misses 2448 # DTB misses +system.cpu1.dtb.accesses 3518503 # DTB accesses +system.cpu1.itb.inst_hits 8182654 # ITB inst hits +system.cpu1.itb.inst_misses 1200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 277 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 234 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 867 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 888 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8186264 # ITB inst accesses -system.cpu1.itb.hits 8185092 # DTB hits -system.cpu1.itb.misses 1172 # DTB misses -system.cpu1.itb.accesses 8186264 # DTB accesses -system.cpu1.numCycles 580203625 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8183854 # ITB inst accesses +system.cpu1.itb.hits 8182654 # DTB hits +system.cpu1.itb.misses 1200 # DTB misses +system.cpu1.itb.accesses 8183854 # DTB accesses +system.cpu1.numCycles 581318737 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7980801 # Number of instructions committed -system.cpu1.committedOps 10142634 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9072894 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2143 # Number of float alu accesses -system.cpu1.num_func_calls 304668 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1116676 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9072894 # number of integer instructions -system.cpu1.num_fp_insts 2143 # number of float instructions -system.cpu1.num_int_register_reads 52281658 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9864872 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1630 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 514 # number of times the floating registers were written -system.cpu1.num_mem_refs 3686646 # number of memory refs -system.cpu1.num_load_insts 2191239 # Number of load instructions -system.cpu1.num_store_insts 1495407 # Number of store instructions -system.cpu1.num_idle_cycles 544226668.771142 # Number of idle cycles -system.cpu1.num_busy_cycles 35976956.228858 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062007 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937993 # Percentage of idle cycles +system.cpu1.committedInsts 7974693 # Number of instructions committed +system.cpu1.committedOps 10126531 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9058549 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 1938 # Number of float alu accesses +system.cpu1.num_func_calls 304877 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114107 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9058549 # number of integer instructions +system.cpu1.num_fp_insts 1938 # number of float instructions +system.cpu1.num_int_register_reads 52214198 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9844324 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1424 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3684398 # number of memory refs +system.cpu1.num_load_insts 2190368 # Number of load instructions +system.cpu1.num_store_insts 1494030 # Number of store instructions +system.cpu1.num_idle_cycles 546218260.044225 # Number of idle cycles +system.cpu1.num_busy_cycles 35100476.955774 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060381 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939619 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4715473 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3836739 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223495 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3141743 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2527502 # Number of BTB hits +system.cpu2.branchPred.lookups 4723221 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3843292 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 222521 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3120017 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2528037 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 80.449037 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 411571 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21589 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 81.026385 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 412365 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21211 # Number of incorrect RAS predictions. system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10976033 # DTB read hits -system.cpu2.dtb.read_misses 22752 # DTB read misses -system.cpu2.dtb.write_hits 3346841 # DTB write hits -system.cpu2.dtb.write_misses 6453 # DTB write misses +system.cpu2.dtb.read_hits 10969613 # DTB read hits +system.cpu2.dtb.read_misses 23045 # DTB read misses +system.cpu2.dtb.write_hits 3352330 # DTB write hits +system.cpu2.dtb.write_misses 6440 # DTB write misses system.cpu2.dtb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2303 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 671 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 173 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2328 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 714 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 159 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 460 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10998785 # DTB read accesses -system.cpu2.dtb.write_accesses 3353294 # DTB write accesses +system.cpu2.dtb.perms_faults 478 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10992658 # DTB read accesses +system.cpu2.dtb.write_accesses 3358770 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14322874 # DTB hits -system.cpu2.dtb.misses 29205 # DTB misses -system.cpu2.dtb.accesses 14352079 # DTB accesses -system.cpu2.itb.inst_hits 4041881 # ITB inst hits -system.cpu2.itb.inst_misses 4586 # ITB inst misses +system.cpu2.dtb.hits 14321943 # DTB hits +system.cpu2.dtb.misses 29485 # DTB misses +system.cpu2.dtb.accesses 14351428 # DTB accesses +system.cpu2.itb.inst_hits 4048520 # ITB inst hits +system.cpu2.itb.inst_misses 4581 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 276 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 521 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 531 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1634 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1671 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 1002 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1028 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4046467 # ITB inst accesses -system.cpu2.itb.hits 4041881 # DTB hits -system.cpu2.itb.misses 4586 # DTB misses -system.cpu2.itb.accesses 4046467 # DTB accesses -system.cpu2.numCycles 88343562 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4053101 # ITB inst accesses +system.cpu2.itb.hits 4048520 # DTB hits +system.cpu2.itb.misses 4581 # DTB misses +system.cpu2.itb.accesses 4053101 # DTB accesses +system.cpu2.numCycles 88363580 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9345666 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32463757 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4715473 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2939073 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6849430 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1758819 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50954 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 18707448 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 397 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 820 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 32452 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 720275 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 489 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4040467 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 290046 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2014 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.056921 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.443441 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9342746 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32497136 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4723221 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2940402 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6855397 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1756636 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 50446 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18848050 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 334 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 925 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34178 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 721824 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 449 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4047074 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 289511 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1970 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.053700 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.440521 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30071749 81.46% 81.46% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 384570 1.04% 82.50% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 513519 1.39% 83.89% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 818109 2.22% 86.11% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 634612 1.72% 87.83% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341178 0.92% 88.75% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1041484 2.82% 91.57% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 228835 0.62% 92.19% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2882050 7.81% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 30210914 81.52% 81.52% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 385385 1.04% 82.56% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 515477 1.39% 83.95% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 820134 2.21% 86.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 628486 1.70% 87.86% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 342820 0.93% 88.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1044433 2.82% 91.60% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 229207 0.62% 92.22% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2884462 7.78% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 36916106 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.053377 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.367472 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9928442 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19318553 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6233841 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 278394 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1155918 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 607967 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 53425 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36920328 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 180410 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1155918 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10478416 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6754031 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11105712 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5942637 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1478447 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34829842 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 2448 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 324847 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 890462 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 131 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37304234 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 159387361 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148242103 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3218 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26430435 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10873798 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 231762 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 208068 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3242623 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6608021 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3899448 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 530191 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 761841 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32138723 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 510591 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34782251 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 56051 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7186073 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19057300 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 153940 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 36916106 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.942197 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.600639 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 37061318 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.053452 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.367766 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9926500 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19460558 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6238388 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 279816 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1155131 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 608208 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53066 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 36958585 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 178391 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1155131 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10476553 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 6920166 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11076723 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 5947862 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 1483966 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 34870863 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 2458 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 328650 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 889849 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.FullRegisterEvents 96 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37358262 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 159586833 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 148423376 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3369 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26507725 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 10850536 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 232822 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 209087 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3256835 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6623705 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3904787 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 530493 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 775113 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32195808 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 505146 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34809127 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 54913 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7172484 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19086467 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 147942 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 37061318 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.939231 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.598560 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24329752 65.91% 65.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3820331 10.35% 76.25% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2317804 6.28% 82.53% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 2003808 5.43% 87.96% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2797781 7.58% 95.54% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 970796 2.63% 98.17% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 496090 1.34% 99.51% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144708 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 35036 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24455957 65.99% 65.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3833682 10.34% 76.33% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2322342 6.27% 82.60% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 2005181 5.41% 88.01% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2795966 7.54% 95.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 971107 2.62% 98.17% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 498292 1.34% 99.52% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 144261 0.39% 99.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 34530 0.09% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 36916106 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 37061318 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19314 1.26% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.26% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1407095 91.52% 92.77% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 111138 7.23% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19660 1.28% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1402550 91.51% 92.79% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 110445 7.21% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 61377 0.18% 0.18% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19718575 56.69% 56.87% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 27760 0.08% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 371 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.95% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11459171 32.95% 89.89% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3514969 10.11% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 61175 0.18% 0.18% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19747110 56.73% 56.91% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 27980 0.08% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 1 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 388 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 6 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 56.99% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11452276 32.90% 89.89% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3520179 10.11% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34782251 # Type of FU issued -system.cpu2.iq.rate 0.393716 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1537548 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.044205 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108096303 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39840742 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28020326 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 6981 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 3693 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3127 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36254698 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3724 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 204617 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34809127 # Type of FU issued +system.cpu2.iq.rate 0.393931 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1532656 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044030 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108288948 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 39878610 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28070823 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7546 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3965 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3367 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36276582 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 4026 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 205280 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1527306 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 1908 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9375 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 562929 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1528845 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1875 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9489 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 562920 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5348773 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344308 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5328051 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 344229 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1155918 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5077664 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 88593 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32732277 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 60627 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6608021 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3899448 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 368370 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29616 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2740 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9375 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107393 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89251 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 196644 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33865771 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11188559 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916480 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1155131 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 5244365 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 89322 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 32783919 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 60352 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6623705 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3904787 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 362611 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 30261 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 2481 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9489 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 106879 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89021 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 195900 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33894861 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11182187 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 914266 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82963 # number of nop insts executed -system.cpu2.iew.exec_refs 14669578 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3700003 # Number of branches executed -system.cpu2.iew.exec_stores 3481019 # Number of stores executed -system.cpu2.iew.exec_rate 0.383342 # Inst execution rate -system.cpu2.iew.wb_sent 33465265 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28023453 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16087448 # num instructions producing a value -system.cpu2.iew.wb_consumers 29114707 # num instructions consuming a value +system.cpu2.iew.exec_nop 82965 # number of nop insts executed +system.cpu2.iew.exec_refs 14668868 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3706634 # Number of branches executed +system.cpu2.iew.exec_stores 3486681 # Number of stores executed +system.cpu2.iew.exec_rate 0.383584 # Inst execution rate +system.cpu2.iew.wb_sent 33494578 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28074190 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16115456 # num instructions producing a value +system.cpu2.iew.wb_consumers 29164308 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317210 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.552554 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.317712 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.552575 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7129352 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356651 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 170839 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 35759991 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.708498 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.752281 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7126752 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357204 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170224 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35906001 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.707499 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.751012 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27025739 75.58% 75.58% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4219923 11.80% 87.38% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1248297 3.49% 90.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 635334 1.78% 92.64% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 557295 1.56% 94.20% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 319233 0.89% 95.09% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 417712 1.17% 96.26% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309905 0.87% 97.13% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1026553 2.87% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 27147368 75.61% 75.61% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4230684 11.78% 87.39% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1251387 3.49% 90.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 639812 1.78% 92.66% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 559957 1.56% 94.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 318640 0.89% 95.10% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 417979 1.16% 96.27% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 311730 0.87% 97.14% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1028444 2.86% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 35759991 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20506693 # Number of instructions committed -system.cpu2.commit.committedOps 25335895 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35906001 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20561870 # Number of instructions committed +system.cpu2.commit.committedOps 25403458 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8417234 # Number of memory references committed -system.cpu2.commit.loads 5080715 # Number of loads committed -system.cpu2.commit.membars 94304 # Number of memory barriers committed -system.cpu2.commit.branches 3173719 # Number of branches committed -system.cpu2.commit.fp_insts 3091 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22548127 # Number of committed integer instructions. -system.cpu2.commit.function_calls 294799 # Number of function calls committed. -system.cpu2.commit.bw_lim_events 1026553 # number cycles where commit BW limit reached +system.cpu2.commit.refs 8436727 # Number of memory references committed +system.cpu2.commit.loads 5094860 # Number of loads committed +system.cpu2.commit.membars 94449 # Number of memory barriers committed +system.cpu2.commit.branches 3185060 # Number of branches committed +system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22606405 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295605 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 1028444 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 66675347 # The number of ROB reads -system.cpu2.rob.rob_writes 66130617 # The number of ROB writes -system.cpu2.timesIdled 360964 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 51427456 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3556668435 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20451214 # Number of Instructions Simulated -system.cpu2.committedOps 25280416 # Number of Ops (including micro ops) Simulated -system.cpu2.committedInsts_total 20451214 # Number of Instructions Simulated -system.cpu2.cpi 4.319722 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.319722 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.231496 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.231496 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 156902302 # number of integer regfile reads -system.cpu2.int_regfile_writes 29839836 # number of integer regfile writes -system.cpu2.fp_regfile_reads 22382 # number of floating regfile reads -system.cpu2.fp_regfile_writes 20836 # number of floating regfile writes -system.cpu2.misc_regfile_reads 9252861 # number of misc regfile reads -system.cpu2.misc_regfile_writes 241910 # number of misc regfile writes +system.cpu2.rob.rob_reads 66885510 # The number of ROB reads +system.cpu2.rob.rob_writes 66259648 # The number of ROB writes +system.cpu2.timesIdled 359925 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51302262 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3553994827 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20506347 # Number of Instructions Simulated +system.cpu2.committedOps 25347935 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 20506347 # Number of Instructions Simulated +system.cpu2.cpi 4.309084 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.309084 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.232068 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.232068 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157055367 # number of integer regfile reads +system.cpu2.int_regfile_writes 29889640 # number of integer regfile writes +system.cpu2.fp_regfile_reads 22622 # number of floating regfile reads +system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes +system.cpu2.misc_regfile_reads 9269321 # number of misc regfile reads +system.cpu2.misc_regfile_writes 242794 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -1838,10 +1972,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1279629373750 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1279629373750 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1279629373750 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1346583006000 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1346583006000 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1346583006000 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency |