diff options
| author | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
|---|---|---|
| committer | Steve Reinhardt <steve.reinhardt@amd.com> | 2014-06-22 14:33:09 -0700 |
| commit | 5b08e211ab35fd6d936dafda45014c78b5e68300 (patch) | |
| tree | 771950b6f1e0c775d83a5f03f2387f2e3850cc58 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full | |
| parent | b085db84afcbb4824d34b8755f4c09c1fcfefcee (diff) | |
| download | gem5-5b08e211ab35fd6d936dafda45014c78b5e68300.tar.xz | |
stats: update for O3 changes
Mostly small differences in total ticks, but O3 stall causes
shifted significantly.
30.eon does speed up by ~6% on Alpha and ARM, and 50.vortex
by 4.5% on ARM. At the other extreme, X86 70.twolf is 0.8%
slower.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full')
4 files changed, 1515 insertions, 1502 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini index b551f2cf3..e53092e6a 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini @@ -12,8 +12,8 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain atags_addr=256 -boot_loader=/dist/binaries/boot.arm -boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 +boot_loader=/home/stever/m5/m5_system_2.0b3/binaries/boot.arm +boot_osflags=earlyprintk=pl011,0x1c090000 console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 boot_release_addr=65528 cache_line_size=64 clk_domain=system.clk_domain @@ -30,7 +30,7 @@ have_security=false have_virtualization=false highest_el_is_64=false init_param=0 -kernel=/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/home/stever/m5/m5_system_2.0b3/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 load_offset=0 machine_type=RealView_PBX @@ -42,7 +42,7 @@ num_work_ids=16 panic_on_oops=true panic_on_panic=true phys_addr_range_64=40 -readfile=tests/halt.sh +readfile=/home/stever/hg/m5sim.org/gem5/tests/halt.sh reset_addr_64=0 symbolfile= work_begin_ckpt_count=0 @@ -85,7 +85,7 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage eventq_index=0 -image_file=/dist/disks/linux-arm-ael.img +image_file=/home/stever/m5/m5_system_2.0b3/disks/linux-arm-ael.img read_only=true [system.clk_domain] @@ -97,6 +97,7 @@ voltage_domain=system.voltage_domain [system.cpu0] type=AtomicSimpleCPU children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -126,6 +127,7 @@ simpoint_profile_file=simpoint.bb.gz simpoint_start_insts= simulate_data_stalls=false simulate_inst_stalls=false +socket_id=0 switched_out=false system=system tracer=system.cpu0.tracer @@ -326,6 +328,7 @@ eventq_index=0 [system.cpu1] type=TimingSimpleCPU children=dstage2_mmu dtb isa istage2_mmu itb tracer +branchPred=Null checker=Null clk_domain=system.cpu_clk_domain cpu_id=0 @@ -349,6 +352,7 @@ numThreads=1 profile=0 progress_interval=0 simpoint_start_insts= +socket_id=0 switched_out=true system=system tracer=system.cpu1.tracer @@ -543,6 +547,7 @@ smtLSQThreshold=100 smtNumFetchingThreads=1 smtROBPolicy=Partitioned smtROBThreshold=100 +socket_id=0 squashWidth=8 store_set_clear_period=250000 switched_out=true @@ -1111,9 +1116,9 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleDRAM +type=DRAMCtrl activation_limit=4 -addr_mapping=RaBaChCo +addr_mapping=RoRaBaChCo banks_per_rank=8 burst_length=8 channels=1 @@ -1124,27 +1129,33 @@ device_rowbuffer_size=1024 devices_per_rank=8 eventq_index=0 in_addr_map=true +max_accesses_per_row=16 mem_sched_policy=frfcfs +min_writes_per_switch=16 null=false -page_policy=open +page_policy=open_adaptive range=0:134217727 ranks_per_channel=2 read_buffer_size=32 static_backend_latency=10000 static_frontend_latency=10000 tBURST=5000 +tCK=1250 tCL=13750 tRAS=35000 tRCD=13750 tREFI=7800000 -tRFC=300000 +tRFC=260000 tRP=13750 -tRRD=6250 +tRRD=6000 +tRTP=7500 +tRTW=2500 +tWR=15000 tWTR=7500 -tXAW=40000 -write_buffer_size=32 -write_high_thresh_perc=70 -write_low_thresh_perc=0 +tXAW=30000 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 port=system.membus.master[6] [system.realview] diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout index 21d388ebd..bb9bfcfdd 100755 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jan 23 2014 12:08:08 -gem5 started Jan 23 2014 19:05:28 -gem5 executing on u200540-lin -command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full +gem5 compiled Jun 21 2014 11:22:42 +gem5 started Jun 21 2014 21:27:42 +gem5 executing on phenom +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re /home/stever/hg/m5sim.org/gem5/tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full Global frequency set at 1000000000000 ticks per second - 0: system.cpu0.isa: ISA system set to: 0x5606400 0x5606400 - 0: system.cpu1.isa: ISA system set to: 0x5606400 0x5606400 - 0: system.cpu2.isa: ISA system set to: 0x5606400 0x5606400 + 0: system.cpu0.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu1.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 + 0: system.cpu2.isa: ISA system set to: 0x61c8fe0 0x61c8fe0 diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt index 60f6414c0..d741bed70 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt @@ -1,168 +1,168 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.403852 # Number of seconds simulated -sim_ticks 2403852457500 # Number of ticks simulated -final_tick 2403852457500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.403860 # Number of seconds simulated +sim_ticks 2403859810000 # Number of ticks simulated +final_tick 2403859810000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 165592 # Simulator instruction rate (inst/s) -host_op_rate 212680 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 6597855857 # Simulator tick rate (ticks/s) -host_mem_usage 469068 # Number of bytes of host memory used -host_seconds 364.34 # Real time elapsed on the host -sim_insts 60331653 # Number of instructions simulated -sim_ops 77487544 # Number of ops (including micro ops) simulated +host_inst_rate 189252 # Simulator instruction rate (inst/s) +host_op_rate 243065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 7540617560 # Simulator tick rate (ticks/s) +host_mem_usage 419508 # Number of bytes of host memory used +host_seconds 318.79 # Real time elapsed on the host +sim_insts 60331162 # Number of instructions simulated +sim_ops 77486236 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 7048216 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 510792 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 7044824 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 63936 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 680960 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.dtb.walker 576 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 186944 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 1348288 # Number of bytes read from this memory -system.physmem.bytes_read::total 124660704 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 63936 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 186944 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3743808 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0.data 1298564 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1.data 159248 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2.data 1558004 # Number of bytes written to this memory -system.physmem.bytes_written::total 6759624 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 65024 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 679232 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.dtb.walker 768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.inst 188416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2.data 1352768 # Number of bytes read from this memory +system.physmem.bytes_read::total 124661152 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 510792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 65024 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu2.inst 188416 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 764232 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3745216 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 1298452 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 159256 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2.data 1558108 # Number of bytes written to this memory +system.physmem.bytes_written::total 6761032 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 110164 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14193 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 110111 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 999 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 10640 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.dtb.walker 9 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2921 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 21067 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14512407 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 58497 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0.data 324641 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1.data 39812 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2.data 389501 # Number of write requests responded to by this memory -system.physmem.num_writes::total 812451 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47764609 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_reads::cpu1.inst 1016 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 10613 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.dtb.walker 12 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.inst 2944 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2.data 21137 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14512414 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 58519 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0.data 324613 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1.data 39814 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2.data 389527 # Number of write requests responded to by this memory +system.physmem.num_writes::total 812473 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47764463 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 213181 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 2932050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 212488 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 2930630 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 26597 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 283279 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.dtb.walker 240 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 77769 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 560886 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51858717 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 213181 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 26597 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 77769 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 317547 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1557420 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 540201 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 66247 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2.data 648128 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2811996 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1557420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47764609 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 27050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 282559 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.dtb.walker 319 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 78381 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 562748 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51858745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 212488 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 27050 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 78381 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 317919 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1558001 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 540153 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 66250 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2.data 648169 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2812573 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1558001 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47764463 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 213181 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3472251 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 212488 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 3470783 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 26597 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 349526 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.dtb.walker 240 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 77769 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 1209014 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54670713 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 13446501 # Number of read requests accepted -system.physmem.writeReqs 446412 # Number of write requests accepted -system.physmem.readBursts 13446501 # Number of DRAM read bursts, including those serviced by the write queue -system.physmem.writeBursts 446412 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 860576000 # Total number of bytes read from DRAM +system.physmem.bw_total::cpu1.inst 27050 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 348809 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.dtb.walker 319 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 78381 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 1210918 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54671318 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 13444811 # Number of read requests accepted +system.physmem.writeReqs 446538 # Number of write requests accepted +system.physmem.readBursts 13444811 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.writeBursts 446538 # Number of DRAM write bursts, including those merged in the write queue +system.physmem.bytesReadDRAM 860467840 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 64 # Total number of bytes read from write queue -system.physmem.bytesWritten 2816640 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 109567680 # Total read bytes from the system interface side -system.physmem.bytesWrittenSys 2811588 # Total written bytes from the system interface side +system.physmem.bytesWritten 2823232 # Total number of bytes written to DRAM +system.physmem.bytesReadSys 109558976 # Total read bytes from the system interface side +system.physmem.bytesWrittenSys 2817972 # Total written bytes from the system interface side system.physmem.servicedByWrQ 1 # Number of DRAM read bursts serviced by the write queue -system.physmem.mergedWrBursts 402376 # Number of DRAM write bursts merged with an existing one -system.physmem.neitherReadNorWriteReqs 2365 # Number of requests that are neither read nor write -system.physmem.perBankRdBursts::0 835689 # Per bank write bursts -system.physmem.perBankRdBursts::1 835334 # Per bank write bursts -system.physmem.perBankRdBursts::2 835514 # Per bank write bursts -system.physmem.perBankRdBursts::3 835992 # Per bank write bursts -system.physmem.perBankRdBursts::4 837083 # Per bank write bursts -system.physmem.perBankRdBursts::5 837766 # Per bank write bursts -system.physmem.perBankRdBursts::6 837910 # Per bank write bursts -system.physmem.perBankRdBursts::7 839140 # Per bank write bursts -system.physmem.perBankRdBursts::8 840643 # Per bank write bursts -system.physmem.perBankRdBursts::9 843328 # Per bank write bursts -system.physmem.perBankRdBursts::10 843395 # Per bank write bursts -system.physmem.perBankRdBursts::11 843892 # Per bank write bursts -system.physmem.perBankRdBursts::12 845429 # Per bank write bursts -system.physmem.perBankRdBursts::13 846004 # Per bank write bursts -system.physmem.perBankRdBursts::14 844795 # Per bank write bursts -system.physmem.perBankRdBursts::15 844586 # Per bank write bursts -system.physmem.perBankWrBursts::0 2674 # Per bank write bursts -system.physmem.perBankWrBursts::1 2534 # Per bank write bursts -system.physmem.perBankWrBursts::2 2538 # Per bank write bursts -system.physmem.perBankWrBursts::3 3024 # Per bank write bursts -system.physmem.perBankWrBursts::4 3410 # Per bank write bursts -system.physmem.perBankWrBursts::5 3131 # Per bank write bursts -system.physmem.perBankWrBursts::6 2493 # Per bank write bursts -system.physmem.perBankWrBursts::7 2267 # Per bank write bursts -system.physmem.perBankWrBursts::8 2164 # Per bank write bursts +system.physmem.mergedWrBursts 402393 # Number of DRAM write bursts merged with an existing one +system.physmem.neitherReadNorWriteReqs 2368 # Number of requests that are neither read nor write +system.physmem.perBankRdBursts::0 835670 # Per bank write bursts +system.physmem.perBankRdBursts::1 835346 # Per bank write bursts +system.physmem.perBankRdBursts::2 835517 # Per bank write bursts +system.physmem.perBankRdBursts::3 836010 # Per bank write bursts +system.physmem.perBankRdBursts::4 837094 # Per bank write bursts +system.physmem.perBankRdBursts::5 837780 # Per bank write bursts +system.physmem.perBankRdBursts::6 837922 # Per bank write bursts +system.physmem.perBankRdBursts::7 839142 # Per bank write bursts +system.physmem.perBankRdBursts::8 840618 # Per bank write bursts +system.physmem.perBankRdBursts::9 843327 # Per bank write bursts +system.physmem.perBankRdBursts::10 843373 # Per bank write bursts +system.physmem.perBankRdBursts::11 843894 # Per bank write bursts +system.physmem.perBankRdBursts::12 845193 # Per bank write bursts +system.physmem.perBankRdBursts::13 844981 # Per bank write bursts +system.physmem.perBankRdBursts::14 844356 # Per bank write bursts +system.physmem.perBankRdBursts::15 844587 # Per bank write bursts +system.physmem.perBankWrBursts::0 2683 # Per bank write bursts +system.physmem.perBankWrBursts::1 2536 # Per bank write bursts +system.physmem.perBankWrBursts::2 2524 # Per bank write bursts +system.physmem.perBankWrBursts::3 3040 # Per bank write bursts +system.physmem.perBankWrBursts::4 3434 # Per bank write bursts +system.physmem.perBankWrBursts::5 3138 # Per bank write bursts +system.physmem.perBankWrBursts::6 2510 # Per bank write bursts +system.physmem.perBankWrBursts::7 2271 # Per bank write bursts +system.physmem.perBankWrBursts::8 2160 # Per bank write bursts system.physmem.perBankWrBursts::9 2378 # Per bank write bursts -system.physmem.perBankWrBursts::10 2328 # Per bank write bursts +system.physmem.perBankWrBursts::10 2319 # Per bank write bursts system.physmem.perBankWrBursts::11 2803 # Per bank write bursts -system.physmem.perBankWrBursts::12 3718 # Per bank write bursts -system.physmem.perBankWrBursts::13 3446 # Per bank write bursts -system.physmem.perBankWrBursts::14 2595 # Per bank write bursts -system.physmem.perBankWrBursts::15 2507 # Per bank write bursts +system.physmem.perBankWrBursts::12 3771 # Per bank write bursts +system.physmem.perBankWrBursts::13 3447 # Per bank write bursts +system.physmem.perBankWrBursts::14 2601 # Per bank write bursts +system.physmem.perBankWrBursts::15 2498 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 2402816386500 # Total gap between requests +system.physmem.totGap 2402823771000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) -system.physmem.readPktSize::3 13410864 # Read request sizes (log2) +system.physmem.readPktSize::3 13409088 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 35637 # Read request sizes (log2) +system.physmem.readPktSize::6 35723 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) -system.physmem.writePktSize::2 429313 # Write request sizes (log2) +system.physmem.writePktSize::2 429341 # Write request sizes (log2) system.physmem.writePktSize::3 0 # Write request sizes (log2) system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) -system.physmem.writePktSize::6 17099 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 877452 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 853858 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 853065 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 937219 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 861122 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 912169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2402802 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 2330624 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 3052022 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 86874 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 80661 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 76244 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 73288 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 16615 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 16291 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 16173 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 21 # What read queue length does an incoming req see +system.physmem.writePktSize::6 17197 # Write request sizes (log2) +system.physmem.rdQLenPdf::0 877930 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 852855 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 852810 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 941410 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 861042 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 915654 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2398641 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 2321801 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 3038639 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 92226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 84687 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 80541 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 77647 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 16577 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 16214 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 16108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 28 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -178,10 +178,10 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 99 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 99 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 100 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 100 # What write queue length does an incoming req see system.physmem.wrQLenPdf::2 98 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 96 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 97 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 96 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 95 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 95 # What write queue length does an incoming req see @@ -193,27 +193,27 @@ system.physmem.wrQLenPdf::11 93 # Wh system.physmem.wrQLenPdf::12 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::13 92 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 92 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 1916 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 1920 # What write queue length does an incoming req see system.physmem.wrQLenPdf::16 2109 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 2309 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 2421 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 2538 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 2461 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 2402 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 2681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 2411 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2396 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 2417 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 2368 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 2356 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::28 2413 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::29 2343 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::30 2346 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 2344 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::32 2313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::33 36 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::34 22 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::35 13 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 2300 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 2423 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 2579 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 2455 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 2431 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 2665 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 2414 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 2438 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 2433 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 2373 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 2390 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::28 2400 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::29 2348 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::30 2337 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::31 2336 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::32 2315 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::33 27 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::34 19 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::35 9 # What write queue length does an incoming req see system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see @@ -242,63 +242,64 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 866032 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 996.952353 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 964.296727 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 145.584191 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 8288 0.96% 0.96% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 8846 1.02% 1.98% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 6189 0.71% 2.69% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 800 0.09% 2.79% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 916 0.11% 2.89% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 687 0.08% 2.97% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 7828 0.90% 3.87% # Bytes accessed per row activation +system.physmem.bytesPerActivate::samples 865990 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 996.883419 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 964.040735 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 145.863432 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8417 0.97% 0.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 8847 1.02% 1.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 6111 0.71% 2.70% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 842 0.10% 2.80% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 894 0.10% 2.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 743 0.09% 2.99% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 7672 0.89% 3.87% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 243 0.03% 3.90% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 832235 96.10% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 866032 # Bytes accessed per row activation -system.physmem.rdPerTurnAround::samples 2414 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::mean 5570.207125 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::stdev 258157.496677 # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::0-524287 2413 99.96% 99.96% # Reads before turning the bus around for writes +system.physmem.bytesPerActivate::1024-1151 832221 96.10% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 865990 # Bytes accessed per row activation +system.physmem.rdPerTurnAround::samples 2416 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::mean 5564.893626 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::stdev 258050.737776 # Reads before turning the bus around for writes +system.physmem.rdPerTurnAround::0-524287 2415 99.96% 99.96% # Reads before turning the bus around for writes system.physmem.rdPerTurnAround::1.25829e+07-1.31072e+07 1 0.04% 100.00% # Reads before turning the bus around for writes -system.physmem.rdPerTurnAround::total 2414 # Reads before turning the bus around for writes -system.physmem.wrPerTurnAround::samples 2414 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::mean 18.231152 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::gmean 18.108696 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::stdev 1.979905 # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::2 1 0.04% 0.04% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::3 2 0.08% 0.12% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::4 1 0.04% 0.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::5 1 0.04% 0.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::7 2 0.08% 0.29% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::9 1 0.04% 0.33% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::12 1 0.04% 0.37% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::14 1 0.04% 0.41% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::15 7 0.29% 0.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::16 485 20.09% 20.80% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::17 15 0.62% 21.42% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::18 872 36.12% 57.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::19 845 35.00% 92.54% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::20 52 2.15% 94.70% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::21 24 0.99% 95.69% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::22 26 1.08% 96.77% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::23 34 1.41% 98.18% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::24 13 0.54% 98.72% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::25 5 0.21% 98.92% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::26 6 0.25% 99.17% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::27 1 0.04% 99.21% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::28 6 0.25% 99.46% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::29 7 0.29% 99.75% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::30 2 0.08% 99.83% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::31 4 0.17% 100.00% # Writes before turning the bus around for reads -system.physmem.wrPerTurnAround::total 2414 # Writes before turning the bus around for reads -system.physmem.totQLat 345783645500 # Total ticks spent queuing -system.physmem.totMemAccLat 597905520500 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 67232500000 # Total ticks spent in databus transfers -system.physmem.avgQLat 25715.51 # Average queueing delay per DRAM burst +system.physmem.rdPerTurnAround::total 2416 # Reads before turning the bus around for writes +system.physmem.wrPerTurnAround::samples 2416 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::mean 18.258692 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::gmean 18.106432 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::stdev 2.116221 # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::1 1 0.04% 0.04% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::2 2 0.08% 0.12% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::3 2 0.08% 0.21% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::4 1 0.04% 0.25% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::5 1 0.04% 0.29% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::7 1 0.04% 0.33% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::9 1 0.04% 0.37% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::11 2 0.08% 0.46% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::15 5 0.21% 0.66% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::16 486 20.12% 20.78% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::17 13 0.54% 21.32% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::18 855 35.39% 56.71% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::19 862 35.68% 92.38% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::20 56 2.32% 94.70% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::21 20 0.83% 95.53% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::22 20 0.83% 96.36% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::23 33 1.37% 97.72% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::24 16 0.66% 98.39% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::25 6 0.25% 98.63% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::26 6 0.25% 98.88% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::27 4 0.17% 99.05% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::28 7 0.29% 99.34% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::29 6 0.25% 99.59% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::30 4 0.17% 99.75% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::31 4 0.17% 99.92% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::32 2 0.08% 100.00% # Writes before turning the bus around for reads +system.physmem.wrPerTurnAround::total 2416 # Writes before turning the bus around for reads +system.physmem.totQLat 346456254750 # Total ticks spent queuing +system.physmem.totMemAccLat 598546442250 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 67224050000 # Total ticks spent in databus transfers +system.physmem.avgQLat 25768.77 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 44465.51 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 358.00 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 44518.77 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 357.95 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 1.17 # Average achieved write bandwidth in MiByte/s system.physmem.avgRdBWSys 45.58 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s @@ -306,18 +307,18 @@ system.physmem.peakBW 12800.00 # Th system.physmem.busUtil 2.81 # Data bus utilization in percentage system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 7.51 # Average read queue length when enqueuing -system.physmem.avgWrQLen 4.43 # Average write queue length when enqueuing -system.physmem.readRowHits 12586631 # Number of row buffer hits during reads -system.physmem.writeRowHits 37847 # Number of row buffer hits during writes +system.physmem.avgRdQLen 8.26 # Average read queue length when enqueuing +system.physmem.avgWrQLen 5.37 # Average write queue length when enqueuing +system.physmem.readRowHits 12585053 # Number of row buffer hits during reads +system.physmem.writeRowHits 37880 # Number of row buffer hits during writes system.physmem.readRowHitRate 93.61 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 85.95 # Row buffer hit rate for writes -system.physmem.avgGap 172952.67 # Average gap between requests +system.physmem.writeRowHitRate 85.81 # Row buffer hit rate for writes +system.physmem.avgGap 172972.67 # Average gap between requests system.physmem.pageHitRate 93.58 # Row buffer hit rate, read and write combined -system.physmem.memoryStateTime::IDLE 2167477603250 # Time in different power states -system.physmem.memoryStateTime::REF 80269800000 # Time in different power states +system.physmem.memoryStateTime::IDLE 2167576169750 # Time in different power states +system.physmem.memoryStateTime::REF 80270060000 # Time in different power states system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem.memoryStateTime::ACT 156101819250 # Time in different power states +system.physmem.memoryStateTime::ACT 156010779000 # Time in different power states system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory @@ -331,322 +332,322 @@ system.realview.nvmem.bw_inst_read::cpu0.inst 8 system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) -system.membus.throughput 55667977 # Throughput (bytes/s) -system.membus.trans_dist::ReadReq 13781620 # Transaction distribution -system.membus.trans_dist::ReadResp 13781620 # Transaction distribution -system.membus.trans_dist::WriteReq 432153 # Transaction distribution -system.membus.trans_dist::WriteResp 432153 # Transaction distribution -system.membus.trans_dist::Writeback 17099 # Transaction distribution -system.membus.trans_dist::UpgradeReq 2365 # Transaction distribution -system.membus.trans_dist::UpgradeResp 2365 # Transaction distribution -system.membus.trans_dist::ReadExReq 28041 # Transaction distribution -system.membus.trans_dist::ReadExResp 28041 # Transaction distribution -system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731786 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.l2c.mem_side::total 1683729 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26821728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count_system.iocache.mem_side::total 26821728 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 28505457 # Packet count per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735662 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5092356 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.l2c.mem_side::total 5828446 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107286912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size_system.iocache.mem_side::total 107286912 # Cumulative packet size per connected master and slave (bytes) -system.membus.tot_pkt_size::total 113115358 # Cumulative packet size per connected master and slave (bytes) -system.membus.data_through_bus 133817603 # Total data (bytes) +system.membus.throughput 55668579 # Throughput (bytes/s) +system.membus.trans_dist::ReadReq 13780402 # Transaction distribution +system.membus.trans_dist::ReadResp 13780402 # Transaction distribution +system.membus.trans_dist::WriteReq 432242 # Transaction distribution +system.membus.trans_dist::WriteResp 432242 # Transaction distribution +system.membus.trans_dist::Writeback 17197 # Transaction distribution +system.membus.trans_dist::UpgradeReq 2368 # Transaction distribution +system.membus.trans_dist::UpgradeResp 2368 # Transaction distribution +system.membus.trans_dist::ReadExReq 28083 # Transaction distribution +system.membus.trans_dist::ReadExResp 28083 # Transaction distribution +system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 732930 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 220 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 952061 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2c.mem_side::total 1685211 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26818176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.iocache.mem_side::total 26818176 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 28503387 # Packet count per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 736825 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 440 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5104244 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.l2c.mem_side::total 5841509 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size_system.iocache.mem_side::total 107272704 # Cumulative packet size per connected master and slave (bytes) +system.membus.tot_pkt_size::total 113114213 # Cumulative packet size per connected master and slave (bytes) +system.membus.data_through_bus 133819459 # Total data (bytes) system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) -system.membus.reqLayer0.occupancy 416874000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 417666500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer2.occupancy 199500 # Layer occupancy (ticks) +system.membus.reqLayer2.occupancy 209500 # Layer occupancy (ticks) system.membus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.membus.reqLayer6.occupancy 14576510500 # Layer occupancy (ticks) +system.membus.reqLayer6.occupancy 14570118500 # Layer occupancy (ticks) system.membus.reqLayer6.utilization 0.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 1596663785 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 1595700088 # Layer occupancy (ticks) system.membus.respLayer1.utilization 0.1 # Layer utilization (%) -system.membus.respLayer2.occupancy 33229062000 # Layer occupancy (ticks) +system.membus.respLayer2.occupancy 33207877250 # Layer occupancy (ticks) system.membus.respLayer2.utilization 1.4 # Layer utilization (%) system.cpu_clk_domain.clock 500 # Clock period in ticks -system.l2c.tags.replacements 63248 # number of replacements -system.l2c.tags.tagsinuse 50398.234461 # Cycle average of tags in use -system.l2c.tags.total_refs 1749256 # Total number of references to valid blocks. -system.l2c.tags.sampled_refs 128641 # Sample count of references to valid blocks. -system.l2c.tags.avg_refs 13.597966 # Average number of references to valid blocks. -system.l2c.tags.warmup_cycle 2375562300000 # Cycle when the warmup percentage was hit. -system.l2c.tags.occ_blocks::writebacks 36845.662788 # Average occupied blocks per requestor +system.l2c.tags.replacements 63255 # number of replacements +system.l2c.tags.tagsinuse 50395.732810 # Cycle average of tags in use +system.l2c.tags.total_refs 1749595 # Total number of references to valid blocks. +system.l2c.tags.sampled_refs 128654 # Sample count of references to valid blocks. +system.l2c.tags.avg_refs 13.599227 # Average number of references to valid blocks. +system.l2c.tags.warmup_cycle 2375537274500 # Cycle when the warmup percentage was hit. +system.l2c.tags.occ_blocks::writebacks 36859.250431 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.inst 5231.089770 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu0.data 3832.891832 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993317 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.inst 496.025776 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu1.data 690.296020 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.dtb.walker 8.797358 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.inst 1694.464698 # Average occupied blocks per requestor -system.l2c.tags.occ_blocks::cpu2.data 1598.012760 # Average occupied blocks per requestor -system.l2c.tags.occ_percent::writebacks 0.562220 # Average percentage of cache occupancy +system.l2c.tags.occ_blocks::cpu0.inst 5225.740605 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu0.data 3831.207928 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993318 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.inst 514.351835 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu1.data 694.414886 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.dtb.walker 10.820575 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.inst 1674.526375 # Average occupied blocks per requestor +system.l2c.tags.occ_blocks::cpu2.data 1584.426715 # Average occupied blocks per requestor +system.l2c.tags.occ_percent::writebacks 0.562428 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.inst 0.079820 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu0.data 0.058485 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.inst 0.079738 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu0.data 0.058460 # Average percentage of cache occupancy system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.inst 0.007569 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu1.data 0.010533 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000134 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.inst 0.025855 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::cpu2.data 0.024384 # Average percentage of cache occupancy -system.l2c.tags.occ_percent::total 0.769016 # Average percentage of cache occupancy -system.l2c.tags.occ_task_id_blocks::1023 4 # Occupied blocks per task id -system.l2c.tags.occ_task_id_blocks::1024 65389 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1023::4 4 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::3 6488 # Occupied blocks per task id -system.l2c.tags.age_task_id_blocks_1024::4 55889 # Occupied blocks per task id -system.l2c.tags.occ_task_id_percent::1023 0.000061 # Percentage of cache occupancy per task id -system.l2c.tags.occ_task_id_percent::1024 0.997757 # Percentage of cache occupancy per task id -system.l2c.tags.tag_accesses 17683113 # Number of tag accesses -system.l2c.tags.data_accesses 17683113 # Number of data accesses -system.l2c.ReadReq_hits::cpu0.dtb.walker 8690 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 3137 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 468117 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 177120 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 2623 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.itb.walker 1184 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 129717 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 64377 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.dtb.walker 18993 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.itb.walker 4195 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 281260 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 131724 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1291137 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 597632 # number of Writeback hits -system.l2c.Writeback_hits::total 597632 # number of Writeback hits +system.l2c.tags.occ_percent::cpu1.inst 0.007848 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu1.data 0.010596 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000165 # Average percentage of cache occupancy +system.l2c.tags.occ_percent::cpu2.inst 0.025551 # Average percentage of cache occupancy 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-system.l2c.overall_hits::cpu0.dtb.walker 8690 # number of overall hits -system.l2c.overall_hits::cpu0.itb.walker 3137 # number of overall hits -system.l2c.overall_hits::cpu0.inst 468117 # number of overall hits -system.l2c.overall_hits::cpu0.data 239121 # number of overall hits -system.l2c.overall_hits::cpu1.dtb.walker 2623 # number of overall hits -system.l2c.overall_hits::cpu1.itb.walker 1184 # number of overall hits -system.l2c.overall_hits::cpu1.inst 129717 # number of overall hits -system.l2c.overall_hits::cpu1.data 82786 # number of overall hits -system.l2c.overall_hits::cpu2.dtb.walker 18993 # number of overall hits -system.l2c.overall_hits::cpu2.itb.walker 4195 # number of overall hits -system.l2c.overall_hits::cpu2.inst 281260 # number of overall hits -system.l2c.overall_hits::cpu2.data 164925 # number of overall hits -system.l2c.overall_hits::total 1404748 # number of overall hits +system.l2c.SCUpgradeReq_hits::cpu2.data 3 # number of SCUpgradeReq hits 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-system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34694058000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 60700071100 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017085 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018967 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.005786 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991543 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988361 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.507157 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.347268 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365485 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.117086 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.023410 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000381 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007643 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.116469 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000474 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010279 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2.data 0.116131 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.023410 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_latency::cpu1.inst 58931500 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 655020019 # number of overall MSHR miss cycles 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9471519545 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 25972104545 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34826489500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 60798594045 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017173 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018905 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.005820 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991753 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.988304 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.509196 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.343485 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.365679 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.117225 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.023462 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000382 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007733 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.115803 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000634 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010303 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.116314 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.023462 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64058.310992 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64394.188850 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 63013.296340 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63559.280639 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 64023.022432 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 63001.570681 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59891.492036 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61174.798891 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 60740.166229 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10003.464497 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10002.671572 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 59804.455617 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 61130.396042 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 60683.653578 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58264.514515 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60318.750389 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 62500 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63034.748374 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61553.174888 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 61213.045024 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 58003.444882 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 60192.980978 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 61354.166667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63638.417120 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 61468.474495 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 61167.555826 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -799,52 +800,52 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.toL2Bus.throughput 58808825 # Throughput (bytes/s) -system.toL2Bus.trans_dist::ReadReq 1019736 # Transaction distribution -system.toL2Bus.trans_dist::ReadResp 1019735 # Transaction distribution -system.toL2Bus.trans_dist::WriteReq 432153 # Transaction distribution -system.toL2Bus.trans_dist::WriteResp 432153 # Transaction distribution -system.toL2Bus.trans_dist::Writeback 265208 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeReq 1504 # Transaction distribution -system.toL2Bus.trans_dist::SCUpgradeReq 4 # Transaction distribution -system.toL2Bus.trans_dist::UpgradeResp 1508 # Transaction distribution -system.toL2Bus.trans_dist::ReadExReq 80528 # Transaction distribution -system.toL2Bus.trans_dist::ReadExResp 80528 # Transaction distribution -system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 830481 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419466 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15414 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52803 # Packet count per connected master and slave (bytes) -system.toL2Bus.pkt_count::total 3318164 # Packet count per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26553408 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37366366 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21516 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86504 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.tot_pkt_size::total 64027794 # Cumulative packet size per connected master and slave (bytes) -system.toL2Bus.data_through_bus 141267007 # Total data (bytes) -system.toL2Bus.snoop_data_through_bus 100732 # Total snoop data (bytes) -system.toL2Bus.reqLayer0.occupancy 2176624753 # Layer occupancy (ticks) +system.toL2Bus.throughput 58812389 # Throughput (bytes/s) +system.toL2Bus.trans_dist::ReadReq 1022771 # Transaction distribution +system.toL2Bus.trans_dist::ReadResp 1022770 # Transaction distribution +system.toL2Bus.trans_dist::WriteReq 432242 # Transaction distribution +system.toL2Bus.trans_dist::WriteResp 432242 # Transaction distribution +system.toL2Bus.trans_dist::Writeback 265826 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeReq 1511 # Transaction distribution +system.toL2Bus.trans_dist::SCUpgradeReq 3 # Transaction distribution +system.toL2Bus.trans_dist::UpgradeResp 1514 # Transaction distribution +system.toL2Bus.trans_dist::ReadExReq 80908 # Transaction distribution +system.toL2Bus.trans_dist::ReadExResp 80908 # Transaction distribution +system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 834992 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2422460 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15408 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52756 # Packet count per connected master and slave (bytes) +system.toL2Bus.pkt_count::total 3325616 # Packet count per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26696960 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37444261 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21472 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 86120 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.tot_pkt_size::total 64248813 # Cumulative packet size per connected master and slave (bytes) +system.toL2Bus.data_through_bus 141273763 # Total data (bytes) +system.toL2Bus.snoop_data_through_bus 102976 # Total snoop data (bytes) +system.toL2Bus.reqLayer0.occupancy 2181217728 # Layer occupancy (ticks) system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer0.occupancy 1870991697 # Layer occupancy (ticks) +system.toL2Bus.respLayer0.occupancy 1881226404 # Layer occupancy (ticks) system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer1.occupancy 1845922726 # Layer occupancy (ticks) +system.toL2Bus.respLayer1.occupancy 1849082178 # Layer occupancy (ticks) system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%) -system.toL2Bus.respLayer2.occupancy 10050964 # Layer occupancy (ticks) +system.toL2Bus.respLayer2.occupancy 10054967 # Layer occupancy (ticks) system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%) -system.toL2Bus.respLayer3.occupancy 31304739 # Layer occupancy (ticks) +system.toL2Bus.respLayer3.occupancy 31351984 # Layer occupancy (ticks) system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%) -system.iobus.throughput 48758959 # Throughput (bytes/s) -system.iobus.trans_dist::ReadReq 13773981 # Transaction distribution -system.iobus.trans_dist::ReadResp 13773981 # Transaction distribution -system.iobus.trans_dist::WriteReq 2776 # Transaction distribution -system.iobus.trans_dist::WriteResp 2776 # Transaction distribution -system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11410 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3028 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes) +system.iobus.throughput 48758810 # Throughput (bytes/s) +system.iobus.trans_dist::ReadReq 13772718 # Transaction distribution +system.iobus.trans_dist::ReadResp 13772718 # Transaction distribution +system.iobus.trans_dist::WriteReq 2835 # Transaction distribution +system.iobus.trans_dist::WriteResp 2835 # Transaction distribution +system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11646 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3040 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 20 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 258 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716788 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 717678 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes) @@ -860,18 +861,18 @@ system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes) system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.bridge.master::total 731786 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26821728 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count_system.realview.clcd.dma::total 26821728 # Packet count per connected master and slave (bytes) -system.iobus.pkt_count::total 27553514 # Packet count per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15374 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6056 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes) +system.iobus.pkt_count_system.bridge.master::total 732930 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26818176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count_system.realview.clcd.dma::total 26818176 # Packet count per connected master and slave (bytes) +system.iobus.pkt_count::total 27551106 # Packet count per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15610 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6080 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 40 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 516 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713112 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 714003 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) @@ -887,18 +888,18 @@ system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes) system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.bridge.master::total 735662 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107286912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107286912 # Cumulative packet size per connected master and slave (bytes) -system.iobus.tot_pkt_size::total 108022574 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.bridge.master::total 736825 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107272704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107272704 # Cumulative packet size per connected master and slave (bytes) +system.iobus.tot_pkt_size::total 108009529 # Cumulative packet size per connected master and slave (bytes) system.iobus.data_through_bus 117209343 # Total data (bytes) -system.iobus.reqLayer0.occupancy 7968000 # Layer occupancy (ticks) +system.iobus.reqLayer0.occupancy 8145000 # Layer occupancy (ticks) system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer1.occupancy 1514000 # Layer occupancy (ticks) +system.iobus.reqLayer1.occupancy 1520000 # Layer occupancy (ticks) system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks) +system.iobus.reqLayer2.occupancy 20000 # Layer occupancy (ticks) system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks) +system.iobus.reqLayer3.occupancy 129000 # Layer occupancy (ticks) system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%) @@ -906,7 +907,7 @@ system.iobus.reqLayer5.occupancy 8000 # La system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer7.occupancy 358898000 # Layer occupancy (ticks) +system.iobus.reqLayer7.occupancy 359342000 # Layer occupancy (ticks) system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%) @@ -938,11 +939,11 @@ system.iobus.reqLayer22.occupancy 8000 # La system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%) system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks) system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%) -system.iobus.reqLayer25.occupancy 13410864000 # Layer occupancy (ticks) +system.iobus.reqLayer25.occupancy 13409088000 # Layer occupancy (ticks) system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%) -system.iobus.respLayer0.occupancy 729010000 # Layer occupancy (ticks) +system.iobus.respLayer0.occupancy 730095000 # Layer occupancy (ticks) system.iobus.respLayer0.utilization 0.0 # Layer utilization (%) -system.iobus.respLayer1.occupancy 33767373000 # Layer occupancy (ticks) +system.iobus.respLayer1.occupancy 33780437750 # Layer occupancy (ticks) system.iobus.respLayer1.utilization 1.4 # Layer utilization (%) system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses @@ -967,25 +968,25 @@ system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7995700 # DTB read hits -system.cpu0.dtb.read_misses 6195 # DTB read misses -system.cpu0.dtb.write_hits 6594454 # DTB write hits -system.cpu0.dtb.write_misses 1984 # DTB write misses +system.cpu0.dtb.read_hits 7992228 # DTB read hits +system.cpu0.dtb.read_misses 6211 # DTB read misses +system.cpu0.dtb.write_hits 6585208 # DTB write hits +system.cpu0.dtb.write_misses 1983 # DTB write misses system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5669 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 5702 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 121 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 117 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 8001895 # DTB read accesses -system.cpu0.dtb.write_accesses 6596438 # DTB write accesses +system.cpu0.dtb.perms_faults 210 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7998439 # DTB read accesses +system.cpu0.dtb.write_accesses 6587191 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 14590154 # DTB hits -system.cpu0.dtb.misses 8179 # DTB misses -system.cpu0.dtb.accesses 14598333 # DTB accesses +system.cpu0.dtb.hits 14577436 # DTB hits +system.cpu0.dtb.misses 8194 # DTB misses +system.cpu0.dtb.accesses 14585630 # DTB accesses system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1007,468 +1008,468 @@ system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu0.itb.inst_hits 32327896 # ITB inst hits -system.cpu0.itb.inst_misses 3449 # ITB inst misses +system.cpu0.itb.inst_hits 32348466 # ITB inst hits +system.cpu0.itb.inst_misses 3468 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 675 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 676 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2626 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2648 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 32331345 # ITB inst accesses -system.cpu0.itb.hits 32327896 # DTB hits -system.cpu0.itb.misses 3449 # DTB misses -system.cpu0.itb.accesses 32331345 # DTB accesses -system.cpu0.numCycles 113683212 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 32351934 # ITB inst accesses +system.cpu0.itb.hits 32348466 # DTB hits +system.cpu0.itb.misses 3468 # DTB misses +system.cpu0.itb.accesses 32351934 # DTB accesses +system.cpu0.numCycles 113676157 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 31852389 # Number of instructions committed -system.cpu0.committedOps 42022034 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 37405417 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses -system.cpu0.num_func_calls 1199046 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4246321 # number of instructions that are conditional controls -system.cpu0.num_int_insts 37405417 # number of integer instructions -system.cpu0.num_fp_insts 4937 # number of float instructions -system.cpu0.num_int_register_reads 193890675 # number of times the integer registers were read -system.cpu0.num_int_register_writes 39514617 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written -system.cpu0.num_mem_refs 15257672 # number of memory refs -system.cpu0.num_load_insts 8364380 # Number of load instructions -system.cpu0.num_store_insts 6893292 # Number of store instructions -system.cpu0.num_idle_cycles 110986808.765580 # Number of idle cycles -system.cpu0.num_busy_cycles 2696403.234420 # Number of busy cycles -system.cpu0.not_idle_fraction 0.023719 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.976281 # Percentage of idle cycles -system.cpu0.Branches 5614656 # Number of branches fetched -system.cpu0.op_class::No_OpClass 14792 0.04% 0.04% # Class of executed instruction -system.cpu0.op_class::IntAlu 26773719 63.60% 63.63% # Class of executed instruction -system.cpu0.op_class::IntMult 49650 0.12% 63.75% # Class of executed instruction -system.cpu0.op_class::IntDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatMult 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::FloatSqrt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAddAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdAlu 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMisc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMult 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdMultAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdShift 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdSqrt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.75% # Class of executed instruction -system.cpu0.op_class::SimdFloatMisc 1431 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMult 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.76% # Class of executed instruction -system.cpu0.op_class::MemRead 8364380 19.87% 83.63% # Class of executed instruction -system.cpu0.op_class::MemWrite 6893292 16.37% 100.00% # Class of executed instruction +system.cpu0.committedInsts 31863567 # Number of instructions committed +system.cpu0.committedOps 42010857 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 37388293 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5018 # Number of float alu accesses +system.cpu0.num_func_calls 1197302 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4248978 # number of instructions that are conditional controls +system.cpu0.num_int_insts 37388293 # number of integer instructions +system.cpu0.num_fp_insts 5018 # number of float instructions +system.cpu0.num_int_register_reads 193803982 # number of times the integer registers were read +system.cpu0.num_int_register_writes 39520708 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 3589 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 1430 # number of times the floating registers were written +system.cpu0.num_mem_refs 15242780 # number of memory refs +system.cpu0.num_load_insts 8359522 # Number of load instructions +system.cpu0.num_store_insts 6883258 # Number of store instructions +system.cpu0.num_idle_cycles 110978931.176812 # Number of idle cycles +system.cpu0.num_busy_cycles 2697225.823188 # Number of busy cycles +system.cpu0.not_idle_fraction 0.023727 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.976273 # Percentage of idle cycles +system.cpu0.Branches 5616963 # Number of branches fetched +system.cpu0.op_class::No_OpClass 14526 0.03% 0.03% # Class of executed instruction +system.cpu0.op_class::IntAlu 26777156 63.63% 63.66% # Class of executed instruction +system.cpu0.op_class::IntMult 49712 0.12% 63.78% # Class of executed instruction +system.cpu0.op_class::IntDiv 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatAdd 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 1435 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 63.78% # Class of executed instruction +system.cpu0.op_class::MemRead 8359522 19.86% 83.64% # Class of executed instruction +system.cpu0.op_class::MemWrite 6883258 16.36% 100.00% # Class of executed instruction system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu0.op_class::total 42097264 # Class of executed instruction +system.cpu0.op_class::total 42085609 # Class of executed instruction system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed -system.cpu0.icache.tags.replacements 891512 # number of replacements -system.cpu0.icache.tags.tagsinuse 511.602542 # Cycle average of tags in use -system.cpu0.icache.tags.total_refs 43658005 # Total number of references to valid blocks. -system.cpu0.icache.tags.sampled_refs 892024 # Sample count of references to valid blocks. -system.cpu0.icache.tags.avg_refs 48.942635 # Average number of references to valid blocks. -system.cpu0.icache.tags.warmup_cycle 8184230000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.tags.occ_blocks::cpu0.inst 494.829489 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.587272 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_blocks::cpu2.inst 9.185782 # Average occupied blocks per requestor -system.cpu0.icache.tags.occ_percent::cpu0.inst 0.966464 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014819 # Average percentage of cache occupancy -system.cpu0.icache.tags.occ_percent::cpu2.inst 0.017941 # Average percentage of cache occupancy +system.cpu0.icache.tags.replacements 891568 # number of replacements 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miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11778.506088 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11494.774419 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11909.034236 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11778.506088 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.tags.replacements 629833 # number of replacements +system.cpu0.dcache.tags.replacements 629808 # number of replacements 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requestor -system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970786 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015745 # Average percentage of cache occupancy -system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013464 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.011918 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.087644 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.897556 # Average occupied blocks per requestor +system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970726 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015796 # Average percentage of cache occupancy +system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013472 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id -system.cpu0.dcache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::0 196 # Occupied blocks per task id +system.cpu0.dcache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id -system.cpu0.dcache.tags.tag_accesses 98835293 # Number of tag accesses -system.cpu0.dcache.tags.data_accesses 98835293 # Number of data accesses -system.cpu0.dcache.ReadReq_hits::cpu0.data 6864775 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu1.data 1819119 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::cpu2.data 4641948 # number of ReadReq hits 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(read+write) misses -system.cpu0.dcache.demand_misses::cpu1.data 92428 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::cpu2.data 880124 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 1317553 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 345001 # number of overall misses -system.cpu0.dcache.overall_misses::cpu1.data 92428 # number of overall misses -system.cpu0.dcache.overall_misses::cpu2.data 880124 # number of overall misses -system.cpu0.dcache.overall_misses::total 1317553 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 907525000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3898427279 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 4805952279 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 994225242 # number of WriteReq miss cycles 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(read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu1.data 1901750242 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::cpu2.data 26837319822 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 28739070064 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 7041893 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu1.data 1882871 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::cpu2.data 4912422 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 13837186 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6130929 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu1.data 1342989 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu2.data 2742531 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 10216449 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138256 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34751 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77206 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 250213 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138256 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34751 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74382 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.tags.tag_accesses 98838984 # Number of tag accesses +system.cpu0.dcache.tags.data_accesses 98838984 # Number of data accesses +system.cpu0.dcache.ReadReq_hits::cpu0.data 6862400 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu1.data 1819912 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::cpu2.data 4640111 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13322423 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5954558 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu1.data 1318615 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::cpu2.data 2132591 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 9405764 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131484 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 33204 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73477 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 238165 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 137939 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34940 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74507 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 247386 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12816958 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu1.data 3138527 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::cpu2.data 6772702 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 22728187 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12816958 # number of overall hits +system.cpu0.dcache.overall_hits::cpu1.data 3138527 # number of overall hits +system.cpu0.dcache.overall_hits::cpu2.data 6772702 # number of overall hits +system.cpu0.dcache.overall_hits::total 22728187 # number of overall hits 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(read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::cpu2.data 26047196486 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27949531986 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu1.data 1902335500 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::cpu2.data 26047196486 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27949531986 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 7039274 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu1.data 1883743 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::cpu2.data 4915199 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13838216 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 6122087 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu1.data 1347503 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu2.data 2746857 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 10216447 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 137939 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34940 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77235 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 250114 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 137939 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34940 # number of StoreCondReq accesses(hits+misses) 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-system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025152 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033859 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055059 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.036954 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027383 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021352 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.222295 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.078913 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046768 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050186 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.048312 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047719 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000054 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000016 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028652 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114974 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.054776 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028652 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114974 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.054776 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14235.239679 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14413.316175 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 9398.667588 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34670.987655 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 37626.330752 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29685.996789 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13127.723624 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13383.243432 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6098.345729 # average LoadLockedReq miss latency +system.cpu0.dcache.demand_accesses::cpu0.data 13161361 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu1.data 3231246 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::cpu2.data 7662056 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 24054663 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 13161361 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu1.data 3231246 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu2.data 7662056 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 24054663 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025127 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033885 # miss rate for ReadReq accesses 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miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14344.630809 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.746670 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 34403.844157 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 35979.788375 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28488.347401 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13120.391705 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13425.292177 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6128.483388 # average LoadLockedReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 21812.458447 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20575.477583 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30492.657651 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 21812.458447 # average overall miss latency -system.cpu0.dcache.blocked_cycles::no_mshrs 8069 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 3116 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 905 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 48 # number of cycles access was blocked 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LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57799752 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 44000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714080758 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3543058359 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 5257139117 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714080758 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3543058359 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 5257139117 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27392049000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28579464500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55971513500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1440396400 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13339396963 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14779793363 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28832445400 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41918861463 # number of overall MSHR uncacheable cycles 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-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020255 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000054 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000016 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.011505 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028652 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024078 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.011505 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12232.243694 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12934.667725 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12704.722377 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32579.535430 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34670.389239 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33939.184529 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11127.436927 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11550.391697 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11404.844515 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.writebacks::writebacks 597736 # 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cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1853484745 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2786994495 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19304000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38850752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 58154752 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 33000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1714133500 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3553714610 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 5267848110 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1714133500 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3553714610 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 5267848110 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27350994000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28703901500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 56054895500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1444132955 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13356723550 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14800856505 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28795126955 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 42060625050 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70855752005 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033885 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026674 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014087 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021438 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019472 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.008063 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.049685 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.043387 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020339 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000040 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000012 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.011528 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028695 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024092 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.011528 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12229.539722 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12968.360449 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12726.437849 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32314.793340 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 34653.642916 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33833.424321 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11119.815668 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11593.778574 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11432.033025 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18545.037846 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19222.738986 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.397815 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18487.402798 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19251.726023 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 18996.174367 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1502,25 +1503,25 @@ system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 2096038 # DTB read hits -system.cpu1.dtb.read_misses 2089 # DTB read misses -system.cpu1.dtb.write_hits 1418402 # DTB write hits -system.cpu1.dtb.write_misses 376 # DTB write misses +system.cpu1.dtb.read_hits 2096820 # DTB read hits +system.cpu1.dtb.read_misses 2107 # DTB read misses +system.cpu1.dtb.write_hits 1423125 # DTB write hits +system.cpu1.dtb.write_misses 370 # DTB write misses system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1770 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1777 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.dtb.prefetch_faults 37 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 2098127 # DTB read accesses -system.cpu1.dtb.write_accesses 1418778 # DTB write accesses +system.cpu1.dtb.perms_faults 78 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 2098927 # DTB read accesses +system.cpu1.dtb.write_accesses 1423495 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 3514440 # DTB hits -system.cpu1.dtb.misses 2465 # DTB misses -system.cpu1.dtb.accesses 3516905 # DTB accesses +system.cpu1.dtb.hits 3519945 # DTB hits +system.cpu1.dtb.misses 2477 # DTB misses +system.cpu1.dtb.accesses 3522422 # DTB accesses system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1542,96 +1543,96 @@ system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu1.itb.inst_hits 8190394 # ITB inst hits -system.cpu1.itb.inst_misses 1200 # ITB inst misses +system.cpu1.itb.inst_hits 8175454 # ITB inst hits +system.cpu1.itb.inst_misses 1196 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 233 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 949 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 946 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 8191594 # ITB inst accesses -system.cpu1.itb.hits 8190394 # DTB hits -system.cpu1.itb.misses 1200 # DTB misses -system.cpu1.itb.accesses 8191594 # DTB accesses -system.cpu1.numCycles 584767176 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 8176650 # ITB inst accesses +system.cpu1.itb.hits 8175454 # DTB hits +system.cpu1.itb.misses 1196 # DTB misses +system.cpu1.itb.accesses 8176650 # DTB accesses +system.cpu1.numCycles 584791217 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 7979697 # Number of instructions committed -system.cpu1.committedOps 10128513 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 9101420 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses -system.cpu1.num_func_calls 304592 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 1114093 # number of instructions that are conditional controls -system.cpu1.num_int_insts 9101420 # number of integer instructions -system.cpu1.num_fp_insts 2019 # number of float instructions -system.cpu1.num_int_register_reads 53054873 # number of times the integer registers were read -system.cpu1.num_int_register_writes 9892627 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written -system.cpu1.num_mem_refs 3681879 # number of memory refs -system.cpu1.num_load_insts 2189240 # Number of load instructions -system.cpu1.num_store_insts 1492639 # Number of store instructions -system.cpu1.num_idle_cycles 548440957.661697 # Number of idle cycles -system.cpu1.num_busy_cycles 36326218.338303 # Number of busy cycles -system.cpu1.not_idle_fraction 0.062121 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.937879 # Percentage of idle cycles -system.cpu1.Branches 1446987 # Number of branches fetched -system.cpu1.op_class::No_OpClass 5386 0.05% 0.05% # Class of executed instruction -system.cpu1.op_class::IntAlu 6616988 64.14% 64.19% # Class of executed instruction -system.cpu1.op_class::IntMult 11601 0.11% 64.31% # Class of executed instruction -system.cpu1.op_class::IntDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::FloatSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAddAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdAlu 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMisc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdMultAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdShift 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMult 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.31% # Class of executed instruction -system.cpu1.op_class::MemRead 2189240 21.22% 85.53% # Class of executed instruction -system.cpu1.op_class::MemWrite 1492639 14.47% 100.00% # Class of executed instruction +system.cpu1.committedInsts 7972563 # Number of instructions committed +system.cpu1.committedOps 10134873 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 9111769 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 2002 # Number of float alu accesses +system.cpu1.num_func_calls 305506 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1114419 # number of instructions that are conditional controls +system.cpu1.num_int_insts 9111769 # number of integer instructions +system.cpu1.num_fp_insts 2002 # number of float instructions +system.cpu1.num_int_register_reads 53111503 # number of times the integer registers were read +system.cpu1.num_int_register_writes 9891567 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 1488 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 516 # number of times the floating registers were written +system.cpu1.num_mem_refs 3688880 # number of memory refs +system.cpu1.num_load_insts 2190803 # Number of load instructions +system.cpu1.num_store_insts 1498077 # Number of store instructions +system.cpu1.num_idle_cycles 549443201.253140 # Number of idle cycles +system.cpu1.num_busy_cycles 35348015.746859 # Number of busy cycles +system.cpu1.not_idle_fraction 0.060446 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.939554 # Percentage of idle cycles +system.cpu1.Branches 1447411 # Number of branches fetched +system.cpu1.op_class::No_OpClass 5397 0.05% 0.05% # Class of executed instruction +system.cpu1.op_class::IntAlu 6618001 64.10% 64.15% # Class of executed instruction +system.cpu1.op_class::IntMult 11557 0.11% 64.27% # Class of executed instruction +system.cpu1.op_class::IntDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::FloatSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAddAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdAlu 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMisc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdMultAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdShift 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdShiftAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAdd 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatAlu 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCmp 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatCvt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatDiv 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMisc 298 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMult 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::SimdFloatSqrt 0 0.00% 64.27% # Class of executed instruction +system.cpu1.op_class::MemRead 2190803 21.22% 85.49% # Class of executed instruction +system.cpu1.op_class::MemWrite 1498077 14.51% 100.00% # Class of executed instruction system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu1.op_class::total 10316152 # Class of executed instruction +system.cpu1.op_class::total 10324133 # Class of executed instruction system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed -system.cpu2.branchPred.lookups 4788852 # Number of BP lookups -system.cpu2.branchPred.condPredicted 3906949 # Number of conditional branches predicted -system.cpu2.branchPred.condIncorrect 223643 # Number of conditional branches incorrect -system.cpu2.branchPred.BTBLookups 3181584 # Number of BTB lookups -system.cpu2.branchPred.BTBHits 2530711 # Number of BTB hits +system.cpu2.branchPred.lookups 4844951 # Number of BP lookups +system.cpu2.branchPred.condPredicted 3958364 # Number of conditional branches predicted +system.cpu2.branchPred.condIncorrect 223288 # Number of conditional branches incorrect +system.cpu2.branchPred.BTBLookups 3209464 # Number of BTB lookups +system.cpu2.branchPred.BTBHits 2561917 # Number of BTB hits system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu2.branchPred.BTBHitPct 79.542486 # BTB Hit Percentage -system.cpu2.branchPred.usedRAS 413887 # Number of times the RAS was used to get a target. -system.cpu2.branchPred.RASInCorrect 21714 # Number of incorrect RAS predictions. +system.cpu2.branchPred.BTBHitPct 79.823827 # BTB Hit Percentage +system.cpu2.branchPred.usedRAS 415777 # Number of times the RAS was used to get a target. +system.cpu2.branchPred.RASInCorrect 21493 # Number of incorrect RAS predictions. system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1655,25 +1656,25 @@ system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # D system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses system.cpu2.dtb.inst_hits 0 # ITB inst hits system.cpu2.dtb.inst_misses 0 # ITB inst misses -system.cpu2.dtb.read_hits 10930564 # DTB read hits -system.cpu2.dtb.read_misses 23215 # DTB read misses -system.cpu2.dtb.write_hits 3350483 # DTB write hits -system.cpu2.dtb.write_misses 6482 # DTB write misses +system.cpu2.dtb.read_hits 10946099 # DTB read hits +system.cpu2.dtb.read_misses 23259 # DTB read misses +system.cpu2.dtb.write_hits 3358425 # DTB write hits +system.cpu2.dtb.write_misses 6569 # DTB write misses system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.dtb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID +system.cpu2.dtb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB -system.cpu2.dtb.align_faults 733 # Number of TLB faults due to alignment restrictions -system.cpu2.dtb.prefetch_faults 153 # Number of TLB faults due to prefetch +system.cpu2.dtb.flush_entries 2341 # Number of entries that have been flushed from TLB +system.cpu2.dtb.align_faults 761 # Number of TLB faults due to alignment restrictions +system.cpu2.dtb.prefetch_faults 169 # Number of TLB faults due to prefetch system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.dtb.perms_faults 461 # Number of TLB faults due to permissions restrictions -system.cpu2.dtb.read_accesses 10953779 # DTB read accesses -system.cpu2.dtb.write_accesses 3356965 # DTB write accesses +system.cpu2.dtb.perms_faults 490 # Number of TLB faults due to permissions restrictions +system.cpu2.dtb.read_accesses 10969358 # DTB read accesses +system.cpu2.dtb.write_accesses 3364994 # DTB write accesses system.cpu2.dtb.inst_accesses 0 # ITB inst accesses -system.cpu2.dtb.hits 14281047 # DTB hits -system.cpu2.dtb.misses 29697 # DTB misses -system.cpu2.dtb.accesses 14310744 # DTB accesses +system.cpu2.dtb.hits 14304524 # DTB hits +system.cpu2.dtb.misses 29828 # DTB misses +system.cpu2.dtb.accesses 14334352 # DTB accesses system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits @@ -1695,328 +1696,329 @@ system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses -system.cpu2.itb.inst_hits 4054306 # ITB inst hits -system.cpu2.itb.inst_misses 4589 # ITB inst misses +system.cpu2.itb.inst_hits 4066170 # ITB inst hits +system.cpu2.itb.inst_misses 4558 # ITB inst misses system.cpu2.itb.read_hits 0 # DTB read hits system.cpu2.itb.read_misses 0 # DTB read misses system.cpu2.itb.write_hits 0 # DTB write hits system.cpu2.itb.write_misses 0 # DTB write misses system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu2.itb.flush_tlb_mva_asid 543 # Number of times TLB was flushed by MVA & ASID +system.cpu2.itb.flush_tlb_mva_asid 530 # Number of times TLB was flushed by MVA & ASID system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID -system.cpu2.itb.flush_entries 1707 # Number of entries that have been flushed from TLB +system.cpu2.itb.flush_entries 1650 # Number of entries that have been flushed from TLB system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu2.itb.perms_faults 958 # Number of TLB faults due to permissions restrictions +system.cpu2.itb.perms_faults 1020 # Number of TLB faults due to permissions restrictions system.cpu2.itb.read_accesses 0 # DTB read accesses system.cpu2.itb.write_accesses 0 # DTB write accesses -system.cpu2.itb.inst_accesses 4058895 # ITB inst accesses -system.cpu2.itb.hits 4054306 # DTB hits -system.cpu2.itb.misses 4589 # DTB misses -system.cpu2.itb.accesses 4058895 # DTB accesses -system.cpu2.numCycles 88316329 # number of cpu cycles simulated +system.cpu2.itb.inst_accesses 4070728 # ITB inst accesses +system.cpu2.itb.hits 4066170 # DTB hits +system.cpu2.itb.misses 4558 # DTB misses +system.cpu2.itb.accesses 4070728 # DTB accesses +system.cpu2.numCycles 88357644 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.fetch.icacheStallCycles 9351504 # Number of cycles fetch is stalled on an Icache miss -system.cpu2.fetch.Insts 32524106 # Number of instructions fetch has processed -system.cpu2.fetch.Branches 4788852 # Number of branches that fetch encountered -system.cpu2.fetch.predictedBranches 2944598 # Number of branches that fetch has predicted taken -system.cpu2.fetch.Cycles 6861719 # Number of cycles fetch has run and was not squashing or blocked -system.cpu2.fetch.SquashCycles 1761177 # Number of cycles fetch has spent squashing -system.cpu2.fetch.TlbCycles 50498 # Number of cycles fetch has spent waiting for tlb -system.cpu2.fetch.BlockedCycles 19190819 # Number of cycles fetch has spent blocked -system.cpu2.fetch.MiscStallCycles 265 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.PendingDrainCycles 860 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu2.fetch.PendingTrapStallCycles 33145 # Number of stall cycles due to pending traps -system.cpu2.fetch.PendingQuiesceStallCycles 719724 # Number of stall cycles due to pending quiesce instructions -system.cpu2.fetch.IcacheWaitRetryStallCycles 402 # Number of stall cycles due to full MSHR -system.cpu2.fetch.CacheLines 4052907 # Number of cache lines fetched -system.cpu2.fetch.IcacheSquashes 289738 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.ItlbSquashes 2002 # Number of outstanding ITLB misses that were squashed -system.cpu2.fetch.rateDist::samples 37419321 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.044533 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.431855 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.icacheStallCycles 9387256 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32765333 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 4844951 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 2977694 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 6914165 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1793026 # Number of cycles fetch has spent squashing +system.cpu2.fetch.TlbCycles 51157 # Number of cycles fetch has spent waiting for tlb +system.cpu2.fetch.BlockedCycles 18399919 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 356 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingDrainCycles 937 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu2.fetch.PendingTrapStallCycles 34522 # Number of stall cycles due to pending traps +system.cpu2.fetch.PendingQuiesceStallCycles 732881 # Number of stall cycles due to pending quiesce instructions +system.cpu2.fetch.IcacheWaitRetryStallCycles 499 # Number of stall cycles due to full MSHR +system.cpu2.fetch.CacheLines 4064781 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 291170 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.ItlbSquashes 1939 # Number of outstanding ITLB misses that were squashed +system.cpu2.fetch.rateDist::samples 36763653 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.071353 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.456601 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 30562706 81.68% 81.68% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::1 385991 1.03% 82.71% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::2 516133 1.38% 84.09% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::3 820285 2.19% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::4 630351 1.68% 87.96% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::5 341631 0.91% 88.88% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::6 1045289 2.79% 91.67% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::7 230176 0.62% 92.29% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::8 2886759 7.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 29854695 81.21% 81.21% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 388351 1.06% 82.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 517738 1.41% 83.67% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 822514 2.24% 85.91% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 639820 1.74% 87.65% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 344469 0.94% 88.59% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1061447 2.89% 91.47% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 231777 0.63% 92.10% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 2902842 7.90% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 37419321 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.054224 # Number of branch fetches per cycle -system.cpu2.fetch.rate 0.368268 # Number of inst fetches per cycle -system.cpu2.decode.IdleCycles 9979534 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 19757337 # Number of cycles decode is blocked -system.cpu2.decode.RunCycles 6196813 # Number of cycles decode is running -system.cpu2.decode.UnblockCycles 326068 # Number of cycles decode is unblocking -system.cpu2.decode.SquashCycles 1158658 # Number of cycles decode is squashing -system.cpu2.decode.BranchResolved 609699 # Number of times decode resolved a branch -system.cpu2.decode.BranchMispred 52950 # Number of times decode detected a branch misprediction -system.cpu2.decode.DecodedInsts 36983425 # Number of instructions handled by decode -system.cpu2.decode.SquashedInsts 178083 # Number of squashed instructions handled by decode -system.cpu2.rename.SquashCycles 1158658 # Number of cycles rename is squashing -system.cpu2.rename.IdleCycles 10528432 # Number of cycles rename is idle -system.cpu2.rename.BlockCycles 6814826 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11435729 # count of cycles rename stalled for serializing inst -system.cpu2.rename.RunCycles 5959486 # Number of cycles rename is running -system.cpu2.rename.UnblockCycles 1521262 # Number of cycles rename is unblocking -system.cpu2.rename.RenamedInsts 34891179 # Number of instructions processed by rename -system.cpu2.rename.ROBFullEvents 96 # Number of times rename has blocked due to ROB full -system.cpu2.rename.IQFullEvents 325442 # Number of times rename has blocked due to IQ full -system.cpu2.rename.LSQFullEvents 887620 # Number of times rename has blocked due to LSQ full -system.cpu2.rename.FullRegisterEvents 163 # Number of times there has been no free registers -system.cpu2.rename.RenamedOperands 37432161 # Number of destination operands rename has renamed -system.cpu2.rename.RenameLookups 161024301 # Number of register rename lookups that rename has made -system.cpu2.rename.int_rename_lookups 148452649 # Number of integer rename lookups -system.cpu2.rename.fp_rename_lookups 3370 # Number of floating rename lookups -system.cpu2.rename.CommittedMaps 26548024 # Number of HB maps that are committed -system.cpu2.rename.UndoneMaps 10884136 # Number of HB maps that are undone due to squashing -system.cpu2.rename.serializingInsts 285664 # count of serializing insts renamed -system.cpu2.rename.tempSerializingInsts 261962 # count of temporary serializing insts renamed -system.cpu2.rename.skidInsts 3325772 # count of insts added to the skid buffer -system.cpu2.memDep0.insertedLoads 6628163 # Number of loads inserted to the mem dependence unit. -system.cpu2.memDep0.insertedStores 3904378 # Number of stores inserted to the mem dependence unit. -system.cpu2.memDep0.conflictingLoads 525369 # Number of conflicting loads. -system.cpu2.memDep0.conflictingStores 781342 # Number of conflicting stores. -system.cpu2.iq.iqInstsAdded 32207136 # Number of instructions added to the IQ (excludes non-spec) -system.cpu2.iq.iqNonSpecInstsAdded 505175 # Number of non-speculative instructions added to the IQ -system.cpu2.iq.iqInstsIssued 34773283 # Number of instructions issued -system.cpu2.iq.iqSquashedInstsIssued 55288 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 7195240 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 19128466 # Number of squashed operands that are examined and possibly removed from graph -system.cpu2.iq.iqSquashedNonSpecRemoved 148705 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 37419321 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 0.929287 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.589860 # Number of insts issued each cycle +system.cpu2.fetch.rateDist::total 36763653 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.054833 # Number of branch fetches per cycle +system.cpu2.fetch.rate 0.370826 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 9873812 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 19124591 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 6319657 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 254865 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 1189808 # Number of cycles decode is squashing +system.cpu2.decode.BranchResolved 613364 # Number of times decode resolved a branch +system.cpu2.decode.BranchMispred 53448 # Number of times decode detected a branch misprediction +system.cpu2.decode.DecodedInsts 37275302 # Number of instructions handled by decode +system.cpu2.decode.SquashedInsts 179889 # Number of squashed instructions handled by decode +system.cpu2.rename.SquashCycles 1189808 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 10379118 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 2802247 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 11780210 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 6098002 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 4513356 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 35160533 # Number of instructions processed by rename +system.cpu2.rename.ROBFullEvents 386 # Number of times rename has blocked due to ROB full +system.cpu2.rename.IQFullEvents 2869122 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LQFullEvents 3154793 # Number of times rename has blocked due to LQ full +system.cpu2.rename.SQFullEvents 689173 # Number of times rename has blocked due to SQ full +system.cpu2.rename.FullRegisterEvents 383 # Number of times there has been no free registers +system.cpu2.rename.RenamedOperands 37744497 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 162187083 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 149521715 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 3412 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 26544575 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 11199921 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 286052 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 262435 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 2598030 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 6687505 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 3927813 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 542106 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 758032 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 32441943 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 511673 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 34839204 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 63540 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 7431415 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 19915523 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 154345 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 36763653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 0.947653 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.617979 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 24716493 66.05% 66.05% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::1 3990546 10.66% 76.72% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::2 2313548 6.18% 82.90% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::3 1974351 5.28% 88.18% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::4 2779950 7.43% 95.61% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::5 967650 2.59% 98.19% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::6 497474 1.33% 99.52% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::7 144778 0.39% 99.91% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::8 34531 0.09% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 24294475 66.08% 66.08% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 3786923 10.30% 76.38% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 2217252 6.03% 82.41% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 1918473 5.22% 87.63% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 2844306 7.74% 95.37% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 967223 2.63% 98.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 535277 1.46% 99.46% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 160435 0.44% 99.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 39289 0.11% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 37419321 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 36763653 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntAlu 19609 1.29% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntMult 1 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.29% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemRead 1392955 91.52% 92.81% # attempts to use FU when none available -system.cpu2.iq.fu_full::MemWrite 109452 7.19% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 19487 1.25% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 1 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.25% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1415927 90.74% 91.99% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 124952 8.01% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu2.iq.FU_type_0::No_OpClass 8340 0.02% 0.02% # Type of FU issued -system.cpu2.iq.FU_type_0::IntAlu 19803061 56.95% 56.97% # Type of FU issued -system.cpu2.iq.FU_type_0::IntMult 28127 0.08% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMisc 3 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdShiftAcc 3 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.05% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMisc 386 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::No_OpClass 8595 0.02% 0.02% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 19842102 56.95% 56.98% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 28105 0.08% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 10 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 10 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 382 0.00% 57.06% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 57.06% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 10 0.00% 57.06% # Type of FU issued system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.06% # Type of FU issued -system.cpu2.iq.FU_type_0::MemRead 11414599 32.83% 89.88% # Type of FU issued -system.cpu2.iq.FU_type_0::MemWrite 3518761 10.12% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 11432468 32.81% 89.87% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 3527522 10.13% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu2.iq.FU_type_0::total 34773283 # Type of FU issued -system.cpu2.iq.rate 0.393736 # Inst issue rate -system.cpu2.iq.fu_busy_cnt 1522017 # FU busy when requested -system.cpu2.iq.fu_busy_rate 0.043770 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 108565265 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 39912731 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 28072202 # Number of integer instruction queue wakeup accesses -system.cpu2.iq.fp_inst_queue_reads 7477 # Number of floating instruction queue reads -system.cpu2.iq.fp_inst_queue_writes 4009 # Number of floating instruction queue writes -system.cpu2.iq.fp_inst_queue_wakeup_accesses 3345 # Number of floating instruction queue wakeup accesses -system.cpu2.iq.int_alu_accesses 36282976 # Number of integer alu accesses -system.cpu2.iq.fp_alu_accesses 3984 # Number of floating point alu accesses -system.cpu2.iew.lsq.thread0.forwLoads 206198 # Number of loads that had data forwarded from stores +system.cpu2.iq.FU_type_0::total 34839204 # Type of FU issued +system.cpu2.iq.rate 0.394298 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 1560367 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.044788 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 108088247 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 40390587 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 28132113 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 7428 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 3949 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 3288 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 36387010 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 3966 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 216264 # Number of loads that had data forwarded from stores system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu2.iew.lsq.thread0.squashedLoads 1536367 # Number of loads squashed -system.cpu2.iew.lsq.thread0.ignoredResponses 2104 # Number of memory responses ignored because the instruction is squashed -system.cpu2.iew.lsq.thread0.memOrderViolation 9509 # Number of memory ordering violations -system.cpu2.iew.lsq.thread0.squashedStores 563915 # Number of stores squashed +system.cpu2.iew.lsq.thread0.squashedLoads 1592400 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 1668 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9845 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 582754 # Number of stores squashed system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu2.iew.lsq.thread0.rescheduledLoads 5287425 # Number of loads that were rescheduled -system.cpu2.iew.lsq.thread0.cacheBlocked 344896 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.lsq.thread0.rescheduledLoads 5289504 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 343573 # Number of times an access to memory failed due to the cache being blocked system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu2.iew.iewSquashCycles 1158658 # Number of cycles IEW is squashing -system.cpu2.iew.iewBlockCycles 5187034 # Number of cycles IEW is blocking -system.cpu2.iew.iewUnblockCycles 87972 # Number of cycles IEW is unblocking -system.cpu2.iew.iewDispatchedInsts 32794480 # Number of instructions dispatched to IQ -system.cpu2.iew.iewDispSquashedInsts 61964 # Number of squashed instructions skipped by dispatch -system.cpu2.iew.iewDispLoadInsts 6628163 # Number of dispatched load instructions -system.cpu2.iew.iewDispStoreInsts 3904378 # Number of dispatched store instructions -system.cpu2.iew.iewDispNonSpecInsts 362952 # Number of dispatched non-speculative instructions -system.cpu2.iew.iewIQFullEvents 29501 # Number of times the IQ has become full, causing a stall -system.cpu2.iew.iewLSQFullEvents 2651 # Number of times the LSQ has become full, causing a stall -system.cpu2.iew.memOrderViolationEvents 9509 # Number of memory order violations -system.cpu2.iew.predictedTakenIncorrect 107755 # Number of branches that were predicted taken incorrectly -system.cpu2.iew.predictedNotTakenIncorrect 89629 # Number of branches that were predicted not taken incorrectly -system.cpu2.iew.branchMispredicts 197384 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 33857007 # Number of executed instructions -system.cpu2.iew.iewExecLoadInsts 11143266 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 916276 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewSquashCycles 1189808 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 2192287 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 292580 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 33037931 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 55534 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 6687505 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 3927813 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 368987 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 60475 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 207427 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9845 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 107337 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 89487 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 196824 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 33922204 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 11159492 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 917000 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed -system.cpu2.iew.exec_nop 82169 # number of nop insts executed -system.cpu2.iew.exec_refs 14628489 # number of memory reference insts executed -system.cpu2.iew.exec_branches 3765120 # Number of branches executed -system.cpu2.iew.exec_stores 3485223 # Number of stores executed -system.cpu2.iew.exec_rate 0.383361 # Inst execution rate -system.cpu2.iew.wb_sent 33455826 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 28075547 # cumulative count of insts written-back -system.cpu2.iew.wb_producers 16112995 # num instructions producing a value -system.cpu2.iew.wb_consumers 29113416 # num instructions consuming a value +system.cpu2.iew.exec_nop 84315 # number of nop insts executed +system.cpu2.iew.exec_refs 14652861 # number of memory reference insts executed +system.cpu2.iew.exec_branches 3774133 # Number of branches executed +system.cpu2.iew.exec_stores 3493369 # Number of stores executed +system.cpu2.iew.exec_rate 0.383919 # Inst execution rate +system.cpu2.iew.wb_sent 33519345 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 28135401 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 16326972 # num instructions producing a value +system.cpu2.iew.wb_consumers 29693548 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 0.317898 # insts written-back per cycle -system.cpu2.iew.wb_fanout 0.553456 # average fanout of values written-back +system.cpu2.iew.wb_rate 0.318426 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.549849 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu2.commit.commitSquashedInsts 7147493 # The number of squashed insts skipped by commit -system.cpu2.commit.commitNonSpecStalls 356470 # The number of times commit has been forced to stall to communicate backwards -system.cpu2.commit.branchMispredicts 171471 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 36260461 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 0.700277 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.736744 # Number of insts commited each cycle +system.cpu2.commit.commitSquashedInsts 7376982 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 357328 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 170683 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 35573653 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 0.713892 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.756913 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 27338017 75.39% 75.39% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::1 4438533 12.24% 87.63% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::2 1258858 3.47% 91.11% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::3 640995 1.77% 92.87% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::4 514559 1.42% 94.29% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::5 318215 0.88% 95.17% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::6 418287 1.15% 96.32% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::7 309870 0.85% 97.18% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::8 1023127 2.82% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 26733174 75.15% 75.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 4358118 12.25% 87.40% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 1232607 3.46% 90.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 662996 1.86% 92.73% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 505200 1.42% 94.15% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 312825 0.88% 95.03% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 424269 1.19% 96.22% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 302810 0.85% 97.07% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 1041654 2.93% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 36260461 # Number of insts commited each cycle -system.cpu2.commit.committedInsts 20554943 # Number of instructions committed -system.cpu2.commit.committedOps 25392373 # Number of ops (including micro ops) committed +system.cpu2.commit.committed_per_cycle::total 35573653 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 20550287 # Number of instructions committed +system.cpu2.commit.committedOps 25395761 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu2.commit.refs 8432259 # Number of memory references committed -system.cpu2.commit.loads 5091796 # Number of loads committed -system.cpu2.commit.membars 94283 # Number of memory barriers committed -system.cpu2.commit.branches 3240263 # Number of branches committed -system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions. -system.cpu2.commit.int_insts 22648524 # Number of committed integer instructions. -system.cpu2.commit.function_calls 295510 # Number of function calls committed. +system.cpu2.commit.refs 8440164 # Number of memory references committed +system.cpu2.commit.loads 5095105 # Number of loads committed +system.cpu2.commit.membars 94591 # Number of memory barriers committed +system.cpu2.commit.branches 3237542 # Number of branches committed +system.cpu2.commit.fp_insts 3235 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 22655353 # Number of committed integer instructions. +system.cpu2.commit.function_calls 295831 # Number of function calls committed. system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu2.commit.op_class_0::IntAlu 16933133 66.69% 66.69% # Class of committed instruction -system.cpu2.commit.op_class_0::IntMult 26595 0.10% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMisc 386 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.79% # Class of committed instruction -system.cpu2.commit.op_class_0::MemRead 5091796 20.05% 86.84% # Class of committed instruction -system.cpu2.commit.op_class_0::MemWrite 3340463 13.16% 100.00% # Class of committed instruction +system.cpu2.commit.op_class_0::IntAlu 16928638 66.66% 66.66% # Class of committed instruction +system.cpu2.commit.op_class_0::IntMult 26577 0.10% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.76% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMisc 382 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.77% # Class of committed instruction +system.cpu2.commit.op_class_0::MemRead 5095105 20.06% 86.83% # Class of committed instruction +system.cpu2.commit.op_class_0::MemWrite 3345059 13.17% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu2.commit.op_class_0::total 25392373 # Class of committed instruction -system.cpu2.commit.bw_lim_events 1023127 # number cycles where commit BW limit reached +system.cpu2.commit.op_class_0::total 25395761 # Class of committed instruction +system.cpu2.commit.bw_lim_events 1041654 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 67255841 # The number of ROB reads -system.cpu2.rob.rob_writes 66282532 # The number of ROB writes -system.cpu2.timesIdled 358696 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 50897008 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 3546076715 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu2.committedInsts 20499567 # Number of Instructions Simulated -system.cpu2.committedOps 25336997 # Number of Ops (including micro ops) Simulated -system.cpu2.cpi 4.308205 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 4.308205 # CPI: Total CPI of All Threads -system.cpu2.ipc 0.232115 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 0.232115 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 157113831 # number of integer regfile reads -system.cpu2.int_regfile_writes 29893796 # number of integer regfile writes -system.cpu2.fp_regfile_reads 46822 # number of floating regfile reads -system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes -system.cpu2.misc_regfile_reads 67223937 # number of misc regfile reads -system.cpu2.misc_regfile_writes 297064 # number of misc regfile writes +system.cpu2.rob.rob_reads 66778885 # The number of ROB reads +system.cpu2.rob.rob_writes 66779605 # The number of ROB writes +system.cpu2.timesIdled 362907 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 51593991 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 3545947336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 20495032 # Number of Instructions Simulated +system.cpu2.committedOps 25340506 # Number of Ops (including micro ops) Simulated +system.cpu2.cpi 4.311174 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 4.311174 # CPI: Total CPI of All Threads +system.cpu2.ipc 0.231955 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 0.231955 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 157422880 # number of integer regfile reads +system.cpu2.int_regfile_writes 29963931 # number of integer regfile writes +system.cpu2.fp_regfile_reads 46839 # number of floating regfile reads +system.cpu2.fp_regfile_writes 45210 # number of floating regfile writes +system.cpu2.misc_regfile_reads 66597785 # number of misc regfile reads +system.cpu2.misc_regfile_writes 297300 # number of misc regfile writes system.iocache.tags.replacements 0 # number of replacements system.iocache.tags.tagsinuse 0 # Cycle average of tags in use system.iocache.tags.total_refs 0 # Total number of references to valid blocks. @@ -2033,10 +2035,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1535534030000 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1535534030000 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1535534030000 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1536043103750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1536043103750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1536043103750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal Binary files differindex aaf6d88fc..f40477dbc 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal |