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author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-09-16 09:14:31 +0100 |
commit | ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5 (patch) | |
tree | 82c5b4db42b6ade0e4eeed758be629c57e2f5f60 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr | |
parent | 1ecc3628a8fe24d8ed189ee23ca41f2b385b3d8e (diff) | |
download | gem5-ada0e2f02fb3a30d01f62eb124a1d374be0b8ed5.tar.xz |
tests, arm: Make switcheroo and checkpoint tests functional
Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion. Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.
Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr')
-rwxr-xr-x | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr | 66 |
1 files changed, 0 insertions, 66 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr deleted file mode 100755 index 652b4376c..000000000 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr +++ /dev/null @@ -1,66 +0,0 @@ -warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) -warn: Sockets disabled, not accepting vnc client connections -warn: Sockets disabled, not accepting terminal connections -warn: Sockets disabled, not accepting gdb connections -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: ClockedObject: More than one power state change request encountered within the same simulation tick -warn: Existing EnergyCtrl, but no enabled DVFSHandler found. -warn: Not doing anything for miscreg ACTLR -warn: Not doing anything for write of miscreg ACTLR -warn: The clidr register always reports 0 caches. -warn: clidr LoUIS field of 0b001 to match current ARM implementations. -warn: The csselr register isn't implemented. -warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] -warn: CP14 unimplemented crn[0], opc1[6], crm[0], opc2[0] -warn: instruction 'mcr dccmvau' unimplemented -warn: instruction 'mcr icimvau' unimplemented -warn: instruction 'mcr bpiallis' unimplemented -warn: instruction 'mcr icialluis' unimplemented -warn: instruction 'mcr dccimvac' unimplemented -warn: Tried to read RealView I/O at offset 0x60 that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[4] -warn: CP14 unimplemented crn[1], opc1[4], crm[12], opc2[0] -warn: CP14 unimplemented crn[1], opc1[0], crm[1], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] -warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] -warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] -warn: CP14 unimplemented crn[1], opc1[0], crm[5], opc2[4] -warn: CP14 unimplemented crn[5], opc1[4], crm[0], opc2[0] -warn: CP14 unimplemented crn[0], opc1[4], crm[8], opc2[1] -warn: Returning zero for read from miscreg pmcr -warn: Ignoring write to miscreg pmcntenclr -warn: Ignoring write to miscreg pmintenclr -warn: Ignoring write to miscreg pmovsr -warn: Ignoring write to miscreg pmcr -warn: CP14 unimplemented crn[5], opc1[4], crm[8], opc2[2] -warn: CP14 unimplemented crn[0], opc1[4], crm[12], opc2[2] -warn: CP14 unimplemented crn[5], opc1[4], crm[4], opc2[5] -warn: CP14 unimplemented crn[15], opc1[0], crm[8], opc2[0] -warn: CP14 unimplemented crn[3], opc1[4], crm[0], opc2[3] -warn: CP14 unimplemented crn[3], opc1[4], crm[4], opc2[3] -warn: CP14 unimplemented crn[5], opc1[4], crm[12], opc2[0] -warn: instruction 'mcr dcisw' unimplemented -warn: CP14 unimplemented crn[14], opc1[7], crm[1], opc2[0] -warn: CP14 unimplemented crn[14], opc1[7], crm[14], opc2[7] -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: instruction 'mcr bpiall' unimplemented -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR -warn: User mode does not have SPSR |