diff options
author | Andreas Hansson <andreas.hansson@arm.com> | 2013-04-19 09:04:42 -0400 |
---|---|---|
committer | Andreas Hansson <andreas.hansson@arm.com> | 2013-04-19 09:04:42 -0400 |
commit | 5dd23833fdeb0f7b152c972f47ff81d5595c6fea (patch) | |
tree | 70eb9519c91bba922d22723e7e3ba85b65dd7c81 /tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | |
parent | 3d858e5627b539713abb59c14363fb6af180e026 (diff) | |
download | gem5-5dd23833fdeb0f7b152c972f47ff81d5595c6fea.tar.xz |
stats: Update stats for ldr_ret_uop (changeset 35198406dd72)
This patch merely bumps the stats to match the changes introduced in
changeset 35198406dd72.
Diffstat (limited to 'tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt')
-rw-r--r-- | tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt | 2662 |
1 files changed, 1331 insertions, 1331 deletions
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt index eb64a2a8c..83e83b33f 100644 --- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt +++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/stats.txt @@ -1,145 +1,145 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.543226 # Number of seconds simulated -sim_ticks 2543226083000 # Number of ticks simulated -final_tick 2543226083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.543301 # Number of seconds simulated +sim_ticks 2543301032500 # Number of ticks simulated +final_tick 2543301032500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48764 # Simulator instruction rate (inst/s) -host_op_rate 62745 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 2056325427 # Simulator tick rate (ticks/s) -host_mem_usage 443444 # Number of bytes of host memory used -host_seconds 1236.78 # Real time elapsed on the host -sim_insts 60309820 # Number of instructions simulated -sim_ops 77602107 # Number of ops (including micro ops) simulated +host_inst_rate 74756 # Simulator instruction rate (inst/s) +host_op_rate 96190 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3152487696 # Simulator tick rate (ticks/s) +host_mem_usage 404224 # Number of bytes of host memory used +host_seconds 806.76 # Real time elapsed on the host +sim_insts 60309843 # Number of instructions simulated +sim_ops 77602131 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.dtb.walker 2112 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 2048 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 511168 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4147472 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.dtb.walker 1216 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 290304 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4947228 # Number of bytes read from this memory -system.physmem.bytes_read::total 131010156 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 511168 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 290304 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 801472 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3787712 # Number of bytes written to this memory +system.physmem.bytes_read::cpu0.inst 508544 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4232464 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 1280 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 292032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4862300 # Number of bytes read from this memory +system.physmem.bytes_read::total 131009324 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 508544 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 292032 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 800576 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3788480 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 1346148 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 1669964 # Number of bytes written to this memory -system.physmem.bytes_written::total 6803824 # Number of bytes written to this memory +system.physmem.bytes_written::total 6804592 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15138816 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.dtb.walker 33 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 32 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 7987 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 64838 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.dtb.walker 19 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 4536 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 77307 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15293538 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 59183 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu0.inst 7946 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 66166 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 20 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 4563 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 75980 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15293525 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 59195 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 336537 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 417491 # Number of write requests responded to by this memory -system.physmem.num_writes::total 813211 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47620826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.dtb.walker 830 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 813223 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47619423 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.dtb.walker 805 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 50 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 200992 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 1630792 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 478 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 114148 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 1945257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51513374 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 200992 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 114148 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 315140 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1489334 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 529307 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 656632 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2675273 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1489334 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47620826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.dtb.walker 830 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 199954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 1664162 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 503 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 114824 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 1911807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51511529 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 199954 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 114824 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 314778 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1489592 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 529292 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 656613 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2675496 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1489592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47619423 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.dtb.walker 805 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 50 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 200992 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 2160099 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 478 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 114148 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 2601889 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54188647 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15293538 # Total number of read requests seen -system.physmem.writeReqs 813211 # Total number of write requests seen -system.physmem.cpureqs 218552 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 978786432 # Total number of bytes read from memory -system.physmem.bytesWritten 52045504 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 131010156 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6803824 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu0.inst 199954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 2193453 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 503 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 114824 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 2568420 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54187025 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15293525 # Total number of read requests seen +system.physmem.writeReqs 813223 # Total number of write requests seen +system.physmem.cpureqs 218526 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 978785600 # Total number of bytes read from memory +system.physmem.bytesWritten 52046272 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 131009324 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6804592 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 11 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 4690 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 956233 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 4665 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 956243 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 955738 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 955679 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 956493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 956273 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 955443 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 955569 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 956157 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 956101 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 955609 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 955527 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 955677 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 956490 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 956276 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 955444 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 955565 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 956160 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 956100 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 955611 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 955526 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 955934 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 956035 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 955435 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 955318 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 955983 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50828 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50414 # Track writes on a per bank basis -system.physmem.perBankWrReqs::2 50437 # Track writes on a per bank basis +system.physmem.perBankRdReqs::12 956026 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 955429 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 955315 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 955980 # Track reads on a per bank basis +system.physmem.perBankWrReqs::0 50841 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50418 # Track writes on a per bank basis +system.physmem.perBankWrReqs::2 50434 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 51162 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50915 # Track writes on a per bank basis -system.physmem.perBankWrReqs::5 50189 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 50286 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 50860 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51367 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 50905 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 50807 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51194 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51255 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 50732 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 50629 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51231 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50916 # Track writes on a per bank basis +system.physmem.perBankWrReqs::5 50190 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 50284 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 50863 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51375 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 50908 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 50806 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51196 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51248 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 50726 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 50627 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51229 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry -system.physmem.numWrRetry 32473 # Number of times wr buffer was full causing retry -system.physmem.totGap 2543224928500 # Total gap between requests +system.physmem.numWrRetry 32474 # Number of times wr buffer was full causing retry +system.physmem.totGap 2543299855000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 43 # Categorize read packet sizes system.physmem.readPktSize::3 15138816 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 154679 # Categorize read packet sizes +system.physmem.readPktSize::6 154666 # Categorize read packet sizes system.physmem.writePktSize::0 0 # Categorize write packet sizes system.physmem.writePktSize::1 0 # Categorize write packet sizes system.physmem.writePktSize::2 754028 # Categorize write packet sizes system.physmem.writePktSize::3 0 # Categorize write packet sizes system.physmem.writePktSize::4 0 # Categorize write packet sizes system.physmem.writePktSize::5 0 # Categorize write packet sizes -system.physmem.writePktSize::6 59183 # Categorize write packet sizes -system.physmem.rdQLenPdf::0 1054814 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 991597 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 961229 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3605153 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 2718410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2722334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 2700441 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 59924 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 59389 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 109988 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 160459 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 109884 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 10035 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 9981 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 10663 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 9196 # What read queue length does an incoming req see +system.physmem.writePktSize::6 59195 # Categorize write packet sizes +system.physmem.rdQLenPdf::0 1054830 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 991608 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 961225 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 3605146 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2718488 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2722266 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2700528 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 59953 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 59337 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 109948 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 160370 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 109866 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 10050 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 9990 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 10676 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 9203 # What read queue length does an incoming req see system.physmem.rdQLenPdf::16 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 7 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 3 # What read queue length does an incoming req see @@ -156,59 +156,59 @@ system.physmem.rdQLenPdf::28 0 # Wh system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 2747 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 2854 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 2886 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 2942 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 2939 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 2938 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 2931 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 2921 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 2912 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35378 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35362 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35351 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35338 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35329 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35313 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35297 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35285 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35261 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35250 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 2755 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 2858 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 2891 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 2947 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 2942 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 2932 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 2925 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 2915 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 2908 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35379 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35360 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35349 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35339 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35328 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35316 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35305 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35290 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35275 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35262 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35249 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35236 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35229 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35223 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35231 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35222 # What write queue length does an incoming req see system.physmem.wrQLenPdf::23 32763 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 32640 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 32599 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 32639 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 32598 # What write queue length does an incoming req see system.physmem.wrQLenPdf::26 32527 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 32514 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 32504 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 32495 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 32489 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::31 32479 # What write queue length does an incoming req see -system.physmem.totQLat 346835420750 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 440002912000 # Sum of mem lat for all requests -system.physmem.totBusLat 76467635000 # Total cycles spent in databus access -system.physmem.totBankLat 16699856250 # Total cycles spent in bank access -system.physmem.avgQLat 22678.58 # Average queueing delay per request -system.physmem.avgBankLat 1091.96 # Average bank access latency per request +system.physmem.wrQLenPdf::31 32480 # What write queue length does an incoming req see +system.physmem.totQLat 346872048750 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 440039818750 # Sum of mem lat for all requests +system.physmem.totBusLat 76467570000 # Total cycles spent in databus access +system.physmem.totBankLat 16700200000 # Total cycles spent in bank access +system.physmem.avgQLat 22680.99 # Average queueing delay per request +system.physmem.avgBankLat 1091.98 # Average bank access latency per request system.physmem.avgBusLat 5000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28770.53 # Average memory access latency -system.physmem.avgRdBW 384.86 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 28772.97 # Average memory access latency +system.physmem.avgRdBW 384.85 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 20.46 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 51.51 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.68 # Average consumed write bandwidth in MB/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 3.17 # Data bus utilization in percentage system.physmem.avgRdQLen 0.17 # Average read queue length over time -system.physmem.avgWrQLen 1.12 # Average write queue length over time -system.physmem.readRowHits 15218407 # Number of row buffer hits during reads -system.physmem.writeRowHits 794595 # Number of row buffer hits during writes +system.physmem.avgWrQLen 1.13 # Average write queue length over time +system.physmem.readRowHits 15218379 # Number of row buffer hits during reads +system.physmem.writeRowHits 794608 # Number of row buffer hits during writes system.physmem.readRowHitRate 99.51 # Row buffer hit rate for reads system.physmem.writeRowHitRate 97.71 # Row buffer hit rate for writes -system.physmem.avgGap 157898.09 # Average gap between requests +system.physmem.avgGap 157902.75 # Average gap between requests system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 64 # 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average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 44923.505625 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 45270.066766 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 45932.968947 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 44667.486130 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 46182.170647 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 44780.273841 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10001 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10002.168355 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001.514237 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39391.340751 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37310.197052 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 38243.781232 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 39776.667972 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 37204.758462 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 38383.571238 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40272.034142 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71341.878788 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 37743.478047 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 39328.980007 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 71782.218750 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 46625.500000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42770.439629 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 39899.423301 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 42869.239044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40272.034142 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 56251 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 46088.732584 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37818.828816 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 39193.233044 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 45753.236467 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 37743.478047 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 39328.980007 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency @@ -622,680 +622,680 @@ system.cf0.dma_read_txs 0 # Nu system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes. system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes. system.cf0.dma_write_txs 0 # Number of DMA write transactions. -system.cpu0.branchPred.lookups 7719049 # Number of BP lookups -system.cpu0.branchPred.condPredicted 6144205 # Number of conditional branches predicted -system.cpu0.branchPred.condIncorrect 388400 # Number of conditional branches incorrect -system.cpu0.branchPred.BTBLookups 5016002 # Number of BTB lookups -system.cpu0.branchPred.BTBHits 4082948 # Number of BTB hits +system.cpu0.branchPred.lookups 7635591 # Number of BP lookups +system.cpu0.branchPred.condPredicted 6085397 # Number of conditional branches predicted +system.cpu0.branchPred.condIncorrect 382495 # Number of conditional branches incorrect +system.cpu0.branchPred.BTBLookups 4962348 # Number of BTB lookups +system.cpu0.branchPred.BTBHits 4056906 # Number of BTB hits system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu0.branchPred.BTBHitPct 81.398452 # BTB Hit Percentage -system.cpu0.branchPred.usedRAS 737953 # Number of times the RAS was used to get a target. -system.cpu0.branchPred.RASInCorrect 39729 # Number of incorrect RAS predictions. +system.cpu0.branchPred.BTBHitPct 81.753759 # BTB Hit Percentage +system.cpu0.branchPred.usedRAS 731596 # Number of times the RAS was used to get a target. +system.cpu0.branchPred.RASInCorrect 39324 # Number of incorrect RAS predictions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 26145640 # DTB read hits -system.cpu0.dtb.read_misses 41213 # DTB read misses -system.cpu0.dtb.write_hits 5906110 # DTB write hits -system.cpu0.dtb.write_misses 9202 # DTB write misses +system.cpu0.dtb.read_hits 26057064 # DTB read hits +system.cpu0.dtb.read_misses 40223 # DTB read misses +system.cpu0.dtb.write_hits 5918699 # DTB write hits +system.cpu0.dtb.write_misses 9531 # DTB write misses system.cpu0.dtb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.dtb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.dtb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 5753 # Number of entries that have been flushed from TLB -system.cpu0.dtb.align_faults 1471 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 281 # Number of TLB faults due to prefetch +system.cpu0.dtb.flush_entries 5688 # Number of entries that have been flushed from TLB +system.cpu0.dtb.align_faults 1419 # Number of TLB faults due to alignment restrictions +system.cpu0.dtb.prefetch_faults 294 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 691 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 26186853 # DTB read accesses -system.cpu0.dtb.write_accesses 5915312 # DTB write accesses +system.cpu0.dtb.perms_faults 673 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 26097287 # DTB read accesses +system.cpu0.dtb.write_accesses 5928230 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 32051750 # DTB hits -system.cpu0.dtb.misses 50415 # DTB misses -system.cpu0.dtb.accesses 32102165 # DTB accesses -system.cpu0.itb.inst_hits 6183534 # ITB inst hits -system.cpu0.itb.inst_misses 7751 # ITB inst misses +system.cpu0.dtb.hits 31975763 # DTB hits +system.cpu0.dtb.misses 49754 # DTB misses +system.cpu0.dtb.accesses 32025517 # DTB accesses +system.cpu0.itb.inst_hits 6123062 # ITB inst hits +system.cpu0.itb.inst_misses 7629 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits system.cpu0.itb.write_misses 0 # DTB write misses system.cpu0.itb.flush_tlb 257 # Number of times complete TLB was flushed system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu0.itb.flush_tlb_mva_asid 775 # Number of times TLB was flushed by MVA & ASID +system.cpu0.itb.flush_tlb_mva_asid 769 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 33 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 2745 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 2663 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.itb.perms_faults 1565 # Number of TLB faults due to permissions restrictions +system.cpu0.itb.perms_faults 1589 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 6191285 # ITB inst accesses -system.cpu0.itb.hits 6183534 # DTB hits -system.cpu0.itb.misses 7751 # DTB misses -system.cpu0.itb.accesses 6191285 # DTB accesses -system.cpu0.numCycles 239079415 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 6130691 # ITB inst accesses +system.cpu0.itb.hits 6123062 # DTB hits +system.cpu0.itb.misses 7629 # DTB misses +system.cpu0.itb.accesses 6130691 # DTB accesses +system.cpu0.numCycles 239038664 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.fetch.icacheStallCycles 15644570 # Number of cycles fetch is stalled on an Icache miss -system.cpu0.fetch.Insts 48338125 # Number of instructions fetch has processed -system.cpu0.fetch.Branches 7719049 # Number of branches that fetch encountered -system.cpu0.fetch.predictedBranches 4820901 # Number of branches that fetch has predicted taken -system.cpu0.fetch.Cycles 10703205 # Number of cycles fetch has run and was not squashing or blocked -system.cpu0.fetch.SquashCycles 2596540 # Number of cycles fetch has spent squashing -system.cpu0.fetch.TlbCycles 94746 # Number of cycles fetch has spent waiting for tlb -system.cpu0.fetch.BlockedCycles 49591987 # Number of cycles fetch has spent blocked -system.cpu0.fetch.MiscStallCycles 1783 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu0.fetch.PendingDrainCycles 1964 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu0.fetch.PendingTrapStallCycles 53331 # Number of stall cycles due to pending traps -system.cpu0.fetch.PendingQuiesceStallCycles 101492 # Number of stall cycles due to pending quiesce instructions -system.cpu0.fetch.IcacheWaitRetryStallCycles 276 # Number of stall cycles due to full MSHR -system.cpu0.fetch.CacheLines 6181495 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 400642 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.ItlbSquashes 3259 # Number of outstanding ITLB misses that were squashed -system.cpu0.fetch.rateDist::samples 77992242 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 0.765373 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.123716 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.icacheStallCycles 15574951 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 47914738 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 7635591 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 4788502 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 10629711 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2569699 # Number of cycles fetch has spent squashing +system.cpu0.fetch.TlbCycles 94247 # Number of cycles fetch has spent waiting for tlb +system.cpu0.fetch.BlockedCycles 49519281 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 1748 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingDrainCycles 2018 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu0.fetch.PendingTrapStallCycles 51773 # Number of stall cycles due to pending traps +system.cpu0.fetch.PendingQuiesceStallCycles 101169 # Number of stall cycles due to pending quiesce instructions +system.cpu0.fetch.IcacheWaitRetryStallCycles 218 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 6121027 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 398928 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.ItlbSquashes 3254 # Number of outstanding ITLB misses that were squashed +system.cpu0.fetch.rateDist::samples 77753565 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 0.762466 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.119834 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 67296980 86.29% 86.29% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 702662 0.90% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::2 892389 1.14% 88.33% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 1243235 1.59% 89.93% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::4 1139067 1.46% 91.39% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 581520 0.75% 92.13% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 1338462 1.72% 93.85% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::7 402047 0.52% 94.36% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::8 4395880 5.64% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 67131545 86.34% 86.34% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 691431 0.89% 87.23% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 886662 1.14% 88.37% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 1230744 1.58% 89.95% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 1150970 1.48% 91.43% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 576090 0.74% 92.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1323248 1.70% 93.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 399344 0.51% 94.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 4363531 5.61% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 77992242 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.032287 # Number of branch fetches per cycle -system.cpu0.fetch.rate 0.202184 # Number of inst fetches per cycle -system.cpu0.decode.IdleCycles 16701716 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 49328258 # Number of cycles decode is blocked -system.cpu0.decode.RunCycles 9693840 # Number of cycles decode is running -system.cpu0.decode.UnblockCycles 556609 # Number of cycles decode is unblocking -system.cpu0.decode.SquashCycles 1709696 # Number of cycles decode is squashing -system.cpu0.decode.BranchResolved 1049154 # Number of times decode resolved a branch -system.cpu0.decode.BranchMispred 91765 # Number of times decode detected a branch misprediction -system.cpu0.decode.DecodedInsts 56812427 # Number of instructions handled by decode -system.cpu0.decode.SquashedInsts 306906 # Number of squashed instructions handled by decode -system.cpu0.rename.SquashCycles 1709696 # Number of cycles rename is squashing -system.cpu0.rename.IdleCycles 17642458 # Number of cycles rename is idle -system.cpu0.rename.BlockCycles 18978880 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 27077809 # count of cycles rename stalled for serializing inst -system.cpu0.rename.RunCycles 9239108 # Number of cycles rename is running -system.cpu0.rename.UnblockCycles 3342271 # Number of cycles rename is unblocking -system.cpu0.rename.RenamedInsts 53967560 # Number of instructions processed by rename -system.cpu0.rename.ROBFullEvents 13437 # Number of times rename has blocked due to ROB full -system.cpu0.rename.IQFullEvents 629408 # Number of times rename has blocked due to IQ full -system.cpu0.rename.LSQFullEvents 2165949 # Number of times rename has blocked due to LSQ full -system.cpu0.rename.FullRegisterEvents 513 # Number of times there has been no free registers -system.cpu0.rename.RenamedOperands 56184131 # Number of destination operands rename has renamed -system.cpu0.rename.RenameLookups 245540949 # Number of register rename lookups that rename has made -system.cpu0.rename.int_rename_lookups 245492809 # Number of integer rename lookups -system.cpu0.rename.fp_rename_lookups 48140 # Number of floating rename lookups -system.cpu0.rename.CommittedMaps 40778039 # Number of HB maps that are committed -system.cpu0.rename.UndoneMaps 15406092 # Number of HB maps that are undone due to squashing -system.cpu0.rename.serializingInsts 434005 # count of serializing insts renamed -system.cpu0.rename.tempSerializingInsts 385260 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 6805574 # count of insts added to the skid buffer -system.cpu0.memDep0.insertedLoads 10494917 # Number of loads inserted to the mem dependence unit. -system.cpu0.memDep0.insertedStores 6795022 # Number of stores inserted to the mem dependence unit. -system.cpu0.memDep0.conflictingLoads 1080492 # Number of conflicting loads. -system.cpu0.memDep0.conflictingStores 1313371 # Number of conflicting stores. -system.cpu0.iq.iqInstsAdded 50078322 # Number of instructions added to the IQ (excludes non-spec) -system.cpu0.iq.iqNonSpecInstsAdded 1031134 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 63522685 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 99823 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10628436 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 26923896 # Number of squashed operands that are examined and possibly removed from graph -system.cpu0.iq.iqSquashedNonSpecRemoved 250828 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 77992242 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 0.814474 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.519995 # Number of insts issued each cycle +system.cpu0.fetch.rateDist::total 77753565 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.031943 # Number of branch fetches per cycle +system.cpu0.fetch.rate 0.200448 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 16625563 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 49255605 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 9626158 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 554470 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 1689651 # Number of cycles decode is squashing +system.cpu0.decode.BranchResolved 1030343 # Number of times decode resolved a branch +system.cpu0.decode.BranchMispred 91400 # Number of times decode detected a branch misprediction +system.cpu0.decode.DecodedInsts 56424531 # Number of instructions handled by decode +system.cpu0.decode.SquashedInsts 305535 # Number of squashed instructions handled by decode +system.cpu0.rename.SquashCycles 1689651 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 17561755 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 18982691 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 27011773 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 9171817 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 3333839 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 53601005 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 13486 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 625862 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 2162558 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 496 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 55732914 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 244003598 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 243955563 # Number of integer rename lookups +system.cpu0.rename.fp_rename_lookups 48035 # Number of floating rename lookups +system.cpu0.rename.CommittedMaps 40460066 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 15272848 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 429896 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 381627 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 6785358 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 10376846 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 6807542 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 1061382 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1293746 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 49728955 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 1043658 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 63251434 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 97401 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10543512 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 26574090 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 266492 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 77753565 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 0.813486 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.519509 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 55011307 70.53% 70.53% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 7277871 9.33% 79.87% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 3728534 4.78% 84.65% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 3132981 4.02% 88.66% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 6315907 8.10% 96.76% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 1400012 1.80% 98.56% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::6 822343 1.05% 99.61% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::7 235239 0.30% 99.91% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::8 68048 0.09% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 54887435 70.59% 70.59% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 7226514 9.29% 79.89% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 3706413 4.77% 84.65% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 3121683 4.01% 88.67% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 6295236 8.10% 96.76% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 1399247 1.80% 98.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 816831 1.05% 99.61% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 232768 0.30% 99.91% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 67438 0.09% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 77992242 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 77753565 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntAlu 33040 0.74% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntMult 3 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.74% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemRead 4225834 94.61% 95.35% # attempts to use FU when none available -system.cpu0.iq.fu_full::MemWrite 207543 4.65% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 32377 0.72% 0.72% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 4 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 0.73% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 4226171 94.63% 95.36% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 207252 4.64% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu0.iq.FU_type_0::No_OpClass 193689 0.30% 0.30% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 30176884 47.51% 47.81% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 47977 0.08% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 8 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 1 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 5 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 1219 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 5 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.89% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 26869653 42.30% 90.19% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 6233244 9.81% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::No_OpClass 195848 0.31% 0.31% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 29986404 47.41% 47.72% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 47518 0.08% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 4 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 3 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 2 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 1215 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 2 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.79% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 26774233 42.33% 90.12% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 6246205 9.88% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 63522685 # Type of FU issued -system.cpu0.iq.rate 0.265697 # Inst issue rate -system.cpu0.iq.fu_busy_cnt 4466420 # FU busy when requested -system.cpu0.iq.fu_busy_rate 0.070312 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 209641938 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 61746831 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 44505201 # Number of integer instruction queue wakeup accesses -system.cpu0.iq.fp_inst_queue_reads 12130 # Number of floating instruction queue reads -system.cpu0.iq.fp_inst_queue_writes 6615 # Number of floating instruction queue writes -system.cpu0.iq.fp_inst_queue_wakeup_accesses 5501 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 67789033 # Number of integer alu accesses -system.cpu0.iq.fp_alu_accesses 6383 # Number of floating point alu accesses -system.cpu0.iew.lsq.thread0.forwLoads 329345 # Number of loads that had data forwarded from stores +system.cpu0.iq.FU_type_0::total 63251434 # Type of FU issued +system.cpu0.iq.rate 0.264608 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 4465804 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.070604 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 208856960 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 61325058 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 44235430 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 12232 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 6621 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 5553 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 67514929 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 6461 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 324203 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu0.iew.lsq.thread0.squashedLoads 2321629 # Number of loads squashed -system.cpu0.iew.lsq.thread0.ignoredResponses 3668 # Number of memory responses ignored because the instruction is squashed -system.cpu0.iew.lsq.thread0.memOrderViolation 16120 # Number of memory ordering violations -system.cpu0.iew.lsq.thread0.squashedStores 899548 # Number of stores squashed +system.cpu0.iew.lsq.thread0.squashedLoads 2284618 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 3570 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 16131 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 894521 # Number of stores squashed system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu0.iew.lsq.thread0.rescheduledLoads 17127140 # Number of loads that were rescheduled -system.cpu0.iew.lsq.thread0.cacheBlocked 367757 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.lsq.thread0.rescheduledLoads 17140357 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 367566 # Number of times an access to memory failed due to the cache being blocked system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu0.iew.iewSquashCycles 1709696 # Number of cycles IEW is squashing -system.cpu0.iew.iewBlockCycles 14213295 # Number of cycles IEW is blocking -system.cpu0.iew.iewUnblockCycles 236264 # Number of cycles IEW is unblocking -system.cpu0.iew.iewDispatchedInsts 51235944 # Number of instructions dispatched to IQ -system.cpu0.iew.iewDispSquashedInsts 105063 # Number of squashed instructions skipped by dispatch -system.cpu0.iew.iewDispLoadInsts 10494917 # Number of dispatched load instructions -system.cpu0.iew.iewDispStoreInsts 6795022 # Number of dispatched store instructions -system.cpu0.iew.iewDispNonSpecInsts 726682 # Number of dispatched non-speculative instructions -system.cpu0.iew.iewIQFullEvents 58301 # Number of times the IQ has become full, causing a stall -system.cpu0.iew.iewLSQFullEvents 3691 # Number of times the LSQ has become full, causing a stall -system.cpu0.iew.memOrderViolationEvents 16120 # Number of memory order violations -system.cpu0.iew.predictedTakenIncorrect 190260 # Number of branches that were predicted taken incorrectly -system.cpu0.iew.predictedNotTakenIncorrect 151203 # Number of branches that were predicted not taken incorrectly -system.cpu0.iew.branchMispredicts 341463 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 62339008 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 26506413 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1183677 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewSquashCycles 1689651 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 14217323 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 235152 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 50889581 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 104636 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 10376846 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 6807542 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 742609 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 56975 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 3444 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 16131 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 187025 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 148295 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 335320 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 62072955 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 26415193 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1178479 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed -system.cpu0.iew.exec_nop 126488 # number of nop insts executed -system.cpu0.iew.exec_refs 32682490 # number of memory reference insts executed -system.cpu0.iew.exec_branches 6088882 # Number of branches executed -system.cpu0.iew.exec_stores 6176077 # Number of stores executed -system.cpu0.iew.exec_rate 0.260746 # Inst execution rate -system.cpu0.iew.wb_sent 61801058 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 44510702 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 24520944 # num instructions producing a value -system.cpu0.iew.wb_consumers 44899908 # num instructions consuming a value +system.cpu0.iew.exec_nop 116968 # number of nop insts executed +system.cpu0.iew.exec_refs 32604278 # number of memory reference insts executed +system.cpu0.iew.exec_branches 6035543 # Number of branches executed +system.cpu0.iew.exec_stores 6189085 # Number of stores executed +system.cpu0.iew.exec_rate 0.259677 # Inst execution rate +system.cpu0.iew.wb_sent 61541297 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 44240983 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 24348710 # num instructions producing a value +system.cpu0.iew.wb_consumers 44715244 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 0.186175 # insts written-back per cycle -system.cpu0.iew.wb_fanout 0.546125 # average fanout of values written-back +system.cpu0.iew.wb_rate 0.185079 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.544528 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu0.commit.commitSquashedInsts 10516243 # The number of squashed insts skipped by commit -system.cpu0.commit.commitNonSpecStalls 780306 # The number of times commit has been forced to stall to communicate backwards -system.cpu0.commit.branchMispredicts 297973 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 76282546 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 0.527732 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 1.509463 # Number of insts commited each cycle +system.cpu0.commit.commitSquashedInsts 10387971 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 777166 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 292435 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 76063914 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 0.525878 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.507211 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 61930092 81.19% 81.19% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::1 6958991 9.12% 90.31% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2075873 2.72% 93.03% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::3 1156776 1.52% 94.55% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::4 1044437 1.37% 95.91% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 552027 0.72% 96.64% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::6 702446 0.92% 97.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 372143 0.49% 98.05% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::8 1489761 1.95% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 61806692 81.26% 81.26% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 6917678 9.09% 90.35% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2055110 2.70% 93.05% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 1140236 1.50% 94.55% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 1042779 1.37% 95.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 551797 0.73% 96.65% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 701755 0.92% 97.57% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 371851 0.49% 98.06% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 1476016 1.94% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 76282546 # Number of insts commited each cycle -system.cpu0.commit.committedInsts 31604949 # Number of instructions committed -system.cpu0.commit.committedOps 40256713 # Number of ops (including micro ops) committed +system.cpu0.commit.committed_per_cycle::total 76063914 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 31320190 # Number of instructions committed +system.cpu0.commit.committedOps 40000322 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu0.commit.refs 14068762 # Number of memory references committed -system.cpu0.commit.loads 8173288 # Number of loads committed -system.cpu0.commit.membars 214624 # Number of memory barriers committed -system.cpu0.commit.branches 5267155 # Number of branches committed -system.cpu0.commit.fp_insts 5449 # Number of committed floating point instructions. -system.cpu0.commit.int_insts 35547917 # Number of committed integer instructions. -system.cpu0.commit.function_calls 518151 # Number of function calls committed. -system.cpu0.commit.bw_lim_events 1489761 # number cycles where commit BW limit reached +system.cpu0.commit.refs 14005249 # Number of memory references committed +system.cpu0.commit.loads 8092228 # Number of loads committed +system.cpu0.commit.membars 212474 # Number of memory barriers committed +system.cpu0.commit.branches 5211695 # Number of branches committed +system.cpu0.commit.fp_insts 5465 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 35344589 # Number of committed integer instructions. +system.cpu0.commit.function_calls 514446 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 1476016 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 124585414 # The number of ROB reads -system.cpu0.rob.rob_writes 103297804 # The number of ROB writes -system.cpu0.timesIdled 884994 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 161087173 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu0.quiesceCycles 2289793652 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu0.committedInsts 31519096 # Number of Instructions Simulated -system.cpu0.committedOps 40170860 # Number of Ops (including micro ops) Simulated -system.cpu0.committedInsts_total 31519096 # Number of Instructions Simulated -system.cpu0.cpi 7.585224 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 7.585224 # CPI: Total CPI of All Threads -system.cpu0.ipc 0.131835 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 0.131835 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 282333154 # number of integer regfile reads -system.cpu0.int_regfile_writes 45811922 # number of integer regfile writes -system.cpu0.fp_regfile_reads 22666 # number of floating regfile reads -system.cpu0.fp_regfile_writes 19880 # number of floating regfile writes -system.cpu0.misc_regfile_reads 15681354 # number of misc regfile reads -system.cpu0.misc_regfile_writes 434463 # number of misc regfile writes -system.cpu0.icache.replacements 984470 # number of replacements -system.cpu0.icache.tagsinuse 511.608417 # Cycle average of tags in use -system.cpu0.icache.total_refs 11039436 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 984982 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 11.207754 # Average number of references to valid blocks. +system.cpu0.rob.rob_reads 123998072 # The number of ROB reads +system.cpu0.rob.rob_writes 102508386 # The number of ROB writes +system.cpu0.timesIdled 885261 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 161285099 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.quiesceCycles 2289741427 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu0.committedInsts 31240748 # Number of Instructions Simulated +system.cpu0.committedOps 39920880 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 31240748 # Number of Instructions Simulated +system.cpu0.cpi 7.651503 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 7.651503 # CPI: Total CPI of All Threads +system.cpu0.ipc 0.130693 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 0.130693 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 281024230 # number of integer regfile reads +system.cpu0.int_regfile_writes 45498524 # number of integer regfile writes +system.cpu0.fp_regfile_reads 22712 # number of floating regfile reads +system.cpu0.fp_regfile_writes 19798 # number of floating regfile writes +system.cpu0.misc_regfile_reads 15634103 # number of misc regfile reads +system.cpu0.misc_regfile_writes 430225 # number of misc regfile writes +system.cpu0.icache.replacements 984356 # number of replacements +system.cpu0.icache.tagsinuse 511.608403 # Cycle average of tags in use +system.cpu0.icache.total_refs 11036978 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 984868 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 11.206556 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 6537508000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 358.593548 # Average occupied blocks per requestor -system.cpu0.icache.occ_blocks::cpu1.inst 153.014869 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.700378 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::cpu1.inst 0.298857 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 359.190801 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu1.inst 152.417601 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.701545 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::cpu1.inst 0.297691 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.999235 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 5636954 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::cpu1.inst 5402482 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 11039436 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 5636954 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::cpu1.inst 5402482 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 11039436 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 5636954 # number of overall hits -system.cpu0.icache.overall_hits::cpu1.inst 5402482 # number of overall hits -system.cpu0.icache.overall_hits::total 11039436 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 544416 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::cpu1.inst 521534 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 1065950 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 544416 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::cpu1.inst 521534 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 1065950 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 544416 # number of overall misses -system.cpu0.icache.overall_misses::cpu1.inst 521534 # number of overall misses -system.cpu0.icache.overall_misses::total 1065950 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7382097491 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6930257996 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 14312355487 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7382097491 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::cpu1.inst 6930257996 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 14312355487 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7382097491 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::cpu1.inst 6930257996 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 14312355487 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 6181370 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::cpu1.inst 5924016 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 12105386 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 6181370 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::cpu1.inst 5924016 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 12105386 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 6181370 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::cpu1.inst 5924016 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 12105386 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088074 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.088037 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.088056 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088074 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::cpu1.inst 0.088037 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.088056 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088074 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::cpu1.inst 0.088037 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.088056 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13559.662999 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13288.218977 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13426.854437 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13426.854437 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13559.662999 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13288.218977 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13426.854437 # average overall miss latency -system.cpu0.icache.blocked_cycles::no_mshrs 5254 # number of cycles access was blocked +system.cpu0.icache.ReadReq_hits::cpu0.inst 5577013 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::cpu1.inst 5459965 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 11036978 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 5577013 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::cpu1.inst 5459965 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 11036978 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 5577013 # number of overall hits +system.cpu0.icache.overall_hits::cpu1.inst 5459965 # number of overall hits +system.cpu0.icache.overall_hits::total 11036978 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 543890 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::cpu1.inst 521924 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 1065814 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 543890 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::cpu1.inst 521924 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 1065814 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 543890 # number of overall misses +system.cpu0.icache.overall_misses::cpu1.inst 521924 # number of overall misses +system.cpu0.icache.overall_misses::total 1065814 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7368318492 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 6936357997 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14304676489 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7368318492 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::cpu1.inst 6936357997 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14304676489 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7368318492 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::cpu1.inst 6936357997 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14304676489 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 6120903 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::cpu1.inst 5981889 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 12102792 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 6120903 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::cpu1.inst 5981889 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 12102792 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 6120903 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::cpu1.inst 5981889 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 12102792 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.088858 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.087251 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.088063 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.088858 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::cpu1.inst 0.087251 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.088063 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.088858 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::cpu1.inst 0.087251 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.088063 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13547.442483 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13289.977079 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13421.362910 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13547.442483 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13289.977079 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13421.362910 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13547.442483 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13289.977079 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13421.362910 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 4739 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 847 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 386 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 348 # number of cycles access was blocked system.cpu0.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.611399 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 13.617816 # average number of cycles each access was blocked system.cpu0.icache.avg_blocked_cycles::no_targets 847 # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41493 # 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number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 4423017439 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8455829431 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72820000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73471000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 146291000 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 44000 # number of StoreCondReq MSHR miss cycles system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 55000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 88000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6887825990 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6783576942 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 13671402932 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6887825990 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6783576942 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 13671402932 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91735466000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90620432500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182355898500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14921149436 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18671847220 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33592996656 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 99000 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6945203992 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 6745943439 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 13691147431 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6945203992 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 6745943439 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 13691147431 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 91812195000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 90543970000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 182356165000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 14920751936 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 18671646220 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 33592398156 # number of WriteReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::cpu1.data 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.LoadLockedReq_mshr_uncacheable_latency::total 118000 # number of LoadLockedReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::cpu1.data 69000 # number of StoreCondReq MSHR uncacheable cycles system.cpu0.dcache.StoreCondReq_mshr_uncacheable_latency::total 69000 # number of StoreCondReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106656615436 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109292279720 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948895156 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028364 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024533 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026555 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023050 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025672 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 106732946936 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 109215616220 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 215948563156 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.028290 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.024665 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.026554 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.023234 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.025493 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.024348 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046824 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.047971 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047376 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000023 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.046835 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.048056 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.047426 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.000031 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.000042 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000032 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for demand accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000036 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.026236 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.025012 # mshr miss rate for demand accesses system.cpu0.dcache.demand_mshr_miss_rate::total 0.025643 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026225 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025017 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.026236 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.025012 # mshr miss rate for overall accesses system.cpu0.dcache.overall_mshr_miss_rate::total 0.025643 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13560.452775 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13571.458702 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13565.254696 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33092.358985 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34643.924773 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33901.937429 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11692.836585 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12205.417227 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11942.613543 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 13597.997927 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13537.732605 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13571.191937 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33496.507264 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 34418.762073 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33972.661544 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11711.161145 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 12279.959886 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11990.082780 # average LoadLockedReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 11000 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20469.691402 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22749.405380 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21540.759272 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 20758.411444 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 22479.359666 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 21572.140759 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 20758.411444 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 22479.359666 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 21572.140759 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -1310,324 +1310,324 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.branchPred.lookups 6924581 # Number of BP lookups -system.cpu1.branchPred.condPredicted 5562771 # Number of conditional branches predicted -system.cpu1.branchPred.condIncorrect 336228 # Number of conditional branches incorrect -system.cpu1.branchPred.BTBLookups 4476731 # Number of BTB lookups -system.cpu1.branchPred.BTBHits 3769892 # Number of BTB hits +system.cpu1.branchPred.lookups 7008518 # Number of BP lookups +system.cpu1.branchPred.condPredicted 5622209 # Number of conditional branches predicted +system.cpu1.branchPred.condIncorrect 340954 # Number of conditional branches incorrect +system.cpu1.branchPred.BTBLookups 4512372 # Number of BTB lookups +system.cpu1.branchPred.BTBHits 3795619 # Number of BTB hits system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu1.branchPred.BTBHitPct 84.210823 # BTB Hit Percentage -system.cpu1.branchPred.usedRAS 665809 # Number of times the RAS was used to get a target. -system.cpu1.branchPred.RASInCorrect 34604 # Number of incorrect RAS predictions. +system.cpu1.branchPred.BTBHitPct 84.115826 # BTB Hit Percentage +system.cpu1.branchPred.usedRAS 671281 # Number of times the RAS was used to get a target. +system.cpu1.branchPred.RASInCorrect 35132 # Number of incorrect RAS predictions. system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 25217799 # DTB read hits -system.cpu1.dtb.read_misses 35648 # DTB read misses -system.cpu1.dtb.write_hits 5810779 # DTB write hits -system.cpu1.dtb.write_misses 9529 # DTB write misses +system.cpu1.dtb.read_hits 25306381 # DTB read hits +system.cpu1.dtb.read_misses 36302 # DTB read misses +system.cpu1.dtb.write_hits 5796978 # DTB write hits +system.cpu1.dtb.write_misses 9188 # DTB write misses system.cpu1.dtb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.dtb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.dtb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 5398 # Number of entries that have been flushed from TLB -system.cpu1.dtb.align_faults 1388 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 230 # Number of TLB faults due to prefetch +system.cpu1.dtb.flush_entries 5467 # Number of entries that have been flushed from TLB +system.cpu1.dtb.align_faults 1344 # Number of TLB faults due to alignment restrictions +system.cpu1.dtb.prefetch_faults 228 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 634 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 25253447 # DTB read accesses -system.cpu1.dtb.write_accesses 5820308 # DTB write accesses +system.cpu1.dtb.perms_faults 638 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 25342683 # DTB read accesses +system.cpu1.dtb.write_accesses 5806166 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 31028578 # DTB hits -system.cpu1.dtb.misses 45177 # DTB misses -system.cpu1.dtb.accesses 31073755 # DTB accesses -system.cpu1.itb.inst_hits 5925943 # ITB inst hits -system.cpu1.itb.inst_misses 6573 # ITB inst misses +system.cpu1.dtb.hits 31103359 # DTB hits +system.cpu1.dtb.misses 45490 # DTB misses +system.cpu1.dtb.accesses 31148849 # DTB accesses +system.cpu1.itb.inst_hits 5983864 # ITB inst hits +system.cpu1.itb.inst_misses 6799 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits system.cpu1.itb.write_misses 0 # DTB write misses system.cpu1.itb.flush_tlb 254 # Number of times complete TLB was flushed system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA -system.cpu1.itb.flush_tlb_mva_asid 664 # Number of times TLB was flushed by MVA & ASID +system.cpu1.itb.flush_tlb_mva_asid 670 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 2476 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 2574 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.itb.perms_faults 1382 # Number of TLB faults due to permissions restrictions +system.cpu1.itb.perms_faults 1412 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 5932516 # ITB inst accesses -system.cpu1.itb.hits 5925943 # DTB hits -system.cpu1.itb.misses 6573 # DTB misses -system.cpu1.itb.accesses 5932516 # DTB accesses -system.cpu1.numCycles 234244847 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 5990663 # ITB inst accesses +system.cpu1.itb.hits 5983864 # DTB hits +system.cpu1.itb.misses 6799 # DTB misses +system.cpu1.itb.accesses 5990663 # DTB accesses +system.cpu1.numCycles 234290379 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.fetch.icacheStallCycles 15045426 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 46051404 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 6924581 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 4435701 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 10180178 # Number of cycles fetch has run and was not squashing or blocked -system.cpu1.fetch.SquashCycles 2576164 # Number of cycles fetch has spent squashing -system.cpu1.fetch.TlbCycles 79323 # Number of cycles fetch has spent waiting for tlb -system.cpu1.fetch.BlockedCycles 47488838 # Number of cycles fetch has spent blocked -system.cpu1.fetch.MiscStallCycles 962 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.PendingDrainCycles 2036 # Number of cycles fetch has spent waiting on pipes to drain -system.cpu1.fetch.PendingTrapStallCycles 40665 # Number of stall cycles due to pending traps -system.cpu1.fetch.PendingQuiesceStallCycles 94257 # Number of stall cycles due to pending quiesce instructions -system.cpu1.fetch.IcacheWaitRetryStallCycles 230 # Number of stall cycles due to full MSHR -system.cpu1.fetch.CacheLines 5924019 # Number of cache lines fetched -system.cpu1.fetch.IcacheSquashes 441347 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.ItlbSquashes 2911 # Number of outstanding ITLB misses that were squashed -system.cpu1.fetch.rateDist::samples 74691954 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 0.768024 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.131487 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.icacheStallCycles 15116451 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 46466902 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 7008518 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 4466900 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 10252429 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2600331 # Number of cycles fetch has spent squashing +system.cpu1.fetch.TlbCycles 81459 # Number of cycles fetch has spent waiting for tlb +system.cpu1.fetch.BlockedCycles 47550524 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 905 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingDrainCycles 2006 # Number of cycles fetch has spent waiting on pipes to drain +system.cpu1.fetch.PendingTrapStallCycles 43802 # Number of stall cycles due to pending traps +system.cpu1.fetch.PendingQuiesceStallCycles 94777 # Number of stall cycles due to pending quiesce instructions +system.cpu1.fetch.IcacheWaitRetryStallCycles 144 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 5981892 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 442637 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.ItlbSquashes 2912 # Number of outstanding ITLB misses that were squashed +system.cpu1.fetch.rateDist::samples 74921475 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 0.771035 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.135527 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 64519001 86.38% 86.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 606919 0.81% 87.19% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::2 824654 1.10% 88.30% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::3 1190723 1.59% 89.89% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::4 1057088 1.42% 91.31% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 528345 0.71% 92.01% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::6 1354186 1.81% 93.83% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::7 346670 0.46% 94.29% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::8 4264368 5.71% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 64676712 86.33% 86.33% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 618864 0.83% 87.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 829977 1.11% 88.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 1202840 1.61% 89.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 1044061 1.39% 91.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 533999 0.71% 91.97% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1368584 1.83% 93.80% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 349498 0.47% 94.26% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 4296940 5.74% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 74691954 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.029561 # Number of branch fetches per cycle -system.cpu1.fetch.rate 0.196595 # Number of inst fetches per cycle -system.cpu1.decode.IdleCycles 16048040 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 47278235 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 9237318 # Number of cycles decode is running -system.cpu1.decode.UnblockCycles 448383 # Number of cycles decode is unblocking -system.cpu1.decode.SquashCycles 1677844 # Number of cycles decode is squashing -system.cpu1.decode.BranchResolved 921418 # Number of times decode resolved a branch -system.cpu1.decode.BranchMispred 84751 # Number of times decode detected a branch misprediction -system.cpu1.decode.DecodedInsts 54328734 # Number of instructions handled by decode -system.cpu1.decode.SquashedInsts 282420 # Number of squashed instructions handled by decode -system.cpu1.rename.SquashCycles 1677844 # Number of cycles rename is squashing -system.cpu1.rename.IdleCycles 16980429 # Number of cycles rename is idle -system.cpu1.rename.BlockCycles 18581446 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 25685933 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 8674589 # Number of cycles rename is running -system.cpu1.rename.UnblockCycles 3089642 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 51185611 # Number of instructions processed by rename -system.cpu1.rename.ROBFullEvents 7172 # Number of times rename has blocked due to ROB full -system.cpu1.rename.IQFullEvents 483859 # Number of times rename has blocked due to IQ full -system.cpu1.rename.LSQFullEvents 2112197 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.FullRegisterEvents 97 # Number of times there has been no free registers -system.cpu1.rename.RenamedOperands 53156547 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 235159359 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 235117285 # Number of integer rename lookups -system.cpu1.rename.fp_rename_lookups 42074 # Number of floating rename lookups -system.cpu1.rename.CommittedMaps 37614805 # Number of HB maps that are committed -system.cpu1.rename.UndoneMaps 15541741 # Number of HB maps that are undone due to squashing -system.cpu1.rename.serializingInsts 399062 # count of serializing insts renamed -system.cpu1.rename.tempSerializingInsts 353498 # count of temporary serializing insts renamed -system.cpu1.rename.skidInsts 6213195 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 9696990 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 6683769 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 865241 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 1058674 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 47161259 # Number of instructions added to the IQ (excludes non-spec) -system.cpu1.iq.iqNonSpecInstsAdded 954916 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 60450494 # Number of instructions issued -system.cpu1.iq.iqSquashedInstsIssued 77232 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10409443 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 27466585 # Number of squashed operands that are examined and possibly removed from graph -system.cpu1.iq.iqSquashedNonSpecRemoved 252722 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 74691954 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 0.809331 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::stdev 1.520957 # Number of insts issued each cycle +system.cpu1.fetch.rateDist::total 74921475 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.029914 # Number of branch fetches per cycle +system.cpu1.fetch.rate 0.198330 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 16127430 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 47340991 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 9302277 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 452157 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1696491 # Number of cycles decode is squashing +system.cpu1.decode.BranchResolved 939788 # Number of times decode resolved a branch +system.cpu1.decode.BranchMispred 85014 # Number of times decode detected a branch misprediction +system.cpu1.decode.DecodedInsts 54712393 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 283938 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1696491 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 17063579 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 18568678 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 25752424 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 8740556 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3097679 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 51550474 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 7120 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 486939 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 2114664 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.FullRegisterEvents 95 # Number of times there has been no free registers +system.cpu1.rename.RenamedOperands 53606265 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 236686025 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 236643642 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 42383 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 37932809 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 15673455 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 402617 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 356688 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 6237356 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 9815438 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 6669487 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 880329 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1133832 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 47508806 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 941900 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 60718178 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 80732 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 10491137 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 27821920 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 236570 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 74921475 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 0.810424 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.521077 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 53120438 71.12% 71.12% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::1 6581682 8.81% 79.93% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 3495899 4.68% 84.61% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 2849080 3.81% 88.43% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::4 6224305 8.33% 96.76% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::5 1417719 1.90% 98.66% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::6 735156 0.98% 99.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::7 208377 0.28% 99.92% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::8 59298 0.08% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 53226617 71.04% 71.04% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6639225 8.86% 79.90% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 3521147 4.70% 84.60% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 2865539 3.82% 88.43% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 6243808 8.33% 96.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 1415606 1.89% 98.65% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 739373 0.99% 99.64% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 210738 0.28% 99.92% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 59422 0.08% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 74691954 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 74921475 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntAlu 25658 0.59% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.59% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemRead 4148051 94.78% 95.37% # attempts to use FU when none available -system.cpu1.iq.fu_full::MemWrite 202723 4.63% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 26168 0.60% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 1 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 0.60% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 4150795 94.85% 95.45% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 199100 4.55% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu1.iq.FU_type_0::No_OpClass 169977 0.28% 0.28% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 28184247 46.62% 46.90% # Type of FU issued -system.cpu1.iq.FU_type_0::IntMult 45636 0.08% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMisc 8 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdShiftAcc 4 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMisc 892 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 46.98% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 25945360 42.92% 89.90% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 6104366 10.10% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::No_OpClass 167818 0.28% 0.28% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 28373691 46.73% 47.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 46091 0.08% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 12 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 9 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 896 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 9 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.08% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 26040141 42.89% 89.97% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 6089511 10.03% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 60450494 # Type of FU issued -system.cpu1.iq.rate 0.258065 # Inst issue rate -system.cpu1.iq.fu_busy_cnt 4376432 # FU busy when requested -system.cpu1.iq.fu_busy_rate 0.072397 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 200080953 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 58533998 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 41393677 # Number of integer instruction queue wakeup accesses -system.cpu1.iq.fp_inst_queue_reads 10638 # Number of floating instruction queue reads -system.cpu1.iq.fp_inst_queue_writes 5781 # Number of floating instruction queue writes -system.cpu1.iq.fp_inst_queue_wakeup_accesses 4780 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 64651317 # Number of integer alu accesses -system.cpu1.iq.fp_alu_accesses 5632 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 296486 # Number of loads that had data forwarded from stores +system.cpu1.iq.FU_type_0::total 60718178 # Type of FU issued +system.cpu1.iq.rate 0.259158 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 4376064 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.072072 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 200849206 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 58949996 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 41661656 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 10739 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 5891 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4795 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 64920728 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 5696 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 301587 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu1.iew.lsq.thread0.squashedLoads 2215043 # Number of loads squashed -system.cpu1.iew.lsq.thread0.ignoredResponses 3144 # Number of memory responses ignored because the instruction is squashed -system.cpu1.iew.lsq.thread0.memOrderViolation 14677 # Number of memory ordering violations -system.cpu1.iew.lsq.thread0.squashedStores 846684 # Number of stores squashed +system.cpu1.iew.lsq.thread0.squashedLoads 2252430 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 3185 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 14519 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 849951 # Number of stores squashed system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu1.iew.lsq.thread0.rescheduledLoads 16976661 # Number of loads that were rescheduled -system.cpu1.iew.lsq.thread0.cacheBlocked 457892 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.lsq.thread0.rescheduledLoads 16963490 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 458141 # Number of times an access to memory failed due to the cache being blocked system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu1.iew.iewSquashCycles 1677844 # Number of cycles IEW is squashing -system.cpu1.iew.iewBlockCycles 14002380 # Number of cycles IEW is blocking -system.cpu1.iew.iewUnblockCycles 233104 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 48212114 # Number of instructions dispatched to IQ -system.cpu1.iew.iewDispSquashedInsts 96608 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 9696990 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 6683769 # Number of dispatched store instructions -system.cpu1.iew.iewDispNonSpecInsts 685390 # Number of dispatched non-speculative instructions -system.cpu1.iew.iewIQFullEvents 50588 # Number of times the IQ has become full, causing a stall -system.cpu1.iew.iewLSQFullEvents 3685 # Number of times the LSQ has become full, causing a stall -system.cpu1.iew.memOrderViolationEvents 14677 # Number of memory order violations -system.cpu1.iew.predictedTakenIncorrect 163070 # Number of branches that were predicted taken incorrectly -system.cpu1.iew.predictedNotTakenIncorrect 129112 # Number of branches that were predicted not taken incorrectly -system.cpu1.iew.branchMispredicts 292182 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 59083319 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 25544592 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1367175 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewSquashCycles 1696491 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 13989696 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 234454 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 48555942 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 97471 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 9815438 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 6669487 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 669348 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 52364 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 3770 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 14519 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 165263 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 131892 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 297155 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 59347630 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 25635579 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1370548 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 95939 # number of nop insts executed -system.cpu1.iew.exec_refs 31597721 # number of memory reference insts executed -system.cpu1.iew.exec_branches 5452623 # Number of branches executed -system.cpu1.iew.exec_stores 6053129 # Number of stores executed -system.cpu1.iew.exec_rate 0.252229 # Inst execution rate -system.cpu1.iew.wb_sent 58512296 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 41398457 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 22553116 # num instructions producing a value -system.cpu1.iew.wb_consumers 41520902 # num instructions consuming a value +system.cpu1.iew.exec_nop 105236 # number of nop insts executed +system.cpu1.iew.exec_refs 31674399 # number of memory reference insts executed +system.cpu1.iew.exec_branches 5507310 # Number of branches executed +system.cpu1.iew.exec_stores 6038820 # Number of stores executed +system.cpu1.iew.exec_rate 0.253308 # Inst execution rate +system.cpu1.iew.wb_sent 58770434 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 41666451 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 22724136 # num instructions producing a value +system.cpu1.iew.wb_consumers 41696356 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 0.176732 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.543175 # average fanout of values written-back +system.cpu1.iew.wb_rate 0.177841 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.544991 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu1.commit.commitSquashedInsts 10281991 # The number of squashed insts skipped by commit -system.cpu1.commit.commitNonSpecStalls 702194 # The number of times commit has been forced to stall to communicate backwards -system.cpu1.commit.branchMispredicts 252752 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 73014110 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 0.513541 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 1.493879 # Number of insts commited each cycle +system.cpu1.commit.commitSquashedInsts 10406617 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 705330 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 257195 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 73224984 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 0.515564 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.495876 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 59627220 81.67% 81.67% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 6596697 9.03% 90.70% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::2 1882997 2.58% 93.28% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 995941 1.36% 94.64% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::4 953813 1.31% 95.95% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 518436 0.71% 96.66% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::6 701051 0.96% 97.62% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::7 372117 0.51% 98.13% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::8 1365838 1.87% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 59733735 81.58% 81.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 6648402 9.08% 90.66% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 1900730 2.60% 93.25% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 1014899 1.39% 94.64% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 955667 1.31% 95.94% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 519546 0.71% 96.65% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 702094 0.96% 97.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 374619 0.51% 98.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 1375292 1.88% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 73014110 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 28855252 # Number of instructions committed -system.cpu1.commit.committedOps 37495775 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 73224984 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 29140034 # Number of instructions committed +system.cpu1.commit.committedOps 37752190 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 13319032 # Number of memory references committed -system.cpu1.commit.loads 7481947 # Number of loads committed -system.cpu1.commit.membars 189014 # Number of memory barriers committed -system.cpu1.commit.branches 4694468 # Number of branches committed -system.cpu1.commit.fp_insts 4763 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 33309565 # Number of committed integer instructions. -system.cpu1.commit.function_calls 473164 # Number of function calls committed. -system.cpu1.commit.bw_lim_events 1365838 # number cycles where commit BW limit reached +system.cpu1.commit.refs 13382544 # Number of memory references committed +system.cpu1.commit.loads 7563008 # Number of loads committed +system.cpu1.commit.membars 191164 # Number of memory barriers committed +system.cpu1.commit.branches 4749934 # Number of branches committed +system.cpu1.commit.fp_insts 4747 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 33512913 # Number of committed integer instructions. +system.cpu1.commit.function_calls 476869 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 1375292 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 118557028 # The number of ROB reads -system.cpu1.rob.rob_writes 97285221 # The number of ROB writes -system.cpu1.timesIdled 872406 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 159552893 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 2285658129 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 28790724 # Number of Instructions Simulated -system.cpu1.committedOps 37431247 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 28790724 # Number of Instructions Simulated -system.cpu1.cpi 8.136122 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 8.136122 # CPI: Total CPI of All Threads -system.cpu1.ipc 0.122909 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 0.122909 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 267548470 # number of integer regfile reads -system.cpu1.int_regfile_writes 42457075 # number of integer regfile writes -system.cpu1.fp_regfile_reads 22098 # number of floating regfile reads -system.cpu1.fp_regfile_writes 19630 # number of floating regfile writes -system.cpu1.misc_regfile_reads 14600215 # number of misc regfile reads -system.cpu1.misc_regfile_writes 398004 # number of misc regfile writes +system.cpu1.rob.rob_reads 119137293 # The number of ROB reads +system.cpu1.rob.rob_writes 98065994 # The number of ROB writes +system.cpu1.timesIdled 872405 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 159368904 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 2285729995 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 29069095 # Number of Instructions Simulated +system.cpu1.committedOps 37681251 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 29069095 # Number of Instructions Simulated +system.cpu1.cpi 8.059775 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 8.059775 # CPI: Total CPI of All Threads +system.cpu1.ipc 0.124073 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 0.124073 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 268846383 # number of integer regfile reads +system.cpu1.int_regfile_writes 42770958 # number of integer regfile writes +system.cpu1.fp_regfile_reads 22164 # number of floating regfile reads +system.cpu1.fp_regfile_writes 19740 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14685681 # number of misc regfile reads +system.cpu1.misc_regfile_writes 402240 # number of misc regfile writes system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -1642,17 +1642,17 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1192831582801 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192831582801 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1192831582801 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1192848371945 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1192848371945 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1192848371945 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1192848371945 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 83052 # number of quiesce instructions executed +system.cpu0.kern.inst.quiesce 83051 # number of quiesce instructions executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed |